Method for manufacturing semiconductor device, semiconductor device, and three-dimensional memory

Abstract

The application discloses a semiconductor device manufacturing method, a semiconductor device and a three-dimensional memory. The method comprises the following steps: forming a shallow trench isolation groove in a substrate, the shallow trench isolation groove being located at the periphery of an active region of the substrate; forming a bottom isolation layer in the shallow trench isolation groove; forming a gate structure on a channel region of the substrate; and forming a hard insulation layer on the sidewall of the active region, so that the hard insulation layer covers a source region and a drain region of the substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device, a semiconductor device, and a three-dimensional memory. Background Technology

[0002] In semiconductor devices, the source and drain regions of transistors (especially low-voltage transistors) in the peripheral CMOS structure are relatively small, resulting in a small landing window between the source and drain regions and the contact structure (CT). Since the source and drain regions are adjacent to the shallow trench isolation structure, if the connection position of the contact structure deviates slightly from the source or drain regions—for example, if part of the contact structure is located on the source or drain region and part on the shallow trench isolation structure—the contact structure is prone to collapse due to the oxide material of the shallow trench isolation structure, thus affecting the performance of the semiconductor device.

[0003] Technical issues

[0004] This invention provides a method for fabricating a semiconductor device, a semiconductor device, and a three-dimensional memory, which can increase the connection window between the source and drain regions and improve the performance of the semiconductor device.

[0005] Technical solutions

[0006] This invention provides a method for fabricating a semiconductor device, comprising:

[0007] A shallow trench isolation trench is formed in a substrate, the substrate including an active region, the shallow trench isolation trench being located on the periphery of the active region, the active region including a source region, a channel region and a drain region connected in sequence;

[0008] A bottom isolation layer is formed in the shallow trench;

[0009] A gate structure is formed on the channel region;

[0010] A hard insulating layer is formed on the sidewall of the active region, so that the hard insulating layer covers the source region and the drain region.

[0011] More preferably, the step of forming a bottom isolation layer in the shallow trench includes:

[0012] A medium layer is filled into the shallow isolation trench;

[0013] The dielectric layer is etched so that the etched dielectric layer constitutes the bottom isolation layer.

[0014] More preferably, the step of forming a gate structure on the channel region includes:

[0015] A gate insulating layer is formed on the inner surface of the shallow trench isolation trench and on the substrate;

[0016] A gate layer is formed on the gate insulating layer;

[0017] The gate insulating layer and the gate layer are etched so that the etched gate insulating layer and the gate layer form the gate structure located on the channel region.

[0018] More preferably, the method further includes:

[0019] The hard insulating layer extends to the bottom isolation layer, the source region, the drain region, and the gate structure.

[0020] More preferably, prior to the step of forming a hard insulating layer on the sidewall of the active region, the method further includes:

[0021] Sidewalls are formed on the sidewalls of the shallow trench isolation groove and the sidewalls of the gate structure.

[0022] More preferably, prior to the step of forming a hard insulating layer on the sidewall of the active region, the method further includes:

[0023] An ohmic contact layer is formed on the source region, the drain region, and the gate structure.

[0024] More preferably, the method further includes:

[0025] A first contact structure and a second contact structure are formed, wherein the first contact structure is connected to the source region and the second contact structure is connected to the drain region.

[0026] The present invention also provides a semiconductor device, comprising:

[0027] The active region includes the source region, channel region, and drain region connected in sequence.

[0028] The bottom isolation layer located around the active region;

[0029] A gate structure, the gate structure being located on the channel region; and,

[0030] A hard insulating layer is located on the sidewall of the active region, the hard insulating layer covering the source region and the drain region.

[0031] More preferably, the gate structure includes a gate insulating layer and a gate layer located on the gate insulating layer.

[0032] More preferably, the hard insulating layer is also located on the bottom isolation layer, the source region, the drain region, and the gate structure.

[0033] More preferably, the semiconductor device further includes:

[0034] An ohmic contact layer located between the source region, the drain region, the gate structure, and the hard insulating layer.

[0035] More preferably, the semiconductor device further includes:

[0036] The sidewalls are located between the hard insulating layer and the sidewalls of the active region, and on the sidewalls of the gate structure.

[0037] More preferably, the semiconductor device further includes:

[0038] A first contact structure and a second contact structure are provided, wherein the first contact structure is connected to the source region and the second contact structure is connected to the drain region.

[0039] More preferably, the gate structure extends along the sidewall of the active region to the bottom isolation layer.

[0040] The present invention also provides a three-dimensional memory, including a memory array structure and a peripheral structure connected to the memory array structure, the peripheral structure including semiconductor devices;

[0041] The semiconductor device includes:

[0042] The active region includes the source region, channel region, and drain region connected in sequence.

[0043] The bottom isolation layer located around the active region;

[0044] A gate structure, the gate structure being located on the channel region; and,

[0045] A hard insulating layer is located on the sidewall of the active region, the hard insulating layer covering the source region and the drain region.

[0046] More preferably, the hard insulating layer is also located on the bottom isolation layer, the source region, the drain region, and the gate structure.

[0047] More preferably, the semiconductor device further includes:

[0048] An ohmic contact layer located between the source region, the drain region, the gate structure, and the hard insulating layer.

[0049] More preferably, the semiconductor device further includes:

[0050] The sidewalls are located between the hard insulating layer and the sidewalls of the active region, and on the sidewalls of the gate structure.

[0051] More preferably, the semiconductor device further includes:

[0052] A first contact structure and a second contact structure are provided, wherein the first contact structure is connected to the source region and the second contact structure is connected to the drain region.

[0053] More preferably, the gate structure extends along the sidewall of the active region to the bottom isolation layer.

[0054] Beneficial effects

[0055] The beneficial effects of this invention are as follows: First, a shallow trench isolation is formed in the substrate, and a bottom isolation layer is formed in the shallow trench isolation. Then, a gate structure is formed, with the gate structure located on the channel region between the source region and the drain region in the substrate. Then, a hard insulating layer is formed on the sidewall of the active region, covering the source region and the drain region. Subsequently, when forming the contact structure, even if the contact structure is partially located on the source region or the drain region and partially located on the hard insulating layer, the contact structure will not collapse, thereby increasing the connection window between the source region and the drain region and improving the performance of the semiconductor device. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments or prior art, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0058] Figures 2a to 2j This is a schematic diagram of the structure of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0059] Figure 3 This is a schematic diagram of the structure of the semiconductor device provided in the embodiment of the present invention;

[0060] Figure 4 This is a schematic diagram of the structure of a transistor in a semiconductor device provided in an embodiment of the present invention;

[0061] Figure 5 This is a schematic diagram of the structure of the three-dimensional memory provided in an embodiment of the present invention.

[0062] Embodiments of the present invention

[0063] The specific structural and functional details disclosed herein are merely representative and are intended to describe exemplary embodiments of the invention. However, the invention can be embodied in many alternative forms and should not be construed as being limited solely to the embodiments set forth herein.

[0064] In the description of this invention, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.

[0065] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0066] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural. It should also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, units, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.

[0067] See Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device provided in an embodiment of the present invention.

[0068] like Figure 1 As shown, this embodiment provides a method for fabricating a semiconductor device, the method including steps 101 to 104, as detailed below:

[0069] Step 101: Form a shallow trench isolation trench in a substrate, wherein the substrate includes an active region, the shallow trench isolation trench is located on the periphery of the active region, and the active region includes a source region, a channel region and a drain region connected in sequence.

[0070] In this embodiment of the invention, a substrate is first provided. The substrate can be a silicon substrate, a germanium substrate, or a semiconductor substrate containing other elements. Trace amounts of trivalent elements, such as boron, indium, gallium, and aluminum, can be doped into the substrate to form a P-type semiconductor substrate; trace amounts of pentavalent elements, such as phosphorus, antimony, and arsenic, can also be doped into the substrate to form an N-type semiconductor substrate. An active region can also be formed in the substrate, located near the upper surface of the substrate. P-type or N-type active regions can be formed in the substrate by implanting P-type or N-type dopants into the active region through ion implantation (IMP).

[0071] Then, through ion implantation, specific regions within the active area of ​​the substrate can be doped to form source and drain regions. These source and drain regions are located close to the upper surface of the substrate and are spaced apart. The active region between the source and drain regions forms the channel region; that is, the source, channel, and drain regions are connected sequentially. The source and drain regions can be p-type or n-type doped by implanting p-type or n-type dopant. The doping types of the source and drain regions are the same. If the desired semiconductor device is an n-type transistor, n-type dopant is implanted into the source and drain regions; if the desired semiconductor device is a p-type transistor, p-type dopant is implanted into the source and drain regions.

[0072] Ion implantation can be used to dope specific regions within the active region of a substrate, forming a first doped region and a second doped region. These two doped regions are located near the upper surface of the substrate. The first and second doped regions are spaced apart, with the first doped region located on the side of the source region away from the drain region, and the second doped region located on the side of the drain region away from the source region. The first and second doped regions can be converted into P-type or N-type doped regions through P-type or N-type doping. The first and second doped regions have the same doping type. These regions are used to bring out the active region, allowing an external bias voltage to be applied to the active region, thus providing different substrate bias voltages to the transistor.

[0073] like Figure 2a As shown, the substrate 1 includes an active region 2, which includes a source region 21, a channel region 23, and a drain region 22 connected in sequence. A shallow trench isolation trench 3 is formed around the active region 2 on the periphery of the substrate 1, that is, the shallow trench isolation trench 3 surrounds the active region 2.

[0074] Step 102: Form a bottom isolation layer in the shallow trench.

[0075] In this embodiment of the invention, the bottom isolation layer can be formed directly at the bottom of the shallow trench isolation trench by spin coating, or it can be formed by filling the shallow trench isolation trench with a dielectric layer and then etching.

[0076] Specifically, step 102, forming a bottom isolation layer in the shallow trench, includes:

[0077] A medium layer is filled into the shallow isolation trench;

[0078] The dielectric layer is etched so that the etched dielectric layer constitutes the bottom isolation layer.

[0079] In this process, a dielectric layer fills a shallow isolation trench, and then the dielectric layer is partially etched, leaving the remaining dielectric layer to form the bottom isolation layer. For example... Figure 2b As shown, a bottom isolation layer 4 is formed in the shallow isolation trench 3. Combined with... Figure 2c As shown, Figure 2c for Figure 2b A cross-sectional diagram at point A (dashed line). The bottom isolation layer 4 is located at the bottom of the shallow trench isolation trough 3.

[0080] Step 103: Form a gate structure on the channel region.

[0081] In this embodiment of the invention, a gate structure is formed on the channel region between the source and drain regions to form a transistor with the source and drain regions in the active region. The active region can be an ultra-low voltage active region, a low voltage active region, or a high voltage active region. The transistor corresponding to the ultra-low voltage active region is an ultra-low voltage transistor, the transistor corresponding to the low voltage active region is a low voltage transistor, and the transistor corresponding to the high voltage active region is a high voltage transistor. Ultra-low voltage, low voltage, and high voltage are relative concepts. The operating voltage of the ultra-low voltage transistor (i.e., the voltage applied to the gate layer in the gate structure) is relatively small, for example, 0V to 5V; the operating voltage of the high voltage transistor is relatively large, for example, 15V to 25V; and the operating voltage of the low voltage transistor is between the operating voltages of the ultra-low voltage transistor and the high voltage transistor, for example, 5V to 15V. Among ultra-low voltage transistors, low voltage transistors, and high voltage transistors, the high voltage active region is the largest, the ultra-low voltage active region is the smallest, and the low voltage active region is located between the high voltage active region and the low voltage active region. The high voltage transistor has the largest channel depth, the ultra-low voltage transistor has the smallest channel depth, and the low voltage transistor's channel depth is located between the high voltage transistor's channel depth and the ultra-low voltage transistor's channel depth.

[0082] The transistors in this embodiment can be applied to the peripheral structure of a three-dimensional memory. This peripheral structure may include page buffer circuits, I / O circuits, word line driver circuits, etc. Specifically, the page buffer circuit may include the aforementioned high-voltage transistors, the I / O circuits may include the aforementioned low-voltage transistors, and the word line driver circuits may include the aforementioned ultra-low-voltage transistors.

[0083] In some implementations, the gate structure is located on the channel region and extends along the sidewall of the active region, which can reduce the area of ​​the transistor, thereby reducing the area of ​​the semiconductor device.

[0084] Specifically, the step 103 of forming a gate structure on the channel region includes:

[0085] A gate insulating layer is formed on the inner surface of the shallow trench isolation trench and on the substrate;

[0086] A gate layer is formed on the gate insulating layer;

[0087] The gate insulating layer and the gate layer are etched so that the etched gate insulating layer and the gate layer form the gate structure located on the channel region.

[0088] Combination Figure 2b and Figure 2d As shown, Figure 2d for Figure 2b A cross-sectional schematic diagram at point B (dashed line). First, a gate insulating layer 51 is formed on the inner surface of the shallow trench isolation 3 and on the substrate 1. The gate insulating layer 51 is very thin. Then, a gate layer 52 is formed on the gate insulating layer 51, and the gate layer 52 fills the shallow trench isolation 3. Next, the gate insulating layer 51 and the gate layer 52 are etched to form a gate structure 5, which includes the etched gate insulating layer 51 and the gate layer 52. The gate structure 5 is located on the channel region 23 between the source region 21 and the drain region 22. The gate structure 5 can also extend along the sidewall of the active region 2 to the bottom isolation layer 4. The sidewall of the active region 2 covered by the gate structure 5 is the sidewall between the source region 21 and the drain region 22, combined with... Figure 2b and Figure 2d As shown. The gate insulating layer 51 is located between the active region 2 and the gate layer 52, and is used to isolate the active region 2 and the gate layer 52.

[0089] Step 104: Form a hard insulating layer on the sidewall of the active region, so that the hard insulating layer covers the source region and the drain region.

[0090] In this embodiment of the invention, a portion of the sidewalls of the active region is covered by a gate structure. A hard insulating layer can be formed on the sidewalls of the active region not covered by the gate structure, such that the hard insulating layer covers at least the source and drain regions. The hard insulating layer and the hard mask layer can be made of the same material; for example, the material of the hard insulating layer can be silicon nitride (SiN).

[0091] When contact structures are subsequently formed on the source and drain regions, the contact structures are partially located on the source or drain regions and partially on the hard insulating layer, which will not cause the contact structures to collapse. This increases the connection window between the source and drain regions and improves the performance of the semiconductor device.

[0092] Furthermore, prior to the step of forming a hard insulating layer on the sidewall of the active region, the method further includes:

[0093] Sidewalls are formed on the sidewalls of the shallow trench isolation groove and the sidewalls of the gate structure.

[0094] exist Figure 2c On the basis of, such as Figure 2e As shown, sidewalls 6 are first formed on the inner surface (including sidewalls and bottom) of the shallow trench isolation trench 3, the outer surface (including sidewalls and top surface) of the gate structure 5, and the substrate 1. Then, the sidewalls 6 are etched so that the etched sidewalls 6 are located on the sidewalls of the shallow trench isolation trench 3 and the gate structure 5. The sidewalls 6 can be an ONO (silicon oxide-silicon nitride-silicon oxide) structure (not shown in the figure), meaning that the sidewalls 6 can include a silicon oxide layer on the sidewalls of the shallow trench isolation trench 3 and the gate structure 5, a silicon nitride layer on the surface of the silicon oxide layer, and another silicon oxide layer on the surface of the silicon nitride layer. The sidewalls 6 are used to protect the active region 2 and the gate structure 5.

[0095] Furthermore, prior to the step of forming a hard insulating layer on the sidewall of the active region, the method further includes:

[0096] An ohmic contact layer is formed on the source region, the drain region, and the gate structure.

[0097] like Figure 2e As shown, after sidewalls 6 are formed on the sidewalls of the shallow trench isolation trench 3 and the gate structure 5, an ohmic contact layer 7 is formed on the upper surface of the source region 21, the upper surface of the drain region 22, and the upper surface of the gate structure 5. The ohmic contact layer 7 is used to reduce the contact resistance between the source region 21, the drain region 22, and the gate structure 5 and their corresponding contact structures. The ohmic contact layer 7 forms ohmic contacts with the source region 21, the drain region 22, and the gate structure 5 so that the voltage drop at the contact point is sufficiently small when a voltage is applied to the source region 21, the drain region 22, and the gate structure 5, thereby reducing the impact on the electrical performance of the device. The material of the ohmic contact layer 7 can be nickel silicide (NiSi).

[0098] After forming the ohmic contact layer 7, a hard insulating layer 8 can be formed on the sidewall 20 of the active region 2, such that the hard insulating layer 8 at least covers the source region 21 and the drain region 22, as shown. Figure 2f As shown. Since the source region 21 and the drain region 22 are spaced apart in the active region 2, and the source region 21 and the drain region 22 are located at opposite ends of the active region 2, a portion of the sidewall of the active region 2 (i.e., the sidewall 20 of the active region 2) serves as the sidewall of the source region 21 and the drain region 22. The hard insulating layer 8 at least covers the sidewall 20 of the active region 2, so that the hard insulating layer 8 covers the source region 21 and the drain region 22 on the sidewall of the active region 2. When the sidewall of the active region 2 has a sidewall 6, the hard insulating layer 8 is formed on the surface of the sidewall 6.

[0099] In one embodiment, the hard insulating layer 8 may cover only the source region 21 and the drain region 22 on the sidewall 20 of the active region 2. The hard insulating layer 8 may not cover the other sidewalls of the active region 2 besides the sidewall 20 (the other sidewalls of the active region 2 include the sidewall between the source region 21 and the drain region 22). Figure 2f and Figure 2g As shown, Figure 2g for Figure 2f A cross-sectional schematic diagram at point C (dashed line). In another embodiment, the hard insulating layer 8 can completely cover the current structure, that is, the hard insulating layer 8 can cover all sidewalls of the active region 2, the upper surface of the bottom isolation layer 4, the upper surface of the source region 21, the upper surface of the drain region 22, and the sidewalls and upper surface of the gate structure 5, such as... Figure 2h and Figure 2i As shown, Figure 2i for Figure 2h A cross-sectional view at point D (dashed line). The hard insulating layer 8 completely covers the current structure, preventing moisture from entering the transistor during subsequent manufacturing processes.

[0100] Furthermore, the method also includes:

[0101] A first contact structure and a second contact structure are formed, wherein the first contact structure is connected to the source region and the second contact structure is connected to the drain region.

[0102] exist Figure 2i On the basis of, such as Figure 2jAs shown, after forming a hard insulating layer 8 (which covers the upper surface of the bottom isolation layer 4, all sidewalls of the active region 2, the upper surface of the source region 21, the upper surface of the drain region 22, and the sidewalls and upper surface of the gate structure 5), an insulating layer 9 is formed on the hard insulating layer 8, and the insulating layer 9 fills the shallow trench isolation trench 3. Then, a first contact structure 11 and a second contact structure 12 are formed that penetrate the insulating layer 9. The first contact structure 11 is connected to the upper surface of the source region 21, and the second contact structure 12 is connected to the upper surface of the drain region 22. It should be noted that when the hard insulating layer 8 also covers the upper surface of the source region 21 and the upper surface of the drain region 22, the first contact structure 11 and the second contact structure 12 also penetrate the hard insulating layer 8 on the source region 21 and the drain region 22, respectively. Figure 2j As shown. When an ohmic contact layer 7 is formed on the upper surface of the source region 21 and the upper surface of the drain region 22, the first contact structure 11 is connected to the source region 21 through the ohmic contact layer 7, and the second contact structure 12 is connected to the drain region 22 through the ohmic contact layer 7.

[0103] Since the hard insulating layer 8 is located on the sidewall of the active region 2 and covers the source region 21 and the drain region 22, even if the first contact structure 11 is slightly offset from the source region 21 (i.e., part of the first contact structure 11 is located on the source region 21 and part of it is located on the hard insulating layer 8), the first contact structure 11 will not collapse, thereby increasing the connection window of the source region 21. Similarly, even if the second contact structure 12 is slightly offset from the drain region 22 (i.e., part of the second contact structure 12 is located on the drain region 22 and part of it is located on the hard insulating layer 8), the second contact structure 12 will not collapse, thereby increasing the connection window of the drain region 22.

[0104] The semiconductor device fabrication method provided in this invention can first form a shallow isolation trench in a substrate, form a bottom isolation layer in the shallow isolation trench, and then form a gate structure, such that the gate structure is located on the channel region between the source region and the drain region in the substrate. Then, a hard insulating layer is formed on the sidewall of the active region, so that the hard insulating layer covers the source region and the drain region. When the contact structure is subsequently formed, even if the contact structure is partially located on the source region or the drain region and partially located on the hard insulating layer, the contact structure will not collapse, thereby increasing the connection window between the source region and the drain region and improving the performance of the semiconductor device.

[0105] This invention also provides a semiconductor device, such as... Figure 3 As shown, the semiconductor device includes a substrate 1, a bottom isolation layer 4, a gate structure 5, and a hard insulating layer 8.

[0106] The substrate 1 includes an active region 2, which comprises a source region 21, a channel region 23, and a drain region 22 connected in sequence. Figure 4As shown, the bottom isolation layer 4 is located on the bottom periphery of the active region 2, that is, the isolation layer 4 is arranged around the bottom of the active region 2.

[0107] The gate structure 5 is located on the channel region 23 between the source region 21 and the drain region 22. In some embodiments, the gate structure 5 may also extend along the sidewall of the active region 2 to the bottom isolation layer 4. The sidewall of the active region 2 covered by the gate structure 5 may be the sidewall between the source region 21 and the drain region 22.

[0108] Specifically, the gate structure 5 includes a gate insulating layer 51 and a gate layer 52 located on the gate insulating layer 51, such as Figure 3 As shown. The gate insulating layer 51 is used to isolate the gate layer 52 from the active region 2. The material of the gate insulating layer 51 can be silicon oxide, etc., and the material of the gate layer 52 can be polysilicon, etc.

[0109] In the active region 2, the source region 21, the drain region 22, and the gate layer 52 can form a transistor. The gate layer 52 in the transistor is located on the channel region 23 and extends along the sidewall of the active region 2, thereby reducing the area of ​​the transistor.

[0110] like Figure 4 As shown, the hard insulating layer 8 can be located on the sidewall of the active region 2, such that the hard insulating layer 8 at least covers the source region 21 and the drain region 22. The material of the hard insulating layer 8 and the hard mask layer can be the same, for example, the material of the hard insulating layer can be silicon nitride (SiN).

[0111] like Figure 3 As shown, the semiconductor device also includes a first contact structure 11 and a second contact structure 22. The first contact structure 11 is connected to the source region 21, and the second contact structure 12 is connected to the drain region 22. Since the hard insulating layer 8 is located on the sidewall of the active region 2 and covers both the source region 21 and the drain region 22, even if the first contact structure 11 is slightly offset from the source region 21 (i.e., partially on the source region 21 and partially on the hard insulating layer 8), it will not collapse, thus increasing the connection window of the source region 21. Similarly, even if the second contact structure 12 is slightly offset from the drain region 22 (i.e., partially on the drain region 22 and partially on the hard insulating layer 8), it will not collapse, thus increasing the connection window of the drain region 22.

[0112] The hard insulating layer 8 can cover the source region 21 and drain region 22 on the sidewalls of the active region 2, and can also cover the upper surface of the bottom isolation layer 4, all the sidewalls of the active region 2, the upper surface of the source region 21, the upper surface of the drain region 22, and the sidewalls and upper surface of the gate structure 5, such as... Figure 2j As shown, this is to prevent moisture generated during subsequent manufacturing processes from entering the transistor.

[0113] like Figure 2j As shown, the semiconductor device may further include a sidewall 6, located between the sidewall of the active region 2 and the hard insulating layer 8, and between the sidewall of the gate structure 5 and the hard insulating layer 8. The sidewall 6 is used to protect the active region 2 and the gate structure 5. The sidewall 6 can be an ONO (silicon oxide-silicon nitride-silicon oxide) structure (not shown in the figure).

[0114] The semiconductor device may further include an ohmic contact layer 7, which is located on the upper surface of the source region 21, the upper surface of the drain region 22, and the upper surface of the gate structure 5. When the hard insulating layer 8 extends to the upper surfaces of the source region 21, the drain region 22, and the gate structure 5, the ohmic contact layer 7 is located between the upper surface of the source region 21 and the hard insulating layer 8, between the upper surface of the drain region 22 and the hard insulating layer 8, and between the upper surface of the gate structure 5 and the hard insulating layer 8. The material of the ohmic contact layer 7 may be nickel silicide (NiSi).

[0115] The ohmic contact layer 7 is used to reduce the contact resistance between the source region 21, the drain region 22, and the gate structure 5 and the corresponding contact structures. When the semiconductor device includes the ohmic contact layer 7, the first contact structure 11 penetrates the hard insulating layer 8 and is connected to the source region 21 through the ohmic contact layer 7, and the second contact structure 12 penetrates the hard insulating layer 8 and is connected to the drain region 22 through the ohmic contact layer 7.

[0116] The ohmic contact layer 7 forms an ohmic contact with the source region 21, the drain region 22, and the gate structure 5 so that the voltage drop at the contact is small enough when a voltage is applied to the source region 21, the drain region 22, and the gate structure 5, thereby reducing the impact on the electrical performance of the device.

[0117] The semiconductor device provided in this embodiment of the invention first forms a shallow trench isolation trench in a substrate, forms a bottom isolation layer in the shallow trench isolation trench, and then forms a gate structure, such that the gate structure is located on the channel region between the source region and the drain region in the substrate. Then, a hard insulating layer is formed on the sidewall of the active region, so that the hard insulating layer covers the source region and the drain region. When the contact structure is subsequently formed, even if the contact structure is partially located on the source region or the drain region and partially located on the hard insulating layer, the contact structure will not collapse, thereby increasing the connection window between the source region and the drain region and improving the performance of the semiconductor device.

[0118] See Figure 5 This is a schematic diagram of the structure of the three-dimensional memory provided in an embodiment of the present invention.

[0119] like Figure 5As shown, the three-dimensional memory includes a memory array structure 100 and a peripheral structure 200. The memory array structure 100 can be a non-volatile memory array structure, such as NAND flash memory, NOR flash memory, etc.

[0120] Specifically, the memory array structure 100 may include a substrate 101 and a stacked layer 102 located on the substrate 101. The stacked layer 102 includes a plurality of vertically alternating gate layers 103 and interlayer insulating layers 104. Here, "vertical" refers to the direction perpendicular to the upper surface of the substrate 101. The number of stacked gate layers 103 and interlayer insulating layers 104 is not limited, for example, 48 layers, 64 layers, etc. The memory array structure 100 may also include a memory channel structure 105 that extends vertically through the stacked layer 102 and into the substrate 101. The memory channel structure 105 may include a vertically extending channel layer (not shown in the figure) and a memory dielectric layer (not shown in the figure) disposed around the periphery of the channel layer.

[0121] The peripheral structure 200 may include devices such as CMOS (Complementary Metal-Oxide-Semiconductor), SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), FPGA (Field Programmable Gate Array), CPU (Central Processing Unit), and Xpoint chip.

[0122] Specifically, the peripheral structure 200 may be located on the memory array structure 100, and the peripheral structure 200 may be connected to the memory array structure 100. The peripheral structure 200 may include the semiconductor devices in the above embodiments, which will not be described in detail here.

[0123] The storage array structure 100 and the peripheral structure 200 can also adopt other architectural forms. For example, the peripheral structure 200 is located below the storage array structure 100, i.e., the PUC (periphery under core array) architecture, or the peripheral structure 200 and the storage array structure 100 are set up side by side, i.e., the PNC (periphery near core array) architecture, etc. No specific limitation is made here.

[0124] The three-dimensional memory provided in this invention can first form a shallow trench isolation trench in a substrate, form a bottom isolation layer in the shallow trench isolation trench, and then form a gate structure, so that the gate structure is located on the channel region between the source region and the drain region in the substrate. Then, a hard insulating layer is formed on the sidewall of the active region, so that the hard insulating layer covers the source region and the drain region. When the contact structure is subsequently formed, even if the contact structure is partially located on the source region or the drain region and partially located on the hard insulating layer, the contact structure will not collapse, thereby increasing the connection window between the source region and the drain region and improving the performance of the three-dimensional memory.

[0125] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A method of fabricating a semiconductor device, wherein, The method comprises: forming a shallow trench isolation trench in a substrate, the substrate comprising an active region, the shallow trench isolation trench being located on a periphery side of the active region, the active region comprising a source region, a channel region and a drain region connected in sequence; forming a bottom isolation layer in the shallow trench isolation trench; forming a gate structure on the channel region; forming a side wall on a sidewall of the shallow trench isolation trench; forming an ohmic contact layer on an upper surface of the source region and an upper surface of the drain region; forming a hard insulation layer on a sidewall of the active region, the hard insulation layer covering the source region and the drain region, the hard insulation layer covering a surface of the side wall, and the ohmic contact layer and the side wall having part of the hard insulation layer therebetween; and forming a first contact structure and a second contact structure, the first contact structure connecting the source region, the second contact structure connecting the drain region, the first contact structure and the second contact structure partially penetrating through the hard insulation layer and partially being located on the hard insulation layer.

2. The method of manufacturing a semiconductor device according to claim 1, wherein The step of forming the bottom isolation layer in the shallow trench isolation trench comprises: filling a dielectric layer in the shallow trench isolation trench; etching the dielectric layer, so that the etched dielectric layer forms the bottom isolation layer.

3. The method of fabricating a semiconductor device according to Claim 1, wherein The step of forming the gate structure on the channel region comprises: forming a gate insulation layer on an inner surface of the shallow trench isolation trench and the substrate; forming a gate layer on the gate insulation layer; etching the gate insulation layer and the gate layer, so that the etched gate insulation layer and the gate layer form the gate structure on the channel region.

4. The method of fabricating a semiconductor device according to Claim 1, wherein The method further comprises: extending the hard insulation layer to the bottom isolation layer, the source region, the drain region and the gate structure.

5. The method of fabricating a semiconductor device according to Claim 1, wherein Before the step of forming the hard insulation layer on the sidewall of the active region, the method further comprises: forming a side wall on a sidewall of the gate structure, the side wall comprising a laminated structure of silicon nitride and silicon oxide, and a material of the hard insulation layer comprising silicon nitride.

6. The method of fabricating a semiconductor device according to Claim 1, wherein Before the step of forming the hard insulation layer on the sidewall of the active region, the method further comprises: forming an ohmic contact layer on the gate structure.

7. A semiconductor device, wherein, The method comprises: an active region comprising a source region, a channel region and a drain region connected in sequence; a bottom isolation layer located on a periphery side of the active region; a gate structure, the gate structure being located on the channel region; an ohmic contact layer located on an upper surface of the source region and an upper surface of the drain region; a hard insulation layer located on a sidewall of the active region, the hard insulation layer covering the source region and the drain region; a side wall located between the sidewall of the active region and the hard insulation layer, the hard insulation layer covering a surface of the side wall, and the ohmic contact layer and the side wall having part of the hard insulation layer therebetween; and a first contact structure and a second contact structure, the first contact structure connecting the source region, the second contact structure connecting the drain region, the first contact structure and the second contact structure partially penetrating through the hard insulation layer and partially being located on the hard insulation layer.

8. The semiconductor device of claim 7, wherein, The gate structure comprises a gate insulation layer and a gate layer located on the gate insulation layer.

9. The semiconductor device of claim 7, wherein, The hard insulation layer is also on the bottom isolation layer, the source region, the drain region, and the gate structure.

10. The semiconductor device of claim 9, wherein, The semiconductor device further includes: An ohmic contact layer between the gate structure and the hard insulation layer.

11. The semiconductor device of claim 7, wherein, The semiconductor device further includes: A sidewall on a sidewall of the gate structure, the sidewall including a stack structure of silicon nitride and silicon oxide, a material of the hard insulation layer including silicon nitride.

12. The semiconductor device of claim 7, wherein, The gate structure also extends along a sidewall of the active region onto the bottom isolation layer.

13. A three-dimensional memory, wherein, A memory array structure and a peripheral structure connected to the memory array structure; The peripheral structure includes a semiconductor device; The semiconductor device includes: An active region including a source region, a channel region, and a drain region connected in sequence; A bottom isolation layer on a side of the active region; A gate structure on the channel region; An ohmic contact layer on an upper surface of the source region and an upper surface of the drain region; A hard insulation layer on a sidewall of the active region, the hard insulation layer covering the source region and the drain region; A sidewall between the sidewall of the active region and the hard insulation layer, a surface of the sidewall being covered by the hard insulation layer, and the ohmic contact layer having a portion of the hard insulation layer between the sidewall; and A first contact structure connected to the source region and a second contact structure connected to the drain region, the first and second contact structures partially penetrating the hard insulation layer and partially on the hard insulation layer.

14. The three-dimensional memory of Claim 13 wherein, The hard insulation layer is also on the bottom isolation layer, the source region, the drain region, and the gate structure.

15. The three-dimensional memory of Claim 14, wherein, The semiconductor device further includes: An ohmic contact layer between the gate structure and the hard insulation layer.

16. The three-dimensional memory of Claim 13 wherein, The semiconductor device further includes: A sidewall on a sidewall of the gate structure, the sidewall including a stack structure of silicon nitride and silicon oxide, a material of the hard insulation layer including silicon nitride.

17. The three-dimensional memory of Claim 13 wherein, The gate structure also extends along a sidewall of the active region onto the bottom isolation layer.

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