Alignment carrier for interconnect bridge assembly

Abstract

An alignment carrier, assembly and method for achieving precise alignment and assembly of two or more semiconductor dies using an interconnect bridge. The alignment carrier includes a substrate composed of a material having a thermal expansion coefficient substantially matching that of the interconnect bridge. The alignment carrier also includes a plurality of solder balls located on the substrate and configured to align the two or more semiconductor dies.

Description

Background Art

[0001] The present invention relates to semiconductor technology, and more particularly to the alignment and assembly of two or more semiconductor dies using an interconnect bridge.

[0002] Semiconductor dies (i.e., chips) have continued to become more complex and grow in size. This has resulted in lower yield semiconductor dies since the defect density remains the same, but the semiconductor die size has a greater chance of being affected by random defects. To reduce yield losses, semiconductor dies are scaling in size, but now need to have a larger number of input / outputs (I / O) to communicate between chips at a fast enough rate.

[0003] In order to achieve fast communication between semiconductor dies, wiring sizes that can be achieved in semiconductor manufacturing are required. Interconnect bridges, such as silicon (Si) bridges, have been tried in the past. However, the interconnect bridges of the prior art may cause significant challenges in assembly. For example, multiple interconnect bridges are usually required to assemble multiple semiconductor dies. This makes it difficult to align the interconnect bridge areas between semiconductor dies and attach the interconnect bridges to multiple semiconductor dies during assembly.

[0004] Since the interconnect bridge connection area can be plated first and the large bump area can be plated second, there is typically some misalignment between the low density interconnect (LDI) area and the high density interconnect (HDI) area of ​​the semiconductor die due to this two-step plating process. This makes the alignment of using large pitch controlled collapse chip connection (C4) solder in the interconnect bridge less than ideal. At the same time, it is necessary to handle properly aligned semiconductor dies with very thin interconnect bridges attached.

[0005] Therefore, there is a need to provide alignment and assembly of two or more semiconductor dies using an interconnect bridge that avoids the problems discussed above. Summary of the invention

[0006] The present invention provides an alignment carrier, assembly and method that can accurately align and assemble two or more semiconductor dies using an interconnect bridge, avoiding the above-mentioned problems.

[0007] In one aspect of the present invention, an alignment carrier is provided that can be used to align and assemble two or more semiconductor dies (i.e., chips) using an interconnect bridge. In one embodiment, the alignment carrier includes a substrate having a coefficient of thermal expansion (CTE) that substantially matches the interconnect bridge. The alignment carrier also includes a plurality of solder balls, which are located on a surface of the substrate and are configured to align the two or more semiconductor dies. In an embodiment, the solder balls present on the substrate of the alignment carrier are formed in positions corresponding to the peripheral regions of each semiconductor die that will subsequently be aligned therewith.

[0008] In some embodiments, and when the interconnect bridge is composed of silicon, the substrate is composed of silicon or glass. In some embodiments, the solder balls of the alignment carrier are located on a surface of the substrate that corresponds to the corners of each semiconductor die in the semiconductor die to be aligned. In some embodiments, the alignment carrier includes a window (i.e., an opening) that is located in a central area of ​​the substrate. In such embodiments, the window is configured for placement and access of the interconnect bridge. The presence of the window provides access to a high density interconnect (HDI) area of ​​the semiconductor die for interconnect bridge placement.

[0009] In some embodiments, a plurality of solder balls present on the substrate are larger in size than solder balls present in a low density interconnect (LDI) region of two or more semiconductor dies. This size difference in the solder balls allows solder balls present on the substrate of the alignment carrier to contact sacrificial bonding pads located at a peripheral region of the semiconductor die without allowing solder balls present on the semiconductor die to contact the alignment carrier. In some embodiments, each solder ball of the plurality of solder balls is a controlled collapse chip connection (C4) solder ball.

[0010] In another aspect of the present invention, an assembly is provided. In one embodiment, the assembly includes a first semiconductor die, a first solder ball, and a first bonding pad, the first semiconductor die including a plurality of first sacrificial bonding pads located at a peripheral region of the first semiconductor die, the first solder ball being located in a low density interconnect (LDI) region of the first semiconductor die, and the first bonding pad being located in a high density interconnect (HDI) region of the first semiconductor die. A second semiconductor die is positioned laterally adjacent to the first semiconductor die and includes a plurality of second sacrificial bonding pads located at a peripheral region of the second semiconductor die, a second solder ball located in the LDI region of the second semiconductor die, and a second bonding pad located in the HDI region of the second semiconductor die.

[0011] The assembly further includes an alignment carrier including a substrate having a thermal expansion coefficient substantially matching that of the interconnect bridge, and a plurality of solder balls on the substrate corresponding to peripheral regions of the first semiconductor die and the second semiconductor die being aligned. According to an embodiment, a first plurality of solder balls on the substrate are aligned with and in contact with a plurality of first sacrificial bonding pads at the peripheral region of the first semiconductor die, and a second plurality of solder balls on the substrate are aligned with and in contact with a plurality of second sacrificial bonding pads at the peripheral region of the second semiconductor die.

[0012] In some embodiments, the alignment carrier includes a window present in a central region of the substrate, the window corresponding to the HDI region of the first semiconductor die and the HDI region of the second semiconductor die, thereby allowing proximity to the placement of the interconnect bridge. In some embodiments, the interconnect bridge present in the assembly is composed of silicon, and the substrate of the alignment carrier is composed of silicon or glass. In some embodiments, a plurality of first sacrificial bonding pads are located at each corner of the first semiconductor die, and a plurality of second sacrificial bonding pads are located at each corner of the second semiconductor die. In some embodiments, the size of the plurality of solder balls of the alignment carrier is larger than the solder balls present in the first LDI region of the first semiconductor die and the second LDI region of the second semiconductor die. In some embodiments, a backing structure can be attached to the back side of the first semiconductor die and the second semiconductor die.

[0013] In some embodiments, there is an interconnect bridge across the first semiconductor die and the second semiconductor die in the assembly.In an embodiment, the interconnect bridge connects the HDI region of the first semiconductor die to the HDI region of the second semiconductor die.

[0014] In another aspect of the present invention, a method for aligning and assembling two or more semiconductor dies (i.e., semiconductor chips) using an interconnect bridge is provided. In a first embodiment, the method includes providing a first assembly, the first assembly including a first semiconductor die, a second semiconductor die positioned laterally adjacent to the first semiconductor die, and an alignment carrier. The first semiconductor die includes a plurality of first sacrificial bonding pads located at a peripheral region of the first semiconductor die, a first solder ball located in a low density interconnect (LDI) region of the first semiconductor die, and a first bonding pad located in a high density interconnect (HDI) region of the first semiconductor die. The second semiconductor die includes a plurality of second sacrificial bonding pads located in a peripheral region of the second semiconductor die, a second solder ball located in an LDI region of the second semiconductor die, and a second bonding pad located in an HDI region of the second semiconductor die. The alignment carrier includes: a substrate having a thermal expansion coefficient substantially matching that of the interconnect bridge; and a plurality of solder balls located on the substrate corresponding to the peripheral regions of both the first semiconductor die and the second semiconductor die. In the first component, a first plurality of solder balls located on the substrate are aligned with and in contact with a first plurality of sacrificial bonding pads located at a peripheral region of a first semiconductor die, and a second plurality of solder balls located on the substrate are aligned with and in contact with a second plurality of sacrificial bonding pads located at a peripheral region of a second semiconductor die.

[0015] The method of the first embodiment also includes first attaching a backing structure to the back side of the first semiconductor die and the second semiconductor die. Next, removing the alignment carrier to provide a second assembly including the first semiconductor die, the second semiconductor die, and the backing structure. The method of the first embodiment continues by secondly attaching an interconnect bridge between the first semiconductor die and the second semiconductor die to provide a third assembly including the first semiconductor die, the second semiconductor die, the backing structure, and the interconnect bridge. In the third assembly, the interconnect bridge connects the HDI region of the first semiconductor die to the HDI region of the second semiconductor die. The method of the first embodiment continues by thirdly attaching the laminate to the third assembly.

[0016] In a second embodiment, the method includes providing a first assembly including a first semiconductor die, a second semiconductor die positioned laterally adjacent to the first semiconductor die, and an alignment carrier. The first semiconductor die includes a plurality of first sacrificial bonding pads located at a peripheral region of the first semiconductor die, a first solder ball located in a low density interconnect (LDI) region of the first semiconductor die, and a first bonding pad located in a high density interconnect (HDI) region of the first semiconductor die. The second semiconductor die includes a plurality of second sacrificial bonding pads located in a peripheral region of the second semiconductor die, a second solder ball located in an LDI region of the second semiconductor die, and a second bonding pad located in an HDI region of the second semiconductor die. The alignment carrier includes: a substrate having a thermal expansion coefficient substantially matching a thermal expansion coefficient of an interconnect bridge; a window located in a central portion of the substrate; and a plurality of solder balls located on the substrate corresponding to peripheral regions of both the first semiconductor die and the second semiconductor die. In the first component, a first plurality of solder balls located on the substrate are aligned with and in contact with a first plurality of sacrificial bonding pads located at a peripheral region of a first semiconductor die, and a second plurality of solder balls located on the substrate are aligned with and in contact with a second plurality of sacrificial bonding pads located at a peripheral region of a second semiconductor die.

[0017] The method of the second embodiment also includes forming an interconnection bridge through the window and across the first semiconductor die and the second semiconductor die to provide a second component including the first semiconductor die, the second semiconductor die, and the interconnection bridge, wherein the interconnection bridge connects the HDI area of ​​the first semiconductor die to the HDI area of ​​the second semiconductor die, and thereafter first attaching the backing structure to the back of the first semiconductor die and the second semiconductor die of the second component. Next, removing the alignment carrier to provide a third component including the first semiconductor die, the second semiconductor die, the interconnection bridge and the backing structure. The method of the second embodiment continues by secondly attaching the laminate to the third component.

[0018] A third embodiment is also provided that is similar to the second embodiment but does not attach a backing structure to the first semiconductor die and the second semiconductor die during the assembly process.

[0019] In any of the above method embodiments, a plurality of first sacrificial bonding pads are formed simultaneously with first bonding pads in the HDI region of the first semiconductor die, and a plurality of second sacrificial bonding pads are formed simultaneously with second bonding pads in the HDI region of the second semiconductor die. By forming the sacrificial bonding strips simultaneously with the bonding pads in the HDI region of the semiconductor die, aligning the HDI region of the semiconductor die no longer results in misalignment between the low density interconnect (LDI) region and the high density interconnect (HDI) region of the semiconductor die due to the two-step plating process. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a top view of an alignment carrier in an embodiment of the present invention.

[0021] Figure 2 is a top view of two semiconductor dies in an embodiment of the present invention.

[0022] Figure 3 is included to align and attach to Figure 1 Alignment of the carrier Figure 2 A cross-sectional view of a first assembly of two semiconductor dies.

[0023] Figure 4 yes Figure 3 A cross-sectional view of the first assembly after first attaching the backing structure to the back sides of the first and second dies.

[0024] Figure 5 yes Figure 4 A cross-sectional view of a first assembly after removing the alignment carrier to provide a second assembly including the first and second dies and the backing structure.

[0025] Figure 6 yes Figure 5 A cross-sectional view of a second assembly after attaching an interconnect bridge between the first and second dies to provide a third assembly including the first and second dies, a backing structure, and an interconnect bridge, wherein the interconnect bridge connects a high-density interconnect region of the first die to a high-density interconnect region of the second die.

[0026] Figure 7 is after the laminate is thirdly attached to the third component to provide a fourth component Figure 6 A cross-sectional view of a third component.

[0027] Figure 8 After performing the bottom fill and removing the backing structure Figure 7 A cross-sectional view of a fourth component.

[0028] Fig. 9 is a cross-sectional view of a first assembly including a first semiconductor die, a second semiconductor die positioned laterally adjacent to the first die, and an alignment carrier including a window in another embodiment of the present invention.

[0029] Fig.10 yes Fig. 9 A cross-sectional view of a first assembly after forming an interconnect bridge through the window and spanning the first and second dies to provide a second assembly including the first and second dies and the interconnect bridge, wherein the interconnect bridge connects a high-density interconnect region of the first die to a high-density interconnect region of the second die.

[0030] Fig.11 After first attaching the backing structure to the backsides of the first and second dies of the second assembly Fig.10 A cross-sectional view of a second component.

[0031] Fig.12 after removing the alignment carrier to provide a third assembly including the first and second dies, the interconnect bridge, and the backing structure Fig.11 A cross-sectional view of a second component.

[0032] Fig.13 is after the laminate is secondly attached to the third component to provide a fourth component Fig.12 A cross-sectional view of a third component.

[0033] Fig.14 After performing the bottom fill and removing the backing structure Fig.13 A cross-sectional view of a fourth component.

[0034] Fig.15 is a cross-sectional view of a first assembly including a first semiconductor die, a second semiconductor die positioned laterally adjacent to the first die, and an alignment carrier including a window in yet another embodiment of the present invention.

[0035] Fig.16 After forming an interconnect bridge through the window and across the first and second dies to provide a second assembly including the first and second dies and the interconnect bridge Fig.15 A cross-sectional view of a first assembly of FIG. 1 , wherein an interconnect bridge connects a high density interconnect region of a first die to a high density interconnect region of a second die.

[0036] Fig.17 after removing the alignment carrier to provide a third assembly including the first die and the second die and the interconnect bridge Fig.16 A cross-sectional view of a second component.

[0037] Fig.18After attaching the laminate to the third component to provide the fourth component and after performing the underfill Fig.17 A cross-sectional view of a third component. DETAILED DESCRIPTION

[0038] Embodiments of the present invention will now be described in more detail with reference to the following discussion and accompanying drawings. It should be noted that the accompanying drawings are provided for illustrative purposes only and, therefore, are not drawn to scale. It should also be noted that similar and corresponding elements are referred to by similar reference numerals.

[0039] In the following description, many specific details are set forth, such as specific structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments. However, it will be appreciated by those of ordinary skill in the art that the various embodiments may be implemented without these specific details. In other cases, well-known structures or processing steps are not described in detail in order to avoid obscuring the present invention.

[0040] It will be understood that when an element as a layer, region, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly on" or "directly on" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "under" or "beneath" another element, it can be directly under or beneath the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly under" or "directly beneath" another element, there are no intervening elements.

[0041] First reference Figure 1 , the alignment carrier 10 is used for precise alignment and assembly of semiconductor dies. The alignment carrier 10 includes a substrate 12, which includes a plurality of solder balls 14 located on a surface of the substrate 12. In an embodiment, the solder balls are configured for alignment of two or more semiconductor dies. It is noteworthy that the solder balls 14 present on the substrate 12 are located in an area of ​​the substrate 12 corresponding to a peripheral area of ​​each semiconductor die aligned therewith. "Peripheral area" refers to an area of ​​a material located away from a central (or middle) area of ​​the material; the peripheral area of ​​the material is typically close to the edge of the material. In some embodiments, a plurality of solder balls 14 are located in an area on the substrate 12 corresponding to each corner of a semiconductor die to be subsequently aligned.

[0042] The substrate 12 providing the alignment carrier 10 has a coefficient of thermal expansion (CTE) that substantially matches that of the interconnect bridge; CTE is a measure of the change in length of a material in response to a change in the material's temperature. "Substantially matching" means that the substrate 12 has a CTE that differs from the CTE of the interconnect bridge by ±10%, preferably ±5%, and more preferably ±2. The substantial matching of the CTE of the substrate 12 with the interconnect bridge reduces misalignment during die assembly. The term "interconnect bridge" is used herein to refer to a structure used during die assembly to connect a high density interconnect (HDI) region of one semiconductor die to an HDI region of another semiconductor die.

[0043] In one embodiment, and when the interconnect bridge is composed of silicon (Si), substrate 12 is composed of silicon or glass. Other materials for substrate 12 may be used, as long as the material selected for substrate 12 has a CTE that substantially matches the CTE of the interconnect bridge.

[0044] In some embodiments, window 16 (i.e., opening) is located in the central region of substrate 12 and is configured for placement and access of an interconnect bridge. When window 16 is present, window 16 can be formed by photolithography and etching. Window 16 extends completely through substrate 12. Window formation can occur before or after solder ball 14 is formed. Window 16 is designed to have a size larger than the size of the interconnect bridge.

[0045] In some embodiments, the plurality of solder balls 14 present on the substrate 12 have a size greater than that of the solder balls present in the LDI region of the semiconductor die. The plurality of solder balls 14 present on the substrate 12 may be composed of any conventional solder ball material. The solder ball material may contain lead or may be lead-free. In some embodiments, each of the plurality of solder balls 14 is a controlled collapse chip connection (C4) solder ball. In other embodiments, the solder ball 14 may be composed of a low temperature (150° C. or lower) solder. The solder balls 14 present on the substrate 12 may be formed using conventional techniques well known to those skilled in the art. In some embodiments, the solder balls 14 may be formed directly on the surface of the substrate 12. In other embodiments (not shown), the solder balls 14 may be formed on a bonding pad, such as, for example, an under-bump metallization (UBM) bonding pad.

[0046] See now Figure 2 , Figure 2A first semiconductor die 50L and a second semiconductor die 50R are shown. The first and second dies (50L, 50R) include materials and components known to those skilled in the art. The first and second dies (50L, 50R) can be formed using techniques known to those skilled in the art. In order not to obscure any aspect of the present invention, details about the materials / components of the dies and methods for forming them are not provided herein. Note that although two dies are described and shown, multiple dies may be used.

[0047] The first die 50L includes a plurality of first sacrificial bonding pads 52L at a peripheral region of the first die 50L, first solder balls 54L in a low density interconnect (LDI) region of the first die 50L, and first bonding pads 56L in a high density interconnect (HDI) region of the first die 50L.

[0048] The second die 50R includes a plurality of second sacrificial bonding pads 52R located at a peripheral region of the second die 50R, second solder balls 54R located at an LDI region of the second die 50R, and second bonding pads 56R located at an HDI region of the second die 50R.

[0049] The term "LDI region" is used herein to refer to a region of a semiconductor die where solder joints (54L, 54R) are present and those solder balls (54L, 54R) are spaced apart from each other. In some embodiments, the spacing between each solder ball (54L, 54R) present in the LDI region may be from 100 microns to 200 microns.

[0050] The term "HDI region" refers to a region of the semiconductor die where bonding pads (56L, 56R) are present and are spaced apart from each other. In some embodiments, the spacing between each bonding pad (56L, 56R) present in the HDI region may be 10 microns to 100 microns.

[0051] The sacrificial bonding pads (52L, 52R) are dummy features of the die (50L, 50R) for alignment purposes. That is, the sacrificial bonding pads (52L, 52R) can be bonded to the solder balls 14 located on the substrate 12 that provides the alignment carrier 10. The die (50L, 50R) will be aligned to each other using the self-centering feature of mass reflow. The term "self-centering" refers to the wetting force combined with the surface tension of the solder balls that pulls the components into the correct position on the bonding pads during the solder reflow process. This allows for proper alignment of the HDI areas of the die (50L, 50R) that need to have interconnect bridges attached.

[0052] In some embodiments, sacrificial bonding pads (52L, 52R) are present at the corners of each of the dies (50L, 50R). The corner placement of the sacrificial bonding pads (52L, 52R) does not interfere with the LDI or HDI regions of the dies (50L, 50L) and, in some cases, provides optimal alignment. The spacing between each sacrificial bonding pad (52L, 52R) located at the peripheral region of the dies (50L, 50R) can be from 100 microns to 400 microns.

[0053] In an embodiment, a plurality of first sacrificial bonding pads 52L are formed simultaneously with first bonding pads 56L in the HDI region of the first die 50L, and a plurality of second sacrificial bonding pads 52R are formed simultaneously with second bonding pads 56R in the HDI region of the second die 50R. By forming the sacrificial bonding pads (52L, 52R) simultaneously with the bonding pads (56L, 56R) in the HDI region of the die, misalignment between the LDI region and the HDI region of the die due to the two-step plating process is avoided. In the case where interconnect bridge placement requires the formation of features for HDI region alignment during the patterning of the LDI region of the die, misalignment between the patterning of the LDI region and the HDI region may introduce alignment errors.

[0054] In some embodiments, sacrificial bonding pads (52L, 52R) may have the same size as bonding pads (56L, 56R). In other embodiments, sacrificial bonding pads (52L, 52R) may have a size that is larger than the size of bonding pads (56L, 56R). In one example, sacrificial bonding pads (52L, 52R) are 2 times larger than bonding pads (56L, 56R).

[0055] The sacrificial bonding pads (52L, 52R) and the bonding pads (56L, 56R) can be composed of any conventional bonding pad material (e.g., copper) or bonding pad material stack. The sacrificial bonding pads (52L, 52R) and the bonding pads (56L, 56R) can be formed by depositing a bonding pad material or a bonding material stack and then subjecting the deposited layers to a patterning process. Likewise, the sacrificial bonding pads (52L, 52R) and the bonding pads (56L, 56R) present in the HDI region of the semiconductor die (50R, 50L) are formed simultaneously.

[0056] The solder balls (54L, 54R) present in the LDI region of the tube core (50L, 50R) are composed of any conventional solder ball material. The solder balls (54L, 54R) can be the same in composition or different in composition from the solder balls 14. In some embodiments, the solder balls (54L, 54R) present in the LDI region of the tube core (50L, 50R) are controlled collapse chip connection (C4) solder balls. The solder balls (54L, 54R) present in the LDI region of the tube core (50L, 50R) can be formed using conventional techniques known to those skilled in the art. The solder balls (54L, 54R) present in the LDI region of the tube core (50L, 50R) are typically smaller than the size of the multiple solder balls 14 present on the substrate 12 of the alignment carrier 10. The smaller size of the solder balls (54L, 54R) compared to the solder balls 14 prevents the solder balls (54L, 54R) from undesirably interfering with the alignment carrier 10 in the LDI region of the die.

[0057] Now refer to Figures 3 to 8 , which shows the method in the first embodiment. In the first embodiment, first provide Figure 3 The first assembly A1 shown in FIG. The first assembly includes a first semiconductor die 50L, a second semiconductor die 50R and an alignment carrier 10. Note that the alignment carrier 10 of this embodiment does not include a window 16. Then, as shown in FIG. Figure 4 The backing structure 100 is shown attached to the tube core (50L, 50R) of the first assembly A1. Figure 5 As shown, the alignment carrier 10 is removed to provide a second assembly A2 including the first die 50L, the second die 50R and the backing structure 100. The interconnect bridge 102 is then attached between the first die 50L and the second die 50R to provide a third assembly A3, as shown in FIG. Figure 6 As shown. The third assembly A3 includes a first die 50L, a second die 50R, a backing structure 100, and an interconnection bridge 102. In an embodiment, the interconnection bridge 102 connects the HDI region of the first die 50L to the HDI region of the second die 50R. Next, as shown Figure 7 The laminate 104 shown is attached to the third assembly A3 to provide the fourth assembly A4. Figure 8 The bottom is filled with epoxy resin 106 as shown. In some embodiments, and as Figure 8 As shown, the backing structure 100 can be removed from the assembly. The method of the first embodiment will now be described in more detail.

[0058] First reference Figure 3 , showing that including Figure 2 A first assembly A1 of two semiconductor dies (50L, 50R) aligned and attached to Figure 2The alignment carrier 10 has no window 16. In an embodiment, the first assembly A1 can be formed by bringing two tube cores (50L, 50R) into close contact with the alignment carrier so that a first plurality of solder balls 14X located on the substrate 12 are aligned and contacted with the plurality of first sacrificial bonding pads (not shown for clarity) located at the peripheral area of ​​the first tube core 50L, and a second plurality of solder balls 14Y on the substrate 12 are aligned and contacted with the plurality of second sacrificial bonding pads (not shown for clarity) located at the peripheral area of ​​the second tube core 50R. The solder balls 14X, 14Y correspond to Figure 1 The solder ball 14.

[0059] A mass reflow anneal may then be performed to bond the die (50L, 50R) to the alignment carrier 10. The die (50L, 50R) will be aligned to each other using the self-centering features of the mass reflow, as described above. The mass reflow may be performed using conditions well known to those skilled in the art. In one example, the mass reflow may be performed at a peak temperature of 235°C to 255°C.

[0060] See now Figure 4 , showing the backing structure 100 after first attaching it to the backside of the first die 50L and the second die 50R Figure 3 In an embodiment, the backside of the first and second dies (50L, 50R) is a surface opposite to a surface including sacrificial bonding pads (52L, 52R), solder balls (54L, 54R) and bonding pads (56L, 56R).

[0061] The backing structure 100 can be made of any material having a CTE that substantially matches the CTE of the tube core, and such materials are well known to those skilled in the art, including, for example, silicon, glass, or silicon carbide. In one embodiment, the backing structure 100 can be attached to the back of the first and second tube cores (50L, 50R) using a high temperature (greater than 260°C) reprocessable tape or liquid adhesive. In such an embodiment, the backing structure 100 can be a temporary structure that can be subsequently removed during the assembly process. In other embodiments, if the backing structure 100 is made of a material that provides minimal impact on the final assembly, the backing structure 100 can be a permanent structure. The possible impact on the final assembly can be a combination of mechanical and thermal.

[0062] See now Figure 5 , showing the alignment carrier 10 after removal Figure 4The first assembly A1 is reflowed to provide a second assembly A2 including a first die 50L, a second die 50R, and a backing structure 100. In some embodiments, the alignment carrier 10 can be removed by remelting the solder joint formed by the mass reflow described above. In such an embodiment, the structure can be heated to a temperature that melts the solder joint so that the alignment carrier 10 is separated from the second assembly A2. In another embodiment, the alignment carrier 10 can be removed by mechanical shearing. In such an embodiment, a force can be applied that disconnects the sacrificial bonding pads (52L, 52R) from the die (50L, 50R) so that the solder balls (14X, 14Y) remain on the alignment carrier 10 and are not transferred to the die (50L, 50R).

[0063] See now Figure 6 , showing after the second attachment interconnect bridge 102 between the first die 50L and the second die 50R Figure 5 The second component A2 is used to provide a third component A3. Figure 6 The third component A3 shown in FIG. Figure 5 The second assembly shown in FIG. 5 is rotated 180°. The third assembly A3 includes the first die 50L, the second die 50R, the backing structure 100, and the interconnection bridge 102. In an embodiment, the interconnection bridge 102 connects the HDI region of the first die 50L to the HDI region of the second die 50R.

[0064] In one embodiment, the interconnect bridge 102 is made of silicon. Other materials besides silicon, such as glass, can be used as the interconnect bridge 102. In a first embodiment, the interconnect bridge 102 can be attached using thermal compression bonding (TCB). TCB allows copper-to-copper bonding and the use of thin (less than 50 microns) interconnect bridges 102.

[0065] Reference now Figure 7 , showing after the laminate 104 is thirdly attached to the third component A3 Figure 6 The third component A3. Figure 7 The third component A3 shown is from Figure 6 The third assembly is shown rotated 180°. The laminate 104 comprises materials well known to those skilled in the art. For example, the laminate 104 may comprise a circuit board made of a layer of insulating material and copper wiring. The laminate 104 may be attached to the substrate by performing mass reflow as described above. Figure 6 During the mass reflow process, the solder balls (52L, 52R) reflow and are bonded to the laminate 104. Figure 6 A solder joint is formed between the third component A3. Figure 7The assembly shown is a fourth assembly, which includes the first die 50L, the second die 50R, the backing structure 100, the interconnect bridge 102, and the laminate 104. In some embodiments, the fourth assembly A4 is the final assembly of the present invention.

[0066] See now Figure 8 , showing the bottom filling and removal of the backing structure 100 after Figure 7 In some embodiments, the step of removing the backing structure 100 is not performed.

[0067] The underfill process includes forming an underfill epoxy resin in the space between the laminate 104, the first and second semiconductors (50L, 50R) and the interconnect bridge 102 of the fourth component A4. To ensure that the space is completely filled with the underfill epoxy resin, the fourth component is usually heated to enhance the flow of the underfill epoxy resin and initiate curing. Figure 8 , element 106 represents the hardened underfill epoxy.

[0068] In some embodiments, the backing structure 100 can be removed from the final assembly using techniques known to those skilled in the art. In some embodiments, the removal of the backing structure 100 can be performed by a lift-off process.

[0069] Now refer to Figures 9 to 14 , which shows the method in the second embodiment. In the second embodiment, firstly provide Fig. 9 The first assembly A1 shown in FIG. The first assembly A1 includes a first semiconductor die 50L, a second semiconductor die 50R, and an alignment carrier 10 having a window 16 for bridge placement and alignment. Then, a bridge is formed through the window 16 of the alignment carrier 10. Fig.10 The interconnect bridge 102 shown in FIG. 1 and spans the first die 50L and the second die 50R to provide a second assembly A2 including the first die 50L, the second die 50R, and the interconnect bridge 102. In an embodiment, the interconnect bridge 102 connects the HDI area of ​​the first die 50L to the HDI area of ​​the second die 50R. The backing structure 100 is then attached to the back side of the first die 50R and the second die 50L of the second assembly A2. Next, and as shown in FIG. Fig.12 As shown, the alignment carrier 10 is removed to provide a third assembly A3 including the first die 50L, the second die 50R, the interconnect bridge 102 and the backing structure 100. Fig.13 The laminate 104 shown in FIG. 1 is attached to the third assembly to provide a fourth assembly A4. Fig.14 The bottom is filled with epoxy resin 106 as shown. In some embodiments, and as Fig.14 As shown, the backing structure 100 may be removed from the assembly. The method of the second embodiment will now be described in more detail.

[0070] First reference Fig. 9 , showing a first assembly A1, which includes aligning and attaching to Figure 1 The alignment carrier 10 having the window 16 Figure 2 In an embodiment, the first assembly A1 can be formed by bringing the two dies (50L, 50R) into close contact with an alignment carrier so that a first plurality of solder balls 14X located on the substrate 12 are aligned with and contacted with a plurality of first sacrificial bonding pads (not shown for clarity) located at a peripheral region of the first die 50L, and a second plurality of solder balls 14Y located on the substrate 12 are aligned with and contacted with the plurality of second sacrificial bonding pads (not shown for clarity) located at a peripheral region of the second die 50R. The solder balls 14X, 14Y correspond to Figure 1 The solder ball 14.

[0071] See now Fig.10 , showing after forming the interconnect bridge 102 through the window 16 of the alignment carrier 10 and spanning the first die 50L and the second die 50R Fig. 9 A first component A1 is provided to provide a second component A2. Fig.10 The second component A2 shown in FIG. Fig. 9 The first assembly shown in FIG. 1 is rotated 180°. The second assembly A2 includes the first die 50L, the second die 50R, and the interconnection bridge 102. In an embodiment, the interconnection bridge 102 connects the HDI region of the first die 50L to the HDI region of the second die 50R.

[0072] In one embodiment, the interconnect bridge 102 is made of silicon. Other materials besides silicon, such as glass, can be used as the interconnect bridge 102. In a second embodiment, the interconnect bridge 102 can be attached using a mass reflow process. During the mass reflow process, the die can be realigned and self-centered with the interconnect bridge 102. In a second embodiment, a window 16 present in the alignment carrier 10 allows access into the first assembly A1 for interconnect bridge 102 attachment.

[0073] See now Fig.11 , showing the backing structure 100 attached to the backside of the first die 50L and the second die 50R of the first assembly A2 after Fig.10 The second component A2. Fig.11 The second component A2 shown in FIG. Fig.10 The second assembly is shown rotated 180. The backing structure 100 of this embodiment is the same as in the previous embodiment.

[0074] See now Fig.12 , shows that after removing the alignment carrier 10 Fig.11The second assembly A2 is further modified to provide a third assembly A3 including the first die 50L, the second die 50R, the interconnect bridge 102 and the backing structure 100. Fig.12 The third component A3 shown in FIG. Fig.11 The second assembly shown in FIG. 1 is rotated 180°. The removal of the alignment carrier 10 used in the present embodiment may include a heating process or a mechanical shearing process as described above.

[0075] See now Fig.13 , showing after the laminate 104 is secondly attached to the third component A3 Fig.12 A third assembly A3 is provided. The laminate 104 includes one of the above materials. The laminate 104 can be attached to the third assembly using a mass reflow anneal as defined above for the previous attachment of the laminate 104. A fourth assembly A4 is provided, which includes the first die 50L, the second die 50R, the interconnect bridge 102, the backing structure 100, and the laminate 104. Fig.13 The fourth component A3 shown in FIG. Fig.12 The third component shown in FIG. 1 is rotated 180°.

[0076] See now Fig.14 , showing the bottom filling and removal of the backing structure 100 after Fig.13 In some embodiments, the step of removing the backing structure 100 is not performed.

[0077] The underfill process includes forming an underfill epoxy resin in the space between the laminate 104, the first and second semiconductors (50L, 50R) and the interconnect bridge 102 of the fourth component A4. To ensure that the space is filled with the underfill epoxy resin, the fourth component is usually heated to enhance the flow of the underfill epoxy resin and initiate the curing of the underfill epoxy resin. Fig.14 , element 106 represents the hardened underfill epoxy.

[0078] In some embodiments, the backing structure 100 can be removed from the final assembly using techniques known to those skilled in the art. In some embodiments, the removal of the backing structure 100 can be performed by a lift-off process.

[0079] Now refer to Figures 15 to 18 , showing a method according to a third embodiment. The third embodiment is similar to the second embodiment, except that no backing structure is used. In the third embodiment, first provide Fig.15 The first assembly A1 includes a first die 50L, a second die 50R, and an alignment carrier 10 having an alignment window 16. Then, a first assembly A1 is formed through the window 16 of the alignment carrier 10. Fig.16The interconnect bridge 102 shown crosses the first die 50L and the second die 50R to provide a second assembly A2 including the first die 50L, the second die 50R, and the interconnect bridge 102. In an embodiment, the interconnect bridge 102 connects the HDI region of the first die 50L to the HDI region of the second die 50R. Next, as shown in FIG. Fig.17 As shown, the alignment carrier 10 is removed to provide a third assembly A3 including the first die 50L, the second die 50R and the interconnect bridge 102. Fig.18 The laminate 104 shown is attached to the third assembly to provide a fourth assembly A4. Fig.18 The underfill is shown as epoxy 106 .

[0080] Although the present invention has been specifically shown and described with respect to its preferred embodiments, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made without departing from the scope of the present invention. Therefore, it is intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

[0081] In a preferred embodiment of the present invention, a method is now provided, the method comprising: providing a first component, the first component comprising a first semiconductor die, a second semiconductor die positioned laterally adjacent to the first semiconductor die, and an alignment carrier, wherein the first semiconductor die comprises a plurality of first sacrificial bonding pads located at a peripheral region of the first semiconductor die, a first solder ball located in a low density interconnect (LDI) region of the first semiconductor die, and a first bonding pad located in a high density interconnect (HDI) region of the first semiconductor die, the second semiconductor die comprises a plurality of second sacrificial bonding pads located at a peripheral region of the second semiconductor die, a second solder ball located in the LDI region of the second semiconductor die, and a second bonding pad located in the HDI region of the second semiconductor die, and the alignment carrier comprises: a substrate having a thermal expansion coefficient substantially matching that of an interconnect bridge; a window located in a central portion of the substrate, and a plurality of solder balls located on the substrate, wherein the first semiconductor die comprises a plurality of first sacrificial bonding pads located at a peripheral region of the first semiconductor die, a first solder ball located in a low density interconnect (LDI) region of the first semiconductor die, and a first bonding pad located in a high density interconnect (HDI) region of the first semiconductor die. The method further comprises: aligning and contacting a first group of the plurality of solder balls on the substrate, the plurality of first sacrificial bonding pads located at the peripheral region of the first semiconductor die, and a second group of the plurality of solder balls on the substrate, and aligning and contacting the plurality of second sacrificial bonding pads, the plurality of second sacrificial bonding pads located at the peripheral region of the second semiconductor die; forming the interconnect bridge through the window and across the first semiconductor die and the second semiconductor die to provide a second assembly including the first semiconductor die, the second semiconductor die, and the interconnect bridge, wherein the interconnect bridge connects the HDI region of the first semiconductor die to the HDI region of the second semiconductor die; first attaching a backing structure to the back side of the first semiconductor die and the second semiconductor die of the second assembly; removing the alignment carrier to provide a third assembly including the first semiconductor die, the second semiconductor die, the interconnect bridge, and the backing structure; and second attaching the laminate to the third assembly. The third attachment preferably includes mass reflow of the first and second solder balls. The plurality of first sacrificial bonding pads are preferably formed simultaneously with the first bonding pads in the HDI region of the first semiconductor die, and the plurality of second sacrificial bonding pads are formed simultaneously with the second bonding pads in the HDI region of the second semiconductor die.The method may further include removing the backing structure after second attaching the laminate.

[0082] In a preferred embodiment of the present invention described herein, a method is provided, comprising: providing a first component, the first component comprising a first semiconductor die, a second semiconductor die positioned laterally adjacent to the first semiconductor die, and an alignment carrier, wherein the first semiconductor die comprises a plurality of first sacrificial bonding pads located at a peripheral region of the first semiconductor die, a first solder ball located in a low density interconnect (LDI) region of the first semiconductor die, and a first bonding pad located in a high density interconnect (HDI) region of the first semiconductor die, the second semiconductor die comprises a plurality of second sacrificial bonding pads located in a peripheral region of the second semiconductor die, a second solder ball located in an LDI region of the second semiconductor die, and a second bonding pad located in an HDI region of the second semiconductor die, and the alignment carrier comprises: a substrate having a thermal expansion coefficient substantially matching that of an interconnect bridge; a window located at the substrate a central portion, and a plurality of solder balls on the substrate, wherein a first group of the plurality of solder balls on the substrate are aligned with and in contact with the plurality of first sacrificial bonding pads at the peripheral region of the first semiconductor die, and a second group of the plurality of solder balls on the substrate are aligned with and in contact with the plurality of second sacrificial bonding pads, the plurality of second sacrificial bonding pads being located at the peripheral region of the second semiconductor die; forming the interconnect bridge through the window and across the first semiconductor die and the second semiconductor die to provide a second assembly including the first semiconductor die, the second semiconductor die, and the interconnect bridge, wherein the interconnect bridge connects the HDI region of the first semiconductor die to the HDI region of the second semiconductor die; removing the alignment carrier to provide a second assembly including the first semiconductor die, the second semiconductor die, and the interconnect bridge; and attaching a laminate to the second assembly. The plurality of first sacrificial bonding pads are preferably formed simultaneously with the first bonding pads in the HDI region of the first semiconductor die, and the plurality of second sacrificial bonding pads are formed simultaneously with the second bonding pads in the HDI region of the second semiconductor die.

Claims

1. A component comprising: a first semiconductor die including a plurality of first sacrificial bonding pads located at a peripheral region of the first semiconductor die, first solder balls located in a low density interconnect (LDI) region of the first semiconductor die, and first bonding pads located in a high density interconnect (HDI) region of the first semiconductor die; a second semiconductor die positioned laterally adjacent to the first semiconductor die and comprising a plurality of second sacrificial bonding pads at a peripheral region of the second semiconductor die, second solder balls located in an LDI region of the second semiconductor die, and second bonding pads located in an HDI region of the second semiconductor die; as well as An alignment carrier, the alignment carrier comprising a substrate and a plurality of solder balls located on the substrate, wherein the substrate has a thermal expansion coefficient that matches the thermal expansion coefficient of the interconnect bridge, wherein a first group of the plurality of solder balls located on the substrate is aligned with and in contact with the plurality of first sacrificial bonding pads located at the peripheral area of ​​the first semiconductor tube core, and a second group of the plurality of solder balls located on the substrate is aligned with and in contact with the plurality of second sacrificial bonding pads located at the peripheral area of ​​the second semiconductor tube core, and wherein the size of the solder balls of the alignment carrier is larger than the first solder balls present in the LDI area of ​​the first semiconductor tube core and the second solder balls present in the LDI area of ​​the second semiconductor tube core. 2 . The assembly of claim 1 , further comprising a window located in a central portion of the substrate of the alignment carrier and configured to place the interconnect bridge.

3. The assembly of claim 2, further comprising the interconnect bridge spanning the first semiconductor die and the second semiconductor die, wherein The interconnect bridge connects the HDI region of the first semiconductor die to the HDI region of the second semiconductor die.

4. The assembly according to claim 3, wherein: The interconnect bridges consist of silicon, and the substrate of the alignment carrier consists of silicon or glass.

5. The assembly according to claim 1, wherein: The plurality of first sacrificial bond pads are located at each corner of the first semiconductor die, and the plurality of second sacrificial bond pads are located at each corner of the second semiconductor die. 6 . The assembly of claim 1 , further comprising a backing structure attached to the first semiconductor die and the second semiconductor die.

7. A method comprising: Providing a first component, the first component comprising a first semiconductor die, a second semiconductor die positioned laterally adjacent to the first semiconductor die, and an alignment carrier, wherein the first semiconductor die comprises a plurality of first sacrificial bonding pads located at a peripheral region of the first semiconductor die, a first solder ball located in a low density interconnect (LDI) region of the first semiconductor die, and a first bonding pad located in a high density interconnect (HDI) region of the first semiconductor die, the second semiconductor die comprises a plurality of second sacrificial bonding pads located at a peripheral region of the second semiconductor die, a second solder ball located in an LDI region of the second semiconductor die, and a second bonding pad located in an HDI region of the second semiconductor die, and the alignment carrier comprises a substrate having a thermal expansion coefficient matched to a thermal expansion coefficient of an interconnect bridge and a plurality of solder balls located on the substrate, wherein a first group of the plurality of solder balls located on the substrate are aligned with and in contact with the plurality of first sacrificial bonding pads located at the peripheral region of the first semiconductor die, and a second group of the plurality of solder balls located on the substrate are aligned with and in contact with the plurality of second sacrificial bonding pads located at the peripheral region of the second semiconductor die; attaching a backing structure to back sides of the first semiconductor die and the second semiconductor die; removing the alignment carrier to provide a second assembly including the first semiconductor die, the second semiconductor die, and the backing structure; attaching the interconnect bridge between the first semiconductor die and the second semiconductor die to provide a third assembly including the first semiconductor die, the second semiconductor die, the backing structure, and the interconnect bridge, wherein the interconnect bridge connects the HDI region of the first semiconductor die to the HDI region of the second semiconductor die; and A laminate is attached to the third component.

8. The method of claim 7, further comprising removing the backing structure from the third component.

9. The method according to claim 7, wherein: Attaching the laminate to the third assembly includes mass reflow of the first solder balls and the second solder balls.

10. The method according to claim 7, wherein: The plurality of first sacrificial bond pads are formed simultaneously with the first bond pads in the HDI region of the first semiconductor die, and the plurality of second sacrificial bond pads are formed simultaneously with the second bond pads in the HDI region of the second semiconductor die.

11. The method of claim 7, further comprising removing the backing structure after attaching the laminate to the third component.

Images