Semiconductor circuit devices

Abstract

The layout of the electrode pads (21a, 21b, 22, 23a, 23b) on the front side of the semiconductor chip (10) differs from that of at least one of the semiconductor chips (10) mounted on the insulating substrate (80), resulting in two or more patterns. The overall layout of the semiconductor chips (10) mounted on the insulating substrate (80), and the layout of the electrode pads (21a, 21b, 22, 23a, 23b) on the front side of the semiconductor chip (10) are determined in a manner that minimizes the length of the wiring (96) connecting the main semiconductor elements (11) in parallel, or in a manner that makes the resistive or reactive components of the wiring (96) approximately uniform among the same type of electrode pads (21b) of the multiple semiconductor chips (10) connected in parallel, or both. This allows for the suppression of vibrations in the current waveform between the semiconductor devices (20) fabricated from the multiple semiconductor chips (10).

Description

Technical Field

[0001] This invention relates to a semiconductor circuit device. Background Technology

[0002] Previously, power modules or intelligent power modules (IPMs) were used in inverter devices, uninterruptible power supply (UPS), machine tools, industrial robots, railway systems, railway vehicles (trolleybuses), hybrid electric vehicles (HEVs), and battery electric vehicles (BEVs).

[0003] A power module is an integrated circuit (IC) that integrates multiple electronic components and circuits, including a power semiconductor device, onto the same insulating substrate. An IPM (Integrated Circuit Panel) is an IC that integrates a power semiconductor device and its drive and protection circuitry onto the same insulating substrate. A power semiconductor device is a semiconductor device used for power control, controlling high voltage and / or high current to perform power conversion (converting physical quantities such as voltage, current, and frequency into other physical quantities) or rectification.

[0004] Power semiconductor devices include various types such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), which are used separately depending on their applications.

[0005] For example, compared to MOSFETs, although bipolar transistors or IGBTs have higher current densities and can operate at high currents, they cannot switch at high speeds. Specifically, for bipolar transistors, the operating limit is around a few kHz, and for IGBTs, the limit is around tens of kHz. On the other hand, compared to bipolar transistors or IGBTs, although MOSFETs have lower current densities and are difficult to operate at high currents, they can perform high-speed switching operations up to around a few MHz.

[0006] Silicon (Si) is used as a constituent material for power semiconductor devices. With strong market demand for power semiconductor devices that combine high current and high speed, IGBTs and MOSFETs are constantly being improved, and development has now reached almost the material's limits. Therefore, from the perspective of power semiconductor devices, alternative semiconductor materials to silicon are being discussed, and silicon carbide (SiC) is attracting attention as a semiconductor material capable of producing next-generation power semiconductor devices with low on-state voltage, high-speed characteristics, and excellent high-temperature performance.

[0007] Silicon carbide is a chemically very stable semiconductor material with a band gap of 3 eV, and it can be used as a semiconductor with extreme stability even at high temperatures. Furthermore, since the maximum electric field strength of silicon carbide is more than one digit greater than that of silicon, it is expected to be a semiconductor material that can significantly reduce on-resistance. Not only silicon carbide possesses these advantages, but all semiconductors with band gaps wider than silicon (hereinafter referred to as wide-bandgap semiconductors) also share these advantages.

[0008] Furthermore, with the increasing demand for high current, it is cost-effective to construct a trench gate structure where the power semiconductor device has a channel (inversion layer) formed along the sidewalls of the gate trench in a direction orthogonal to the front side of the semiconductor chip, compared to a planar gate structure where the device has a channel (inversion layer) formed along the front side of the semiconductor chip. This is because the trench gate structure increases the density of unit cells (the constituent units of the device) per unit area, thus increasing the current density per unit area.

[0009] As the current density per unit area increases, the rate of temperature rise corresponding to the volume occupied per unit cell also increases. Therefore, a double-sided cooling structure is required to improve discharge efficiency and stabilize reliability. Furthermore, a power semiconductor device with improved reliability is proposed by employing a high-functionality structure. This high-functionality structure arranges high-functionality components such as a current sensing unit, a temperature sensing unit, and an overvoltage protection unit on the same semiconductor chip as the main semiconductor element that performs the main operation of the power semiconductor device, serving as circuitry for protecting and controlling that main semiconductor element.

[0010] Taking an IPM (Insulating Device) formed by integrating multiple semiconductor chips with power semiconductor devices on an insulating substrate as an example, and the power semiconductor device having a main semiconductor element, a current sensing unit, and a temperature sensing unit on the same semiconductor chip, the structure of a conventional semiconductor circuit device will be explained. Figure 21 It is a schematic top view showing the layout of an existing semiconductor circuit device as seen from the front side of an insulating substrate. Figure 22 This is a schematic cross-sectional view illustrating the structure of an existing semiconductor circuit device. Figure 22 The middle shows Figure 21 The cross-sectional structure of the semiconductor circuit device 200.

[0011] Figure 21 , Figure 22 The existing semiconductor circuit device 200 shown includes a semiconductor chip 210, an insulating substrate 220, a printed circuit board 230, and external electrode terminals 228a and 228b. A copper (Cu) plate 222 and a heat sink 223 are respectively bonded to the two main surfaces of the insulating plate 221 of the insulating substrate 220. Multiple semiconductor chips 210 are mounted on the copper plate 222 of the insulating substrate 220. The semiconductor chips 210 are fabricated with a vertical MOSFET as the main semiconductor element, and a current sensing section and a temperature sensing section as high-functionality components.

[0012] All semiconductor chips 210 have the same configuration and are arranged in the same way with multiple electrode pads on the front side. The electrode pads on the front side of the semiconductor chip 210 are the electrode pads of the main semiconductor element (source pad 211a and gate pad 211b), the electrode pads of the current sensing part (hereinafter referred to as OC pad) 212, and the electrode pads of the temperature sensing part (anode pad 213a and cathode pad 213b). The electrode pads on the back side are the drain pads of the main semiconductor element and the current sensing part (not shown).

[0013] The layout of the electrode pads on the front side of the semiconductor chip 210, as viewed from the front side of the insulating substrate 220 (the main surface on the side of the copper plate 222), is the same in all (four in this case) semiconductor chips 210 mounted on the insulating substrate 220. For example, the gate pad 211b, OC pad 212, anode pad 213a, and cathode pad 213b are arranged in a row along one side of the generally rectangular planar shape of the semiconductor chip 210. The source pad 211a covers most of the front side of the semiconductor chip 210 and is opposite to all the other electrode pads 211b, 212, 213a, and 213b.

[0014] Multiple semiconductor chips 210 are arranged in a row at equal intervals. Viewed from the front of the insulating substrate 220, in one direction of the arrangement of the multiple semiconductor chips 210, the same metal pattern formed by multiple electrode pads on the front of each semiconductor chip 210 is repeatedly and regularly arranged according to the number of semiconductor chips 210, so that the orientation of all semiconductor chips 210 is uniform. On each semiconductor chip 210, multiple implanted pins (conductive pillars) 226 are bonded to the source pad 211a via a solder layer 225.

[0015] On each semiconductor chip 210, different implanted pins (conductive posts) 227 are respectively bonded to the gate pad 211b, OC pad 212, anode pad 213a, and cathode pad 213b. The implanted pins 226 and 227 penetrate the printed circuit board 230 facing the front side of the semiconductor chip 210 and are directly bonded to or electrically connected via a circuit pattern (not shown) to predetermined electrode pads formed on the main surface of the printed circuit board 230 on the opposite side to the semiconductor chip 210.

[0016] For example, each source pad 211a of all semiconductor chips 210 is electrically connected to a source pad 231a of the printed circuit board 230 via an implanted pin 226. The gate pad 211b, OC pad 212, anode pad 213a, and cathode pad 213b of semiconductor chips 210 are electrically connected to the gate pad 231b, OC pad 232, anode pad 233a, and cathode pad 233b of the printed circuit board 230 via different implanted pins 227.

[0017] The source pads 231a of the printed circuit board 230 are disposed in the printed circuit board 230 at positions, for example, opposite to the source pads 211a of all semiconductor chips 210. The gate pads 231b, OC pads 232, anode pads 233a and cathode pads 233b of the printed circuit board 230 are disposed in each semiconductor chip 210 mounted on the insulating substrate 220, and are disposed in the printed circuit board 230 at positions, for example, opposite to the semiconductor chip 210 to which they are connected.

[0018] exist Figure 21 In the diagram, source pads 211a and 231a, gate pads 211b and 231b, OC pads 212 and 232, anode pads 213a and 233a, and cathode pads 213b and 233b are represented as rectangles labeled S, G, OC, A, and K, respectively. Furthermore, to clarify the arrangement of the semiconductor chip 210, the portion with the source pad 231a of the printed circuit board 230 is shown on the upper side of the semiconductor chip 210, and the portion with electrode pads other than the source pad 231a is shown on the lower side of the semiconductor chip 210.

[0019] The gate pads 231b of the printed circuit board 230 are electrically connected to each other via wiring 234. The source pads 211a on the front side of the plurality of semiconductor chips 210 are electrically connected to the source pads 231a of the printed circuit board 230 via implanted pins 226, and the drain pads on the back side are bonded to the copper plate 222 of the insulating substrate 220 described later, thereby connecting the main semiconductor elements (MOSFETs) of the semiconductor device fabricated on the plurality of semiconductor chips 210 in parallel.

[0020] One end of the external electrode terminal 228a is bonded to the copper plate 222 on the front side of the insulating substrate 220. The electrode pads on the back side of the semiconductor chip 210 are bonded to the copper plate 222 on the front side of the insulating substrate 220 via the solder layer 224, and are electrically connected to the external electrode terminal 228a via the copper plate 222. One end of the external electrode terminal 228b is bonded to the circuit pattern (not shown) of the printed circuit board 230. The other ends of the external electrode terminals 228a and 228b protrude outward from the sealing material 229 described later.

[0021] The insulating substrate 220, semiconductor chip 210, implanted pins 226 and 227, printed circuit board 230, and external electrode terminals 228a and 228b are sealed by sealing material 229. The heat sink 223 of the insulating substrate 220 is bonded to a cooler (not shown) via thermal paste. When the semiconductor circuit device 200 operates, heat generated by the circuit patterns on the semiconductor chip 210 and / or printed circuit board 230 is conducted from the insulating substrate 220 to the cooler for heat dissipation, thereby cooling the semiconductor chip 210 and / or printed circuit board 230. Reference numeral 235 indicates a control unit that controls high-functionality components.

[0022] As a conventional semiconductor circuit device, a semiconductor module is proposed that mounts multiple semiconductor chips in a row on an insulating substrate, and connects semiconductor devices fabricated from these multiple semiconductor chips in parallel (for example, see Patent Document 1 and Patent Document 2 below). Patent Document 1 discloses that MOSFETs fabricated from multiple semiconductor chips using silicon carbide as the semiconductor material are connected in parallel via implanted pins. Patent Document 2 discloses that each semiconductor chip has multiple electrode pads.

[0023] Existing technical documents

[0024] Patent documents

[0025] Patent Document 1: Japanese Patent Application Publication No. 2017-005094

[0026] Patent Document 2: International Publication No. 2015 / 093169 Summary of the Invention

[0027] Technical issues

[0028] However, in existing semiconductor circuit devices 200 (refer to...) Figure 21 , 22In this process, if the number of main semiconductor devices (MOSFETs) connected in parallel increases with the increase in current, the number of semiconductor chips 210 mounted on the insulating substrate 220 increases. As a result, the mounting area (surface area) of the insulating substrate 220 increases, and the winding length of the wiring 234 used to connect the MOSFETs fabricated from the multiple semiconductor chips 210 arranged in a row in parallel increases.

[0029] Therefore, the more the number of main semiconductor elements connected in parallel increases, the more adversely the resistance (R) and / or reactance (L) components of wiring 234 are affected. For each MOSFET fabricated on each semiconductor chip 210, the voltage waveform 143 of the gate voltage Vg oscillates, and the gate threshold voltage Vth deviates. Consequently, for each MOSFET, the rising edge of the drain-source voltage Vds waveform during turn-off becomes different.

[0030] Because the rising edge of the drain-source voltage Vds during turn-off differs for each MOSFET fabricated on each semiconductor chip 10, the voltage waveform 142 of the drain-source voltage Vds during turn-off of the semiconductor circuit device 200 becomes prone to oscillation. Consequently, the current waveform 141 of the drain-source current Ids during turn-off of the semiconductor circuit device 200 also becomes prone to oscillation (see below). Figure 20 ).

[0031] When silicon carbide is used as the semiconductor material, the MOSFET is more susceptible to adverse effects from wiring 234 because it can also perform high-speed switching. This further increases the deviation of the rising edge of the voltage waveform 142 of the drain-source voltage Vds when each MOSFET fabricated in each semiconductor chip 210 is turned off. Consequently, the vibration of the current waveform 141 of the drain-source current Ids of the semiconductor circuit device 200 also increases.

[0032] Therefore, in order to suppress the vibration of the current waveform 141 of the drain-source current Ids of the semiconductor circuit device 200, an external circuit is required, which may lead to the enlargement of the semiconductor circuit device 200 and / or increased cost. In addition, because the current waveform 141 of the drain-source current Ids of the semiconductor circuit device 200 vibrates, the semiconductor circuit device 200 may malfunction, and in the worst case, it may lead to damage, thus reducing the reliability of the semiconductor circuit device 200.

[0033] In order to eliminate the problems caused by the prior art, the present invention aims to provide a semiconductor circuit device that connects multiple semiconductor devices fabricated from semiconductor chips in parallel, wherein the semiconductor circuit device is capable of suppressing the vibration of the current waveform.

[0034] Technical solution

[0035] To solve the above-mentioned problems and achieve the objectives of the present invention, the semiconductor circuit device of the present invention includes a semiconductor chip, electrode pads, a first substrate, and metal components, and has the following features: The semiconductor chip is made of a semiconductor with a bandgap wider than that of silicon. A plurality of semiconductor elements are disposed on the semiconductor chip. The plurality of electrode pads are disposed separately from each other on the front side of the semiconductor chip and are electrically connected to different semiconductor elements. The plurality of semiconductor chips are bonded to the first substrate, and the plurality of semiconductor chips are separated from each other.

[0036] The metal component connects the electrode pads, which are connected to the same portions of the semiconductor elements, in parallel among the plurality of semiconductor chips. The layout of the electrode pads of at least one of the semiconductor chips differs from the layout of the electrode pads of the remaining semiconductor chips. By setting the layout of the electrode pads on the front side of the semiconductor chips and the layout of the plurality of semiconductor chips on the first substrate, a layout is obtained in which the resistive components are uniform, or the reactive components are uniform, or both resistive and reactive components are uniform among the electrode pads connected in parallel via the metal component.

[0037] Furthermore, based on the above-described invention, the semiconductor circuit device of the present invention is characterized in that, by arranging the electrode pads connected in parallel via the metal components at equal distances on the first substrate, the resistive or reactive components, or both, between the electrode pads connected in parallel via the metal components become uniform.

[0038] Furthermore, based on the above-described invention, the semiconductor circuit device of the present invention is characterized in that the metal component is a metal lead.

[0039] Furthermore, based on the above-described invention, the semiconductor circuit device of the present invention is characterized in that the metal component comprises terminal pins for leading out the potential of the electrode pads and metal wiring formed on a second substrate disposed opposite to the front side of the plurality of semiconductor chips. Between the plurality of semiconductor chips, different terminal pins are respectively bonded to the electrode pads connected to the same portion of the semiconductor elements, and these different terminal pins are connected to each other via the metal wiring.

[0040] Furthermore, based on the above-described invention, the semiconductor circuit device of the present invention is characterized in that the semiconductor circuit device further comprises a resistor formed on the second substrate and electrically connected to the metal wiring.

[0041] Furthermore, the semiconductor circuit device of the present invention, based on the above-described invention, is characterized in that a plurality of terminal pins are bonded to the same electrode pads. A portion of the plurality of terminal pins bonded to the same electrode pads is provided with a reactive component, which is formed by partially bending that portion of the terminal pin.

[0042] According to the invention described above, when the semiconductor circuit device is turned off, deviations in the gate threshold voltage of each main semiconductor element fabricated in each semiconductor chip can be suppressed, and the voltage waveform of the gate voltage of the semiconductor circuit device can be made less prone to vibration. Therefore, the rising edges of the drain-source voltage waveform during turn-off can be made approximately the same in the main semiconductor elements of each semiconductor chip, and the voltage waveform of the drain-source voltage of the semiconductor circuit device can be made less prone to vibration.

[0043] Technical effect

[0044] The semiconductor circuit device according to the present invention has the effect of suppressing the vibration of the current waveform when a semiconductor circuit device consisting of multiple semiconductor chips connected in parallel is turned off. Attached Figure Description

[0045] Figure 1 This is a top view showing an example of the layout of a semiconductor chip mounted on an insulating substrate of the semiconductor circuit device of Embodiment 1, viewed from the front side.

[0046] Figure 2 This is a top view showing an example of the layout of a semiconductor chip mounted on an insulating substrate of the semiconductor circuit device of Embodiment 1, viewed from the front side.

[0047] Figure 3 This is a top view showing an example of the layout of a semiconductor chip mounted on an insulating substrate of the semiconductor circuit device of Embodiment 1, viewed from the front side.

[0048] Figure 4 It is shown Figure 1 A cross-sectional view of the active region structure.

[0049] Figure 5 It is shown Figure 1 A cross-sectional view of the active region structure.

[0050] Figure 6This is a top view schematically showing an example of the layout of the semiconductor circuit device of Embodiment 1 as viewed from the front side of the insulating substrate.

[0051] Figure 7 This is a top view schematically showing an example of the layout of the semiconductor circuit device of Embodiment 1 as viewed from the front side of the insulating substrate.

[0052] Figure 8 This is a top view schematically showing an example of the layout of the semiconductor circuit device of Embodiment 1 as viewed from the front side of the insulating substrate.

[0053] Figure 9 This is a cross-sectional view schematically showing the structure of the semiconductor circuit device according to Embodiment 1.

[0054] Figure 10 This is a circuit diagram showing the equivalent circuit of the semiconductor circuit device according to Embodiment 1.

[0055] Figure 11 This is a cross-sectional view showing the state of a semiconductor chip assembled on an insulating substrate of the semiconductor circuit device of Embodiment 1 during manufacturing.

[0056] Figure 12 This is a cross-sectional view showing the state of a semiconductor chip assembled on an insulating substrate of the semiconductor circuit device of Embodiment 1 during manufacturing.

[0057] Figure 13 This is a cross-sectional view showing the state of a semiconductor chip assembled on an insulating substrate of the semiconductor circuit device of Embodiment 1 during manufacturing.

[0058] Figure 14 This is a cross-sectional view showing the state of a semiconductor chip assembled on an insulating substrate of the semiconductor circuit device of Embodiment 1 during manufacturing.

[0059] Figure 15 This is a cross-sectional view showing the state of a semiconductor chip assembled on an insulating substrate of the semiconductor circuit device of Embodiment 1 during manufacturing.

[0060] Figure 16 This is a cross-sectional view showing the state of a semiconductor chip assembled on an insulating substrate of the semiconductor circuit device of Embodiment 1 during manufacturing.

[0061] Figure 17 This is a top view showing an example of the layout of a semiconductor chip mounted on an insulating substrate of the semiconductor circuit device of Embodiment 2, viewed from the front side.

[0062] Figure 18 This is a top view showing an example of the layout of a semiconductor chip mounted on an insulating substrate of the semiconductor circuit device of Embodiment 2, viewed from the front side.

[0063] Figure 19 This is a characteristic diagram showing the voltage and current waveforms when the embodiment is turned off.

[0064] Figure 20 This is a characteristic diagram showing the voltage and current waveforms during the turn-off of an existing example.

[0065] Figure 21 It is a schematic top view showing the layout of an existing semiconductor circuit device as seen from the front side of an insulating substrate.

[0066] Figure 22 It is a schematic cross-sectional view showing the structure of an existing semiconductor circuit device.

[0067] Symbol Explanation

[0068] 1. Active region

[0069] 1a Main effective area

[0070] 1b Primary Invalid Region

[0071] 2 Edge terminal area

[0072] 10, 10a, 10b, 10c semiconductor chips

[0073] 11. Main semiconductor components

[0074] 12 Current sensing unit

[0075] 12a Sensing Effective Area

[0076] 12b Sensing Invalid Area

[0077] 13 Temperature sensing unit

[0078] 14 Gate pad section

[0079] Resistors 15, 94a, 94a', 94b, 94b'

[0080] 16 Gate resistor

[0081] 17 Source wiring

[0082] 18 Drain wiring

[0083] 19 Gate wiring

[0084] 20 Semiconductor Devices

[0085] 21a Source pad (electrode pad)

[0086] 21b Gate pad (electrode pad)

[0087] 22 OC pads (electrode pads)

[0088] 23a Anode pad (electrode pad)

[0089] 23b Cathode pad (electrode pad)

[0090] 31 n + Type of starting substrate

[0091] 32 n - Type Drift Zone

[0092] 32a n - Type area

[0093] 33a, 33b n-type current diffusion region

[0094] 34a, 34b p-type base regions

[0095] 35a, 35b n + Source area

[0096] 36a, 36b p ++ Type contact area

[0097] 37a, 37b trenches

[0098] 38a, 38b gate insulating film

[0099] 39a, 39b gate electrodes

[0100] 40 and 75 interlayer insulating film

[0101] Contact holes 40a, 40b, 75a, 75b

[0102] 41a, 41b, 41e NiSi films

[0103] 42a, 42b, 42e First TiN film

[0104] 43a, 43b, 43e First Ti film

[0105] 44a, 44b, 44e Second TiN film

[0106] 45a, 45b, 45e Second Ti film

[0107] 46a, 46b, 46e Barrier Metal

[0108] 47a~47e Coating

[0109] 48a~48e terminal pins

[0110] 49a~49c, 49e First protective film

[0111] 50a~50c, 50e Second protective film

[0112] 51 Drain electrode

[0113] 61a, 61b, 62a, 62b, 101, 103p + Type area

[0114] 71 n - Type silicon carbide layer

[0115] 71a n - The increased thickness of the silicon carbide layer

[0116] 72 p-type silicon carbide layer

[0117] 73 p-type polycrystalline silicon layer

[0118] 74 n-type polycrystalline silicon layer

[0119] 80 Insulating substrate

[0120] 81 Insulation Board

[0121] 82 copper coins

[0122] 83 Heatsink

[0123] Solder layers 84 and 85

[0124] 86, 86a, 87 implanted pins

[0125] 86' and 87' leads

[0126] 88a, 88b External electrode terminals

[0127] 89 Sealing materials

[0128] 90 Printed substrate

[0129] 91a source pad

[0130] 91b, 91b' gate pads

[0131] 92', 92' OC pads

[0132] 93a, 93a' anode pads

[0133] 93b, 93b' cathode pads

[0134] Wiring for 95a, 95a', 95b, 95b', 96, 96'

[0135] 100 Semiconductor circuit devices

[0136] Connection points 100a to 100b

[0137] 102, 104 n-type regions

[0138] GND grounding point

[0139] d1 p + Depth of type region

[0140] d2 adjacent p + Distance between type regions

[0141] Depth of d3 n-type region

[0142] t1 n - The initial deposition of the type silicon carbide layer is in n + Thickness on the type starting substrate

[0143] t2 n - The thickness of the increased portion of the silicon carbide layer.

[0144] Thickness of t3 p-type silicon carbide layer

[0145] X is the direction parallel to the front side of the semiconductor chip (first direction).

[0146] Y is the direction parallel to the front side of the semiconductor chip and orthogonal to the first direction (the second direction).

[0147] Z Depth Direction Detailed Implementation

[0148] Hereinafter, preferred embodiments of the semiconductor circuit device of the present invention will be described in detail with reference to the accompanying drawings. In this specification and the drawings, layers or regions prefixed with n or p respectively represent layers or regions where electrons or holes are the majority carriers. Furthermore, the + and - symbols marked with n or p respectively indicate that the impurity concentration is higher and lower than that of layers or regions not marked with + and -. It should be noted that in the following description of the embodiments and the accompanying drawings, the same symbols are used for the same components, and repeated descriptions are omitted.

[0149] (Implementation Method 1)

[0150] The semiconductor circuit device of Embodiment 1 is a power module or IPM constructed by using a semiconductor with a wider bandgap than silicon (Si) (wide bandgap semiconductor) as the semiconductor material. The structure of the semiconductor circuit device of Embodiment 1 will be described using, for example, silicon carbide (SiC) as the wide bandgap semiconductor. Figures 1-3 This is a top view showing an example of the layout of a semiconductor chip mounted on an insulating substrate of the semiconductor circuit device of Embodiment 1, viewed from the front side.

[0151] First, the insulating substrate (first substrate) 80 (described later) assembled in the semiconductor circuit device 100 of Embodiment 1 is... Figure 8 , 9 The structure of the semiconductor chip 10 will be described. Figures 1-3 The semiconductor chip 10 (10a-10c) shown has different layouts for the multiple electrode pads 21a, 21b, 22, 23a, and 23b on the front side. A semiconductor device 20 is fabricated on the semiconductor chip 10. The semiconductor device 20 has a main semiconductor element 11 in the active region 1 and one or more circuit sections for protecting and controlling the main semiconductor element 11.

[0152] The main semiconductor element 11 is a vertical MOSFET that performs the main operation of the semiconductor device 20, and is composed of multiple unit cells (functional units of the element) connected in parallel to each other via source pads 21a (described later). The main semiconductor element 11 is disposed in the effective region (hereinafter referred to as the main effective region) 1a of the active region 1. The main effective region 1a is the region in which the main current of the main semiconductor element 11 flows when the main semiconductor element 11 is turned on. The main effective region 1a has, for example, a generally rectangular planar shape and occupies most of the surface area of ​​the active region 1.

[0153] The circuitry used to protect and control the main semiconductor element 11 includes high-functionality components such as a current sensing unit 12, a temperature sensing unit 13, an overvoltage protection unit (not shown), and an arithmetic circuit unit (not shown), and is disposed in the main invalid region 1b of the active region 1. The main invalid region 1b is a region in which no unit cell of the main semiconductor element 11 is disposed, and does not function as a main semiconductor element 11. The main invalid region 1b has a planar shape, for example, a generally rectangular shape, and is disposed between the main active region 1a and the edge terminal region 2.

[0154] Edge termination region 2 is the region between the active region 1 and the end of the semiconductor chip 10, surrounding the active region 1 and mitigating the electric field on the front side of the semiconductor chip 10 to maintain withstand voltage. A withstand voltage structure (not shown) such as a field limiting ring (FLR) or a junction termination extension (JTE) is configured in edge termination region 2. Withstand voltage refers to the limit of voltage at which a component will not malfunction and / or be damaged.

[0155] The source pad (electrode pad) 21a of the main semiconductor element 11 is disposed on the front side of the semiconductor chip 10 in the main active region 1a. The main semiconductor element 11 has a larger current capability compared to other circuit sections. Therefore, the source pad 21a of the main semiconductor element 11 has a planar shape that is substantially the same as that of the main active region 1a, covering substantially the entire surface of the main active region 1a. The source pad 21a of the main semiconductor element 11 is disposed separately from the electrode pads other than the source pad 21a.

[0156] The electrode pads, excluding the source pad 21a, are arranged separately on the front side of the semiconductor chip 10 in the main invalid region 1b. The electrode pads, excluding the source pad 21a, refer to the gate pad 21b of the main semiconductor element 11, the electrode pads (OC pad (second source pad)) 22 of the current sensing unit 12, the electrode pads (anode pad and cathode pad) 23a and 23b of the temperature sensing unit 13, the electrode pads of the overvoltage protection unit (hereinafter referred to as OV pads: not shown), and the electrode pads of the operational circuit unit (not shown), etc.

[0157] The electrode pads, excluding the source pad 21a, have a planar shape, for example, generally rectangular, and have the surface area required to engage with the terminal leads (metal parts) 48b-48e and / or bonding wires (not shown), which will be described later. The layout of the electrode pads, excluding the source pad 21a, is as described later, depending on the mounting on the insulating substrate 80 (see reference). Figure 8 , Figure 9 The overall layout of all semiconductor chips 10 is determined by the arrangement of the electrode pads, except for the source pad 21a. The electrode pads can be arranged in a row along one side of a roughly rectangular boundary between, for example, the active region 1 and the edge termination region 2. Figure 1 , Figure 2 ).

[0158] Electrode pads other than source pad 21a can also be configured as L-shaped along both sides. Figure 3 The two sides share a vertex of a roughly rectangular boundary between the active region 1 and the edge terminal region 2. The planar shapes of the main active region 1a and the main inactive region 1b can be set according to the layout of the electrode pads, excluding the source pad 21a. Figures 1-3 In the diagram, the source pad 21a, gate pad 21b, OC pad 22, anode pad 23a, and cathode pad 23b are respectively represented as rectangles labeled S, G, OC, A, and K (in... Figures 6-8 (The same applies to China).

[0159] The current sensing unit 12 operates under the same conditions as the main semiconductor element 11 and has the function of detecting overcurrent (OC) flowing through the main semiconductor element 11. The current sensing unit 12 is disposed separately from the main semiconductor element 11. The current sensing unit 12 has a number (for example, about ten) fewer than the number of unit cells of the main semiconductor element 11 (for example, more than one thousand) of vertically oriented MOSFETs with the same configuration as the main semiconductor element 11, and its surface area is smaller than that of the main semiconductor element 11.

[0160] The unit cells of the current sensing unit 12 are disposed in a portion of the area of ​​the semiconductor chip 10 covered by the OC pad 22 (hereinafter referred to as the effective sensing area: shaded area) 12a. The unit cells of the current sensing unit 12 are disposed adjacent to each other in a direction parallel to the front surface of the semiconductor chip 10. The direction in which the unit cells of the current sensing unit 12 are adjacent to each other is the same as the direction in which the unit cells of the main semiconductor element 11 are adjacent to each other. The unit cells of the current sensing unit 12 are connected in parallel to each other through the OC pad 22.

[0161] Additionally, the area of ​​the semiconductor chip 10 covered by the OC pad 22, excluding the active sensing area 12a, is a non-active sensing area 12b that does not function as a current sensing unit 12. No unit cell of the current sensing unit 12 is disposed in the non-active sensing area 12b. The p-type base region 34b (described later) encompasses approximately the entire area of ​​the main non-active sensing area 1b, excluding the active sensing area 12a. Figure 5 () Extends from the sensing active area 12a to the surface area on the front side of the semiconductor chip 10.

[0162] The temperature sensing unit 13 has the function of detecting the temperature of the main semiconductor element 11 by utilizing the temperature characteristics of a diode. The temperature sensing unit 13 is disposed directly below the anode pad 23a and the cathode pad 23b. The temperature sensing unit 13 may be, for example, a polysilicon diode composed of a polysilicon layer provided on the interlayer insulating film 40 on the front side of the semiconductor chip 10, or a diffused diode formed by a pn junction of a p-type region and an n-type region formed inside the semiconductor chip 10.

[0163] The overvoltage protection unit (not shown) is, for example, a diode that protects the main semiconductor element 11 from overvoltages (OV) such as surges. The current sensing unit 12, the temperature sensing unit 13, and the overvoltage protection unit are controlled by the arithmetic circuit unit. The main semiconductor element 11 is controlled based on the output signals of the current sensing unit 12, the temperature sensing unit 13, and the overvoltage protection unit. The arithmetic circuit unit is composed of multiple semiconductor elements, such as CMOS (Complementary MOS) circuits.

[0164] Next, the cross-sectional structure of the active region 1 of the semiconductor device 20 fabricated on the semiconductor chip 10 will be described. Figure 4 , Figure 5 It is shown Figure 1 A cross-sectional view of the active region structure. Figure 4 The cross-sectional structure of the main effective area 1a, the sensing effective area 12a, and the temperature sensing unit 13 is shown in the figure. Figure 1 (Cross-sectional structures at cut lines X1-X2, X3-X4, and Y1-Y2). Figure 5 The diagram shows the cross-sectional structure of the main active region 1a, the sensing inactive region 12b, and the gate pad portion 14. Figure 1 (The cross-sectional structure at the cut lines X1-X2-X3 and Y2-Y3).

[0165] Although Figure 4 , Figure 5 Only a portion of the unit cells in the main effective region 1a and the sensing effective region 12a are shown, but all unit cells in the main effective region 1a and the sensing effective region 12a have the same structure. Although in Figure 4 , Figure 5 The middle shows Figure 1 The structure of active region 1, but Figures 1-3 The structure of the active region 1 is identical except for the layout of the electrode pads on the front side of the semiconductor chip 10. Therefore, Figure 2 , Figure 3 The main effective region 1a, the sensing effective region 12a, the sensing ineffective region 12b, the temperature sensing unit 13, and the gate pad unit 14 are also... Figure 4 , Figure 5 same.

[0166] The main semiconductor element 11 is a vertical MOSFET with a MOS gate (an insulated gate composed of a three-layer structure of metal-oxide-semiconductor) on the front side of the semiconductor chip 10 in the main effective region 1a. Here, we will describe an example in which the main semiconductor element 11 and the circuit section that protects and controls the main semiconductor element 11 have the same wiring structure using pin-shaped wiring components (implanted pins (conductive posts): terminal pins 48a to 48e described later). However, a wiring structure using leads (metal components) can also be used instead of pin-shaped wiring components.

[0167] Semiconductor chip 10 is made of silicon carbide n + n-type starting substrate 31 is epitaxially grown sequentially on the front side. - The silicon carbide layers 71 and 72 of the p-type drift region 32 and the p-type base region 34a. The main surface of the silicon carbide layer 71 side of the semiconductor chip 10 is designated as the front side, and the n-type base region 34a is... +The main surface of the starting substrate 31 is designated as the back side. The main semiconductor element 11 has a p-type base region 34a, n-type base region 34a on the front side of the semiconductor chip 10. + A conventional MOS gate is formed by source region 35a, trench 37a, gate insulating film 38a and gate electrode 39a.

[0168] Trench 37a extends from the front side of semiconductor chip 10 (the surface of p-type silicon carbide layer 72) along the depth direction Z through p-type silicon carbide layer 72 to n. - A silicon carbide layer 71 is used. Trench 37a can be configured, for example, as a strip extending in a direction parallel to the front side of the semiconductor chip 10, or as a matrix when viewed from the front side of the semiconductor chip 10. Figure 4 , Figure 5 The diagram shows, for example, electrode pads 21b, 23a, 23b, 22 (see reference). Figure 1 The grooves 37a extend in a strip-like pattern in the first direction X.

[0169] A gate electrode 39a is disposed inside the trench 37a via a gate insulating film 38a. Between adjacent trenches 37a, p-type base regions 34a and n-type base regions 35a are selectively disposed on the surface region of the front side of the semiconductor chip 10. + Source region 35a and p ++ Type contact area 36a. n + Source regions 35a and p ++ The p-type contact region 36a is located between the front side of the semiconductor chip 10 and the p-type base region 34a, and is disposed in contact with the p-type base region 34a.

[0170] n + The source region 35a is located on the sidewall of the trench 37a and is in contact with the gate insulating film 38a. ++ Type contact area 36a ratio n + The source area 35a is positioned further away from the trench 37a. Alternatively, p can be omitted. ++ Type contact area 36a. In this case, instead of p... ++ The p-type contact region 36a allows the p-type base region 34a to reach the front side of the semiconductor chip 10, and it is parallel to the front side of the semiconductor chip 10 and orthogonal to the first direction X in the second direction Y, which is adjacent to the n-type base region 34a. + The source region 35a is in contact.

[0171] Inside the semiconductor chip 10, in the p-type base region 34a and n + Type leak area (n) + Between the type-initiating substrate 31) and the p-type base region 34a and n + The type starting substrate 31 is contacted and provided with n - Type drift region 32. It can also be located in the p-type base region 34a and n.- Between the n-type drift regions 32, an n-type current diffusion region 33a is provided in contact with these regions. The n-type current diffusion region 33a is a so-called current spreading layer (CSL) that reduces the spreading resistance of charge carriers.

[0172] Furthermore, inside the semiconductor chip 10, closer to the n-type base region than the p-type base region 34a... + The location of the drain area can also be configured with a first p to alleviate the electric field applied to the bottom surface of the trench 37a. + Type region 61a, second p + Type region 62a. First p + The p-type region 61a is separated from the p-type base region 34a and is positioned opposite the bottom surface of the trench 37a in the depth direction Z. Second p + Type region 62a is between adjacent trenches 37a, and is adjacent to the first p + The p-type region 61a and the trench 37a are separated and are in contact with the p-type base region 34a.

[0173] An interlayer insulating film 40 is disposed on the entire front side of the semiconductor chip 10 and covers the gate electrode 39a. All gate electrodes 39a of the main semiconductor element 11, in the portion not shown, are connected to the gate pad 21b (see reference 10) via gate channels (not shown). Figure 1 Electrical connection. The gate flow channel is located in the edge termination region 2 (refer to...). Figures 1-3 The active region 1 is disposed on the front side of the semiconductor chip 10 via an interlayer insulating film 40 and is formed by a gate polysilicon layer surrounding the active region 1.

[0174] A first contact hole 40a is provided, which penetrates the interlayer insulating film 40 in the depth direction Z to reach the semiconductor chip 10. The n of the main semiconductor element 11 is exposed in the first contact hole 40a. + Source regions 35a and p ++ Type contact area 36a. Inside the first contact hole 40a, a nickel silicide (NiSi, Ni2Si or thermally stable NiSi2; hereinafter, the whole is NiSi) film 41a is provided only on the front side of the semiconductor chip 10.

[0175] The NiSi film 41a makes 10-ohm contact with the semiconductor chip inside the first contact hole 40a, and is in contact with n + Source regions 35a and p ++ Type 36a contact area electrical connection. Without setting p... ++ In the case of contact area 36a, replacing p ++ The p-type contact area 36a exposes the p-type base area 34a in the first contact hole 40a and is electrically connected to the NiSi film 41a.

[0176] A barrier metal 46a is disposed along the entire surface of the interlayer insulating film 40 and the NiSi film 41a in the main effective region 1a. The barrier metal 46a has the function of preventing mutual reaction between the metal films of the barrier metal 46a or between opposing regions separated by the barrier metal 46a. The barrier metal 46a may have a laminated structure, for example, formed by sequentially depositing a first titanium nitride (TiN) film 42a, a first titanium (Ti) film 43a, a second TiN film 44a, and a second Ti film 45a.

[0177] The first TiN film 42a covers the entire surface of the interlayer insulating film 40. The first TiN film 42a is not disposed on the front side of the semiconductor chip 10 where the NiSi film 41a is formed. A first Ti film 43a is disposed on the surfaces of the first TiN film 42a and the NiSi film 41a. A second TiN film 44a is disposed on the surface of the first Ti film 43a. A second Ti film 45a is disposed on the surface of the second TiN film 44a. A barrier metal is not disposed, for example, in the temperature sensing section 13.

[0178] The source pad 21a is disposed on the entire surface of the second Ti film 45a, and is connected to the n via the barrier metal 46a and the NiSi film 41a. + The p-type source region 35a and the p-type base region 34a are electrically connected. The source pad 21a can be, for example, an aluminum (Al) film, an aluminum-silicon (Al-Si) film, or an aluminum-silicon-copper (Al-Si-Cu) film with a thickness of about 5 μm. The source pad 21a, the barrier metal 46a, and the NiSi film 41a function as the source electrode of the main semiconductor element 11.

[0179] One end of a terminal pin 48a is bonded to the source pad 21a via a plating layer 47a and a solder layer (not shown). The other end of the terminal pin 48a is bonded to a source pad 91a on a printed circuit board (second substrate) 90 arranged opposite the front side of the semiconductor chip 10 (see reference 21a). Figures 6-9 The semiconductor chip 10 can be directly coupled or electrically connected via a circuit pattern (not shown). The other end of the terminal pin 48a protrudes to the outside of the housing (not shown) on which the semiconductor chip 10 is mounted and is electrically connected to an external device (not shown).

[0180] Terminal pin 48a is a rod-shaped (cylindrical) wiring component with a predetermined diameter. Terminal pin 48a is soldered to the plating film 47a in a substantially perpendicular position relative to the front side of the semiconductor chip 10. Terminal pin 48a is an external connection terminal that leads the potential of the source pad 21a to the outside and is connected to the external ground potential (lowest potential). The surface of the source pad 21a, excluding the plating film 47a, is covered by a first protective film 49a. The boundary between the plating film 47a and the first protective film 49a is covered by a second protective film 50a.

[0181] The first protective film 49a and the second protective film 50a are, for example, polyimide films. The drain electrode 51 is adjacent to the entire back surface (n) of the semiconductor chip 10. + (Back side of the type-starting substrate 31) Ohmic contact. On the drain electrode 51, a drain pad (electrode pad: not shown) is provided using a laminated structure, for example, by sequentially depositing a Ti film, a nickel (Ni) film, and a gold (Au) film. The drain pad is soldered to the copper plate 82 of the insulating substrate 80 (see reference). Figure 9 On the copper plate 82, and at least a portion thereof is in contact with the base of the cooling plate (not shown).

[0182] By bonding the terminal pins 48a to the source pads 21a on the front side of the semiconductor chip 10 and bonding the drain pads on the back side to the copper plate 82 of the insulating substrate 80, the semiconductor chip 10 becomes a double-sided cooling structure with cooling structures on both main surfaces. The heat generated by the semiconductor chip 10 is dissipated from the sheet portion of the cooling pad via the copper plate 82 bonded to the drain pads on the back side of the semiconductor chip 10, and also from the printed circuit board 90 bonded to the terminal pins 48a on the front side of the semiconductor chip 10.

[0183] The current sensing unit 12 has p-type base regions 34b and n that are configured identically to those of the corresponding parts of the main semiconductor element 11. + Source region 35b, p ++ The p-type base region 34b includes a contact area 36b, a trench 37b, a gate insulating film 38b, a gate electrode 39b, and an interlayer insulating film 40. Each portion of the MOS gate of the current sensing unit 12 is disposed in the sensing active region 12a of the main inactive region 1b. The p-type base region 34b passes through the n-type base region of the front surface area of ​​the semiconductor chip 10. - The p-type base region 32a is separated from the p-type base region 34a of the main semiconductor element 11.

[0184] The p-type base region 34b extends from, for example, the sensing active region 12a to approximately the entire area of ​​the main inactive region 1b. The current sensing unit 12 may also have an n-type current diffusion region 33b, a first p-type base region, similar to the main semiconductor element 11. + Type region 61b, and the second p +Type region 62b. Alternatively, p can be left unset. ++ Type contact area 36b. Gate electrode 39b connects to gate pad 21b (see reference 21b) via gate channel (not shown). Figures 1-3 Electrical connection. The gate electrode 39b is covered by an interlayer insulating film 40.

[0185] In the effective sensing area 12a, a second contact hole 40b is provided in the interlayer insulating film 40, extending along the depth direction Z to reach the semiconductor chip 10, and exposing n + Source region 35b and p ++ Type contact area 36b. In the sensing effective area 12a, on the front side of the semiconductor chip 10, a NiSi film 41b and a barrier metal 46b are disposed similarly to the main semiconductor element 11. Reference numerals 42b to 45b are respectively the first TiN film, the first Ti film, the second TiN film, and the second Ti film constituting the barrier metal 46b.

[0186] The NiSi film 41b is inside the second contact hole 40b, making 10-ohm contact with the semiconductor chip, and is in contact with n + Source region 35b and p ++ Type contact area 36b electrical connection. Without setting p... ++ In the case of contact area 36b, replacing p ++ The p-type contact area 36b exposes the p-type base region 34b in the second contact hole 40b and is electrically connected to the NiSi film 41b. The blocking metal 46b extends on the interlayer insulating film 40 in the sensing ineffective region 12b.

[0187] An OC pad 22 is disposed on the entire surface of the barrier metal 46b, separated from the source pad 21a. The OC pad 22 is connected to the n-type source pad 21a via the barrier metal 46b and the NiSi film 41b. + The p-type source region 35b and the p-type base region 34b are electrically connected. The OC pad 22 is formed simultaneously with the source pad 21a, for example, using the same material as the source pad 21a. The OC pad 22, the barrier metal 46b, and the NiSi film 41b function as the source electrode of the current sensing unit 12.

[0188] On the OC pad 22, a terminal pin 48b is attached with the same wiring structure as on the source pad 21a. The terminal pin 48b is a rod-shaped (cylindrical) wiring component with a smaller diameter than the terminal pin 48a. The terminal pin 48b is, for example, an external connection terminal for leading the potential of the OC pad 22 to the outside via an external resistor 15 (see reference). Figure 10 This connects the OC pad 22 to the ground potential. Symbols 47b, 49b, and 50b represent the coating, first protective film, and second protective film that constitute the wiring structure on the OC pad 22, respectively.

[0189] The p-type base region 34a of the main effective region 1a and the p-type base region 34b of the sensing effective region 12a pass through the n (omitted illustration) of the surface region of the semiconductor chip 10. - The n-type region is separated from the p-type region (not shown) used for component separation. The p-type region used for component separation refers to a roughly rectangular shape that surrounds the active region 1 at the edge terminal region 2, and is separated from the n-type region by the n-type region. - The floating p-type region of the parasitic diode is formed by the pn junction of the drift region 32, which electrically separates the active region 1 from the edge terminal region 2.

[0190] The temperature sensing unit 13 is, for example, a polysilicon diode formed by a pn junction of a p-type polysilicon layer 73 as the p-type anode region and an n-type polysilicon layer 74 as the n-type cathode region. Figure 4 The p-type polysilicon layer 73 and the n-type polysilicon layer 74 are disposed on the interlayer insulating film 40 in the main invalid region 1b. The temperature sensing unit 13 is electrically insulated from the semiconductor chip 10, the main semiconductor element 11 and the current sensing unit 12 through the interlayer insulating film 40.

[0191] Anode pad 23a and cathode pad 23b are in contact with p-type polysilicon layer 73 and n-type polysilicon layer 74, respectively, through third contact holes 75a and fourth contact holes 75b of the interlayer insulating film 75 covering them. Anode pad 23a and cathode pad 23b are formed simultaneously with source pad 21a, for example, using the same material as source pad 21a. Terminal leads 48c and 48d are attached to anode pad 23a and cathode pad 23b, respectively, with the same wiring structure as that on source pad 21a.

[0192] Terminal pins 48c and 48d are external connection terminals for leading the potential of the anode pad 23a and cathode pad 23b to the outside. Terminal pins 48c and 48d are rod-shaped wiring components with a predetermined diameter corresponding to the current capability of the temperature sensing unit 13. Symbols 47c and 47d are the coatings constituting the wiring structure on the anode pad 23a and the wiring structure on the cathode pad 23b, respectively. Symbols 49c and 50c are the first protective film and the second protective film constituting the wiring structure on the temperature sensing unit 13, respectively.

[0193] In addition to the current sensing unit 12 and the temperature sensing unit 13, a gate pad portion 14 is also provided in the main invalid region 1b. The gate pad portion 14 is the area where the gate pad 21b of the main semiconductor element 11 is provided. Figure 5 The MOS gate of the main semiconductor element 11 can extend from the main active region 1a to the gate pad portion 14. The MOS gate formed in the gate pad portion 14 is covered by an interlayer insulating film 40.

[0194] On the gate pad portion 14, on the front side of the semiconductor chip 10, a NiSi film 41e and a barrier metal 46e are provided in the same manner as the main semiconductor element 11. The gate pad 21b is disposed separately from other electrode pads on the interlayer insulating film 40 in the main invalid region 1b. The gate pad 21b is formed simultaneously with the source pad 21a using, for example, the same material as the source pad 21a. Terminal pins 48e are also bonded to the gate pad 21b with, for example, the same wiring structure as that on the source pad 21a.

[0195] Terminal pin 48e is an external connection terminal for leading the potential of gate pad 21b to the outside. Terminal pin 48e is a rod-shaped wiring component with a predetermined diameter corresponding to the gate voltage applied to the main semiconductor element 11. Symbols 42e to 45e are the first TiN film, the first Ti film, the second TiN film, and the second Ti film constituting the barrier metal 46e, respectively. Symbols 47e, 49e, and 50e are the plating, the first protective film, and the second protective film constituting the wiring structure on the gate pad 21b, respectively.

[0196] The structure of the semiconductor circuit device 100 according to Embodiment 1 will be described. Figures 6-8 This is a schematic top view illustrating an example of the layout of the semiconductor circuit device of Embodiment 1, viewed from the front side of the insulating substrate. Except for the insulating substrate 80, in... Figure 6 A portion of the printed circuit board 90 is also shown. Figure 9 This is a cross-sectional view schematically showing the structure of the semiconductor circuit device according to Embodiment 1. Figure 9 yes Figure 6 The cross-sectional structure of the semiconductor circuit device 100. In Figure 9 In order to clarify the structure within the sealing material 89, in order to... Figure 6 Different configurations are used to illustrate semiconductor chip 10.

[0197] Figure 6 , Figure 9 The semiconductor circuit device 100 of Embodiment 1 shown includes a semiconductor chip 10, an insulating substrate 80, a printed circuit board 90, and external electrode terminals 88a and 88b. A copper (Cu) plate 82 and a heat sink 83 are respectively bonded to the two main surfaces of the insulating plate 81 of the insulating substrate 80. A plurality of (at least two) semiconductor chips 10 are disposed on the copper plate 82 of the insulating substrate 80 (see Figure 1). Figures 1-3 ). Figure 6 shown in the Figure 1 , Figure 2 The semiconductor chips 10 (10a, 10b) shown are arranged in a matrix of four. Figure 7 , Figure 8 The same applies to Naka.

[0198] Electrode pads (hereinafter referred to as electrode pads of the same type) that are connected to the same part of the semiconductor device 20 fabricated on each semiconductor chip 10 mounted on the insulating substrate 80 are connected to each other via electrode pads of the printed circuit board 90, implanted pins (metal parts) 86, 87 and wiring (metal parts) 96. Figure 6 ), or lead wire (bonding wire: metal component) 86', 87' (refer to Figure 7 , 8 The semiconductor elements and / or circuit sections fabricated separately and connected in parallel on each semiconductor chip 10 have the same configuration. Regarding the layout of the electrode pads on the front side of the semiconductor chip 10, at least one of the semiconductor chips 10 differs from the others, exhibiting two or more patterns (see reference). Figures 1-3 ).

[0199] The overall layout of the semiconductor chip 10 mounted on the insulating substrate 80, and the layout of the electrode pads on the front side of the semiconductor chip 10, are determined in a manner that is not easily affected by the resistance (R) and / or reactance (L) components caused by the wiring 96, leads 86', 87' that connect multiple semiconductor chips 10 of the same type of electrode pads in parallel. For example, the overall layout of the semiconductor chip 10 mounted on the insulating substrate 80, and the layout of the electrode pads on the front side of the semiconductor chip 10, can also be determined in a manner that minimizes the length of the wiring 96 and / or leads 86', 87'.

[0200] Alternatively, among the electrode pads of the same type of semiconductor chips 10 connected in parallel via wiring 96 and / or leads 86', 87', resistors 94a and 94b can be electrically connected to the electrode pads of the printed circuit board 90 in a manner that makes the resistance (R) component and / or reactance (L) of wiring 96 and / or leads 86', 87' substantially uniform. Resistors 94a and 94b are connected in series between the parallel-connected electrode pads. Reactance component refers to inductive or capacitive reactance. Substantially uniform means identical within a range that includes allowable errors due to process variations. Specifically, substantially uniform is considered to be achieved as long as the deviation of the resistance (R) component or reactance (L) is within 10%.

[0201] For example, consider the case where the gate pads 21b of four semiconductor chips 10 on the insulating substrate 80 are connected in parallel to each other via gate pads 91b on the printed circuit board 90 and wiring (metal components) 95a, 95b, 96. Figure 6The layout of the semiconductor chip 10 and / or the connection points of resistors 94a and 94b will be described. Four semiconductor chips 10 are arranged in a matrix on the copper plate 82 of the insulating substrate 80. For example, each of these four semiconductor chips 10 uses... Figure 1 , Figure 2 Two semiconductor chips (hereinafter referred to as the first semiconductor chip and the second semiconductor chip) 10a and 10b are shown.

[0202] Two first semiconductor chips 10a are aligned in the same direction and arranged adjacent to each other along the first direction X. Therefore, all electrode pads of the first semiconductor chip 10a, except for the source pad 21a (gate pad 21b, OC pad 22, anode pad 23a, and cathode pad 23b), are arranged in a row along the first direction X. Two second semiconductor chips 10b are aligned in the same direction and arranged adjacent to each other along the first direction X. Therefore, all electrode pads of the second semiconductor chip 10a, except for the source pad 21a, are arranged in a row along the first direction X.

[0203] The electrode pads on the front sides of the first semiconductor chip 10a and the second semiconductor chip 10b, excluding the source pad 21a, are arranged in a row along one side of the generally rectangular planar shape of the first semiconductor chip 10a and the second semiconductor chip 10b, as described above. The first semiconductor chip 10a and the second semiconductor chip 10b are arranged adjacent to each other in the second direction Y, such that the sides of the electrode pads, excluding the source pad 21a, are facing each other. In the first semiconductor chip 10a and the second semiconductor chip 10b, the arrangement order of the electrode pads, excluding the source pad 21a, is reversed in the first direction X.

[0204] Therefore, by arranging the first semiconductor chip 10a and the second semiconductor chip 10b adjacent to each other along the second direction Y, the layout of the electrode pads on the front side of the first semiconductor chip 10a and the layout of the electrode pads on the front side of the second semiconductor chip 10b are linearly symmetrical with respect to an axis parallel to the first direction X passing between the first semiconductor chip 10a and the second semiconductor chip 10b. Each electrode pad of the first semiconductor chip 10a, except for the source pad 21a, is opposite to the same type of electrode pad of the second semiconductor chip 10b in the second direction Y.

[0205] Each source pad 21a of the first semiconductor chip 10a and the second semiconductor chip 10b is bonded with a solder layer 85, respectively. Figure 4 , Figure 5 Multiple implanted pins 86 of terminal pin 48a. The gate pad 21b, OC pad 22, anode pad 23a, and cathode pad 23b of the first semiconductor chip 10a and the second semiconductor chip 10b are respectively bonded via solder layer 85 to a plurality of implanted pins 86. Figure 5 Terminal pin 48e, Figure 4 , Figure 5 Terminal pin 48b, and Figure 4 The different implanted pins (conductive posts) 87 of the terminal pins 48c and 48d.

[0206] Pins 86 and 87 are directly connected to predetermined electrodes on the main surface (hereinafter referred to as the front side) of the printed circuit board 90 opposite to the side of the first semiconductor chip 10a and the second semiconductor chip 10b, or electrically connected to predetermined electrodes on the main surface (hereinafter referred to as the front side) of the printed circuit board 90 opposite to the side of the first semiconductor chip 10a and the second semiconductor chip 10b via a circuit pattern (not shown). The side of the printed circuit board 90 facing the first semiconductor chip 10a and the second semiconductor chip 10b is opposite to the front side of the first semiconductor chip 10a and the second semiconductor chip 10b. The printed circuit board 90 has electrode pads corresponding to the electrode pads on the front side of the first semiconductor chip 10a and the second semiconductor chip 10b at positions, for example, as close as possible to the electrode pads on the front side of the first semiconductor chip 10a and the second semiconductor chip 10b.

[0207] For example, each source pad 21a of the first semiconductor chip 10a and the second semiconductor chip 10b is electrically connected to the source pad (not shown) of the printed circuit board 90 via an implanted pin 86 that is bonded to itself. On the printed circuit board 90, a source pad can be respectively arranged at a position opposite to each source pad 21a of the first semiconductor chip 10a and the second semiconductor chip 10b, or a common source pad can be arranged in each group of first semiconductor chips 10a that are adjacent to each other along the first direction X and each group of second semiconductor chips 10b that are adjacent to each other along the first direction X.

[0208] The gate pads 21b, OC pads 22, anode pads 23a and 23b of the first semiconductor chip 10a and the second semiconductor chip 10b are electrically connected to the gate pads 91b, OC pads 92, anode pads 93a and 93b of the printed circuit board 90 via different implantation pins 87. The printed circuit board 90 has a set of gate pads 91b, OC pads 92, anode pads 93a and 93b for each group of first semiconductor chips 10a and second semiconductor chips 10b that are adjacent to each other, for example, along the second direction Y.

[0209] The groups of first semiconductor chips 10a and second semiconductor chips 10b adjacent to each other along the second direction Y each share a set of gate pads 91b, OC pads 92, anode pads 93a, and cathode pads 93b disposed on the printed circuit board 90 at positions opposite to the first semiconductor chips 10a and second semiconductor chips 10b. The gate pads 91b of the printed circuit board 90 are electrically connected to each other via wiring 96 formed on the front side of the printed circuit board 90. The OC pads 92, anode pads 93a, and cathode pads 93b of the printed circuit board 90 can also be electrically connected to each other via wiring (not shown) in the same way as the gate pads 91b.

[0210] The distance between the gate pads 21b of the first semiconductor chip 10a and the second semiconductor chip 10b, which are adjacent to each other along the second direction Y, is greater than that of the existing structure (see reference). Figure 21 , 22 The distance between the gate pads 211b of the semiconductor chip 210 is shorter. Therefore, the length of the wiring 96 that connects the gate pads 21b of all semiconductor chips 10 (10a, 10b) on the insulating substrate 80 in parallel is shorter than the length of the wiring 234 in the conventional structure. The length of the wiring (not shown) that connects the OC pads 92, anode pads 93a, and cathode pads 93b of the printed circuit board 90 in parallel is also shorter than the wiring in the conventional structure.

[0211] Resistors 94a and 94b can be electrically connected to the gate pads 91b of the printed circuit board 90 via wirings 95a and 95b. Resistors 94a and 94b represent, for example, resistive and reactive components, respectively, and are disposed on the front side of the printed circuit board 90. The resistance values ​​and / or configurations of resistors 94a and 94b are set in a manner that makes the resistive and reactive components between the gate pads 21b of the parallel-connected semiconductor chips 10 substantially uniform. Other electrode pads on the printed circuit board 90 may also be connected to their own separate resistors 94a and 94b.

[0212] By electrically connecting the source pads 21a on the front side of all semiconductor chips 10 on the insulating substrate 80 to the source pads of the printed circuit board 90 via implant pins 86 as described above, and by bonding the drain pads on the back side of the plurality of semiconductor chips 10 to the copper plate 82 of the insulating substrate 80 as described later, the main semiconductor elements 11 of the semiconductor device fabricated from the plurality of semiconductor chips 10 are connected in parallel. The gate pads 21b of all semiconductor chips 10 on the insulating substrate 80 are connected in parallel to each other via implant pins 87, gate pads 91b of the printed circuit board 90, and wiring 96.

[0213] One end of the external electrode terminal 88a is bonded to the copper plate 82 on the front side of the insulating substrate 80. The drain pads on the back side of the first semiconductor chip 10a and the second semiconductor chip 10b are bonded to the copper plate 82 on the front side of the insulating substrate 80 via the solder layer 84, and are electrically connected to the external electrode terminal 88a via the copper plate 82. One end of the external electrode terminal 88b is bonded to the circuit pattern (not shown) of the printed circuit board 90. The other ends of the external electrode terminals 88a and 88b protrude outward from the sealing material 89 described later. The external electrode terminals 88a and 88b lead the potential of the parts to which they are connected to to the outside.

[0214] The insulating substrate 80, semiconductor chip 10, implanted pins 86 and 87, printed circuit board 90, and external electrode terminals 88a and 88b are sealed by sealing material 89. The heat sink 83 of the insulating substrate 80 is bonded to a cooler (not shown) via thermal paste. When the semiconductor circuit device 100 is in operation, heat generated on the electrode pads and circuit patterns of the semiconductor chip 10 and / or printed circuit board 90 is conducted from the insulating substrate 80 to the cooler for heat dissipation, thereby cooling the semiconductor chip 10 and the printed circuit board 90. Reference numeral 97 is a control unit that controls the high-functionality section of the semiconductor chip 10.

[0215] like Figure 7 As shown, instead of implanting pin 87, the gate pads 21b of all semiconductor chips 10 (10a, 10b) on the insulating substrate 80 can also be electrically connected to the gate pads 91b' on the insulating substrate 80 via pin-type connection, for example, through lead 87'. The OC pads 22, anode pads 23a, and cathode pads 23b of the semiconductor chips 10 can also be electrically connected to the OC pads 92', anode pads 93a', and cathode pads 93b' on the insulating substrate 80 via different leads, respectively.

[0216] In this case, the insulating substrate 80, for example, has a set of gate pads 91b', OC pads 92', anode pads 93a', and cathode pads 93b' shared by the first semiconductor chip 10a and the second semiconductor chip 10b that are adjacent to each other along the second direction Y. The gate pads 91b' of the insulating substrate 80 are electrically connected to each other through wiring 96'. Alternatively, resistors 94a' and 94b' can be electrically connected to the gate pads 91b' of the insulating substrate 80 through wirings 95a' and 95b', so that the resistive and / or reactive components among the gate pads 21b of the parallel-connected semiconductor chips 10 are substantially uniform.

[0217] In addition, such as Figure 8As shown, when four semiconductor chips 10 (10a, 10b) are arranged in a matrix on the copper plate 82 of the insulating substrate 80, the spacing between all adjacent semiconductor chips 10 is equal. Therefore, instead of implanted pins 86, the source pads 21a of semiconductor chips 10 adjacent to each other along the first direction X and the source pads 21a of semiconductor chips 10 adjacent to each other along the second direction Y can be electrically connected to each other, for example, via leads 86'. As a result, the resistive and / or reactive components among the source pads 21a of the parallel-connected semiconductor chips 10 can be made substantially uniform.

[0218] In addition, such as Figure 9 As shown, a portion of the implanted pins 86 that are connected to the source pads 21a of the semiconductor chip 10 can also be used. Figure 9 The implanted pin 86a is bent into, for example, an L-shape. By setting the implanted pin 86a into a bent shape in this way, a reactive component is added to the implanted pin 86a. Thus, even if the spacing between adjacent semiconductor chips 10 is not equal, the reactive component between the source pads 21a of the parallel-connected semiconductor chips 10 can be adjusted to be approximately uniform.

[0219] Although the illustration is omitted, it can also be configured such that the implanted pins 87, which are respectively bonded to the gate pad 21b, OC pad 22, anode pad 23a, and cathode pad 23b of the semiconductor chip, are bent into an L-shape. In this case, for example, instead of the electrical connection resistors 94a' and 94b' of the gate pad 91b, OC pad 92, anode pad 93a, and cathode pad 93b on the printed circuit board 90, the resistance and / or reactance components between the same type of electrode pads of the parallel-connected semiconductor chip 10 can be adjusted to be approximately uniform by utilizing the different lengths of the L-shaped implanted pins 87.

[0220] The operation of the semiconductor circuit device 100 according to Embodiment 1 will be described. Figure 10 This is a circuit diagram showing the equivalent circuit of the semiconductor circuit device according to Embodiment 1. For example... Figure 10 As shown, semiconductor devices 20 are fabricated on all semiconductor chips 10 on the insulating substrate 80. Each semiconductor device 20 includes a main semiconductor element 11 and a current sensing unit 12 connected in parallel with the main semiconductor element 11. In each semiconductor chip 10, the source terminal (source pad 21a) of the main semiconductor element 11 is electrically connected to the source terminal S of the ground potential of the ground point GND via the source wiring 17.

[0221] A resistor 15, serving as an external component, is connected between the source of the current sensing unit 12 and the ground point GND. The drain (drain pad) of the main semiconductor element 11 is connected to the drain terminal D via the drain wiring 18. The gate of the main semiconductor element 11 is connected to the gate terminal G via the gate resistor 16 and the gate wiring 19. Thus, all the main semiconductor elements 11 of the semiconductor chips 10 that constitute the semiconductor circuit device 100 are connected between the drain wiring 18 and the source wiring 17, forming a parallel connection of multiple main semiconductor elements 11.

[0222] In relation to the main semiconductor element 11 (reference) Figure 4 , Figure 5 If a positive voltage is applied to the source of the main semiconductor element 11 and the drain (drain electrode 51) is applied to the gate (gate electrode 39a) of the main semiconductor element 11, and a voltage greater than or equal to the gate threshold voltage Vth is applied to the gate of the main semiconductor element 11, then the p-type base region 34a of the main semiconductor element 11 will be affected by the n-type gate voltage. + An n-type inversion layer (channel) is formed in the portion sandwiched between the source region 35a and the n-type current diffusion region 33a. As a result, the main current flows from the drain to the source of the main semiconductor element 11, and the main semiconductor element 11 is turned on.

[0223] At this time, if, under the same conditions as the main semiconductor element 11, a positive voltage is applied to the drain (drain electrode 51) relative to the source (OC pad 22) of the current sensing unit 12, and a voltage above the gate threshold voltage is applied to the gate electrode 39b of the current sensing unit 12, then the n-type base region 34b of the sensing effective region 12a will be affected. + An n-type inversion layer is formed in the portion sandwiched between the source region 35b and the n-type current diffusion region 33b. As a result, the sensing current flows from the drain of the current sensing unit 12 to the source, and the current sensing unit 12 is turned on.

[0224] The sensed current flows to the ground point GND through the resistor 15 connected to the source of the current sensing unit 12. This generates a voltage drop across the resistor 15. When current flows through the main semiconductor element 11, the sensed current flowing through the current sensing unit 12 increases depending on the magnitude of the overcurrent flowing through the main semiconductor element 11, and the voltage drop across the resistor 15, caused by the sensed current flowing through it, also increases. By monitoring the magnitude of this voltage drop across the resistor 15, the overcurrent flowing through the main semiconductor element 11 can be detected.

[0225] On the other hand, when a voltage less than the gate threshold voltage Vth is applied to the gate electrode 39a of the main semiconductor element 11, the first p of the main semiconductor element 11... + Type region 61a, second p + Type 62a and n-type current diffusion regions 33a and n -The pn junction between the drift regions 32 is reverse biased. A voltage less than the gate threshold voltage is also applied to the gate electrode 39b of the current sensing unit 12, and the first pn junction of the current sensing unit 12... + Type region 61b, second p + Type 62b and n-type current diffusion region 33b, n - The pn junction between the drift regions 32 is also reverse biased. As a result, the main semiconductor element 11 and the current sensing unit 12 remain in the off state.

[0226] Figure 10 Gate wiring 19 is equivalent to Figures 6-8 Wiring 96, 96'. As described above, in Embodiment 1, the length of gate wiring 19 (wiring 96, 96') is longer than that of wiring 234 in the existing structure (see reference). Figure 21 The length of the semiconductor chip 10 is short. Furthermore, the resistive and / or reactive components between the gate pads 21b of the parallel-connected semiconductor chips 10 become approximately uniform. Therefore, when the semiconductor circuit device 100 is turned off, deviations in the gate threshold voltage Vth of each main semiconductor element 11 fabricated on each semiconductor chip 10 can be suppressed, and thus the voltage waveform 133 of the gate voltage Vg of the semiconductor circuit device 100 is less prone to vibration.

[0227] Therefore, in the main semiconductor element 11 of each semiconductor chip 10 of the semiconductor circuit device 100, the rising edge of the voltage waveform of the drain-source voltage Vds during turn-off can be made approximately the same, and the drain potential at the connection points 100a to 100d between the main semiconductor element 11 of each semiconductor chip 10 and the drain wiring 18 can be made approximately the same. As a result, the voltage waveform 132 of the drain-source voltage Vds of the semiconductor circuit device 100 is less prone to oscillation. Therefore, the oscillation of the current waveform 131 of the drain-source current Ids during turn-off of the semiconductor circuit device 100 can be suppressed (see below). Figure 19 ).

[0228] Next, the manufacturing method of the semiconductor device 20 fabricated on the semiconductor chip 10 will be described. The semiconductor chip 10 is mounted on the insulating substrate 80 of the semiconductor circuit device 100 of Embodiment 1 (see reference 1). Figures 6-9 ). Figures 11-16 This is a cross-sectional view showing the state of a semiconductor chip assembled on an insulating substrate of the semiconductor circuit device of Embodiment 1 during manufacturing. Although in Figures 11-16 Only the main semiconductor element 11 is shown, but the various parts of all the elements fabricated on the same semiconductor chip 10 are formed simultaneously with the various parts of the main semiconductor element 11.

[0229] First, such as Figure 11 As shown, n is prepared from silicon carbide.+ Type-based starting substrate (semiconductor wafer) 31. n + The initial substrate 31 can be, for example, a nitrogen (N)-doped silicon carbide single-crystal substrate. Next, on the n... + The front side of the type-initiating substrate 31 is doped with a ratio of n + The low concentration of nitrogen in the initiator substrate 31 - The silicon carbide layer 71 is epitaxially grown. With the main semiconductor device 11 having a voltage rating of 3300V, n... - The thickness t1 of the silicon carbide layer 71 can be, for example, around 30 μm.

[0230] Next, as Figure 12 As shown, through photolithography and ion implantation of p-type impurities such as Al, the n-type impurities are implanted in the main effective region 1a. - The surface regions of the silicon carbide layer 71 are selectively formed with first p-type silicon carbide. + Type regions 61a and p + Type region 101. First p + Type regions 61a and p + Type region 101, for example, in the first direction X (depth direction: refer to...) Figure 4 Alternately repeat the configuration on the second direction Y (lateral: reference) Figure 4 It extends in a striped pattern.

[0231] Next, through photolithography and ion implantation of n-type impurities such as nitrogen, the entire region of the main effective region 1a is thus covered while in the n - An n-type region 102 is formed on the surface region of the silicon carbide layer 71. In the first p... + Type region 61a and p + Between type 101, and between type n region 102 and these p + The n-type regions 61a and 101 are formed by contact. Alternatively, n-type regions 102 and p can be interchanged. + The formation sequence of type regions 61a and 101.

[0232] adjacent p + The distance d2 between type regions 61a and 101 is, for example, about 1.5 μm. + For example, the depth d1 and impurity concentration in regions 61a and 101 are approximately 0.5 μm and 5.0 × 10⁻⁶, respectively. 18 / cm 3 The depth d3 and impurity concentration of the n-type region 102 are, for example, approximately 0.4 μm and 1.0 × 10⁻⁶ μm, respectively. 17 / cm 3 Left and right. - The portion of the silicon carbide layer 71 that has not been ion implanted is called n. -Type drift zone 32.

[0233] Next, as Figure 13 As shown, in n - On the silicon carbide layer 71, n-type impurities such as nitrogen are further doped with an n-type impurity, for example, at a thickness t2 of about 0.5 μm. - Epitaxial growth of type-n silicon carbide layer, thereby enabling n - The thickness of the p-type silicon carbide layer 71 increases. Then, through photolithography and ion implantation of p-type impurities such as Al, the thickness of the n-type silicon carbide layer increases. - The increased thickness portion 71a of the silicon carbide layer 71 is selectively formed to reach p. + p in type region 101 + Type 103.

[0234] Next, through photolithography and ion implantation of n-type impurities such as nitrogen, n-type impurities are implanted. - The increased thickness portion 71a of the silicon carbide layer 71 is selectively formed into an n-type region 104 that reaches the n-type region 102. + Regions 101 and 103 are connected to form the second p. + The n-type regions 62a and 102 and 104 are interconnected to form the n-type current diffusion region 33a. Alternatively, p can be interchanged. + The formation order of type 103 and n-type region 104.

[0235] Next, as Figure 14 As shown, in n - On the p-type silicon carbide layer 71, a p-type silicon carbide layer 72 doped with p-type impurities such as Al is epitaxially grown. The thickness t3 and impurity concentration of the p-type silicon carbide layer 72 are, for example, approximately 1.3 μm and 4.0 × 10⁻⁶ μm, respectively. 17 / cm 3 Left and right. Through the processes up to this point, the product in n is thus created. + n-type starting substrate 31 are sequentially laminated - Semiconductor wafer with p-type silicon carbide layer 71 and p-type silicon carbide layer 72.

[0236] Next, photolithography and ion implantation are performed as a group process under different conditions to selectively form n-type silicon carbide layers on the surface of the p-type silicon carbide layer 72 in the main effective region 1a. + Source regions 35a and p ++ Type contact region 36a. n of p-type silicon carbide layer 72 + Source region 35a and n - The portion between the silicon carbide layers 71 and p ++ Type contact area 36a and n - The portion between the p-type silicon carbide layers 71 becomes the p-type base region 34a.

[0237] Next, regarding the diffusion region (first p) formed by ion implantation... + Type region 61a, second p + Type 62a, n-type current diffusion region 33a, n + Source region 35a and p ++ The contact area 36a is subjected to heat treatment (activation annealing) at a temperature of approximately 1700°C for about two minutes, for example, for impurity activation. Activation annealing can be performed all at once after all diffusion regions have been formed, or it can be performed each time a diffusion region is formed by ion implantation.

[0238] Next, as Figure 15 As shown, trench 37a is formed by photolithography and etching, and trench 37a extends through the front side of the semiconductor wafer. + The source region 35a and the p-type base region 34a reach the n-type current diffusion region 33a, and in the depth direction Z (longitudinal: see reference) Figure 4 ) and the first p + Type region 61a is opposite. Trench 37a, for example, can reach the first p. + Type region 61a terminates at the first p + The interior of type region 61a.

[0239] Next, as Figure 16 As shown, a gate insulating film 38a is formed along the front side of the semiconductor wafer and the inner wall of the trench 37a. The gate insulating film 38a can be, for example, a thermally oxidized film formed at a temperature of about 1000°C in an oxygen (O2) atmosphere, or a deposited film based on high-temperature oxidation (HTO). Next, a polycrystalline silicon layer, for example, doped with phosphorus, is formed on the front side of the semiconductor wafer in a manner that embeds it into the interior of the trench 37a.

[0240] Next, the polysilicon layer is selectively removed, leaving a portion of the polysilicon layer remaining inside the trench 37a, which becomes the gate electrode 39a. As described above, during the formation of the main semiconductor element 11, all components that should be fabricated on the semiconductor wafer (such as the current sensing unit 12, temperature sensing unit 13, and other high-functionality units; see reference 11) are formed simultaneously with each part of the main semiconductor element 11. Figure 4 , Figure 5 Next, an interlayer insulating film 40 is formed on the entire front side of the semiconductor wafer.

[0241] The main semiconductor element 11 is disposed within an island-shaped p-type base region 34a formed on the surface region of the front side of the semiconductor wafer, and is connected to the n-type base region 34a. -The pn junction of the p-type drift region 32 is separated from all components fabricated on the semiconductor wafer. The current sensing unit 12 can be arranged in the island-shaped p-type base region 34b formed on the surface region of the front side of the semiconductor wafer with the same structure as the main semiconductor element 11.

[0242] Additionally, as a temperature sensing unit 13, for example, a p-type polysilicon layer 73 and an n-type polysilicon layer 74 are formed on the front side of a semiconductor wafer (see reference). Figure 4 The pn junction diode is formed by covering the p-type polysilicon layer 73 and the n-type polysilicon layer 74 with an interlayer insulating film 75. Then, the interlayer insulating film 40 and the gate insulating film 38a are selectively removed by photolithography and etching to form the first to fourth contact holes 40a, 40b, 75a, and 75b.

[0243] Make the n of the main semiconductor element 11 + Source regions 35a and p ++ The contact area 36a is exposed in the first contact hole 40a. This exposes the n-type contact area of ​​the current sensing unit 12. + Source region 35b and p ++ The p-type contact area 36b is exposed in the second contact hole 40b. The p-type polysilicon layer 73 and the n-type polysilicon layer 74 are then exposed in the third contact hole 75a and the fourth contact hole 75b, respectively. Next, the interlayer insulating films 40 and 75 are planarized by heat treatment (reflow soldering).

[0244] Next, a first TiN film 42a is formed, covering only the interlayer insulating film 40. Then, a NiSi film 41a, making ohmic contact with the front side of the semiconductor wafer, is formed on the portion exposed by the first contact hole 40a. Next, a first Ti film 43a, a second TiN film 44a, and a second Ti film 45a are sequentially deposited on the front side of the semiconductor wafer, covering the NiSi film 41a and the first TiN film 42a, to form a barrier metal 46a. Then, source pads 21a are deposited on the second Ti film 45a.

[0245] Furthermore, within the second contact hole 40b, a NiSi film 41b and a barrier metal 46b are formed simultaneously with the NiSi film 41a and the barrier metal 46a within the first contact hole 40a, respectively, with the same configuration as the NiSi film 41a and the barrier metal 46a. Additionally, within the second to fourth contact holes 40b, 75a, and 75b, respectively, an OC pad 22, an anode pad 23a, and a cathode pad 23b are formed simultaneously with the source pad 21a, respectively, with the same configuration as the source pad 21a.

[0246] Next, a drain electrode 51 is formed to make ohmic contact with the back side of the semiconductor wafer. A drain pad (not shown) is formed by sequentially depositing, for example, a Ti film, a Ni film, and a gold (Au) film on the surface of the drain electrode 51. Next, first protective films 49a-49c and 49e made of polyimide are selectively formed on the front side of the semiconductor wafer, exposing the different electrode pads 21a, 21b, 22, 23a, and 23b at the openings of these first protective films 49a-49c and 49e. Then, conventional pre-plating treatment is performed.

[0247] Next, through conventional plating processes, plating films 47a-47e are formed on the portions of electrode pads 21a, 21b, 22, 23a, 23b exposed at the openings of the first protective films 49a-49c, 49e. Then, a heat treatment (baking) is performed to dry the plating films 47a-47e. Next, second protective films 50a-50c, 50e, made of polyimide, are formed, covering the boundaries between the plating films 47a-47e and the first protective films 49a-49c, 49e.

[0248] Next, a heat treatment (curing) is performed to improve the strength of the polyimide films (first protective films 49a-49c, 49e and second protective films 50a-50c, 50e). Then, solder layers ( Figure 9 The terminal pins 48a to 48e are connected using the symbol 85. Next, the semiconductor wafer is monolithically divided into individual chips by cutting (slicing) it, thus completing the process. Figures 1-5 The semiconductor chip 10 shown is used to fabricate the semiconductor device 20.

[0249] The layout of the electrode pads on the front side of the semiconductor chip 10 is determined based on the overall layout of the plurality of semiconductor chips 10 on the insulating substrate 80. Subsequently, the plurality of semiconductor chips 10 are mounted on the insulating substrate 80 using conventional methods, such that the electrode pads on the front side of the semiconductor chips 10 are electrically connected to the electrode pads of the printed circuit board 90. Then, the various portions of the insulating substrate 80 are sealed using a sealing material 89, thereby completing the process. Figures 6-9 The semiconductor circuit device 100 shown.

[0250] As described above, according to Embodiment 1, based on the overall layout of the semiconductor chips mounted on the insulating substrate, the layout of the electrode pads on the front side of the semiconductor chips is configured differently in at least one of all the semiconductor chips mounted on the insulating substrate. This allows semiconductor chips to be mounted on the insulating substrate in a manner that minimizes the length of the wiring connecting the main semiconductor elements in parallel, or in a manner that makes the resistive and / or reactive components generated by the wiring substantially uniform among the same type of electrode pads of the multiple semiconductor chips connected in parallel, or in a manner that satisfies both of these requirements.

[0251] Therefore, when the semiconductor circuit device is turned off, deviations in the gate threshold voltage of each main semiconductor element fabricated in each semiconductor chip can be suppressed, and the voltage waveform of the gate voltage of the semiconductor circuit device can be made less prone to vibration. Consequently, the rising edges of the drain-source voltage waveform during turn-off can be made approximately the same in the main semiconductor elements of each semiconductor chip, and the voltage waveform of the drain-source voltage of the semiconductor circuit device can be made less prone to vibration. Therefore, vibration of the drain-source current waveform during turn-off of the semiconductor circuit device can be suppressed.

[0252] (Implementation Method Two)

[0253] Next, the semiconductor circuit device according to Embodiment 2 will be described. Figure 17 , Figure 18 This is a top view showing an example of the layout of the semiconductor chip mounted on the insulating substrate of the semiconductor circuit device of Embodiment 2, viewed from the front side. The semiconductor chip 120 mounted on the insulating substrate of the semiconductor circuit device of Embodiment 2 and the semiconductor chip 10 mounted on the insulating substrate of the semiconductor circuit device of Embodiment 1 (see reference) Figures 1-3 The difference is that the active region 1 of the same semiconductor chip 10 only has the main semiconductor element 11.

[0254] In Embodiment 2, the semiconductor chip 120 mounted on an insulating substrate of a semiconductor circuit device has only a gate pad 121b in the main invalid region 111b. Therefore, compared to the case where the semiconductor chip 120, identical to the main semiconductor element 11, is configured as a high-function section for protecting and controlling the circuit section of the main semiconductor element 11, the surface area of ​​the main invalid region 1b is smaller. As a result, when electrode pads (here, the gate pad 121b) are partially disposed on the front side of the semiconductor chip 120, Embodiment 1 described above can be applied.

[0255] The layout of the electrode pads (source pads 121a, 121a' and gate pads 121b, 121b') on the front side of the semiconductor chip 120 is different in at least one of the multiple semiconductor chips 120, and there are more than two patterns (see reference). Figure 17 , Figure 18 The main active regions 111a and 111a' may have a generally rectangular planar shape, for example, with a portion recessed inward. The planar shape of the source pads 121a and 121a' is, for example, generally the same as the planar shape of the main active regions 111a and 111a'.

[0256] The primary invalid regions 111b and 111b' are, for example, disposed in the recesses of the primary valid regions 111a and 111a'. The primary invalid region 111b may be a planar shape that is disposed on one side of the boundary of a generally rectangular area between the active region 1 and the edge terminal region 2 and is surrounded on three sides by the primary valid region 111a. Figure 17 The main invalid region 111b' can be a planar shape consisting of a vertex of the boundary of an approximate rectangle between the active region 1 and the edge terminal region 2, and surrounded on both sides by the main valid region 111a'. Figure 18 ).

[0257] The cross-sectional structure of the main effective regions 111a and 111a' of the semiconductor chip 120 and Figure 4 The cross-sectional structure at the cut lines X1-X2 is the same. The cross-sectional structure of the main invalid regions 111b and 111b' (gate pad portion 14) of the semiconductor chip 120 is the same as that of the cut lines X1-X2. Figure 5 The cross-sectional structure at the cut line Y2-Y3 is the same. The semiconductor circuit device of Embodiment 2 (with multiple semiconductor chips 120 mounted on an insulating substrate) has the same configuration as the semiconductor circuit device 100 of Embodiment 1 (see reference 100) except for the layout of the electrode pads on the front side of the semiconductor chips 120. Figures 6-9 )same.

[0258] As described above, according to Embodiment 2, when two or more electrode pads are arranged in a predetermined layout on the front side of a semiconductor chip mounted on an insulating substrate, the same effect as in Embodiment 1 can be obtained.

[0259] (Example)

[0260] Regarding the semiconductor circuit device 100 of the above-described embodiment 1 (refer to...) Figures 1-10 The current waveform was verified. Figure 19 This is a characteristic diagram showing the voltage and current waveforms when the embodiment is turned off. Figure 20 This is a characteristic diagram showing the voltage and current waveforms during the turn-off of an existing example. Figure 19 The semiconductor circuit device 100 of the above-described embodiment 1 is shown (hereinafter referred to as an example: see reference). Figure 1 , 2 The waveforms of the drain-source current Ids, the drain-source voltage Vds, and the gate voltage Vg during turn-off are shown in Figures 131, 132, and 133, respectively.

[0261] In comparison, Figure 20 An existing semiconductor circuit device 200 is shown (hereinafter, it is assumed to be an existing example: see reference). Figure 21 , Figure 22 The waveforms of the drain-source current Ids, drain-source voltage Vds, and gate voltage Vg during turn-off are shown in Figure 141 and 143, respectively. In the conventional example, the overall layout of all semiconductor chips 210 mounted on the insulating substrate 220 and the layout of the electrode pads (source pad 211a, gate pad 211b, OC pad 212, anode pad 213a, and cathode pad 213b) on the front side of the semiconductor chips 210 differ from the embodiment.

[0262] according to Figure 19 The results shown confirm that the embodiment can suppress deviations in the gate threshold voltage Vth of each main semiconductor element 11 fabricated in each semiconductor chip 10 during shutdown, and that the voltage waveform 133 of the gate voltage Vg of the semiconductor circuit device 100 is less prone to vibration. The reason for this is presumably because, in the embodiment, the gate wiring 19 (wiring 96, 96': see...) Figure 6 , Figure 10 The length of the wiring is greater than that of the existing example wiring 234 (see reference). Figure 21 The length of the semiconductor chip 10 is short, and the resistive and / or reactive components between the gate pads 21b of the parallel-connected semiconductor chip 10 are approximately uniform.

[0263] Therefore, it was confirmed that in the embodiment, each main semiconductor element 11 can make the rising edge of the voltage waveform of the drain-source voltage Vds during turn-off approximately the same, and can make the connection points 100a to 100d of each main semiconductor element 11 with the drain wiring 18 (refer to) Figure 10 The drain potential at the location is approximately the same. Thus, it is confirmed that the voltage waveform 132 of the drain-source voltage Vds of the embodiment (semiconductor circuit device 100) is less prone to vibration, and the vibration of the current waveform 131 of the drain-source current Ids during turn-off can be suppressed.

[0264] On the other hand, according to Figure 20The results show that the current waveform 141 of the drain-source current Ids, the voltage waveform 142 of the drain-source voltage Vds, and the voltage waveform 143 of the gate voltage Vg all vibrate when the prior art (semiconductor circuit device 200) is turned off. This is because in the prior art, the resistive and / or reactive components of the wiring 234 are adversely affected, resulting in deviations in the gate threshold voltage Vth of each main semiconductor element fabricated from each semiconductor chip 210. Consequently, the rising edge of the voltage waveform of the drain-source voltage Vds of each main semiconductor element becomes different, and therefore the overall voltage waveform 142 of the drain-source voltage Vds in the prior art is prone to vibration.

[0265] The present invention is not limited to the embodiments described above, and various modifications can be made without departing from the spirit of the invention. Furthermore, the present invention can also be applied when a wide-bandgap semiconductor other than silicon carbide and / or silicon is used instead of silicon carbide as the semiconductor material. Additionally, the present invention also applies even when the conductivity type (n-type, p-type) is reversed.

[0266] Industrial availability

[0267] As described above, the semiconductor device of the present invention is useful for semiconductor circuit devices in which multiple (two or more) semiconductor chips are mounted on a mounting substrate and semiconductor devices with the same current capability, which are respectively fabricated from these multiple semiconductor chips, are connected in parallel.

Claims

1. A semiconductor circuit device, characterized in that, have: Multiple semiconductor chips, which are composed of semiconductors with a bandgap wider than that of silicon; Multiple semiconductor elements are respectively disposed on multiple semiconductor chips; Multiple electrode pads are arranged separately from each other on the front side of each of the multiple semiconductor chips and are electrically connected to different semiconductor elements respectively; A first substrate having a plurality of said semiconductor chips bonded thereto, the semiconductor chips being separate from each other; as well as Metal components, which connect electrode pads that are connected to the same portions of the semiconductor elements in parallel among a plurality of said semiconductor chips, The layout of the electrode pads of at least one of the plurality of semiconductor chips differs from the layout of the electrode pads of the remaining semiconductor chips. In a predetermined layout where the resistive components are uniform, or the reactive components are uniform, or both resistive and reactive components are uniform among the electrode pads connected in parallel via the metal components, the layout of the electrode pads on the front side of the semiconductor chip and the layout of the plurality of semiconductor chips on the first substrate are defined. By arranging the electrode pads connected in parallel via the metal components at equal distances on the first substrate, the resistive components, or the reactive components, or both resistive and reactive components among the electrode pads connected in parallel via the metal components are made uniform.

2. The semiconductor circuit device according to claim 1, characterized in that, The metal component is a metal lead.

3. The semiconductor circuit device according to claim 1, characterized in that, The metal components are terminal pins that lead out the potential of the electrode pads, and metal wiring formed on a second substrate disposed opposite to the front side of the plurality of semiconductor chips. Among the plurality of semiconductor chips, different terminal pins are respectively bonded to the electrode pads that are connected to the same portion of the semiconductor element, and the different terminal pins are connected via the metal wiring.

4. The semiconductor circuit device according to claim 3, characterized in that, The semiconductor circuit device also includes a resistor formed on the second substrate and electrically connected to the metal wiring.

5. The semiconductor circuit device according to claim 3 or 4, characterized in that, Multiple terminal pins are bonded to the same electrode pad. A portion of the terminal pins that are coupled to the same electrode pads are provided with a reactive component, which is formed by partially bending that portion.

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