Method for forming a semiconductor device

Abstract

Aspects of the present disclosure provide a method for semiconductor device manufacturing. The method includes forming a vertical structure in a layer stack with an end in a first layer by processing a first side of a first die. The first layer has a better etch selectivity for the layer stack than a second layer. The method also includes replacing the first layer with the second layer by processing a second side of the first die opposite the first side.

Description

Technical Field

[0001] This application describes embodiments that generally relate to manufacturing processes for semiconductor devices. Background Technology

[0002] Semiconductor manufacturers have developed vertical device technologies such as 3D NAND flash memory to achieve higher transistor density without requiring smaller transistors. In some examples, 3D NAND storage devices comprise arrays of vertically connected strings of memory cells. Each vertical string of memory cells includes multiple memory cells connected in series. Increasing the number of memory cells in a vertical string of memory cells increases data storage density. Summary of the Invention

[0003] This disclosure provides a method for manufacturing a semiconductor device. The method includes: forming a vertical structure in a stack by processing a first side of a first die, wherein an end of the vertical structure is in a first layer. The first layer has better etch selectivity for the stack compared to a second layer. The method further includes: replacing the first layer with the second layer by processing a second side of the first die opposite to the first side.

[0004] In some examples, the first layer comprises tungsten, and the second layer comprises a semiconductor layer such as a polycrystalline silicon layer.

[0005] According to one aspect of this disclosure, the vertical structure corresponds to a channel structure, and an initial first layer stack includes the first layer in a core region. The stack corresponds to an initial second layer stack. The method then includes: forming the initial second layer stack, the initial second layer stack including an insulating layer and a sacrificial gate layer alternately stacked over the initial first layer stack.

[0006] In some examples, the method includes: forming a channel aperture in the initial second-layer stack, wherein the end of the channel aperture is in the first layer; and forming a channel structure in the channel aperture. Specifically, in some examples, the channel structure includes a channel layer encased within a barrier insulating layer, a charge storage layer, and a tunneling insulating layer. Replacing the first layer with the second layer then further includes: removing the first layer by performing the processing on the second side; and removing the barrier insulating layer, the charge storage layer, and the tunneling insulating layer from the end of the channel structure by performing the processing on the second side.

[0007] In some examples, to replace the first layer with the second layer, the method includes forming a second layer in contact with the channel layer at the end of the channel structure. For example, the method may include forming a semiconductor layer in contact with the channel layer at the end of the channel structure by performing the processing on the second side. Specifically, in one example, the method includes forming a liner portion of the semiconductor layer. The liner portion contacts the channel layer at the end of the channel structure. The method then includes performing ion implantation to dope the liner portion and forming a body portion of the semiconductor layer. Furthermore, the method includes forming a pad structure on the second side, the pad structure being electrically connected to the semiconductor layer.

[0008] According to another aspect of this disclosure, the vertical structure corresponds to a dummy channel structure, and the initial first layer stack includes the first layer in the stepped region. In some examples, the stack corresponds to an initial second layer stack, the method comprising: forming the initial second layer stack including an insulating layer and a sacrificial gate layer alternately stacked above the initial first layer stack; and forming a stepped step based on the initial second layer stack in the stepped region. Furthermore, the method comprises: planarizing the stepped region using an insulating material. Then, the method comprises: forming a dummy channel via in the insulating material and the initial second layer stack. The end of the dummy channel via is in the first layer. Then, the method comprises: forming the dummy channel structure in the dummy channel via.

[0009] According to another aspect of this disclosure, the vertical structure corresponds to a gate line gap structure, and the initial first layer stack includes the first layer in the gate line gap region. The stack corresponds to an initial second layer stack, and the method further includes: forming the initial second layer stack, the initial second layer stack including an insulating layer and a sacrificial gate layer alternately stacked over the initial first layer stack. The method then includes: forming a channel structure in the initial second layer stack; forming a trench in the initial second layer stack, the ends of the trench being in the first layer; replacing the sacrificial gate layer with a gate layer through the trench; and forming the gate line gap structure in the trench.

[0010] According to another aspect of this disclosure, the method includes forming a punch-through contact structure in a punch-through region by processing a first side of the first die. In some examples, the method includes forming a bonding structure on the first side of the first die and bonding the first side to a second die prior to the processing of the second side of the first die. In one example, the method includes forming a through-silicon contact by processing the second side of the first die. The through-silicon contact electrically connects the punch-through contact structure to a pad structure on the second side of the first die.

[0011] This disclosure provides various aspects of layout designs used in methods for manufacturing semiconductor devices.

[0012] Various aspects of this disclosure provide semiconductor devices and memory device systems manufactured according to methods for manufacturing semiconductor devices. Attached Figure Description

[0013] The various aspects of this disclosure can be best understood through the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0014] Figure 1A-1B A cross-sectional view of a semiconductor device 100 according to some embodiments of the present disclosure is shown.

[0015] Figure 2A-2C The pattern layout used to define the stop layer is shown.

[0016] Figure 3 A flowchart is shown to outline process 300 in some examples.

[0017] Figure 4A-4P Cross-sectional views of array dies in a semiconductor device at various intermediate steps of wafer-level fabrication, according to some embodiments, are shown.

[0018] Figure 5 A block diagram of a storage system device according to some examples of this disclosure is shown. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which other features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples within this disclosure. Such repetition is merely for simplicity and clarity, and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” “above,” etc., are used herein to describe the relationship of an element or feature as shown in the figures to one or more other elements or features. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0021] According to some aspects of this disclosure, vertical device technology forms vertical structures such as channel structures, dummy channel structures, gate line slot structures, etc., in three-dimensional (3D) NAND flash memory on a wafer. In some examples, vertical structures can be formed in openings (e.g., holes or trenches etched into a layer on a first side (also called the front side) of the wafer). The etching process forming these holes or trenches can affect the depth uniformity of the holes. As the height of the vertical structure increases (e.g., to increase the number of memory cells in a vertical memory cell string), the depth of the holes or trenches becomes difficult to control, and the depth uniformity of the holes or trenches may be poor. When the depth uniformity of the holes or trenches is poor, the ends of the vertical structure have poor depth uniformity, which can lead to significant changes in the electronic characteristics of the device. Some semiconductor technologies use front-side processing and back-side processing to form structures on both sides of the wafer. Poor depth uniformity at the ends of the vertical structure can lead to difficulties in back-side processing.

[0022] Some aspects of this disclosure provide techniques for improving depth control and depth uniformity at the ends of vertical structures, thereby increasing process margins and simplifying back-side processing.

[0023] According to some aspects of this disclosure, a stop layer can be formed beneath the laminate used to form the vertical structure in the region. The vertical structure can be formed by etching holes or trenches into the laminate and filling the holes or trenches with the material of the vertical structure. Etching of the holes or trenches can be stopped in the stop layer. The etching characteristics of the stop layer can be used to control the depth at the ends of the vertical structure. In some examples using back-side processing, the stop layer can be removed by back-side processing, and the stop layer can be replaced with another layer that is a functional layer but has inferior etching characteristics to the stop layer.

[0024] For example, in 3D NAND flash memory technology, a channel structure is formed in a stack, wherein the ends of the channel structure are in a semiconductor layer. In some examples, the semiconductor layer can be used to form an array common source. However, the etching characteristics of the semiconductor layer may lead to poor depth control and poor depth uniformity during the etching process used to form holes for the channel structure in the stack. In some examples, a stop layer can be formed under the stack, wherein the stop layer has better etching characteristics than the semiconductor layer, for example, better etch selectivity to the stack compared to the semiconductor layer. In one example, the semiconductor layer is a polysilicon layer, and the stop layer comprises tungsten. It should be noted that other suitable materials with better etch selectivity to the stack than polysilicon layers can be used in the stop layer. Holes can be etched through the stack and terminated in the stop layer, thereby achieving better depth control and better depth uniformity. After the channel structure is formed, a back-side processing can be used to replace the stop layer with a semiconductor layer.

[0025] Figure 1A-1B A cross-sectional view of a semiconductor device 100 according to some embodiments of the present disclosure is shown. Figure 1A It shows along Figure 1B The diagram shows a cross-sectional view of the semiconductor device 100 along line A'A. Figure 1B It shows along Figure 1A The diagram shows a cross-sectional view of the semiconductor device 100 along line B'B. It should be noted that features are not drawn to scale for ease of explanation.

[0026] like Figure 1A-1B As shown, the semiconductor device 100 includes multiple regions and vertical structures formed in said multiple regions. Specifically, the semiconductor device 100 includes a core region 101 and a channel structure 130 formed in the core region 101; the semiconductor device 100 includes a stepped region 102 and a dummy channel structure 150 formed in the stepped region 102; the semiconductor device 100 includes a gate line gap region 103 and a gate line gap structure 140 formed in the gate line gap region 103.

[0027] According to some aspects of this disclosure, at least one type of vertical structure can be formed using a stop layer to achieve depth control and better depth uniformity in the vertical structure, and then the stop layer can be replaced with a functional layer. In one example, a stop layer is formed in a core region 101 to achieve depth control and better depth uniformity in a channel structure 130. In another example, a stop layer is formed in a stepped region 102 to achieve depth control and better depth uniformity in a dummy channel structure 150. In yet another example, a stop layer is formed in a gate line gap region 103 to achieve depth control and better depth uniformity in a gate line gap structure 140.

[0028] In some examples, stop layers are formed in multiple regions to achieve depth control and better depth uniformity in various types of vertical structures. In one example, stop layers are formed in core region 101, stepped region 102, and gate line slot region 103 to achieve depth control and better depth uniformity for channel structure 130, dummy channel structure 150, and gate line slot structure 140, respectively. It should be noted that although the following description uses the example of using stop layers in core region 101, stepped region 102, and gate line slot region 103 to illustrate techniques for depth control and uniformity control, the techniques shown can be appropriately adapted for other examples.

[0029] It should be noted that, although Figure 1A Semiconductor device 100 is shown to include a die, but semiconductor device 100 may include one or more other dies not shown. In some examples, semiconductor device 100 includes... Figure 1A The first die shown, and a second die (not shown) bonded face-to-face (e.g., face to face). For example, the first die ( Figure 1A and Figure 1B The first die (shown in the diagram) includes an array of memory cells formed on the front side, and the second die (not shown) includes peripheral circuitry formed on the front side, and the second die (not shown) (can be referred to as a peripheral die). In some examples, complementary metal-oxide-semiconductor (CMOS) technology is used to form the peripheral circuitry, and the peripheral die is also referred to as a CMOS die.

[0030] It should be noted that in some other embodiments, the semiconductor device may include a plurality of array dies and CMOS dies. The plurality of array dies and CMOS dies may be stacked and bonded together. The CMOS dies are respectively coupled to the plurality of array dies and can drive the respective array dies.

[0031] Semiconductor device 100 can be any suitable scale (e.g., wafer scale, chip scale, package scale, etc.). In some examples (e.g., wafer scale), semiconductor device 100 includes at least a first wafer and a second wafer bonded face-to-face. Array dies are disposed on the first wafer along with other array dies, while CMOS dies are disposed on the second wafer along with other CMOS dies. The first and second wafers are bonded together, such that the array dies on the first wafer are bonded to corresponding CMOS dies on the second wafer. In some examples (e.g., chip scale), semiconductor device 100 is a chip having at least array dies and CMOS dies bonded together. In one example, the chip is diced from the bonded wafer. In another example (e.g., package scale), semiconductor device 100 is a semiconductor package including one or more semiconductor chips assembled on a package substrate.

[0032] Figure 1A The diagram shows the channel structure 130 in the core region 101, the gate line slot structure 140 in the gate line slot region 103, the dummy channel structure 150 in the stepped region 102, and the through contact structure 160 in the through region 104.

[0033] The channel structure 130 includes a body portion 132 formed in the second stack 120 and an end portion 131 in the first stack 110. The first stack 110 includes a semiconductor layer 111, which is formed by replacing the stop layer (not shown) with a back-side processing. The second stack 120 includes a gate layer 123 and an insulating layer 121 alternately stacked on the front side of the array die. The front and back sides are opposite each other.

[0034] In some embodiments, the channel structure 130 has a columnar shape extending in the Z direction, wherein the Z direction is perpendicular to the direction of the XY plane of the main surface. In one embodiment, the channel structure 130 is formed of a material that is circular (or elliptical or polygonal) in the XY plane, and the channel structure 130 extends in the Z direction. For example, the channel structure 130 includes functional layers such as a barrier insulating layer 133 (e.g., silicon oxide), a charge storage layer 134 (e.g., silicon nitride), a tunneling insulating layer 135 (e.g., silicon oxide), a semiconductor layer 136, and an insulating layer 137, wherein these functional layers are circular (or elliptical or polygonal) in the XY plane and extend in the Z direction. In one example, the barrier insulating layer 133 (e.g., silicon oxide) is formed on the sidewall of the channel hole for the channel structure 130, and then the charge storage layer 134 (e.g., silicon nitride), the tunneling insulating layer 135, the semiconductor layer 136, and the insulating layer 137 are sequentially stacked from the sidewall. Semiconductor layer 136 can be any suitable semiconductor material (e.g., polycrystalline silicon or monocrystalline silicon), and the semiconductor material can be undoped or may include p-type or n-type dopants. In some examples, the semiconductor material is undoped intrinsic silicon. However, due to defects, the intrinsic silicon material may have 10- dopants in some examples. 10 cm -3 The carrier density is on the order of magnitude. The insulating layer 137 is formed of an insulating material such as silicon oxide and / or silicon nitride, and / or the insulating layer 137 may be formed as an air gap.

[0035] According to some aspects of this disclosure, the channel structure 130 and the second stack 120 together form a vertical memory cell string. For example, the semiconductor layer 136 corresponds to the channel portion of a transistor in the memory cell string, while the gate layer 123 corresponds to the gate of a transistor in the vertical memory cell string. Typically, the transistor has a gate that controls the channel and a drain and a source on each side of the channel. For simplicity, in Figure 1A In the example, Figure 1A The upper side of the channel in a transistor is called the drain, while... Figure 1A The lower side of the channel in a transistor is called the source. It should be noted that the drain and source can be switched under certain drive configurations. Figure 1A In the example, semiconductor layer 136 corresponds to the connection channel of the transistor. For a particular transistor, the drain of that particular transistor is connected to the source of the upper transistor above it, and the source of that particular transistor is connected to the drain of the lower transistor below it. Therefore, the transistors in the vertical memory cell string are connected in series.

[0036] exist Figure 1AIn some examples, end 131 includes a semiconductor layer 136 and an insulating layer 137. In some examples, the barrier insulating layer 133, charge storage layer 134, and tunneling insulating layer 135 at end 131 are removed by back-side processing. In some examples, the initial end corresponding to end 131 also includes a barrier insulating layer 133, a charge storage layer 134, and a tunneling insulating layer 135. The initial end is formed in an initial first layer stack in core region 101, wherein the initial first layer stack has a stop layer (not shown). The stop layer can be removed by back-side processing. The barrier insulating layer 133, charge storage layer 134, and tunneling insulating layer 135 at the initial end can be removed by back-side processing. Furthermore, a semiconductor layer 111 can be formed by back-side processing.

[0037] According to some aspects of this disclosure, the semiconductor layer 136 at end 131 corresponds to the source terminal of the vertical memory cell string, and the semiconductor layer 111 in the first stack 110 is configured to connect the source terminal of the array of vertical memory cell strings to the array common source (ACS) terminal, as shown in P2. Figure 1A In one example, semiconductor layer 111 includes a body portion 112 and a pad portion 113 (e.g., a conformal portion). The pad portion 113 contacts semiconductor layer 136. In one example, the pad portion 113 can be doped by ion implantation to achieve a desired doping distribution. In another example, semiconductor layer 111 includes only the body portion 112 in contact with semiconductor layer 136. In some examples, semiconductor layer 111 is a silicon material such as doped polycrystalline silicon (e.g., N-type doped silicon, P-type doped silicon), etc.

[0038] exist Figure 1A-1B In one example, a gate line gap (GLS) structure 140 is formed in the second stack 120, wherein the ends of the GLS structure 140 are in the first stack 110. The GLS structure 140 can be used to facilitate the replacement of the sacrificial layer with the gate layer 123 in a post-gate process. In some examples, the GLS structure 140 is formed by filling trenches with one or more dielectric materials. In some examples, the GLS structure 140 extends through the second stack 120, and the GLS structure 140 can divide vertical memory cell strings (corresponding to channel structures 130) into separate blocks. In some examples, the vertical memory cell strings are configured to be erased block by block. Furthermore, the number and arrangement of the channel structures 130 between the GLS structures 140 can vary.

[0039] The ends of the GLS structure 140 are located in the first layer stack 110. In some examples, the ends of the GLS structure 140 are formed in the initial first layer stack within the gate line gap region 103, wherein the initial first layer stack has a stop layer (not shown). The stop layer can be removed by a back-side processing. Furthermore, a semiconductor layer 111 can be formed by a back-side processing.

[0040] It should be noted that in some examples (not shown), the GLS structure 140 may include conductive material (not shown) and may be configured to be used as an ACS terminal.

[0041] exist Figure 1A In the example, in the stepped region 102, the gate layer 123 and the insulating layer 121 are arranged in a stepped manner. For example, each stepped area may include one or more pairs consisting of the insulating layer 121 and the gate layer 123. The stepped region 102 is also filled with an insulating material 163 and is planarized along with other regions. Gate contact structures (not shown) may be disposed on the stepped areas and connected to the respective gate layers 123. The gate contact structures are used to connect drive circuitry to the respective gate layers 123 to control the stacked memory cells and select the gate.

[0042] exist Figure 1A-1B In one example, a dummy channel structure 150 is formed in a stepped region 102, wherein the end of the dummy channel structure 150 is in the first layer stack 110. The dummy channel structure 150 can prevent the second layer stack 120 from collapsing during the replacement of the sacrificial layer with the gate layer 123 in the post-gate process. The dummy channel structure 150 may include one or more dielectric materials. In one example, the dummy channel structure 150 may be disposed in the stepped region 102 between GLS structures 140. In another example, one or more dummy channel structures 150 may also be disposed in the core region 101.

[0043] The end of the dummy channel structure 150 is located in the first stack 110. In some examples, the end of the dummy channel structure 150 is formed in the initial first stack in the stepped region 102, wherein the initial first stack has a stop layer (not shown). The stop layer can be removed by a back-side processing. Furthermore, the semiconductor layer 111 can be formed by a back-side processing.

[0044] exist Figure 1A-1B In the example, a through-contact structure 160 is formed in the through-region 104. Figure 1AIn the example, the through-hole region 104 is filled with insulating material 163 and is planarized along with other regions. The through-hole contact structure 160 can extend from the front side of the array die to the back side of the array die and electrically interconnects the conductive structures on the front side of the array die with the conductive structures on the back side of the array die.

[0045] In one example, the through-contact structure 160 extends through the capping layer 125, the insulating layer 163, and terminates in the top etch stop layer 115. In some examples, the end of the through-contact structure 160 may contact the conductive layer 167 and be electrically connected to the pad structure P2. The conductive layer 167 may comprise one or more metallic materials such as aluminum (Al), titanium (Ti), etc. The conductive layer 167 may be separated from the semiconductor layer 111 by a spacer layer 165 (e.g., silicon oxide).

[0046] Figure 2A-2C The pattern layout used to define the stop layer is shown. Figure 2A A pattern 201 is shown that can be used to form a stop layer in the core region 101 to achieve depth control and better depth uniformity of the channel structure 130.

[0047] Figure 2B A pattern 203 is shown that can be used to form a stop layer in the gate line gap region 103 to achieve depth control and better depth uniformity of the gate line gap structure 140.

[0048] Figure 2C A pattern 202 is shown that can be used to form a stop layer in the stepped region 102 to achieve depth control and better depth uniformity of the dummy channel structure 150.

[0049] In some examples, the stop layer is not patterned, and no additional layout or mask is required.

[0050] Figure 3 A flowchart is shown to outline process 300 in some examples. Process 300 can be used to form a semiconductor device such as semiconductor device 100, etc. The process begins at S301 and proceeds to S310.

[0051] In S310, a vertical structure is formed in the stack by processing the first side of the wafer. The end of the vertical structure is in the first layer, wherein the first layer has better etch selectivity for the stack compared to the second layer.

[0052] exist Figure 1A-1BIn the example, the initial first layer stack corresponding to the first layer stack 110 may include a stop layer, wherein the stop layer has better etch selectivity for layers above the initial first layer stack compared to the polysilicon layer. In one example, the stop layer includes tungsten (W). Figure 1A-1B In the example, within core region 101, the layers above the initial first-layer stack may include alternating layers of silicon oxide and silicon nitride. Tungsten exhibits better etch selectivity for the layers above the initial first-layer stack compared to polysilicon layers. The channel vias for the channel structure 130 are etched through the layers above the initial first-layer stack and stop in a stop layer. The channel structure 130 is formed in the channel vias, wherein the ends of the channel structure 130 are located in the stop layer within core region 101.

[0053] In the stepped region 102, the layers above the initial first-layer stack may include a subset of alternating silicon oxide and silicon nitride layers, as well as additional insulating material 163. Tungsten exhibits better etch selectivity for these layers above the initial first-layer stack compared to polysilicon layers. The dummy channel vias for the dummy channel structure 150 are etched through these layers above the initial first-layer stack and stop in a stop layer. The dummy channel structure 150 is formed in the dummy channel vias, wherein the ends of the dummy channel structure 150 are in the stop layer within the stepped region 102.

[0054] In the gate line gap region 103, the layers above the initial first layer stack may include alternating layers of silicon oxide and silicon nitride. Tungsten exhibits better etch selectivity for these layers above the initial first layer stack compared to polysilicon layers. Trench etching for the gate line gap structure 140 is performed through the layers above the initial first layer stack and stops in a stop layer. The gate line gap structure 140 is formed in the trench, wherein the ends of the gate line gap structure 140 are in the stop layer.

[0055] In S320, the first layer is replaced with a second layer by processing the second side of the wafer opposite to the first side. Figure 1A-1B In one example, a back-side processing is performed to remove several layers from the back side of the wafer, such as a substrate, an oxide layer, a stop layer, a barrier insulating layer 133 at the end of the channel structure 130, a charge storage layer 134 at the end of the channel structure 130, and a tunneling insulating layer 135 at the end of the channel structure 130. A semiconductor layer 111, such as a polysilicon layer, can then be formed on the back side of the wafer. In some examples, through-silicon contact structures can be formed to electrically connect with through-contact structure 160.

[0056] The process can continue until the manufacturing process is complete.

[0057] Figure 4A-4P This is a cross-sectional view of an array die (e.g., an array die in semiconductor device 100) in various intermediate steps of wafer-level manufacturing according to some embodiments of this disclosure.

[0058] Figure 4A A cross-sectional view of the semiconductor device 100 is shown after the initial first layer stack 110' is deposited on the substrate 171. Figure 4A In one example, the initial first layer stack 110' includes a first oxide layer 173, a stop layer 175, a second oxide layer 177, a top etch stop layer 115, and a third oxide layer 179 sequentially deposited on a substrate 171. In one example, the stop layer 175 comprises tungsten, and the thickness of the stop layer 175 ensures that etching for channel vias forming channel structures, etching for dummy channel vias forming dummy channel structures, and etching for trenches forming gate line slot structures can be stopped in the stop layer 175.

[0059] Figure 4B A cross-sectional view of a semiconductor device 100 is shown after a channel via 183 for forming a channel structure has been etched through an initial second-layer stack 120'. Etching of the channel via 183 stops at a stop layer 175. For example, an initial second-layer stack 120' is formed over an initial first-layer stack 110'. The initial second-layer stack 120' may include an insulating layer 121 (e.g., silicon oxide) and a sacrificial gate layer 122 (e.g., silicon nitride) alternately stacked in the Z-direction. The pattern of the channel via is then defined in a photoresist and / or hard mask layer using photolithography, and the pattern is transferred to the initial second-layer stack 120' and the initial first-layer stack 110' using etching, with the etching stopping at the stop layer 175. The stop layer 175 has relatively high etch selectivity for the insulating layer 121 and the sacrificial gate layer 122, and can well control the depth of the channel hole 183 in the stop layer 175, and the channel hole 183 can have a relatively uniform depth.

[0060] Figure 4C A cross-sectional view of the semiconductor device 100 is shown after the formation of the channel structure 130. In one example, a barrier insulating layer 133 (e.g., silicon dioxide) is formed on the sidewall of the channel hole, and then a charge storage layer 134 (e.g., silicon nitride), a tunneling insulating layer 135, a semiconductor layer 136, and an insulating layer 137 are sequentially stacked from the sidewall.

[0061] It should be noted that the channel structure 130 is not limited to, for example... Figure 4CThe diagram illustrates a single-level deck configuration. In some examples (not shown), multi-level techniques are used to form the channel structure 130. For example, the channel structure 130 includes a lower channel structure in a lower level and an upper channel structure in an upper level. The lower channel structure and the upper channel structure are appropriately joined to form the channel structure 130.

[0062] Figure 4D A cross-sectional view of a semiconductor device 100 is shown after etching dummy channel vias 185, used to form dummy channel structures, through layers in a stepped region. In some examples, stepped steps are suitably formed in the stepped region, and an insulating material 163 (e.g., silicon oxide) is filled and suitably planarized. The dummy channel vias are then patterned in a photoresist and / or hard mask layer using photolithography, and these patterns are transferred to layers in the stepped region using etching, which stops at a stop layer 175. The stop layer 175 has relatively high etch selectivity for the insulating material 163, the insulating layer 121, and the sacrificial gate layer 122, and allows for good control over the depth of the dummy channel vias in the stop layer 175, and these dummy channel vias can have a relatively uniform depth.

[0063] Figure 4E A cross-sectional view of the semiconductor device 100 after the formation of the dummy channel structure 150 is shown. In some examples, one or more insulating layers are formed in the dummy channel via. In one example, one or more insulating layers are deposited, and excess insulating material in areas outside the dummy channel via can be removed, for example, by chemical mechanical polishing (CMP) and / or etching processes.

[0064] Figure 4F A cross-sectional view of a semiconductor device 100 is shown after trenches 184, used to form the gate line slot structure, have been etched through layers in the gate line slot region. Trench 184 is also referred to as a gate line slot or gate line cutout. In some examples, photolithography is used to define the pattern of the trenches in the photoresist and / or hard mask layers, and etching is used to transfer these patterns to the initial second layer stack 120' and the initial first layer stack 110', with the etching stopping at a stop layer 175. The stop layer 175 has relatively high etch selectivity for the insulating layer 121 and the sacrificial gate layer 122, and the depth of the trenches in the stop layer 175 can be well controlled, and these trenches can have a relatively uniform depth.

[0065] Figure 4G A cross-sectional view of a semiconductor device 100 is shown after the gate line slot structure 140 is formed in the gate line slot region 103.

[0066] In some examples, the sacrificial gate layer 122 can be replaced with gate layer 123 by using trenches. In one example, an etchant is applied to the sacrificial gate layer 122 through the trenches to remove the sacrificial gate layer. In one example, the sacrificial gate layer is made of silicon nitride and is removed by applying hot sulfuric acid (H2SO4) through the trenches. Further, the gate stack of transistors in the array region is formed through the trenches. In one example, the gate stack is formed of a high-k dielectric layer, a binder layer, and a metal layer. The high-k dielectric layer can include any suitable material that provides a relatively large dielectric constant, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon nitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanium oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and so on. The adhesive layer may include refractory metals such as titanium (Ti), tantalum (Ta), and their nitrides, such as TiN, TaN, W₂N, TiSiN, TaSiN, etc. The metal layer may include highly conductive metals such as tungsten (W), copper (Cu), etc.

[0067] Furthermore, trenches can be filled to form the gate line slot structure 140. In some examples, one or more insulating layers are formed in the trenches. In one example, one or more insulating layers are deposited, and excess insulating material outside the trenches can be removed, for example, by CMP and / or etching processes. In some examples, conductive materials such as tungsten can be used to form array common source terminals in the gate line slot structure 140.

[0068] Figure 4H A cross-sectional view of a semiconductor device 100 is shown after a through-hole 186, used to form a through-contact structure, has been etched through a layer in the through-region. For example, a capping layer 125 is deposited and planarized. Further, the through-hole pattern is defined in a photoresist and / or hard mask layer using photolithography, and these patterns are transferred to the capping layer 125 and insulating material 163 using etching, which may be stopped in a top etch stop layer 115. It should be noted that the etching may be stopped in other suitable layers. In some examples, the through-hole 186 is formed simultaneously with other contact holes (not shown) (e.g., word line contact holes, bit line contact holes, etc.) through the same process steps.

[0069] Figure 4IA cross-sectional view of a semiconductor device 100 is shown after a through-hole contact structure 160 has been formed in the through-hole. For example, a suitable pad layer (e.g., titanium / titanium nitride) and a metal layer (e.g., tungsten) can be filled into the through-hole to form the through-hole contact structure. In some examples, the through-hole contact structure is formed by the same process steps and simultaneously with other contact structures (e.g., word line contact structures (also referred to as gate contact structures in some examples), bit line contact structures, etc.).

[0070] In some embodiments, a bonding structure (not shown) is then formed on the front side of the array die. Furthermore, the array die is bonded to a CMOS die (not shown) face-to-face. A back-side processing can then be performed on the array die.

[0071] Figure 4J A cross-sectional view of the semiconductor device 100 after the stop layer 175 has been removed by a back-side processing. In some examples, the substrate 171 is removed by a back-side processing (e.g., applying a CMP process and / or etching process to the back of the array die). Then, the oxide layer 173 is removed by a back-side processing (e.g., applying a CMP process and / or etching process to the back of the array die). Then, the stop layer 175 is removed by a back-side processing (e.g., applying a CMP process and / or etching process to the back of the array die).

[0072] As a result, the ends of the channel structure 130, the gate line slot structure 140, and the dummy channel structure 150 can be exposed from the back of the array die.

[0073] Figure 4K A cross-sectional view of the semiconductor device 100 is shown after the barrier insulating layer, charge storage layer, and tunneling insulating layer have been removed from the ends of the channel structure 130 by back-side processing. It should be noted that the second oxide layer 177 is also removed by back-side processing.

[0074] Figure 4LA cross-sectional view of a semiconductor device 100 after a semiconductor layer 111 has been formed via a back-side processing is shown. In some examples, the semiconductor layer 111 includes a body portion 112 and a pad portion 113 (e.g., a conformal portion). The pad portion 113 can be formed, for example, by atomic layer deposition, and then doped by ion implantation. The body portion 112 can then be formed, for example, by chemical vapor deposition (CVD), and planarized by CMP. The body portion 112 can be doped in situ during CVD, or by ion implantation after CVD. A post-annealing step (e.g., laser annealing) can be performed to activate the dopant and / or repair crystal damage. In some examples, the semiconductor layer 111 includes only the body portion 112.

[0075] Figure 4M A cross-sectional view of the semiconductor device 100 is shown after a through-silicon via 187 is formed in the semiconductor layer 111 to expose the end of the through-contact structure 160 from the back side of the array die.

[0076] Figure 4N A cross-sectional view of the semiconductor device 100 is shown after the spacer layer 165 is formed from the back side of the array die.

[0077] Figure 4O A cross-sectional view of the semiconductor device 100 is shown after some portions of the spacer layer 165 have been removed. For example, the spacer layer 165 is removed from the bottom of the through-silicon via 187, thereby exposing the through-contact structure 160. It should be noted that portions of the spacer layer 165 on the semiconductor layer 111 are removed to create the opening 188.

[0078] Figure 4P A cross-sectional view of a semiconductor device 100 is shown after a conductive layer 167 has been formed on the back side of an array die and the conductive layer 167 has been patterned into, for example, pad structures (e.g., shown as P1 and P2). In some examples, the conductive layer 167 comprises aluminum.

[0079] It should be noted that semiconductor device 100 can be used in storage systems.

[0080] Figure 5 A block diagram of a storage system device 500 according to some examples of this disclosure is shown. The storage system device 500 includes one or more semiconductor storage devices, such as semiconductor storage devices 511-514, which are configured similarly to semiconductor device 100. In some examples, the storage system device 500 is a solid-state drive (SSD).

[0081] Storage system device 500 includes other suitable components. For example, storage system device 500 includes, for instance, […]. Figure 5 The interface 501 and main controller 502 are coupled together as shown. The storage system device 500 may include a bus 520 that couples the main controller 502 to semiconductor storage devices 511-514. Furthermore, the main controller 502 is connected to the semiconductor storage devices 511-514 respectively, for example, as shown by the corresponding control lines 521-524.

[0082] Interface 501 is appropriately mechanically and electrically configured to connect between storage system device 500 and host device, and can be used to transfer data between storage system device 500 and host device.

[0083] The main controller 502 is configured to connect the individual semiconductor memory devices 511-514 to the interface 501 for data transmission. For example, the main controller 502 is configured to provide enable / disable signals to the semiconductor memory devices 511-514 respectively to activate one or more semiconductor memory devices 511-514 for data transmission.

[0084] The main controller 502 is responsible for executing various instructions within the storage system device 500. For example, the main controller 502 can perform bad block management, error checking and correction, garbage collection, and so on.

[0085] The foregoing has outlined the features of several examples to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the examples described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

[0086] Several features of embodiments have been outlined above to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: A vertical structure is formed in the laminate by processing a first side of the first die, wherein the end of the vertical structure is in the first layer; and The first layer is replaced with a second layer by processing a second side of the first die opposite to the first side, wherein the second layer is a semiconductor layer and the material of the first layer has better etch selectivity for the stack compared to the material of the semiconductor layer.

2. The method according to claim 1, wherein, The material of the first layer is tungsten, and the material of the semiconductor layer is polycrystalline silicon.

3. The method according to claim 1, wherein, The vertical structure corresponds to the channel structure, and the initial first layer stack includes the first layer in the core region.

4. The method according to claim 3, wherein, The stacked body corresponds to the initial second stacked body, and the method further includes: The initial second-layer stack is formed, the initial second-layer stack comprising an insulating layer and a sacrificial gate layer alternately stacked above the initial first-layer stack.

5. The method according to claim 4, further comprising: Channel holes are formed in the initial second-layer stack, wherein the ends of the channel holes are in the first layer; and The channel structure is formed in the channel hole.

6. The method according to claim 5, wherein, The channel structure includes a channel layer, which is enclosed in a barrier insulating layer, a charge storage layer, and a tunneling insulating layer.

7. The method according to claim 6, wherein, Replacing the first layer with the second layer also includes: The first layer is removed by performing the aforementioned processing on the second side; and The barrier insulation layer, the charge storage layer, and the tunneling insulation layer are removed from the end of the channel structure by performing the aforementioned processing on the second side.

8. The method according to claim 7, wherein, Replacing the first layer with the second layer also includes: At the end of the channel structure, a second layer is formed that contacts the channel layer.

9. The method according to claim 8, wherein, Replacing the first layer with the second layer also includes: The semiconductor layer in contact with the channel layer is formed at the end of the channel structure by performing the aforementioned processing on the second side.

10. The method according to claim 9, wherein, The semiconductor layer forming the contact with the channel layer further includes: A pad portion forming the semiconductor layer, the pad portion contacting the channel layer at the end of the channel structure; Perform ion implantation to dope the pad portion; and The main portion forming the semiconductor layer.

11. The method of claim 9, further comprising: A pad structure is formed on the second side, and the pad structure is electrically connected to the semiconductor layer.

12. The method according to claim 1, wherein, The vertical structure corresponds to the dummy channel structure, and the initial first layer stack includes the first layer in the stepped region.

13. The method according to claim 12, wherein, The stacked body corresponds to the initial second stacked body, and the method further includes: The initial second-layer stack is formed, the initial second-layer stack comprising an insulating layer and a sacrificial gate layer alternately stacked above the initial first-layer stack; A stepped platform is formed based on the initial second layer of stacked structures in the stepped region; and Insulating materials are used to flatten the stepped area.

14. The method of claim 13, further comprising: A dummy channel hole is formed in the insulating material and the initial second layer stack, with the end of the dummy channel hole in the first layer; as well as The dummy channel structure is formed in the dummy channel hole.

15. The method according to claim 1, wherein, The vertical structure corresponds to the gate line gap structure, and the initial first layer stack includes the first layer in the gate line gap region.

16. The method according to claim 15, wherein, The stacked body corresponds to the initial second stacked body, and the method further includes: The initial second-layer stack is formed, the initial second-layer stack comprising an insulating layer and a sacrificial gate layer alternately stacked above the initial first-layer stack.

17. The method of claim 16, further comprising: A channel structure is formed in the initial second layer of the stack; A groove is formed in the initial second layer stack, wherein the ends of the groove are in the first layer; The sacrificial gate layer is replaced with a gate layer through the trench; and The gate line slot structure is formed in the trench.

18. The method according to claim 1, further comprising: A through-contact structure is formed in the through-area by processing the first side of the first die.

19. The method of claim 18, further comprising: A bonding structure is formed on the first side of the first die; as well as Before performing the aforementioned processing on the second side of the first die, the first side is bonded to the second die.

20. The method of claim 19, further comprising: Through-silicon contacts are formed by performing the aforementioned processing on the second side of the first die, and the through-silicon contacts connect the through-contact structure to the pad structure on the second side of the first die.

21. A method for manufacturing a semiconductor device, comprising: An initial first-layer stack is formed by processing a first side of a first die, the initial first-layer stack comprising a first layer; An initial second stack is formed on top of the initial first stack by processing the first side of the first die, the initial second stack comprising alternating insulating layers and sacrificial gate layers; An opening is etched in the initial second-layer stack by processing the first side of the first die, wherein the etching stops in the first layer; A vertical structure is formed in the opening by processing the first side of the first die; and The first layer is replaced with a second layer by processing a second side of the first die opposite to the first side, wherein the second layer is a semiconductor layer and the material of the first layer has better etch selectivity for the initial second layer stack compared to the material of the semiconductor layer.

22. The method according to claim 21, wherein, The material of the first layer is tungsten, and the material of the semiconductor layer is polycrystalline silicon.

23. The method according to claim 21, wherein, The vertical structure corresponds to the channel structure, and the initial first layer stack includes the first layer in the core region.

24. The method according to claim 23, wherein, The channel structure includes a channel layer, which is enclosed in a barrier insulating layer, a charge storage layer, and a tunneling insulating layer.

25. The method according to claim 24, wherein, Replacing the first layer with the second layer also includes: The first layer is removed by performing the aforementioned processing on the second side; and The barrier insulation layer, the charge storage layer, and the tunneling insulation layer are removed from the end of the channel structure by performing the aforementioned processing on the second side.

26. The method of claim 25, wherein, Replacing the first layer with the second layer also includes: At the end of the channel structure, a second layer is formed that contacts the channel layer.

27. The method according to claim 26, wherein, Replacing the first layer with the second layer also includes: The semiconductor layer in contact with the channel layer is formed at the end of the channel structure by performing the aforementioned processing on the second side.

28. The method according to claim 27, wherein, The semiconductor layer forming the contact with the channel layer further includes: A pad portion forming the semiconductor layer, the pad portion contacting the channel layer at the end of the channel structure; Perform ion implantation to dope the pad portion; and The main portion forming the semiconductor layer.

29. The method of claim 28, further comprising: A pad structure is formed on the second side, and the pad structure is electrically connected to the semiconductor layer.

30. The method according to claim 21, wherein, The vertical structure corresponds to the dummy channel structure, and the initial first layer stack includes the first layer in the stepped region.

31. The method of claim 30, further comprising: A stepped structure is formed based on the initial second layer of stacked bodies in the stepped region; as well as Insulating materials are used to flatten the stepped area.

32. The method according to claim 21, wherein, The vertical structure corresponds to the gate line slot structure, and the initial first layer stack includes the first layer in the gate line slot region.

33. The method of claim 32, further comprising: A channel structure is formed in the initial second layer of the stack; A groove is formed in the initial second layer stack, wherein the ends of the groove are in the first layer; The sacrificial gate layer is replaced with a gate layer through the trench; and The gate line slot structure is formed in the trench.

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