Method for fabricating semiconductor nanowires coupled to superconductors

Abstract

A method for manufacturing a device is provided. A first layer (22) of a first deposition material is formed on a top surface of a substrate (10). The first layer of the first deposition material is patterned to create a seed pattern (24) of remaining first deposition material. Homoepitaxy is used to grow a second layer (26) of the first deposition material on the seed pattern.

Description

Technical Field

[0001] The present application relates to the fabrication of devices such as nanoscale structures by means of homoepitaxial growth. One example application is the fabrication of superconductor-semiconductor platforms for use in quantum computers. Background Art

[0002] Quantum computing is a type of computing in which inherent quantum mechanical phenomena, such as superposition and entanglement, are exploited to perform certain calculations at speeds far faster than any classical computer could. In "topological" quantum computers, calculations are performed by manipulating quasiparticles—called "non-Abelian anyons"—that appear in certain physical systems. Anyons possess unique physical properties that distinguish them from both fermions and bosons. Non-Abelian anyons also possess unique properties relative to Abelian anyons. These unique properties serve as the foundation for topological quantum computing, in which information is encoded in the topological properties of non-Abelian anyons; specifically, the weave of their spacetime worldlines. This offers certain advantages over other quantum computing models. A key benefit is stability, as quantum weaving is unaffected by perturbations at scales that can cause error-induced quantum decoherence in other types of quantum computers.

[0003] Broadly speaking, two types of physical systems have so far been considered as potential hosts for non-Abelian anyons: the "5 / 2 fractional quantum Hall" system in condensed matter physics and (more recently) semiconductor superconductor (SE / / SU) nanowires. Regarding the latter, a key advance in the field has been the realization that non-Abelian anyons in the form of "Majorana zero modes" (MZMs) can be formed in semiconductor (SE) nanowires (NWs) coupled to superconductors (SUs).

[0004] One of the issues encountered in the context of SE / / SU nanowires is the presence of so-called "soft-gap" states. The soft-gap problem has been documented in the publicly available literature, sufficiently to indicate that these soft-gap states, when present, are a source of decoherence in MZMs. Analysis and experiments have shown that the source of the soft-gap is disorder in the SE / / SU interface, and recent work in the field has focused on improving the quality of the SE / / SU interface, aiming to provide more stable MZMs. Summary of the Invention

[0005] In conventional selective area growth (SAG) of semiconductors on substrates, an amorphous mask is used to define the substrate area on which the semiconductor is to be grown. SE elements are then grown via heteroepitaxial growth. The inventors of the present invention have determined that for certain material combinations, such as InSb SAG on an InP substrate, this method results in a low yield of semiconductor elements that are successfully grown in the locations specified by the amorphous mask. The low yield of these elements is due to the fact that the semiconductor material and the substrate material are different, resulting in a low probability of the semiconductor material being formed on the substrate, and the grown material containing a high density of defects.

[0006] To increase the yield of successfully grown devices, the inventors devised a method for fabricating SE / / SU nanowires without growing SE devices via heteroepitaxial growth.

[0007] According to one aspect disclosed herein, a method for manufacturing a device is provided, the method comprising: forming a first layer of a first deposition material on a top surface of a substrate; and patterning the first layer of the first deposition material to create a seed pattern of remaining first deposition material; and growing a second layer of the first deposition material on the seed pattern using homoepitaxial growth.

[0008] According to a second aspect of the present invention, there is provided an electronic device comprising: a substrate; a seed pattern protruding outward from a top surface of the substrate and comprising a first deposition material; and a second layer of the first deposition material grown on top of the seed pattern; wherein the seed pattern is formed on the substrate before the second layer is grown on the seed pattern; and wherein the second layer is grown via homoepitaxial growth. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To assist in understanding the present disclosure and to show how embodiments may be practiced, reference is made, by way of example only, to the accompanying drawings, in which:

[0010] Figure 1 shows an example of SAG via heteroepitaxy,

[0011] Figure 2 Three growth structures with different yields are illustrated,

[0012] Figure 3 shows a method of growing a structure via homoepitaxial growth,

[0013] Figure 4 shows an example of a seed pattern for growing a structure via epitaxial growth,

[0014] Figure 5 shows a schematic top view of a quantum circuit comprising SE / SU nanowires and side gate regions, and

[0015] Figures 6a-6dSchematic diagram of SE / / SU nanowires formed on a substrate. DETAILED DESCRIPTION

[0016] In the fabrication techniques disclosed herein, homoepitaxy is used to grow a crystalline semiconductor network on a substrate.

[0017] Although the terms are not always used consistently in the art, for present purposes, "wafer" will refer herein to the base layer, while "substrate" refers to the wafer and any additional layers that may have been added to the wafer at that point in the fabrication process.

[0018] Regarding another point about terminology, it is noted that "on..." and the like herein do not necessarily mean relative to gravity, but rather should be understood as covering the side of the wafer being processed (or at least a portion thereof), i.e., the side on which deposition is currently being performed. In the case of a mask, this means between the wafer and the source (although not necessarily in physical contact with the wafer). Terms such as "under..." and the like should also be interpreted equivalently.

[0019] Figure 1 An example of SAG of a semiconductor on a wafer 10 via heteroepitaxy as is known in the art is shown. Step 1 shows a blank wafer 10. Wafer 10 may be, for example, a crystalline wafer.

[0020] In step 2, a layer of amorphous mask material 12 is deposited on the top surface of substrate 10. For example, the amorphous mask material can be a dielectric material.

[0021] In step 3, amorphous mask material layer 12 is patterned. The pattern produced in layer 12 corresponds to the desired pattern of elements grown via SAG. Layer 12 can be patterned using lithographic techniques such as photolithography, or it can be etched, or it can be patterned by some other mechanical or chemical technique. The patterning process produces gaps 14 in layer 12, corresponding to the desired growth pattern.

[0022] In step 4, a crystalline structure 16 is grown by heteroepitaxial SAG. The material used to form the crystalline structure can be a semiconductor. The crystalline structure 16 is covered in the gap 14 of the amorphous mask material layer 12 so that it grows on the top surface of the substrate 10 and is in electrical contact with the wafer 10.

[0023] In step 5, a layer of superconducting material is deposited onto the exposed surface of the substrate. That is, the top surface of the amorphous masking material layer 12 and the exposed surface of the crystalline structure 16. When deposited onto the two different materials forming the top surface of the substrate, the superconducting material adopts different molecular arrangements. When deposited onto the crystalline structure 16, the superconductor solidifies to form a crystalline superconductor layer 18. However, when deposited onto the amorphous masking material layer 12, the superconductor solidifies to form an amorphous or polycrystalline superconductor layer 20. The crystalline superconductor layer 18 is formed via epitaxial growth. In contrast, the amorphous or polycrystalline superconductor layer 20 is formed via non-epitaxial growth.

[0024] It is desirable that the SU layer deposited on the top surface of the substrate has a high crystallinity.This problem has been identified by the inventors of the present invention.

[0025] Another problem identified by the inventors is that for certain semiconductor materials, such as InAs and InSb, strain induced dislocations are generated when growing the semiconductor on the wafer 10. This is due to the different lattice parameters of the two materials.

[0026] A third problem overcome by the present invention is that for certain materials, such as InSb, the yield of grown structures using the above-described heteroepitaxial SAG method is low. In order to make the manufacturing method scalable, the yield needs to be increased.

[0027] Output can be defined in one of two ways, referring to Figure 2 Explain it.

[0028] Figure 2 Three examples of gaps 14a, 14b, 14c are shown, which have been filled to varying degrees by grown crystal structures 16a, 16b, 16c. In A, the total footprint of gap 14a covered by grown crystal structure 16a is 60%; in B, the entire footprint of gap 14b has been covered by crystal structure 16a; and in C, only 35% of the footprint of gap 14c has been covered by crystal structure 16c.

[0029] Due to the different properties of wafer 10 and crystal structure 16, the entire footprint of gap 14 may not be covered by the grown crystal structure 16. As described above, this results in a low probability of forming crystal structure 16 during heteroepitaxial growth. In some cases, the grown crystal structure 16 may be too small to be useful. This can adversely affect device yield, because if the entire structure is used in a device, the yield of working devices will not be higher than the yield of the grown structure.

[0030] The first yield considered is the full structure yield. That is, the percentage of complete crystal structures16. Figure 2In the example shown, only one of the three structures 16a, 16b, 16c is complete. That is, only one of the three crystal structures 16a, 16b, 16c covers the entire footprint of the gap 14a, 14b, 14c that forms it. Therefore, Figure 2 The complete structure yield in [ 1 ] is 33%. A lower limit can be defined for the footprint of gaps 14 covered by the crystalline structures 16 used that is considered acceptable. For example, a crystalline structure 16 covering 80% of the gap 14, and therefore designed to cover 80% of the area, may be acceptable. Therefore, all structures 16 covering at least 80% of the footprint of the gap 14 in which the structures 16 are grown can contribute to the complete structure yield. In some embodiments, this is only true when certain specific areas of the grown network are used for the device and these areas are filled with SE.

[0031] The second yield to consider is the coverage area yield. This is the percentage of the desired coverage area that is actually covered by the crystal structure 16. Figure 2 In the example shown, the total coverage area is 65%.

[0032] The inventors have devised a method to overcome the above problems.

[0033] Figure 3 A schematic diagram of a method for manufacturing a device proposed by the inventor is shown. The method can be performed in a vacuum.

[0034] The method starts with a blank wafer 10. Figure 3 Although not shown, there may also be complex layers atop wafer 10, such as a pseudo-metamorphic buffer stack. Such stacks are known in the art and include layers of different materials with material properties that gradually differ from those of wafer 10 to the material to be grown atop wafer 10. This allows for better matching of crystal properties. The pseudo-metamorphic buffer stack can be several microns thick. In comparison, wafer 10 can be approximately 0.5 mm thick. Using a complex material stack as part of the substrate in step 1, such that the substrate includes, for example, wafer 10 with a pseudo-metamorphic stack atop it, can improve the quality of the final device by providing a defect engineering path.

[0035] In step 2, a first layer of a first deposition material 22 is formed over the top surface of the substrate. Here, substrate refers to wafer 10 and any other layers that may be thereon before forming the first deposition material layer 22, such as a pseudo-metamorphic buffer stack. The first layer of the first deposition material 22 is formed over the entire top surface of the substrate. The first layer 22 has a substantially uniform thickness.

[0036] The first deposited material is a crystalline material. It is the same material used to form the crystalline structure 16. Therefore, it can be a semiconductor.

[0037] The first layer of first deposition material 22 can be formed in a variety of ways. The method used to form the first layer 22 may depend on the properties of the substrate. For example, if the substrate comprises a crystalline wafer, the first first deposition material layer 22 can be grown via heteroepitaxial growth. Since both the substrate and the first deposition material are crystalline, this growth method is possible for crystalline wafers.

[0038] In another embodiment, the substrate may comprise an amorphous wafer. Here, heteroepitaxial growth cannot be used. Instead, the first first deposition material layer 22 may be mechanically transferred. This method may also be used for crystalline wafer substrates.

[0039] Other methods of forming the first layer of first deposition material 22 on the substrate may also be used. For example, chemical deposition may be used to uniformly deposit the first deposition material on the top surface of the substrate.

[0040] When the first layer 22 is formed using heteroepitaxy, since the first layer 22 is formed over the entire top surface of the substrate, the probability of formation approaches 1. Therefore, this increases the final yield of the structure.

[0041] In step 3, a first layer of first deposition material 22 is patterned. This results in a seed pattern 24 remaining on the top surface of the substrate. The seed pattern 24 protrudes outward from the top surface of the substrate. The seed pattern 24 defines the substrate region where the crystalline structure 16 will grow.

[0042] Figure 4 An example of the substrate is shown after step 3. That is, the substrate includes the wafer 10, any additional layers of the substrate of step 1 such as the dummy metamorphic stack, and the seed pattern 24. Figure 4 The example of shows an InSb network etched from a 60 nm thick planar layer of InSb, where InSb is the first deposited material and the planar layer is the first layer of first deposited material 22. The width of the branches is 72.9 nm.

[0043] In step 4, a second layer of the first deposited material 26 is grown on the seed pattern 24. Since both materials are crystalline, and in this example, homoepitaxial growth can be used to grow the second layer of the first deposited material 26. The seed pattern 24 and the second layer 26 together constitute the crystalline structure 16. In some embodiments, the second layer 26 is thicker than the seed pattern 24 and therefore thicker than the first layer 22, although it will be understood that this is not a requirement in all embodiments. The total thickness of the crystalline structure 16 can be on the order of tens of nanometers. For example, the crystalline structure 16 can have a depth of 100 nm. The width of the crystalline structure can be of a similar order of magnitude.

[0044] It should be understood that the material used to form the seed pattern and the material grown on top of the seed pattern 24 can be different materials. In such an embodiment, the second layer will be grown via heteroepitaxial growth. Both materials can be crystalline SE materials.

[0045] The first deposited material can be a semiconductor. The crystalline structure 16 comprising the seed pattern 24 and the second layer of the first deposited material 26 forms a nanowire. Thus, the seed pattern 24 can be used to define the extent of the nanowire on the resulting device. Nanowires with lengths on the order of 10 microns can be grown.

[0046] In step 5, a second layer of deposited material 18 is formed over the top surface of the substrate. It should be understood that in this step, the substrate includes the wafer 10, any buffer layers that may be present, the seed pattern 24, and the second layer of first deposited material 26. This second layer of deposited material 18 can be grown via epitaxial growth. This is because it is grown on crystalline material because the top surface of the substrate is full of crystals.

[0047] The second deposited material may be a superconducting material. Since all elements of the substrate in contact with the second deposited material layer 18 are crystalline, the second deposited material layer 18 is also crystalline. Thus, the problem of Figure 1 The problem of reduced crystallinity of the superconducting layer in the method is solved.

[0048] In some prior art manufacturing methods, the amorphous mask layer 12 may be removed after the growth of the crystalline structure 16. That is, after the growth of the crystalline structure 16 has been performed Figure 1 Mask layer 12 is removed after step 4 but before step 5. In this manufacturing method, the superconductor layer deposited on the substrate surface in step 5 is generally crystalline. While this also achieves a higher degree of crystallinity in the deposited superconductor layer, the techniques used to remove mask layer 12 are typically destructive and time-consuming. For example, such methods sometimes result in insufficient etching or result in lower-quality components. Therefore, the solution proposed in the present invention for improving the crystallinity of the superconducting layer is preferred because it does not degrade device quality.

[0049] Another advantage of the proposed solution is that both the second layer of first deposited material 26 and the second deposited material layer 18 can be deposited in the same vacuum chamber or in connected vacuum chambers. Therefore, the device is not exposed to air during fabrication. In the prior art, exposure to air is detrimental to the interface quality between the crystalline device 16 and the second deposited material layer 18. Therefore, this fabrication method eliminates interface degradation between these two layers and improves the resulting device quality.

[0050] Figure 3 The method increases the yield of the crystalline structure 16. As described above, this is achieved by depositing a first layer of the first deposition material over the entire top surface of the substrate.

[0051] Furthermore, the grown crystal structure 16 itself can be more Figure 1 The method produces a higher quality crystal structure. This is because the volume of the crystal structure is grown via homoepitaxial growth rather than heteroepitaxial growth. In other words, the second layer 22 of the first deposited material has fewer defects, thereby improving the quality of the crystal structure 16.

[0052] It should be understood that the term "homoepitaxial" refers to the growth of a material under homoepitaxial growth conditions. Similarly, the term "heteroepitaxial" refers to the growth under heteroepitaxial growth conditions.

[0053] Heteroepitaxial growth results in a greater defect density than homoepitaxial growth. These defects reduce the quality of the resulting crystal structure 16. They also result in lower yields when SAG is performed using heteroepitaxial growth. Therefore, crystal structures 16 grown via homoepitaxial growth have a higher yield and contain fewer strain-induced dislocations.

[0054] One example growth condition that can vary between heteroepitaxial and homoepitaxial is the temperature required for growth. Homoepitaxial can be performed at a higher temperature than heteroepitaxial. For example, if the wafer 10 is InP and the first deposited material is InSb, the first layer 22 of InSb can be grown at approximately 400°C, while the second layer 26 can be grown at approximately 500°C. 400°C ensures high-quality planar growth, while 500°C only allows selective area growth on the top layer of the seed pattern 24. This is because at higher temperatures, only the strongest chemical bonds can survive. Therefore, the probability of forming certain pairs of same-pair (e.g., InSb-InSb) bonds is higher than the weaker same-pair (e.g., InP-InSb) bonds.

[0055] As mentioned above, it is not possible to grow a layer of the first deposited material on the top surface of the substrate at the temperature used for homoepitaxy. Figure 1 However, under homoepitaxial conditions, it is easy to grow a second layer of the first deposition material 26 on the seed pattern 24 because they are the same material.

[0056] The first deposition material may be a semiconductor. For example, it may be InSb. Other III-V compounds may alternatively be used as the first deposition material.

[0057] Any of the above techniques can be used to form a semiconductor in a SE / / SU nanowire or nanowire network. As described above, the SE / / SU nanowire can be formed on a substrate 10 composed of any material. As described above, after forming a seed pattern 22 in the semiconductor material, the bulk semiconductor of the SE / / SU nanowire can be grown via homoepitaxial growth. The superconductor of the SE / / SU nanowire can be deposited on the semiconductor after the semiconductor is grown, such as Figure 3 as shown in step 5.

[0058] Figure 6a An example device (or portion thereof) is shown. The device includes a substrate 13, which includes a wafer 2 and multiple layers formed on the wafer 2. The multiple layers include at least a first layer, which includes a structured portion of a semiconductor 4. The semiconductor 4 can be a crystalline structure 16. For example, there can be one or more intermediate layers between the wafer 2 and the semiconductor 4, such as a semiconductor layer.

[0059] Portions of semiconductor 4 are formed over wafer 2 by any suitable known deposition technique. Although not shown, a coating of ferromagnetic insulator may be grown at least partially over each of some or all of the semiconductor portions 4. This layer may be grown by epitaxial means.

[0060] Optionally, one or more further layers may be formed over semiconductor 4 . Figure 6b An example is shown whereby an oxide layer 8 is formed over part or all of each semiconductor structure 4 (or at least some of the semiconductor structures). The oxide layers can be used to protect the semiconductor structures 4 from O2 or H2O in the air. They can be used to protect samples in TEM (transmission electron microscopy) or reflective layers in PNR (polarized neutron reflectivity). The oxide layer 8 can be, for example, silicon oxide, SiOx; or more generally, any dielectric or other insulating material can be used in its place. Note, however, that the oxide layer 8 is optional, and in other cases such protection may not be needed, or may be provided by other upper layers (not shown) of the substrate or IC package. In some cases, the oxide layer 8 may be used only in samples during the experimental phase, or as an intermediate step in manufacturing, but may not remain in the final product.

[0061] Figure 6c An example is shown in which a coating of superconductor material 6 is formed on part or all of each semiconductor 4 (or at least some of the semiconductors 4). The superconductor 6 may be a crystalline superconductor 18. In an embodiment, at least some of the semiconductor structures 4 each comprise a length or line of semiconductor material 4. In this case, Figure 6cRepresents a cross-section in a plane perpendicular to the wire. A superconductor 6 is then formed above each such semiconductor structure 4, covering part or all of the periphery of the wire along some or all of its length. Each such semiconductor structure 4 and its respective superconductor coating 6 thus form a respective semiconductor-superconductor nanowire. A network of such nanowires can be formed above the wafer 2 and can be arranged to form a topological quantum computing device comprising one or more topological qubits. In operation, Majorana zero modes (MZMs) and thus topological states can be induced in portions of some or all of the nanowires by means of a magnetic field and cooling to a temperature at which the superconductor 6 exhibits superconducting behavior. In an embodiment, the induction of MZMs and topological systems can further include gating with an electromagnetic potential. The structures for forming qubits and the induction of MZMs and topological states in semiconductor-superconductor nanowires themselves are known in the art.

[0062] Figure 6d An example is shown having both a superconductor layer 6 and an oxide layer 8. The superconductor 6 may be formed on or over the semiconductor 4 of the nanowire, along some or all of the length of the semiconductor 4, around some or all of the periphery of the semiconductor 4. The oxide 8 may be formed on or over some or all of the superconductor 6, along some or all of the length of the superconductor 6, around some or all of the periphery of the nanowire.

[0063] In other examples, other alternative or additional layers may be formed over semiconductor 4, such as conductive vias between semiconductors 4 and / or between semiconductor 4 and one or more other components. As another example, an upper protective layer of plastic or wax may be formed over the entire structure.

[0064] Notice, Figures 6a to 6d are schematic and the shapes and dimensions shown therein are not intended to be limiting.

[0065] Figure 5 A schematic top view of a T-shaped SE / / SU nanowire structure 406 and additional elements forming the quantum circuit 400 is shown. The SE / / SU nanowire 406 is formed from a length of semiconductor that is at least partially coated with a superconductor. Figure 3 As shown, the disclosed method can be used to form a SE / / SU nanowire structure 406 .

[0066] Contacts 402 of quantum circuit 400 have been added to the SE / / SU nanowires to allow electrical connection thereto. Side gates 404 formed of a gating material are shown. These side gates are designed to manipulate the SE / / SU nanowires and—for example, in the context of topological quantum computing—to manipulate Majorana zero modes carried by the SE / / SU nanowires to facilitate quantum computation.

[0067] The side gates 404 and contacts 402 can be formed using a variety of known techniques. For example, a stencil mask can be used. This is an object that includes holes placed between the substrate and the source and masks areas of the substrate not covered by the source material, so that the material is deposited in the areas defined by the holes.

[0068] Alternatively, photolithography can be used, which uses a photoresist mask. A patterned photoresist, or photomask, is deposited on a substrate, and then a pattern is defined by shining light (UV) through the photoresist. The illuminated areas react by changing their chemical composition. The openings are then washed away after chemically developing the resist. These openings can be used to etch the material below or deposit subsequent materials through them. Thus, the photoresist acts as a mask. Afterwards, a solvent is used to remove the photoresist.

[0069] Another possible masking technique is the use of shadow masks or shadow structures. These are structures placed on the substrate and used to block the path of the directed deposition beam. The structures can be transferred to the substrate or grown on it. After the source material is deposited, these structures can remain on the substrate or be removed.

[0070] The materials used to form the elements of quantum circuit 400 depend on the elements being formed. For example, when forming side gates 404, the material used can be metal. When forming contacts 402, the material used can be metal or a superconductor.

[0071] Figure 5 An example of a plan view of a quantum circuit 400 having one or more elements formed via the above-described techniques is shown. This example is not limiting, and other layouts of quantum circuits can be formed using the above-described methods. It should be understood that a skilled person will be aware of alternative methods for fabricating an MZM.

[0072] It should be understood that the above embodiments are described by way of example only.

[0073] More generally, according to one aspect disclosed herein, a method for manufacturing a device is provided, the method comprising: forming a first layer of a first deposition material on a top surface of a substrate; and patterning the first layer of the first deposition material to create a seed pattern of remaining first deposition material; and using homoepitaxial growth to grow a second layer of the first deposition material on the seed pattern.

[0074] In some embodiments, the first layer of the first deposition material can be formed over the entire top surface of the substrate and can have a substantially uniform thickness.

[0075] In some embodiments, the second layer of the first deposited material can be thicker than the first layer of the first deposited material.

[0076] In some embodiments, the first deposited material may be a crystalline material.

[0077] In some embodiments, the method may include forming a second layer of deposition material over the top surface of the substrate and over the first deposition material and the second layer after the second layer of deposition material has been grown.

[0078] In some embodiments, the second deposited material layer may be grown via epitaxial growth.

[0079] In some embodiments, the second deposited material may be a superconducting material.

[0080] In some embodiments, at least the top surface of the substrate may comprise a material different from the first deposited material, and the first layer of the first deposited material may be formed via heteroepitaxial growth.At least the top layer of the substrate may comprise a crystalline material.

[0081] The temperature of the homoepitaxial growth may be at least 10° C. higher than the temperature of the heteroepitaxial growth.

[0082] In some embodiments, the first layer of the first deposition material may be formed via mechanical transfer.

[0083] In some embodiments, the substrate may include a crystalline wafer.

[0084] In some embodiments, the substrate may include a pseudo-metamorphic buffer stack, wherein the top surface of the substrate is the top surface of the stack.

[0085] In some embodiments, the first deposited material can be a semiconductor, and the seed pattern and the second layer of the first deposited material form a nanowire or a nanowire network.

[0086] In some embodiments, method steps may be performed in a vacuum.

[0087] According to a second aspect of the present invention, there is provided an electronic device comprising: a substrate; a seed pattern protruding outward from a top surface of the substrate and comprising a first deposition material; and a second layer of the first deposition material grown on top of the seed pattern; wherein the seed pattern is formed on the substrate before the second layer is grown on the seed pattern; and wherein the second layer is grown via homoepitaxial growth.

[0088] In some embodiments, the first deposited material can be a semiconductor, and the seed pattern and the second layer of the first deposited material form a nanowire or a nanowire network.

[0089] Other variations and applications of the disclosed technology will become apparent to those skilled in the art once given the disclosure herein.The scope of the present disclosure is not limited by the above-described embodiments, but only by the appended claims.

Claims

1. A method for manufacturing a device, the method comprising: forming a first layer of a first deposition material on the top surface of the substrate; patterning the first layer of the first deposition material to create a seed pattern of remaining first deposition material; as well as growing a second layer of the first deposition material on the seed pattern using homoepitaxy, The first deposition material is a semiconductor, and the seed pattern and the second layer of the first deposition material form a nanowire or a nanowire network. 2 . The method of claim 1 , wherein the first layer of the first deposition material is formed over the entire top surface of the substrate and has a substantially uniform thickness.

3. A method according to any preceding claim, wherein the first deposition material is a crystalline material.

4. A method according to any preceding claim, comprising forming a second layer of deposition material over the top surface of the substrate and the second layer of first deposition material after the second layer of the first deposition material has been grown. The method of claim 4 , wherein the second layer of deposited material is grown via epitaxial growth.

6. A method according to any one of claims 4 and 5, wherein the second deposited material is a superconducting material.

7. A method according to any preceding claim, wherein at least the top surface of the substrate comprises a material different from the first deposited material, and the first layer of first deposited material is formed via heteroepitaxial growth.

8. The method of claim 7, wherein at least the top surface of the substrate comprises a crystalline material.

9. The method according to claim 7 or 8, wherein the temperature of the homoepitaxial growth is at least 10°C higher than the temperature of the heteroepitaxial growth.

10. The method of any one of claims 1 to 6, wherein the first layer of first deposition material is formed via mechanical transfer.

11. A method according to any preceding claim, wherein the substrate comprises a crystalline wafer.

12. A method according to any preceding claim, wherein the substrate comprises a pseudo-metamorphic buffer stack, wherein the top surface of the substrate is the top surface of the stack.

13. An electronic device comprising: substrate; a seed pattern protruding outward from the top surface of the substrate and comprising a first deposition material; as well as A second layer of the first deposition material is grown on top of the seed pattern; wherein the seed pattern is formed on the substrate before the second layer is grown on the seed pattern; and wherein the second layer is grown via homoepitaxial growth, The first deposition material is a semiconductor, and the seed pattern and the second layer of the first deposition material form a nanowire or a nanowire network.

14. The electronic device of claim 13, wherein the first deposited material is a semiconductor, and the seed pattern and the second layer of the first deposited material form a nanowire or a nanowire network.

15. The electronic device of claim 13, wherein the substrate comprises a pseudo-metamorphic buffer stack, wherein the top surface of the substrate is a top surface of the stack. 16 . The electronic device of claim 13 , wherein the first layer of the first deposition material is formed over the entire top surface of the substrate and has a substantially uniform thickness. The electronic device of claim 13 , wherein the first deposited material is a crystalline material.

18. The electronic device of claim 13, wherein the substrate comprises a crystalline wafer.

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