Electronic device and method for decoding a bitstream

Abstract

A method of decoding a bitstream by an electronic device is provided. Encoding data of at least one image frame is received, each image frame comprising one or more regions. When an affine mode comprising an affine tool is enabled in the at least one image frame, a first affine flag is determined according to a first syntax structure associated with the at least one image frame. When the first affine flag is equal to one, a second affine flag is present in the first syntax structure. When the second affine flag is equal to one, a third affine flag corresponding to one of the affine tools is present in a second syntax structure associated with a particular one of the one or more regions. When the third affine flag is equal to zero, the particular region is reconstructed based on first candidate modes, the first candidate modes comprising the one of the affine tools.

Description

[0001] Cross-reference to related applications

[0002] This disclosure claims the benefit and priority of U.S. Provisional Patent Application Serial No. 62 / 884335 (hereinafter referred to as "'335 Provisional Case"), filed August 8, 2019, entitled "High Level Syntax of Affine-Related Mode and Sample Selection of Linear Model". The disclosure of '335 Provisional Case is hereby incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates generally to video coding, and more specifically, to techniques for controlling affine tools that will be enabled or disabled through different syntactic structures with different syntactic levels for reconstructing image frames in encoded data. Background Technology

[0004] In conventional video coding methods, the encoder encodes video data to generate encoded data with multiple flags and provides this encoded data to the decoder. Flags indicate whether multiple coding modes are enabled. For example, the encoded data may include block-based affine flags indicating whether block units are predicted using an affine mode. Furthermore, when the block-based affine flags indicate that block units are predicted using an affine mode, the block units are also refined according to a prediction refinement with optical flow (PROF) mode. However, coding efficiency is not always improved when refining affine-predicted blocks according to the PROF mode. In other words, coding efficiency may decrease for some block units refined according to the PROF mode. Therefore, for the PROF mode, the encoder and decoder need more flags. Moreover, selecting the syntax level of the affine PROF flags is crucial to preventing an excessive increase in the number of bits in the encoded data. Summary of the Invention

[0005] This disclosure relates to an apparatus and method for preventing adjustments to initial prediction results by means of several flags.

[0006] In a first aspect of the disclosure, a method for decoding, by an electronic device, a bitstream is provided. The method includes receiving, as part of the bitstream, encoded data of at least one image frame, wherein each of the at least one image frame includes one or more regions; determining, when an affine mode is enabled in the at least one image frame, a first affine flag according to a first syntax structure associated with the at least one image frame, wherein the first syntax structure is included in the encoded data and the affine mode includes a plurality of affine tools; determining, when the first affine flag is equal to one, that a second affine flag is present in the first syntax structure; determining, when the second affine flag is equal to one, that a third affine flag is present in a second syntax structure associated with a particular one of the one or more regions in a particular one of the at least one image frame, wherein the second syntax structure is included in the encoded data, and the third affine flag corresponds to one of the plurality of affine tools; and reconstructing, when the third affine flag is equal to zero, the particular one of the one or more regions based on a plurality of first candidate modes, the plurality of first candidate modes including the one of the plurality of affine tools.

[0007] In a second aspect of the disclosure, a method for decoding, by an electronic device, a bitstream is provided. The method includes receiving, as part of the bitstream, encoded data of at least one image frame, wherein each of the at least one image frame includes one or more regions; determining, when an affine mode is enabled in the at least one image frame, a first affine flag according to a first syntax structure associated with the at least one image frame, wherein the first syntax structure is included in the encoded data and the affine mode includes a plurality of affine tools; determining, based on the first affine flag, whether a second affine flag is present in the first syntax structure; determining, based on the second affine flag, whether a third affine flag is present in a second syntax structure associated with a particular one of the one or more regions in a particular one of the at least one image frame, wherein the second syntax structure is included in the encoded data, and the third affine flag corresponds to one of the plurality of affine tools; and reconstructing, when the third affine flag is equal to zero, the particular one of the one or more regions based on a plurality of first candidate modes, the plurality of first candidate modes including the one of the plurality of affine tools. BRIEF DESCRIPTION OF DRAWINGS

[0008] Aspects of the disclosure can best be understood with reference to the following detailed description when read in conjunction with the accompanying drawings. Various features are not drawn to scale and the dimensions of various features can be arbitrarily expanded or reduced for the sake of clarity. The various features are depicted with exaggerated relative dimensions for purposes of explanation and are not necessarily drawn to scale with one another.

[0009] Figure 1A block diagram of an exemplary system configured to encode and decode video data according to exemplary embodiments of the present disclosure is shown.

[0010] Figure 2 A block diagram of an exemplary decoder module of a second electronic device shown in Figure 1

[0011] Figure 3 A flowchart of an exemplary reconstruction method for reconstructing a block unit according to exemplary embodiments of the present disclosure is shown.

[0012] Figure 4A A schematic diagram of three image frames having one or more regions according to exemplary embodiments of the present disclosure.

[0013] Figure 4B A schematic diagram of a syntax structure corresponding to Figure 4A

[0014] Figure 5 A flowchart of an exemplary reconstruction method for reconstructing a block unit according to exemplary embodiments of the present disclosure is shown.

[0015] Figure 6 A flowchart of an exemplary reconstruction method for reconstructing a block unit according to exemplary embodiments of the present disclosure is shown.

[0016] Figure 7 A block diagram of an exemplary encoder module of a first electronic device shown in Figure 1 DETAILED DESCRIPTION

[0017] The following description contains specific information pertaining to exemplary embodiments in the present disclosure. The drawings in the present disclosure, and the detailed description thereof, are directed to exemplary embodiments. However, the present disclosure is not limited only to these exemplary embodiments. Other variations and embodiments of the present disclosure will occur to those skilled in the art.

[0018] Unless otherwise indicated, like or corresponding elements in the drawings can be indicated by like or corresponding reference numerals. The drawings and illustrations in the present disclosure are generally not drawn to scale, and are not intended to correspond to actual relative sizes.

[0019] For consistency and ease of understanding, like features are identified by like numerals in the exemplary drawings (although in some examples not shown). Features in different embodiments can differ in other respects, and should not be narrowly limited to what is shown in the drawings.

[0020] ​​​The phrase "in one embodiment" or "in some embodiments" as used herein does not necessarily refer to the same embodiment, although it may. The term "coupled" is defined as connected, whether directly or indirectly, and is not necessarily limited to a physical or mechanical connection. The term "includes" means "comprises but is not limited to" and specifically indicates open-ended includes of the elements, groups, series or equivalents so described.

[0021] For purposes of explanation and not limitation, specific details are set forth, such as functional entities, techniques, protocols, and standards, to provide an understanding of the disclosed technology. In other instances, detailed descriptions of well-known methods, techniques, systems, and

[0022] Those skilled in the art will directly recognize that any one or more of the disclosed encoding functions or algorithms described in this disclosure can be implemented by hardware, software, or a combination of software and hardware. The described functions can correspond to modules, which can be software, hardware, firmware, or any combination thereof.

[0023] Software implementations can include computer-executable instructions stored on a computer-readable medium, such as a memory or other type of storage device. For instance, one or more microprocessors or general purpose computers with communication processing capabilities can be programmed with executable instructions and perform one or more of the disclosed functions or algorithms.

[0024] The microprocessor or microcomputer can be formed of an applications specific integrated circuitry (ASIC), a programmable logic array, and / or using one or more digital signal processors (DSPs). Although some of the disclosed embodiments are oriented to software installed and executed on computer hardware, alternative embodiments implemented as firmware or hardware or a combination of hardware and software are well within the scope of the disclosure. Computer readable media includes, but is not limited to, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash memory, compact disc read only memory (CD-ROM), optical disk storage, magnetic cassette, magnetic tape, magnetic disk storage or any other medium that can be used to store computer readable instructions.

[0025] Figure 1 A block diagram illustrating an exemplary system 100 configured to encode and decode video data in accordance with exemplary embodiments of the disclosure is shown. The system 100 includes a first electronic device 110, a second electronic device 120, and a communication medium 130. The first electronic device 110 can be a source device that includes any device configured to encode video data and transmit the encoded video data to the communication medium 130. The second electronic device 120 can be a destination device that includes any device configured to receive and decode encoded video data via the communication medium 130.

[0026] In at least one embodiment, the first electronic device 110 can be in wired or wireless communication with the second electronic device 120 via the communication medium 130. The first electronic device 110 can include a source module 112, an encoder module 114, and a first interface 116. The second electronic device 120 can include a display module 122, a decoder module 124, and a second interface 126. The first electronic device 110 can be a video encoder and the second electronic device 120 can be a video decoder.

[0027] In at least one implementation, the first electronic device 110 and / or the second electronic device 120 can be a mobile phone, a tablet, a desktop computer, a laptop, or other electronic device. Figure 1 Only one example of the first electronic device 110 and the second electronic device 120 is shown. In other implementations, the first electronic device 110 and the second electronic device 120 can include more or fewer components than shown, or have a different configuration of components.

[0028] In at least one implementation, the source module 112 can include a video capture device to capture new video, a video archive to store previously captured video, and / or a video feed interface to receive video from a video content provider. The source module 112 can generate computer graphics-based data as a source video, or a combination of live video, archived video, and computer-generated video as a source video. The video capture device can be a charge-coupled device (CCD) image sensor, a complementary metal-oxide-semiconductor (CMOS) image sensor, or a camera.

[0029] In at least one implementation, the encoder module 114 and the decoder module 124 can each be implemented as any of a variety of suitable encoder / decoder circuitries, such as one or more microprocessors, central processing units (CPUs), graphic processing units (GPUs), system on chips (SoCs), digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic circuitries, software, hardware, firmware, or any combinations thereof. When implemented partially in software, a device can store instructions for the software in a suitable, non-transitory computer-readable medium and execute the instructions in hardware using one or more processors to perform the disclosed methods. In at least one implementation, each of the encoder module 114 and the decoder module 124 can be included in one or more encoders and decoders, each of which can be integrated as part of a combined encoder / decoder (CODEC) in the device.

[0030] In at least one embodiment, first interface 116 and second interface 126 can utilize a custom protocol or follow an existing or de facto standard, including but not limited to Ethernet, IEEE 802.11 or IEEE 802.15 family, wireless USB, or a telecommunications standard including but not limited to GSM, CDMA2000, TD-SCDMA, WiMAX, 3GPP-LTE, or TD-LTE. In at least one embodiment, first interface 116 and second interface 126 can each include any device configured to transmit and / or store a compatible video bitstream via communication medium 130 and receive a compatible video bitstream via communication medium 130.

[0031] In at least one embodiment, first interface 116 and second interface 126 can include a computer system interface that enables storage of a compatible video bitstream on a storage device or reception of a compatible video bitstream from a storage device. For example, first interface 116 and second interface 126 can include a chipset supporting Peripheral Component Interconnect (PCI) and Peripheral Component Interconnect Express (PCIe) bus protocols, a proprietary bus protocol, Universal Serial Bus (USB) protocols, I2C, or any other logical and physical structure that can be used to interconnect peer devices.

[0032] In at least one embodiment, display module 122 can include a display that uses liquid crystal display (LCD) technology, plasma display technology, organic light emitting diode (OLED) display technology, or light emitting polymer display (LPD) technology, and in other embodiments, other display technologies. Display module 122 can include a high definition display or an ultra-high definition display.

[0033] Figure 2 An exemplary embodiment according to the present disclosure is shown Figure 1A block diagram of an example decoder module 124 of the second electronic device 120 is shown in FIG. 2B. The decoder module 124 includes an entropy decoder (e.g., entropy decoding unit 2241), a prediction processor (e.g., prediction processing unit 2242), an inverse quantization / inverse transform processor (e.g., inverse quantization / inverse transform unit 2243), a summer (e.g., summer 2244), a filter (e.g., filter unit 2245), and a decoded picture buffer (e.g., decoded picture buffer 2246). The prediction processing unit 2242 also includes an intra-prediction processor (e.g., intra-prediction unit 22421) and an inter-prediction processor (e.g., inter-prediction unit 22422). The decoder module 124 receives and decodes a bitstream to output a decoded video.

[0034] The entropy decoding unit 2241 can receive the bitstream including the plurality of syntax elements from the second interface 126 shown in FIG. 2B and perform a parsing operation on the bitstream to extract the syntax elements from the bitstream. As part of the parsing operation, the entropy decoding unit 2241 can entropy decode the bitstream to generate quantized transform coefficients, a quantization parameter, transform data, motion vectors, intra modes, partition information, and other syntax information. Figure 1

[0035] In at least one embodiment, the entropy decoding unit 2241 can perform context adaptive variable length coding (CAVLC), context adaptive binary arithmetic coding (CABAC), syntax-based context-adaptive binary arithmetic coding (SBAC), probability interval partitioning entropy (PIPE) coding, or another entropy coding technique to generate the quantized transform coefficients. In at least one embodiment, the entropy decoding unit 2241 can provide the quantized transform coefficients, the quantization parameter, and the transform data to the inverse quantization / inverse transform unit 2243, and provide the motion vectors, the intra modes, the partition information, and other syntax information to the prediction processing unit 2242.

[0036] In at least one embodiment, the prediction processing unit 2242 can receive syntax elements, such as motion vectors, intra modes, partition information, and other syntax information, from the entropy decoding unit 2241. The prediction processing unit 2242 can receive syntax elements including the partition information and partition the image frame according to the partition information. In at least one embodiment, the prediction processing unit 2242 can receive syntax elements, such as motion vectors, intra modes, partition information, and other syntax information, from the entropy decoding unit 2241. The prediction processing unit 2242 can receive syntax elements including the partition information and partition the image frame according to the partition information.

[0037] In at least one embodiment, each of the image frames can be divided into at least one image block according to partition information. The at least one image block can include a luma block for reconstructing a plurality of luma samples and at least one chroma block for reconstructing a plurality of chroma samples. The luma block and the at least one chroma block can be further divided to generate macroblocks, coding tree units (CTUs), coding blocks (CBs), subunits thereof, and / or another equivalent coding unit.

[0038] In at least one embodiment, during a decoding process, prediction processing unit 2242 receives prediction data including an intra mode and a motion vector for a current block unit of a particular one of the image frames. The current block unit can be one of a luma block or a chroma block in the particular image frame.

[0039] In at least one embodiment, intra prediction unit 22421 can perform intra prediction coding on the current block unit relative to one or more neighboring blocks in the same frame as the current block unit based on syntax elements related to the intra mode to generate a prediction block. The intra mode can specify a position of a reference sample selected from the neighboring blocks in the current frame. In at least one embodiment, when prediction processing unit 2242 reconstructs the chroma components, intra prediction unit 22421 can reconstruct the chroma components of the current block unit based on the luma components of the current block unit.

[0040] In at least one embodiment, when prediction processing unit 2242 reconstructs the luma components of the current block, intra prediction unit 22421 can reconstruct the chroma components of the current block unit based on the luma components of the current block unit.

[0041] In at least one embodiment, inter prediction unit 22422 can perform inter prediction coding on the current block unit relative to one or more blocks of one or more reference image blocks based on syntax elements related to the motion vector to generate a prediction block.

[0042] In at least one embodiment, the motion vector can indicate a displacement of the current block unit within the current block of image samples relative to a reference block unit within a reference block of image samples. The reference block unit is a block determined to closely match the current block unit.

[0043] In at least one embodiment, inter prediction unit 22422 receives reference image blocks stored in decoded picture buffer 2246 and reconstructs the current block unit based on the received reference image blocks.

[0044] In at least one embodiment, inverse quantization / inverse transform unit 2243 can apply inverse quantization and inverse transform to reconstruct a residual block in pixel domain. Inverse quantization / inverse transform unit 2243 applies inverse quantization to residual quantized transform coefficients to generate residual transform coefficients, and then applies inverse transform to residual transform coefficients to generate a residual block in pixel domain.

[0045] In at least one embodiment, inverse transform can be applied by inverse of a transform process such as a discrete cosine transform (DCT), a discrete sine transform (DST), an adaptive multiple transform (AMT), a mode-dependent non-separable secondary transform (MDNSST), a hypercube-givens transform (HyGT), a signal dependent transform, a Karhunen-Loéve transform (KLT), a wavelet transform, an integer transform, a sub-band transform, or conceptually similar transforms.

[0046] In at least one embodiment, inverse transform can convert residual information from a transform domain such as frequency domain back to pixel domain. Degree of inverse quantization can be modified by adjusting quantization parameter. Adder 2244 adds residual block to predicted block from prediction processing unit 2242 to produce a reconstructed block.

[0047] In at least one embodiment, adder 2244 adds reconstructed residual block to predicted block provided from prediction processing unit 2242 to produce a reconstructed block.

[0048] In at least one embodiment, filter unit 2245 can include a deblocking filter, a sample adaptive offset (SAO) filter, a bilateral filter, and / or an adaptive loop filter (ALF) to remove blocking artifacts from reconstructed block. In addition to deblocking filter, SAO filter, bilateral filter, and ALF, additional filters (in-loop or post-loop) can be used. Such filters are not shown for brevity, but output of adder 2244 can be filtered.

[0049] After filter unit 2245 performs filtering process on reconstructed block of a particular image frame, filter unit 2245 can output decoded video to display module 122 or other video receiving unit.

[0050] In at least one implementation, the decoded picture buffer 2246 can be a reference picture memory that stores reference blocks for use by the prediction processing unit 2242 in decoding the bitstream (in inter-coded mode). The decoded picture buffer 2246 can be formed from any of a wide variety of memory devices, such as dynamic random-access memory (DRAM), including synchronous DRAM (SDRAM), magneto-resistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices.

[0051] In at least one implementation, the decoded picture buffer 2246 can be on-chip with, or off-chip relative to, other components of the decoder module 124.

[0052] Figure 3 A flow diagram of an example reconstruction method 300 for reconstructing a block unit, in accordance with example implementations of the disclosure, is shown. The method 300 is just one example as there are many ways to perform the method.

[0053] The method 300 can be performed using the configurations shown in Figure 1 and Figure 2 and various elements in these figures are referenced in explaining the method 300. Figure 3 Each block in

[0054] Further, the order in which the blocks are presented is only illustrative and can vary. Additional blocks can be added or fewer blocks can be used, without departing from the disclosure.

[0055] At block 301, the decoder module 124 receives, as part of a bitstream, encoded data for at least one image frame, each image frame including one or more regions, and determines a first syntax structure from the encoded data.

[0056] Referring to Figure 1 and Figure 2 , the second electronic device 120 can receive, via the second interface 126, a bitstream from an encoder, such as the first electronic device 110 or other video provider. The second interface 126 can provide the bitstream to the decoder module 124. The bitstream can include encoded data corresponding to at least one image frame. Each of the at least one image frame can be divided into one or more regions.

[0057] Figure 4Ais a schematic diagram of three image frames having one or more regions according to example implementations of this disclosure. In the implementations, a number of at least one image frame 4110-4130 in a group of pictures 4100 corresponding to encoded data can equal three, a number of one or more regions in a first image frame 4110 can equal two, a number of one or more regions in a second image frame 4120 can equal one, and a number of one or more regions in a third image frame 4130 can equal three.

[0058] In at least one implementation, the encoded data can include a first syntax structure corresponding to the at least one image frame. In the implementation, the first syntax structure can include a plurality of first structure indications for indicating how to reconstruct the at least one image frame. In at least one implementation, the first syntax structure can be one of a video parameter set (VPS), a sequence parameter set (SPS), and a picture parameter set (PPS).

[0059] In at least one implementation, the entropy decoding unit 2241 can decode the encoded data to determine the first structure indications of the at least one image frame, and the decoder module 124 can further reconstruct the at least one image frame based on the first structure indications. The first structure indications can include a plurality of first structure flags and a plurality of first structure indices.

[0060] At block 302, when affine mode is enabled in the at least one image frame, the decoder module 124 determines a first affine flag from the first syntax structure.

[0061] In at least one implementation, the reference Figure 2 , the decoder module 124 can determine an affine enable flag from the first syntax structure. In the implementation, when the affine enable flag in the first syntax structure equals one, the affine mode can be enabled during the reconstruction of the at least one image frame corresponding to the first syntax structure. In at least one implementation, the affine mode can include a plurality of affine tools. Thus, when the affine enable flag equals one, the affine tools can be enabled during the reconstruction of the at least one image frame. Further, when the affine enable flag in the first syntax structure equals zero, the affine mode can be disabled for the at least one image frame. Thus, when the affine enable flag equals zero, the at least one image frame is not reconstructed based on the affine tools. In at least one implementation, when the first syntax structure is a SPS, the affine enable flag can be a syntax element sps_affine_enabled_flag.

[0062] In at least one embodiment, the first affine flag can indicate whether a particular one of the affine tools is enabled for the at least one picture frame when the affine mode is enabled in the at least one picture frame according to the affine enable flag. In the described embodiment, the first affine flag corresponds to the particular affine tool.

[0063] In at least one embodiment, the particular affine tool can be an affine PROF mode. Further, the first affine flag can be an affine PROF enable flag that indicates whether the affine PROF mode is enabled when reconstructing the at least one picture frame. In one embodiment, when the first syntax structure is an SPS, the affine PROF enable flag can be a syntax element sps affme prof enabled flag.

[0064] In at least one embodiment, the particular affine tool can be an affine adaptive motion vector difference resolution (AMVR) mode. Further, the first affine flag can be an affine AMVR enable flag that indicates whether the affine AMVR mode is enabled when reconstructing the at least one picture frame. In one embodiment, when the first syntax structure is an SPS, the affine AMVR enable flag can be a syntax element sps affme amvr enabled flag.

[0065] At block 303, the decoder module 124 determines whether the first affine flag is equal to a first predefined value. When the decoder module 124 determines that the first affine flag is equal to the first predefined value, the method 300 can proceed to block 304. When the decoder module 124 determines that the first affine flag is not equal to the first predefined value, the method can proceed to block 311.

[0066] In at least one embodiment, the reference Figure 2 When the first affine flag is equal to the first predefined value, the decoder module 124 determines that the particular affine tool is enabled for the at least one picture frame. Further, when the first affine flag is not equal to the first predefined value, the decoder module 124 determines that the particular affine tool is disabled during the reconstruction of the at least one picture frame. In other words, when the first affine flag is not equal to the first predefined value, the at least one picture frame is not reconstructed based on the particular affine tool.

[0067] In at least one embodiment, the first predefined value can be equal to one. Thus, when the first affine flag is equal to one, the decoder module 124 determines that the particular affine tool is enabled for the at least one picture frame. Further, when the first affine flag is equal to zero, the decoder module 124 determines that the particular affine tool is disabled during the reconstruction of the at least one picture frame.

[0068] At block 304, the decoder module 124 determines that the second affine flag is present in the first syntax structure.

[0069] In at least one embodiment, the second affine flag is present in the first syntax structure when the first affine flag is equal to a first predefined value. Figure 2 When the first affine flag is equal to the first predefined value, the decoder module 124 can determine that the first syntax structure includes the second affine flag. Then, when the first affine flag is equal to the first predefined value, the decoder module 124 can determine the second affine flag from the first syntax structure. In one embodiment, the first predefined value is equal to one. Thus, when the first affine flag is equal to one, the decoder module 124 can determine the second affine flag from the first syntax structure.

[0070] In at least one embodiment, the second affine flag can indicate whether the coded data further includes a plurality of secondary flags, each secondary flag indicating whether a particular affine tool is disabled during a particular one of the regions in a particular one of the at least one picture frame when the particular affine tool is enabled in the particular one of the at least one picture frame according to the first affine flag. In said embodiment, the second affine flag corresponds to the particular affine tool.

[0071] In at least one embodiment, the particular affine tool can be an affine PROF mode. Moreover, the second affine flag can be an affine PROF presence flag indicating whether the coded data further includes a secondary flag indicating whether the affine PROF mode is disabled during a particular one of the regions included in one of the at least one picture frame when being reconstructed. In said embodiment, the secondary flag corresponds to the particular one of the regions in the one of the at least one picture frame. In another embodiment, the second affine flag can be an affine AMVR presence flag.

[0072] At block 305, the decoder module 124 determines whether the second affine flag is equal to a second predefined value. When the decoder module 124 determines that the second affine flag is equal to the second predefined value, the method 300 can proceed to block 306. When the decoder module 124 determines that the second affine flag is different from the second predefined value, the method can proceed to block 307.

[0073] In at least one embodiment, the second predefined value is equal to one. Figure 2 When the second affine flag is equal to the second predefined value, the decoder module 124 determines that the coded data further includes a secondary flag indicating whether the particular affine tool is disabled during reconstruction of the corresponding region. Moreover, when the second affine flag is different from the second predefined value, the decoder module 124 determines that the coded data does not include the secondary flag. In other words, when the second affine flag is different from the second predefined value, the secondary flag is not parsed from the coded data.

[0074] In at least one embodiment, the second predefined value can be equal to one. Therefore, when the second affine flag is equal to one, the decoder module 124 determines that the encoded data also includes a secondary flag. Furthermore, when the second affine flag is equal to zero, the decoder module 124 determines that the encoded data does not include a secondary flag.

[0075] At box 306, decoder module 124 determines that the third affine sign exists in a second syntax structure associated with a specific region in one or more regions of a specific image frame in at least one image frame.

[0076] In at least one embodiment, each of the secondary flags is a third affine flag included in a corresponding second syntactic structure among a plurality of second syntactic structures. In at least one embodiment, the encoded data may include a first syntactic structure and a second syntactic structure. Furthermore, the number of first syntactic structures in the encoded data may be equal to one, and the number of second syntactic structures in the encoded data may be equal to the number of regions included in at least one image frame. In at least one embodiment, reference... Figure 4A The number of first grammatical structures corresponding to image group 4100 is equal to one, and the number of second grammatical structures corresponding to one of regions 4111-4112, 4121 and 4131-4133 in image group 4100 is equal to six.

[0077] Figure 4B It corresponds to Figure 4A The diagram illustrates the grammatical structures of image groups and image regions. Specifically, these grammatical structures are a first grammatical structure corresponding to image group 4100 and six second grammatical structures corresponding to the six regions 4111-4112, 4121, and 4131-4133 within image group 4100. In this embodiment, each of the second grammatical structures 4311-4312, 4321, and 4331-4333 corresponds to one of the regions 4111-4112, 4121, and 4131-4133 within image group 4100. Therefore, the number of regions 4111-4112, 4121, and 4131-4133 within image group 4100 may be equal to the number of the second grammatical structures 4311-4312, 4321, and 4331-4333.

[0078] In at least one embodiment, the first syntax level of the first syntax structure 4300 is higher than the second syntax level of the second syntax structures 4311-4312, 4321, and 4331-4333. In said embodiment, each of the second syntax structures 4311-4312, 4321, and 4331-4333 can refer to the first syntax structure 4300, while the first syntax structure 4300 does not refer to the second syntax structures 4311-4312, 4321, and 4331-4333. For example, the second syntax structures 4311-4312, 4321, and 4331-4333 can be slice headers. In another example, the second syntax structure 4321 can be a picture header, and there can be two other second syntax structures in the coded data 4200 each corresponding to one of the image frames 4110 and 4130.

[0079] In at least one embodiment, referring to Figure 2 When the second affine flag is equal to the second predefined value, the decoder module 124 determines that each of the second syntax structures includes one of the third affine flags. Then, when the second affine flag is equal to the second predefined value, the decoder module 124 can determine the third affine flags from the second syntax structures. In said embodiment, each of the third affine flags can indicate whether a particular affine tool is disabled when reconstructing a corresponding region in the region. In one embodiment, the second predefined value is equal to one. Thus, when the second affine flag is equal to one, the decoder module 124 can determine one of the third affine flags from a corresponding second syntax structure in the second syntax structures corresponding to a particular one of the one or more regions in a particular one of the at least one image frames. For example, the decoder module 124 can determine one of the affine flags from the second syntax structure 4331 corresponding to the region 4131 of the third image frame 4130.

[0080] In at least one embodiment, each of the third affine flags included in a corresponding one of the second syntax structures also corresponds to one of the regions in the at least one image frames, as each of the second syntax structures corresponds to one of the regions in the at least one image frames.

[0081] In at least one embodiment, the third affine flags correspond to a particular affine tool, as the third affine flags indicate whether the particular affine tool is disabled in the regions in the at least one image frames.

[0082] In at least one embodiment, the particular affine tool can be affine PROF mode. Furthermore, each of the third affine flags can be an affine PROF disable flag that indicates whether the affine PROF mode is disabled when reconstructing a corresponding region included in a corresponding picture frame of the at least one picture frame. In one embodiment, when the second syntax structure is a picture header, the affine PROF disable flag can be a syntax element ph_prof_disabled_flag. Furthermore, when the first syntax structure is an SPS and the second syntax structure is a picture header, the affine PROF present flag can be a syntax element sps_prof_control_present_in_ph_flag. In the described embodiment, the second affine flag can be an affine present flag that indicates whether the affine PROF disable flag is included in the second syntax structure.

[0083] In at least one embodiment, the particular affine tool can be affine AMVR mode. Furthermore, each of the third affine flags can be an affine AMVR disable flag. In the described embodiment, the second affine flag can be an affine present flag that indicates whether the affine AMVR disable flag is included in the second syntax structure.

[0084] At block 307, the decoder module 124 infers that the third affine flag is equal to zero.

[0085] In at least one embodiment, the second predefined value can be equal to one. Thus, when the second affine flag is equal to zero, the decoder module 124 determines that the third affine flag is not parsed from the second syntax structure. Furthermore, when the second affine flag is equal to zero and the second affine flag is present in the first syntax structure, the third affine flag is inferred to be equal to zero. Figure 2 When the second affine flag is different from the second predefined value, the decoder module 124 determines that the third affine flag is not present in the second syntax structure. Then, when the third affine flag is not present in the second syntax structure and the second affine flag is present in the first syntax structure, the decoder module 124 infers that the third affine flag for the region in the at least one picture frame is equal to zero.

[0086] In at least one embodiment, the second predefined value can be equal to one. Thus, when the second affine flag is equal to zero, the decoder module 124 determines that the third affine flag is not parsed from the second syntax structure. Furthermore, when the second affine flag is equal to zero and the second affine flag is present in the first syntax structure, the third affine flag is inferred to be equal to zero.

[0087] At block 308, the decoder module 124 determines whether the third affine flag is equal to a third predefined value. When the decoder module 124 determines that the third affine flag is equal to the third predefined value, the method 300 can proceed to block 309. When the decoder module 124 determines that the third affine flag is different from the third predefined value, the method can proceed to block 310.

[0088] In at least one embodiment, the third predefined value can be equal to one. Thus, when the third affine flag is equal to zero, the decoder module 124 determines that the affine tool is disabled when reconstructing the region in the at least one picture frame. Furthermore, when the third affine flag is equal to one, the decoder module 124 determines that the affine tool is enabled when reconstructing the region in the at least one picture frame. Figure 2When the third affine flag corresponding to a particular one of the regions is equal to a third predefined value, the decoder module 124 determines that the particular affine tool is enabled in the particular region. Moreover, when the third affine flag corresponding to the particular region is different from the third predefined value, the decoder module 124 determines that the particular affine tool is disabled in the particular region. In other words, when the third affine flag is different from the third predefined value, the particular region can not be reconstructed based on the particular affine tool.

[0089] In at least one embodiment, the third predefined value can be equal to zero. Thus, when the third affine flag is equal to zero, the decoder module 124 determines that the particular affine tool is enabled for the particular region. Moreover, when the third affine flag is equal to one, the decoder module 124 determines that the particular affine tool is disabled in the particular region.

[0090] At block 309, the decoder module 124 reconstructs the particular region based on the first plurality of candidate modes including a particular one of the plurality of affine tools.

[0091] In at least one embodiment, the reference Figure 2 When the third affine flag corresponding to the particular region is equal to a third predefined value, the decoder module 124 can determine that the particular affine tool is enabled in the particular region. Thus, when the third affine flag is equal to the third predefined value, the particular region can be reconstructed based on the first candidate modes including the particular affine tool.

[0092] In at least one embodiment, the particular affine tool is an affine PROF mode, and the third predefined value is equal to zero. In the embodiment, when the third affine PROF disable flag is equal to zero, the decoder module 124 can determine that the affine PROF mode is enabled in the particular region. Thus, the decoder module 124 can determine a block flag of a block unit included in the particular region according to a third syntax structure. The block flag indicates whether the block unit is predicted by an affine mode. When the block flag is equal to one, the decoder module 124 can determine that the block unit is predicted by the affine mode. Thus, the decoder module 124 can predict the block unit based on the affine mode to generate a prediction block, and then refine the prediction block according to the affine PROF mode. In the embodiment, the decoder module 124 can reconstruct the block unit by adding the refined block to a residual block of the block unit determined according to the bitstream.

[0093] In at least one embodiment, the third syntax structure is a block-based syntax corresponding to the block unit. Thus, the third syntax structure is different from the first syntax structure and the second syntax structure, and a third syntax level of the third syntax structure is lower than the first syntax level and the second syntax level.

[0094] In at least one embodiment, when the block flag is equal to zero, the decoder module 124 can determine that the block unit is not predicted by the affine mode. Accordingly, the decoder module 124 can predict the block unit based on another prediction mode different from the affine mode to generate a prediction block. Then, the prediction block is not refined according to the affine PROF mode. In the described embodiment, the decoder module 124 can reconstruct the block unit by adding the prediction block to a residual block of the block unit determined from the bitstream.

[0095] At block 310, the decoder module 124 reconstructs the particular region based on a plurality of second candidate modes excluding the particular affine tool.

[0096] In at least one embodiment, referring to FIG. 1, the decoder module 124 can determine that the particular affine tool is disabled in the particular region when the third affine flag corresponding to the particular region is different from a third predefined value. Accordingly, the particular region can be reconstructed based on the second candidate modes excluding the particular affine tool when the third affine flag is different from the third predefined value. In one embodiment, the third predefined value is equal to zero. In the described embodiment, the decoder module 124 can determine that the particular affine tool is disabled in the particular region when the third affine flag is equal to one. Moreover, the particular region can be reconstructed based on the second candidate modes. In the described embodiment, the particular affine tool is excluded from the first candidate modes to generate the second candidate modes. Figure 2 In at least one embodiment, referring to FIG. 1, the decoder module 124 can determine that the particular affine tool is disabled in the particular region when the third affine flag corresponding to the particular region is different from a third predefined value. Accordingly, the particular region can be reconstructed based on the second candidate modes excluding the particular affine tool when the third affine flag is different from the third predefined value. In one embodiment, the third predefined value is equal to zero. In the described embodiment, the decoder module 124 can determine that the particular affine tool is disabled in the particular region when the third affine flag is equal to one. Moreover, the particular region can be reconstructed based on the second candidate modes. In the described embodiment, the particular affine tool is excluded from the first candidate modes to generate the second candidate modes.

[0097] In at least one embodiment, the particular affine tool is the affine PROF mode and the third affine flag is the affine PROF disable flag. In the described embodiment, the decoder module 124 can determine that the affine PROF mode is disabled in the particular region when the third affine PROF disable flag is equal to one. Accordingly, the decoder module 124 can determine that a plurality of prediction blocks of a plurality of block units in the particular region are not refined according to the affine PROF mode when reconstructing the particular region. In the described embodiment, the particular region is reconstructed based on the second candidate modes excluding the affine PROF mode. In the described embodiment, the affine PROF mode is excluded from the first candidate modes to generate the second candidate modes. For example, the decoder module 124 can predict one block unit in the particular region based on the affine mode to generate one prediction block without further refining the prediction block according to the affine PROF mode, and then directly add the prediction block to a residual block to reconstruct the block unit.

[0098] At block 311, the decoder module 124 reconstructs the at least one image frame based on the second candidate modes.

[0099] In at least one embodiment, referring to FIG. 1, the decoder module 124 can determine that the particular affine tool is disabled in the particular region when the third affine flag corresponding to the particular region is different from a third predefined value. Accordingly, the particular region can be reconstructed based on the second candidate modes excluding the particular affine tool when the third affine flag is different from the third predefined value. In one embodiment, the third predefined value is equal to zero. In the described embodiment, the decoder module 124 can determine that the particular affine tool is disabled in the particular region when the third affine flag is equal to one. Moreover, the particular region can be reconstructed based on the second candidate modes. In the described embodiment, the particular affine tool is excluded from the first candidate modes to generate the second candidate modes. Figure 2When the first affine flag is different from the first predefined value, the decoder module 124 can determine that the particular affine tool is disabled in the at least one picture frame. Thus, when the first affine flag is different from the first predefined value, the at least one picture frame can be reconstructed based on the second candidate modes excluding the particular affine tool. In one implementation, the first predefined value is equal to one. In the implementation, when the first affine flag is equal to zero, the decoder module 124 can determine that the particular affine tool is disabled in the at least one picture frame. Further, when the first affine flag is equal to zero, the at least one picture frame can be reconstructed based on the second candidate modes.

[0100] In at least one implementation, the particular affine tool is an affine PROF mode and the first affine flag is an affine PROF enabling flag. In the implementation, when the first affine PROF enabling flag is equal to zero, the decoder module 124 can determine that the affine PROF mode is disabled in the at least one picture frame. Thus, the decoder module 124 can determine that, in reconstructing the at least one picture frame, a prediction block of a block unit in the at least one picture frame is not refined according to the affine PROF mode. In the implementation, the at least one picture frame is reconstructed based on the second candidate modes excluding the affine PROF mode. In the implementation, the affine PROF mode is excluded from the first candidate modes to generate the second candidate modes. For example, the decoder module 124 can predict one block unit in a particular region based on the affine mode to generate one prediction block without further refining the prediction block according to the affine PROF mode, and then directly add the prediction block to a residual block to reconstruct the block unit.

[0101] In at least one implementation, the reference Figure 2 When the first affine flag is different from the first predefined value, the decoder module 124 determines that the second affine flag is not present in the first syntax structure. Then, when the second affine flag is not present in the first syntax structure, the decoder module 124 infers that the second affine flag of the at least one picture frame is equal to zero. In the implementation, the third affine flag is not present in the second syntax structure because the second affine flag is inferred to be equal to zero. Thus, the third affine flag is not parsed according to the second syntax structure. In the implementation, the decoder module 124 can infer that the third affine flag is equal to one for disabling the particular affine mode because the first affine flag is different from the first predefined value for indicating that the particular affine mode is disabled in the at least one picture frame.

[0102] In at least one embodiment, the particular affine tool is affine PROF mode, and the first affine flag is an affine PROF enable flag. Thus, when the affine PROF enable flag is equal to zero, the decoder module 124 determines not to parse a second affine flag from the first syntax structure. Moreover, when the affine PROF enable flag is equal to zero, the second affine flag is inferred to be equal to zero. Then, when the second affine flag is not present in the first syntax structure, the decoder module 124 infers the second affine flag for the at least one image frame to be equal to zero. In the described embodiment, a third affine flag is not present in the second syntax structure because the second affine flag is inferred to be equal to zero. Thus, the third affine flag is not parsed from the second syntax structure. In the described embodiment, the decoder module 124 can infer the third affine flag to be equal to one for disabling the particular affine mode because the affine PROF enable flag is equal to zero for indicating that the affine PROF mode is disabled in the at least one image frame.

[0103] Figure 5 A flowchart of an exemplary reconstruction method 500 for reconstructing a block unit according to an exemplary embodiment of the disclosure is shown. The method 500 is just an example as there are many ways to perform the method.

[0104] The method 500 can be performed using the configurations shown in Figure 1 and Figure 2 and various elements in these figures are referenced in explaining the method 500. Figure 5 Each block in

[0105] Moreover, the order of the blocks can only be illustrative and can be changed. Additional blocks can be added or fewer blocks can be used, without departing from the disclosure.

[0106] At block 501, the decoder module 124 receives encoded data for at least one image frame as part of a bitstream, each image frame including one or more regions, and determines a first syntax structure from the encoded data.

[0107] Referring to Figure 1 and Figure 2 , the second electronic device 120 can receive a bitstream from an encoder, such as the first electronic device 110 or other video provider, via the second interface 126. The second interface 126 can provide the bitstream to the decoder module 124. The bitstream can include encoded data corresponding to at least one image frame. Each of the at least one image frame can be divided into one or more regions.

[0108] In at least one embodiment, the coded data can include a first syntax structure corresponding to the at least one picture frame. In said embodiment, the first syntax structure can include a plurality of first structure indications for indicating how to reconstruct the at least one picture frame. In at least one embodiment, the first syntax structure can be one of a VPS, an SPS, and a PPS.

[0109] In at least one embodiment, entropy decoding unit 2241 can decode the coded data to determine the first structure indications for the at least one picture frame, and decoder module 124 can further reconstruct the at least one picture frame based on the first structure indications. The first structure indications can include a plurality of first structure flags and a plurality of first structure indices.

[0110] At block 502, decoder module 124 determines a plurality of first refinement flags from the first syntax structure, each first refinement flag corresponding to one of a plurality of refinement tools.

[0111] In at least one embodiment, each of the first refinement flags can indicate whether a corresponding one of the refinement tools is enabled for the at least one picture frame. In at least one embodiment, the refinement tools can include more than one of a bi-directional optical flow (BDOF) mode, a decoder motion vector refinement (DMVR) mode, an affine PROF mode, and other prediction refinement modes. Further, each of the first refinement flags can be a refinement enable flag that indicates whether a corresponding one of the refinement tools is enabled when reconstructing the at least one picture frame. In one embodiment, when the first syntax structure is an SPS, each of the refinement enable flags can be a syntax element sps_refinement_enabled_flag. For example, the refinement enable flags can include more than one of a syntax element sps bdof enabled flag, a syntax element sps dmvr enabled flag, a syntax element sps affine prof enabled flag.

[0112] At block 503, decoder module 124 determines whether at least one of the first refinement flags is equal to a first predefined value. When decoder module 124 determines that one or more of the first refinement flags is equal to the first predefined value, method 500 can proceed to block 504. When decoder module 124 determines that each of the first refinement flags is different from the first predefined value, the method can proceed to block 511.

[0113] In at least one embodiment, the reference Figure 2When at least one of the first refinement flags is equal to the first predefined value, the decoder module 124 determines to enable at least one of the refinement tools for the at least one image frame. Further, when each of the first refinement flags is different from the first predefined value, the decoder module 124 determines to disable all of the refinement tools during the reconstruction of the at least one image frame. In other words, when the first refinement flags are different from the first predefined value, the at least one image frame is not reconstructed based on the refinement tools.

[0114] In at least one embodiment, the first predefined value can be equal to one. Thus, when one of the first refinement flags is equal to one, the decoder module 124 determines to enable one of the refinement tools for the at least one image frame. Further, when all of the first refinement flags are equal to zero, the decoder module 124 determines to disable the refinement tools during the reconstruction of the at least one image frame.

[0115] At block 504, the decoder module 124 determines that a second refinement flag is present in the first syntax structure.

[0116] In at least one embodiment, with reference to Figure 2 When at least one of the first refinement flags is equal to the first predefined value, the decoder module 124 can determine that the first syntax structure includes the second refinement flag. Then, the decoder module 124 can determine the second refinement flag from the first syntax structure. In one embodiment, the first predefined value is equal to one. Thus, when at least one of the first refinement flags is equal to one, the decoder module 124 can determine the second refinement flag from the first syntax structure.

[0117] In at least one embodiment, the second refinement flag can indicate whether the encoded data further includes a plurality of secondary flags, each secondary flag indicating whether all of the refinement tools are disabled during the reconstruction of a corresponding one of the regions in the at least one image frame when at least one of the refinement tools is enabled in the at least one image frame according to the first refinement flags.

[0118] In at least one embodiment, the second refinement flag can be a refinement presence flag indicating whether the encoded data further includes a secondary flag indicating whether the refinement tools are disabled during the reconstruction of one of the regions included in the at least one image frame. In the embodiment, the secondary flag corresponds to the one of the regions in the at least one image frame.

[0119] At block 505, the decoder module 124 determines whether the second refinement flag is equal to a second predefined value. When the decoder module 124 determines that the second refinement flag is equal to the second predefined value, the method 500 can proceed to block 506. When the decoder module 124 determines that the second refinement flag is different from the second predefined value, the method can proceed to block 507.

[0120] In at least one embodiment, the second refinement flag is equal to a second predefined value. In at least one embodiment, the second predefined value is equal to one. In at least one embodiment, the second predefined value is equal to zero. In at least one embodiment, the second predefined value is equal to a value different from one and zero. Figure 2 When the second refinement flag is equal to the second predefined value, the decoder module 124 determines that the encoded data further comprises secondary flags, each secondary flag indicating whether all refinement tools are disabled during the reconstruction of a corresponding region. Moreover, when the second refinement flag is different from the second predefined value, the decoder module 124 determines that the encoded data does not comprise secondary flags. In other words, when the second refinement flag is different from the second predefined value, no secondary flag is parsed from the encoded data.

[0121] In at least one embodiment, the second predefined value can be equal to one. Thus, when the second refinement flag is equal to one, the decoder module 124 determines that the encoded data further comprises secondary flags, each secondary flag corresponding to one of the one or more regions in the at least one image frame. Moreover, when the second refinement flag is equal to zero, the decoder module 124 determines that no secondary flag is comprised in the encoded data.

[0122] At block 506, the decoder module 124 determines that a third refinement flag is present in a second syntax structure associated with a particular one of the one or more regions in a particular one of the at least one image frame.

[0123] In at least one embodiment, each of the secondary flags is a third refinement flag included in a corresponding second syntax structure of the plurality of second syntax structures. In at least one embodiment, the encoded data can comprise the first syntax structure and the second syntax structures. Moreover, the number of first syntax structures in the encoded data can be equal to one, and the number of second syntax structures in the encoded data can be equal to the number of regions comprised in the at least one image frame.

[0124] In at least one embodiment, the second refinement flag is equal to a second predefined value. In at least one embodiment, the second predefined value is equal to one. In at least one embodiment, the second predefined value is equal to zero. In at least one embodiment, the second predefined value is equal to a value different from one and zero. Figure 4A and Figure 4B The number of first syntax structures corresponding to the image group 4100 is equal to one, and the number of second syntax structures each corresponding to one of the regions 4111-4112, 4121 and 4131-4133 in the image group 4100 is equal to six. In said embodiment, each of the second syntax structures 4311-4312, 4321 and 4331-4333 corresponds to one of the regions 4111-4112, 4121 and 4131-4133 in the image group 4110. Thus, the number of regions 4111-4112, 4121 and 4131-4133 in the image group 4100 can be equal to the number of second syntax structures 4311-4312, 4321 and 4331-4333.

[0125] In at least one embodiment, the first syntax level of the first syntax structure 4300 is higher than the second syntax level of the second syntax structures 4311-4312, 4321, and 4331-4333. In the described embodiment, each of the second syntax structures 4311-4312, 4321, and 4331-4333 can refer to the first syntax structure 4300, while the first syntax structure 4300 does not refer to the second syntax structures 4311-4312, 4321, and 4331-4333. For example, the second syntax structures 4311-4312, 4321, and 4331-4333 can be picture headers. In another example, each of the second syntax structures 4311-4312, 4321, and 4331-4333 can be slice headers.

[0126] In at least one embodiment, referring to Figure 2 When the second refinement flag is equal to the second predefined value, the decoder module 124 determines that each of the second syntax structures includes one of the third refinement flags. Then, when the second refinement flag is equal to the second predefined value, the decoder module 124 can determine the third refinement flags from the second syntax structures. In the described embodiment, each of the third refinement flags can indicate whether all refinement tools are disabled when reconstructing a corresponding region of the regions. In one embodiment, the second predefined value is equal to one. Thus, when the second refinement flag is equal to one, the decoder module 124 can determine one of the third refinement flags from a corresponding second syntax structure of the second syntax structures that corresponds to a particular one of the one or more regions in a particular one of the at least one image frames. For example, the decoder module 124 can determine one of the refinement flags from the second syntax structure 4331 that corresponds to the region 4131 of the third image frame 4130.

[0127] In at least one embodiment, each of the third refinement flags included in a corresponding one of the second syntax structures also corresponds to one of the regions in the at least one image frames because each of the second syntax structures corresponds to one of the regions in the at least one image frames.

[0128] In at least one embodiment, each of the third refinement flags corresponds to all refinement tools because each of the third refinement flags indicates whether all refinement tools are disabled in a corresponding one of the regions in the at least one image frames.

[0129] In at least one embodiment, each of the third refinement flags can be a refinement disable flag indicating whether all refinement tools are disabled when reconstructing a corresponding region included in a corresponding picture frame of the at least one picture frame. In one embodiment, when the second syntax structure is a picture header, the refinement disable flag can be a syntax element ph_refinement_disabled_flag. Further, when the first syntax structure is an SPS and the second syntax structure is a picture header, the refinement presence flag can be a syntax element sps_refinement_control_present_in_ph_flag. In the described embodiment, the second refinement flag can be a refinement presence flag indicating whether the refinement disable flag is included in the second syntax structure.

[0130] At block 507, the decoder module 124 infers that the third refinement flag is equal to zero.

[0131] In at least one embodiment, referring to Figure 2 When the second refinement flag is different from the second predefined value, the decoder module 124 determines that the third refinement flag is not present in the second syntax structure. Then, when the third refinement flag is not present in the second syntax structure and the second refinement flag is present in the first syntax structure, the decoder module 124 infers that the third refinement flag for the region in the at least one picture frame is equal to zero.

[0132] In at least one embodiment, the second predefined value can be equal to one. Thus, when the second refinement flag is equal to zero, the decoder module 124 determines that the third refinement flag is not parsed from the second syntax structure. Further, when the second refinement flag is equal to zero and the second refinement flag is present in the first syntax structure, the third refinement flag is inferred to be equal to zero.

[0133] At block 508, the decoder module 124 determines whether the third refinement flag is equal to a third predefined value. When the decoder module 124 determines that the third refinement flag is equal to the third predefined value, the method 500 can proceed to block 509. When the decoder module 124 determines that the third refinement flag is different from the third predefined value, the method can proceed to block 510.

[0134] In at least one embodiment, referring to Figure 2 When the third refinement flag corresponding to a particular region of the regions is equal to the third predefined value, the decoder module 124 determines that at least one of the refinement tools is enabled in the particular region. Further, when the third refinement flag corresponding to the particular region is different from the third predefined value, the decoder module 124 determines that all of the refinement tools are disabled in the particular region. In other words, when the third refinement flag is different from the third predefined value, the particular region can not be reconstructed based on the refinement tools.

[0135] In at least one embodiment, the third predefined value can be equal to zero. Thus, when the third refinement flag is equal to zero, the decoder module 124 determines that at least one of the refinement tools is enabled for the particular region. Further, when the third refinement flag is equal to one, the decoder module 124 determines that all of the refinement tools are disabled in the particular region.

[0136] At block 509, the decoder module 124 reconstructs the particular region based on the plurality of first candidate modes selected according to the first refinement flag.

[0137] In at least one embodiment, the reference Figure 2 When the third refinement flag corresponding to the particular region is equal to the third predefined value, the decoder module 124 can determine that at least one of the refinement tools is enabled in the particular region. Thus, when the third refinement flag is equal to the third predefined value, the particular region can be reconstructed based on the first candidate modes including at least one of the refinement tools. In at least one embodiment, the at least one of the refinement tools can be selected from the refinement tools based on the first refinement flag. For example, when a particular one of the first refinement flags is equal to the first predefined value, a particular one of the refinement tools indicated by the particular one of the first refinement flags can be added to the first candidate modes. Further, when the particular one of the first refinement flags is different from the first predefined value, the particular one of the refinement tools can be excluded from the first candidate modes.

[0138] In at least one embodiment, the third predefined value is equal to zero. In the embodiment, when the refinement disable flag is equal to zero, the decoder module 124 can determine that at least one of the refinement tools is enabled in the particular region. Then, the decoder module 124 can determine a plurality of block flags of block units included in the particular region according to the third syntax structure. The block flags indicate whether a prediction block of the block unit is refined according to a particular one of the refinement tools.

[0139] For example, the first candidate mode can include the affine PROF mode when the first refinement flag of the affine PROF mode is equal to a first predefined value. Accordingly, the third syntax structure can include a particular one of the block flags corresponding to the affine PROF mode when the third refinement flag is equal to a third predefined value. In at least one embodiment, the particular block flag corresponding to the affine PROF mode is the affine flag. When the affine flag of the block unit is equal to one, the decoder module 124 can determine that the block unit is predicted by the affine mode. The decoder module 124 can then predict the block unit based on the affine mode to generate a prediction block, and then refine the prediction block according to the affine PROF mode. Further, the block flag corresponding to the BDOF mode is the two list flag. When the two list flag of the block unit is equal to one, the decoder module 124 can determine that the block unit is predicted based on two reference frames. In the described embodiment, the decoder module 124 can predict the block unit based on the two reference frames to generate a prediction block, and then refine the prediction block according to the BDOF mode. In at least one embodiment, the decoder module 124 can reconstruct the block unit based on the refined block by adding the refined block to a residual block of the block unit determined from the bitstream.

[0140] In at least one embodiment, the third syntax structure is a block-based syntax corresponding to the block unit. Accordingly, the third syntax structure is different from the first syntax structure and the second syntax structure, and the third syntax level of the third syntax structure is lower than the first syntax level and the second syntax level.

[0141] In at least one embodiment, when the particular block flag corresponding to the particular refinement tool is equal to zero, the decoder module 124 can determine that the block unit is not reconstructed by the particular one of the refinement tools. Accordingly, the decoder module 124 can reconstruct the block unit based on another prediction mode different from the particular refinement tool to directly generate a prediction block without refinement according to the particular refinement tool. In the described embodiment, the decoder module 124 can reconstruct the block unit based on the prediction block by adding the prediction block to a residual block of the block unit determined from the bitstream.

[0142] At block 510, the decoder module 124 reconstructs the particular region based on a plurality of second candidate modes excluding the refinement tool.

[0143] In at least one embodiment, the reference Figure 2When the third refinement flag corresponding to the particular region is different from the third predefined value, the decoder module 124 can determine to disable all refinement tools in the particular region. Thus, when the third refinement flag is different from the third predefined value, the particular region can be reconstructed based on the second candidate mode that excludes the refinement tools. In one implementation, the third predefined value is equal to zero. In the implementation, when the third refinement flag is equal to one, the decoder module 124 can determine to disable all refinement tools in the particular region. Further, the particular region can be reconstructed based on the second candidate mode. In the implementation, the refinement tools are excluded from the first candidate mode to generate the second candidate mode.

[0144] In at least one implementation, the third refinement flag is a refinement disable flag. In the implementation, when the refinement disable flag is equal to one, the decoder module 124 can determine to disable all refinement tools in the particular region. Thus, the decoder module 124 can determine not to refine the plurality of prediction blocks of the plurality of block units in the particular region according to the refinement tools when reconstructing the particular region. In the implementation, the particular region is reconstructed based on the second candidate mode that excludes the refinement tools. In the implementation, the refinement tools are excluded from the first candidate mode to generate the second candidate mode. For example, the decoder module 124 can predict one block unit in the particular region to generate one prediction block without further refining the prediction block according to the refinement tools, and then directly add the prediction block to a residual block of the block unit to reconstruct the block unit.

[0145] At block 511, the decoder module 124 reconstructs the at least one image frame based on the second candidate mode.

[0146] In at least one implementation, the reference Figure 2 When each of the first refinement flags is different from the first predefined value, the decoder module 124 can determine to disable all refinement tools in the at least one image frame. Thus, when the first refinement flags are different from the first predefined value, the at least one image frame can be reconstructed based on the second candidate mode that excludes the refinement tools. In one implementation, the first predefined value is equal to one. In the implementation, when the first refinement flags are equal to zero, the decoder module 124 can determine to disable the refinement tools in the at least one image frame. Further, when the first refinement flags are equal to zero, the at least one image frame can be reconstructed based on the second candidate mode.

[0147] In at least one embodiment, the first refinement flag is a refinement enabled flag. In the described embodiment, the decoder module 124 can determine to disable the refinement tool in the at least one image frame when the refinement enabled flag is equal to zero. Accordingly, the decoder module 124 can determine to not refine the plurality of prediction blocks of the plurality of block units in the at least one image frame according to the refinement tool when reconstructing the at least one image frame. In the described embodiment, the at least one image frame is reconstructed based on a second candidate mode that excludes the refinement tool. In the described embodiment, the refinement tool is excluded from the first candidate mode to generate the second candidate mode. For example, the decoder module 124 can predict one block unit in the at least one image frame to generate one prediction block, and then add the prediction block directly to a residual block of the block unit to reconstruct the block unit.

[0148] In at least one embodiment, the reference Figure 2 When the first refinement flag is different from the first predefined value, the decoder module 124 determines that the second refinement flag is not present in the first syntax structure. Then, when the second refinement flag is not present in the first syntax structure, the decoder module 124 infers that the second refinement flag of the at least one image frame is equal to zero. In the described embodiment, the third refinement flag is not present in the second syntax structure because the second refinement flag is inferred to be equal to zero. Accordingly, the third refinement flag is not parsed according to the second syntax structure. In the described embodiment, the decoder module 124 can infer that the third refinement flag is equal to one for disabling all refinement tools because the first refinement flag is different from the first predefined value for indicating that all refinement tools are disabled in the at least one image frame.

[0149] In at least one embodiment, the first refinement flag is a refinement enabled flag. In the described embodiment, the decoder module 124 can infer that the third refinement flag is equal to one for disabling all refinement tools because the refinement enabled flag is equal to zero for indicating that all refinement tools are disabled in the at least one image frame.

[0150] Figure 6 A flowchart of an example reconstruction method 600 for reconstructing a block unit according to an example embodiment of the present disclosure is shown. The method 600 is just an example as there are multiple ways of performing the method.

[0151] The method 600 can be performed using the configurations shown in Figure 1 and Figure 2 and various elements in these figures are referenced when explaining the method 600. Figure 6 Each block shown in the figures can represent one or more processes, methods or subroutines performed by one or more computing devices.

[0152] Also, the order of the blocks can only be illustrative and can change. Additional blocks can be added or fewer blocks can be used, without departing from the disclosure.

[0153] At block 601, the decoder module 124 receives, as part of a bitstream, encoded data for at least one picture frame, each picture frame including one or more regions, and determines a first syntax structure from the encoded data.

[0154] Referring to Figure 1 and Figure 2 , the second electronic device 120 can receive, via the second interface 126, a bitstream from an encoder, such as the first electronic device 110 or other video provider. The bitstream can include encoded data corresponding to at least one picture frame. Each of the at least one picture frame can be divided into one or more regions.

[0155] In at least one embodiment, the encoded data can include a first syntax structure corresponding to the at least one picture frame. In at least one embodiment, the first syntax structure can be one of a VPS, an SPS, and a PPS.

[0156] At block 602, when affine mode is enabled in the at least one picture frame, the decoder module 124 determines, from the first syntax structure, a plurality of first affine flags, each first affine flag corresponding to one of a plurality of affine tools in a tool group.

[0157] In at least one embodiment, referring to Figure 2 , the decoder module 124 can determine, from the first syntax structure, an affine enable flag. In the described embodiment, when the affine enable flag in the first syntax structure is equal to one, affine mode can be enabled during reconstruction of the at least one picture frame corresponding to the first syntax structure. In at least one embodiment, the affine mode can include a plurality of affine tools. Thus, when the affine enable flag is equal to one, the affine tools can be enabled during reconstruction of the at least one picture frame. Further, when the affine enable flag in the first syntax structure is equal to zero, affine mode can be disabled for the at least one picture frame. Thus, when the affine enable flag is equal to zero, the at least one picture frame is not reconstructed based on the affine tools. In at least one embodiment, when the first syntax structure is an SPS, the affine enable flag can be a syntax element sps affme enabled flag.

[0158] In at least one embodiment, each of the first affine flags can indicate whether a corresponding affine tool of the affine tools is enabled for the at least one picture frame when affine mode is enabled in the at least one picture frame according to the affine enable flag. In the described embodiment, one of the first affine flags corresponds to one of the affine tools.

[0159] In at least one embodiment, some of the affine tools can be included in the tool group while others of the affine tools are not included in the tool group. In the described embodiment, the decoder module 124 can determine the first affine flags of the affine tools included in the tool group.

[0160] In at least one embodiment, each of the first affine flags can indicate whether a corresponding one of the affine tools in the tool group is enabled for the at least one picture frame. In at least one embodiment, the affine tools in the tool group can include one or more of an affine PROF mode, an AMVR mode, and other affine tools. Further, each of the first affine flags can be an affine enable flag that indicates whether a corresponding one of the affine tools in the tool group is enabled when reconstructing the at least one picture frame. In one embodiment, when the first syntax structure is an SPS, each of the affine enable flags can be a syntax element sps affme enabled flag. For example, the affine enable flags can include more than one of a syntax element sps affme prof enabled flag, a syntax element sps affme amvr enabled flag.

[0161] At block 603, the decoder module 124 determines whether at least one of the first affine flags is equal to a first predefined value. When the decoder module 124 determines that one or more of the first affine flags is equal to the first predefined value, the method 600 can proceed to block 604. When the decoder module 124 determines that each of the first affine flags is different from the first predefined value, the method can proceed to block 611.

[0162] In at least one embodiment, the reference Figure 2 When at least one of the first affine flags is equal to the first predefined value, the decoder module 124 determines that at least one of the affine tools in the tool group is enabled for the at least one picture frame. Further, when each of the first affine flags is different from the first predefined value, the decoder module 124 determines that all of the affine tools in the tool group are disabled during reconstruction of the at least one picture frame. In other words, when the first affine flags are different from the first predefined value, the at least one picture frame is not reconstructed based on the affine tools in the tool group.

[0163] In at least one embodiment, the first predefined value can be equal to one. Thus, when one of the first affine flags is equal to one, the decoder module 124 determines that one of the affine tools in the tool group is enabled for the at least one picture frame. Further, when all of the first affine flags are equal to zero, the decoder module 124 determines that the affine tools in the tool group are disabled during reconstruction of the at least one picture frame.

[0164] At block 604, the decoder module 124 determines that the second affine flag is present in the first syntax structure.

[0165] In at least one embodiment, the second affine flag is associated with the affine tools of the tool group. Figure 2 When at least one of the first affine flags is equal to the first predefined value, the decoder module 124 can determine that the first syntax structure includes the second affine flag. Then, the decoder module 124 can determine the second affine flag from the first syntax structure. In one embodiment, the first predefined value is equal to one. Thus, when at least one of the first affine flags is equal to one, the decoder module 124 can determine the second affine flag from the first syntax structure.

[0166] In at least one embodiment, the second affine flag can indicate whether the encoded data further includes a plurality of secondary flags, each secondary flag indicating whether all affine tools are disabled during reconstruction of a corresponding region in the at least one image frame when at least one of the affine tools in the group of tools is enabled in the at least one image frame according to the first affine flags.

[0167] In at least one embodiment, the second affine flag can be an affine presence flag indicating whether the encoded data further includes a secondary flag indicating whether all affine tools in the group of tools are disabled during reconstruction of one of the regions included in the at least one image frame. In said embodiment, the secondary flag corresponds to the one of the regions in the at least one image frame.

[0168] In at least one embodiment, the second affine flag is only associated with the affine tools of the tool group. In said embodiment, the second affine flag is independent of affine tools not included in the tool group.

[0169] At block 605, the decoder module 124 determines whether the second affine flag is equal to a second predefined value. When the decoder module 124 determines that the second affine flag is equal to the second predefined value, the method 600 can proceed to block 606. When the decoder module 124 determines that the second affine flag is different from the second predefined value, the method can proceed to block 607.

[0170] In at least one embodiment, the second predefined value is associated with the affine tools of the tool group. Figure 2 When the second affine flag is equal to the second predefined value, the decoder module 124 determines that the encoded data further includes a secondary flag, each secondary flag indicating whether all affine tools in the group of tools are disabled during reconstruction of a corresponding region. Further, when the second affine flag is different from the second predefined value, the decoder module 124 determines that the encoded data does not include a secondary flag. In other words, when the second affine flag is different from the second predefined value, no secondary flag is parsed from the encoded data.

[0171] In at least one embodiment, the second predefined value can be equal to one. Thus, when the second affine flag is equal to one, the decoder module 124 determines that the encoded data further includes a second level of flags, each second level flag corresponding to one of the one or more regions in the particular one of the at least one image frame. Moreover, when the second affine flag is equal to zero, the decoder module 124 determines that the second level of flags is not included in the encoded data.

[0172] At block 606, the decoder module 124 determines that a third affine flag is present in a second syntax structure associated with a particular one of the one or more regions in a particular one of the at least one image frame.

[0173] In at least one embodiment, each of the second level of flags is a third affine flag included in a corresponding second syntax structure of the plurality of second syntax structures. In at least one embodiment, the encoded data can include the first syntax structure and the second syntax structures. Moreover, a number of the first syntax structures in the encoded data can be equal to one, and a number of the second syntax structures in the encoded data can be equal to a number of the regions included in the at least one image frame.

[0174] In at least one embodiment, a first syntax level of the first syntax structure is higher than a second syntax level of the second syntax structures. In such an embodiment, each of the second syntax structures can reference the first syntax structure, and the first syntax structure does not reference the second syntax structures. For example, each of the second syntax structures can be a picture header. In another example, each of the second syntax structures can be a slice header.

[0175] In at least one embodiment, the reference Figure 2 When the second affine flag is equal to the second predefined value, the decoder module 124 determines that each of the second syntax structures includes one of the third affine flags. Then, when the second affine flag is equal to the second predefined value, the decoder module 124 can determine the one of the third affine flags from the second syntax structures. In such an embodiment, each of the third affine flags can indicate whether all affine tools in the group of tools are disabled when reconstructing the corresponding region. In one embodiment, the second predefined value is equal to one. Thus, when the second affine flag is equal to one, the decoder module 124 can determine the one of the third affine flags from a corresponding second syntax structure of the second syntax structures corresponding to a particular one of the one or more regions in a particular one of the at least one image frame.

[0176] In at least one embodiment, each of the third affine flags included in a corresponding second syntax structure of the second syntax structures also corresponds to one of the regions in the at least one image frame, as each of the second syntax structures corresponds to one of the regions in the at least one image frame.

[0177] In at least one embodiment, each of the third affine flags corresponds to all affine tools in the tool group, as each of the third affine flags indicates whether all affine tools in the tool group are disabled in the corresponding region of the region in the at least one image frame. In said embodiment, each of the third affine flags is independent of affine tools not included in the tool group.

[0178] In at least one embodiment, each of the third affine flags can be an affine disable flag that indicates whether all affine tools in the tool group are disabled when reconstructing the corresponding region included in the corresponding one of the at least one image frame.

[0179] At block 607, the decoder module 124 infers that the third affine flags are equal to zero.

[0180] In at least one embodiment, referring to Figure 2 When the second affine flag is different from the second predefined value, the decoder module 124 determines that the third affine flags are not present in the second syntax structure. Then, when the third affine flags are not present in the second syntax structure and the second affine flag is present in the first syntax structure, the decoder module 124 infers that the third affine flags for the region in the at least one image frame are equal to zero.

[0181] In at least one embodiment, the second predefined value can be equal to one. Thus, when the second affine flag is equal to zero, the decoder module 124 determines that the third affine flags are not parsed from the second syntax structure. Moreover, when the second affine flag is equal to zero and the second affine flag is present in the first syntax structure, the third affine flags are inferred to be equal to zero.

[0182] At block 608, the decoder module 124 determines whether the third affine flags are equal to a third predefined value. When the decoder module 124 determines that the third affine flags are equal to the third predefined value, the method 600 can proceed to block 609. When the decoder module 124 determines that the third affine flags are different from the third predefined value, the method can proceed to block 610.

[0183] In at least one embodiment, referring to Figure 2 When the third affine flag corresponding to a particular one of the regions is equal to the third predefined value, the decoder module 124 determines that at least one of the affine tools in the tool group is enabled in the particular region. Moreover, when the third affine flag corresponding to the particular region is different from the third predefined value, the decoder module 124 determines that all affine tools in the tool group are disabled in the particular region. In other words, when the third affine flag is different from the third predefined value, the particular region can not be reconstructed based on the affine tools in the tool group.

[0184] In at least one embodiment, the third predefined value can be equal to zero. Thus, when the third affine flag is equal to zero, the decoder module 124 determines to enable at least one of the affine tools in the tool group for the particular region. Further, when the third affine flag is equal to one, the decoder module 124 determines to disable all the affine tools in the tool group in the particular region.

[0185] At block 609, the decoder module 124 reconstructs the particular region based on the plurality of first candidate modes selected according to the first affine flags.

[0186] In at least one embodiment, the reference Figure 2 When the third affine flag corresponding to the particular region is equal to the third predefined value, the decoder module 124 can determine to enable at least one of the affine tools in the tool group in the particular region. Thus, when the third affine flag is equal to the third predefined value, the particular region can be reconstructed based on the first candidate modes including at least one of the affine tools in the tool group. In at least one embodiment, at least one of the affine tools in the tool group can be selected from the affine tools based on the first affine flags. For example, when a particular one of the first affine flags is equal to the first predefined value, a particular one of the affine tools indicated by the particular one of the first affine flags can be added to the first candidate modes. Further, when the particular one of the first affine flags is different from the first predefined value, the particular one of the affine tools can be excluded from the first candidate modes.

[0187] In at least one embodiment, the affine tools not included in the tool group are independent of the second affine flags and the third affine flags. Thus, the first candidate modes can include the affine tools not included in the tool group, as well as other prediction modes.

[0188] In at least one embodiment, the third predefined value is equal to zero. In the embodiment, when the affine disable flag is equal to zero, the decoder module 124 can determine to enable at least one of the affine tools in the tool group in the particular region. Then, the decoder module 124 can determine a plurality of block flags of the block units included in the particular region according to a third syntax structure. In the embodiment, a particular one of the block flags indicates whether a prediction block of a block unit is reconstructed by a particular one of the affine tools.

[0189] In at least one embodiment, the third syntax structure is a block-based syntax corresponding to the block units. Thus, the third syntax structure is different from the first syntax structure and the second syntax structure, and a third syntax level of the third syntax structure is lower than the first syntax level and the second syntax level.

[0190] At block 610, the decoder module 124 reconstructs the particular region based on a second candidate mode of the affine tools in the excluded tool group.

[0191] In at least one embodiment, the reference Figure 2 When the third affine flag corresponding to the particular region is different from a third predefined value, the decoder module 124 can determine to disable all affine tools in the tool group in the particular region. Thus, when the third affine flag is different from the third predefined value, the particular region can be reconstructed based on the second candidate mode of the affine tools in the excluded tool group. In one embodiment, the third predefined value is equal to zero. In the embodiment, when the third affine flag is equal to one, the decoder module 124 can determine to disable all affine tools in the tool group in the particular region. Further, the particular region can be reconstructed based on the second candidate mode. In the embodiment, the affine tools in the tool group are excluded from the first candidate mode to generate the second candidate mode.

[0192] In at least one embodiment, the affine tools not included in the tool group are independent of the second affine flag and the third affine flag. Thus, when the third affine flag is different from the third predefined value, the affine tools not included in the tool group can still be included in the second candidate mode.

[0193] In at least one embodiment, the third affine flag is an affine disable flag. In the embodiment, when the affine disable flag is equal to one, the decoder module 124 can determine to disable all affine tools in the tool group in the particular region. Thus, the decoder module 124 can determine not to reconstruct a plurality of prediction blocks of a plurality of block units in the particular region by the affine tools in the tool group when reconstructing the particular region. In the embodiment, the particular region is reconstructed based on the second candidate mode of the affine tools in the excluded tool group. In the embodiment, the affine tools in the tool group are excluded from the first candidate mode to generate the second candidate mode.

[0194] At block 611, the decoder module 124 reconstructs the at least one image frame based on the second candidate mode.

[0195] In at least one embodiment, the reference Figure 2When each of the first affine flags differs from a first predefined value, the decoder module 124 can determine that all affine tools in the tool group are disabled in at least one image frame. Therefore, when the first affine flags differ from the first predefined value, at least one image frame can be reconstructed based on a second candidate pattern that excludes affine tools from the tool group. In one embodiment, the first predefined value is equal to one. In this embodiment, when the first affine flag is equal to zero, the decoder module 124 can determine that affine tools in the tool group are disabled in at least one image frame. Furthermore, when the first affine flag is equal to zero, at least one image frame can be reconstructed based on a second candidate pattern.

[0196] In at least one embodiment, reference Figure 7 When all first affine flags are different from the first predefined value, decoder module 124 determines that the second affine flag does not exist in the first syntax structure. Then, when the second affine flag does not exist in the first syntax structure, decoder module 124 infers that the second affine flag of at least one image frame is equal to zero. In this embodiment, the third affine flag does not exist in the second syntax structure because the second affine flag is inferred to be equal to zero. Therefore, the third affine flag is not parsed according to the second syntax structure. In this embodiment, decoder module 124 may infer that the third affine flag is equal to one used to disable all affine tools in the tool group because the first affine flag is different from the first predefined value used to indicate that all affine tools in the tool group are disabled in at least one image frame.

[0197] Figure 1 exhibit Figure 1 The block diagram shows an example of an encoder module 114 of a first electronic device 110. The encoder module 114 may include a prediction processor (e.g., prediction processing unit 7141), at least a first adder (e.g., first adder 7142) and a second adder (e.g., second adder 7145), a transform / quantization processor (e.g., transform / quantization unit 7143), an inverse quantization / inverse transform processor (e.g., inverse quantization / inverse transform unit 7144), a filter (e.g., filter unit 7146), a decoded image buffer (e.g., decoded image buffer 7147), and an entropy encoder (e.g., entropy coding unit 7148). The prediction processing unit 7141 may also include a partition processor (e.g., partition unit 71411), an intra-frame prediction processor (e.g., intra-frame prediction unit 71412), and an inter-frame prediction processor (e.g., inter-frame prediction unit 71413). The encoder module 114 may receive source video and encode the source video to output a bitstream.

[0198] The encoder module 114 can receive a source video comprising multiple image frames, and then divide the image frames according to the encoding structure. Each image frame can be divided into at least one image block.

[0199] The at least one image block can include a luma block having a plurality of luma samples and at least one chroma block having a plurality of chroma samples. The luma block and the at least one chroma block can be further partitioned to generate macroblocks, CTUs, CBs, sub-units thereof, and / or another equivalent coding unit.

[0200] In at least one embodiment, the encoder module 114 can perform additional partitioning of the source video. It should be noted that these embodiments are generally applicable to video encoding regardless of how the source video data is partitioned prior to and / or during encoding.

[0201] In at least one embodiment, during the encoding process, the prediction processing unit 7141 can receive a current image block of a particular one of the image frames during the encoding process. The current image block can be a luma block or one of the chroma blocks in the particular image frame.

[0202] The partition unit 71411 can partition the current image block into a plurality of block units. The intra prediction unit 71412 can perform intra prediction encoding of a current block unit relative to one or more neighboring blocks in the same frame as the current block unit in order to provide spatial prediction. The inter prediction unit 71413 can perform inter prediction encoding of the current block unit relative to one or more of the one or more reference image blocks in order to provide temporal prediction.

[0203] In at least one embodiment, the prediction processing unit 7141 can select one of the encoding results generated by the intra prediction unit 71412 and the inter prediction unit 71413 based on a mode selection method such as a cost function. The mode selection method can be a rate-distortion optimization (RDO) process.

[0204] The prediction processing unit 7141 can determine the selected encoding result and provide the prediction block corresponding to the selected encoding result to a first summer 7142 for generating a residual block and to a second summer 7145 for reconstructing the encoded block unit. The prediction processing unit 7141 can also provide syntax elements such as motion vectors, intra mode indicators, partition information, and other syntax information to the entropy encoding unit 7148.

[0205] In at least one embodiment, the intra prediction unit 71412 can intra predict the current block unit. The intra prediction unit 71412 can determine an intra prediction mode for reconstructed samples neighboring the current block unit in order to encode the current block unit.

[0206] In at least one embodiment, intra prediction unit 71412 can encode current block unit using various intra prediction modes and intra prediction unit 71412 or prediction processing unit 7141 can select an appropriate intra prediction mode from the various intra prediction modes. Intra prediction unit 71412 can encode current block unit using a cross-component prediction mode to predict one of two chroma components of current block unit based on a luma component of current block unit. Intra prediction unit 71412 can predict a second of two chroma components of current block unit based on a first of two chroma components of current block unit.

[0207] In at least one embodiment, inter prediction unit 71413 can inter predict current block unit as an alternative to intra prediction performed by intra prediction unit 71412. Inter prediction unit 71413 can perform motion estimation to estimate motion of current block unit for generating a motion vector.

[0208] A motion vector can indicate a displacement of a current block unit within a current image block relative to a reference block unit within a reference image block. Inter prediction unit 71413 can receive at least one reference image block stored in decoded picture buffer 7147 and estimate a displacement based on the received reference image block to generate a motion vector.

[0209] In at least one embodiment, first summer 7142 can generate a residual block by subtracting a prediction block determined by prediction processing unit 7141 from an original current block unit. First summer 7142 can represent one or more components that perform this subtraction operation.

[0210] In at least one embodiment, transform / quantization unit 7143 can apply a transform to a residual block in order to generate residual transform coefficients and then quantize the residual transform coefficients to further reduce bit rate. The transform can be one of a DCT, a DST, an AMT, an MDNSST, a HyGT, a signal dependent transform, a KLT, a wavelet transform, an integer transform, a subband transform, or a conceptually similar transform.

[0211] In at least one embodiment, a transform can convert residual information from a pixel value domain to a transform domain such as a frequency domain. A degree of quantization can be modified by adjusting a quantization parameter.

[0212] In at least one embodiment, transform / quantization unit 7143 can perform a scan on a matrix including quantized transform coefficients. Alternatively, entropy encoding unit 7148 can perform the scan.

[0213] In at least one embodiment, entropy encoding unit 7148 can receive a plurality of syntax elements from prediction processing unit 7141 and transform / quantization unit 7143, including quantization parameters, transform data, motion vectors, intra modes, partition information, and other syntax information. Entropy encoding unit 7148 can encode the syntax elements into a bitstream.

[0214] In at least one embodiment, entropy encoding unit 7148 can entropy encode quantized transform coefficients by performing CAVLC, CABAC, SBAC, PIPE encoding, or another entropy encoding technique to generate an encoded bitstream. The encoded bitstream can be transmitted to another device (second electronic device 120 shown in FIG. 1) or archived for later transmission or retrieval. Figure 2

[0215] In at least one embodiment, inverse quantization / inverse transform unit 7144 can apply inverse quantization and inverse transforms to reconstruct residual blocks in pixel domain for later use as reference blocks. Second adder 7145 can add the reconstructed residual blocks to prediction blocks provided from prediction processing unit 7141 in order to produce reconstructed blocks for storage in decoded picture buffer 7147.

[0216] In at least one embodiment, filter unit 7146 can include a deblocking filter, a SAO filter, a bilateral filter, and / or an ALF to remove blocking artifacts from reconstructed blocks. In addition to deblocking filter, SAO filter, bilateral filter, and ALF, additional filters (in-loop or post-loop) can be used. Such filters are not shown for brevity and the output of second adder 7145 can be filtered.

[0217] In at least one embodiment, decoded picture buffer 7147 can be a reference picture memory that stores reference blocks for use by encoder module 114 to, for example, encode video in intra- or inter-coding modes. Decoded picture buffer 7147 can include a variety of memory devices, such as DRAM (including SDRAM, MRAM, RRAM), or other types of memory devices. Decoded picture buffer 7147 can be on-chip or off-chip relative to other components of encoder module 114.

[0218] In at least one embodiment, encoder module 114 can receive video data and predict a plurality of image frames in the video data using a plurality of prediction modes. In such an embodiment, the prediction modes can include a plurality of refinement tools and an affine mode with a plurality of affine tools. In at least one embodiment, with respect to ​ ​In another implementation, the encoder module 114 can signal at least one of a plurality of first refinement flags, a second refinement flag, and a plurality of third refinement flags according to the prediction results to generate the encoded data corresponding to the at least one image frame of the video data, and then add the encoded data to the bitstream for providing to the decoder module 124.

[0219] The described implementations are to be considered in all respects as illustrative and not restrictive. It should also be understood that the present disclosure is not limited to the particular implementations described herein but can vary in many respects without departing from the scope of the present disclosure.

Claims

1. A method of decoding, by an electronic device, a bitstream, the method comprising: receiving, as part of the bitstream, encoded data of at least one picture frame, wherein each of the at least one picture frame comprises one or more regions; when an affine mode is enabled in the at least one picture frame, determining a first affine flag according to a first syntax structure associated with the at least one picture frame, wherein the first syntax structure is included in the encoded data and the affine mode comprises a plurality of affine tools; when the first affine flag is equal to one, determining that a second affine flag is present in the first syntax structure; when the second affine flag is equal to one, determining that a third affine flag is present in a second syntax structure associated with a particular one of the one or more regions in a particular one of the at least one picture frame, wherein: the second syntax structure is included in the encoded data, and the third affine flag corresponds to one of the plurality of affine tools, and the one of the plurality of affine tools is an affine prediction refinement with optical flow (PROF) mode; and when the third affine flag is equal to zero, reconstructing the particular one of the one or more regions based on a plurality of first candidate modes, the plurality of first candidate modes including the one of the plurality of affine tools, wherein the third affine flag is an affine PROF disable flag that indicates whether the affine PROF mode is disabled when reconstructing the particular one of the one or more regions associated with the second syntax structure.

2. The method of claim 1, further comprising: when the second affine flag is equal to zero, determining that the third affine flag is not present in the second syntax structure.

3. The method of claim 2, further comprising: when the first affine flag is equal to zero, determining that the second affine flag is not present in the first syntax structure; and when the second affine flag is not present in the first syntax structure, inferring that the second affine flag is equal to zero.

4. The method of claim 2, further comprising: when the second affine flag is present in the first syntax structure and the third affine flag is not present in the second syntax structure, inferring that the third affine flag is equal to zero.

5. The method of claim 1, further comprising: when the third affine flag is equal to one, disabling, for the particular one of the one or more regions, the one of the plurality of affine tools; and reconstructing the particular one of the one or more regions based on a plurality of second candidate modes, wherein the one of the plurality of affine tools is excluded from the plurality of first candidate modes to generate the plurality of second candidate modes.

6. The method of claim 1, wherein: the first syntax structure is one of a video parameter set, a sequence parameter set, and a picture parameter set; and the second syntax structure is one of a picture header and a slice header.

7. The method of claim 1, wherein: the first affine flag is an affine PROF enabling flag that indicates whether the affine PROF mode is enabled when reconstructing the at least one picture frame associated with the first syntax structure; and the second affine flag is an affine PROF presence flag that indicates whether the affine PROF disabling flag is included in the second syntax structure.

8. The method of claim 7, further comprising: when the affine PROF enabling flag is equal to zero, disabling the affine PROF mode for the at least one picture frame associated with the first syntax structure; and reconstructing the at least one picture frame based on a plurality of second candidate modes, wherein the affine PROF mode is excluded from the plurality of first candidate modes to generate the plurality of second candidate modes.

9. The method of claim 7, further comprising: when the affine PROF disabling flag is equal to zero, enabling the affine PROF mode for the particular one of the one or more regions associated with the second syntax structure; determining whether a block unit in the particular one of the one or more regions is predicted by the affine mode based on a block flag, wherein the block flag is included in a third syntax structure different from the first syntax structure and the second syntax structure, and the third syntax structure corresponds to the block unit; when the block flag is equal to one, predicting the block unit based on the affine mode to generate a predicted block; and refining the predicted block according to the affine PROF mode.

10. An electronic device for decoding a bitstream, the electronic device comprising: at least one processor; and a storage device coupled to the at least one processor and storing a plurality of instructions that, when executed by the at least one processor, cause the at least one processor to: receive encoded data of at least one picture frame as part of the bitstream, wherein each of the at least one picture frame comprises one or more regions; when an affine mode is enabled in the at least one picture frame, determine a first affine flag from a first syntax structure associated with the at least one picture frame, wherein the first syntax structure is included in the encoded data and the affine mode comprises a plurality of affine tools; when the first affine flag is equal to one, determine that a second affine flag is present in the first syntax structure; when the second affine flag is equal to one, determine that a third affine flag is present in a second syntax structure associated with a particular one of the one or more regions in a particular one of the at least one picture frame, wherein: the second syntax structure is included in the encoded data, and the third affine flag corresponds to one of the plurality of affine tools, and the one of the plurality of affine tools is an affine utilize optical flow for prediction refinement (PROF) mode; and ​ ​ reconstructing the particular one of the one or more regions based on a plurality of first candidate modes, the plurality of first candidate modes including the one of the plurality of affine tools, when the third affine flag is equal to zero, wherein the third affine flag is an affine PROF disable flag that indicates whether the affine PROF mode is disabled when reconstructing the particular one of the one or more regions associated with the second syntax structure.

11. The electronic device of claim 10, wherein, The plurality of instructions, when executed by the at least one processor, further cause the at least one processor to: determine that the second affine flag is not present in the first syntax structure when the first affine flag is equal to zero; infer that the second affine flag is equal to zero when the second affine flag is not present in the first syntax structure; and determine that the third affine flag is not present in the second syntax structure when the second affine flag is equal to zero.

12. The electronic device of claim 10, wherein, The plurality of instructions, when executed by the at least one processor, further cause the at least one processor to: determine that the third affine flag is not present in the second syntax structure when the second affine flag is equal to zero; and infer that the third affine flag is equal to zero when the second affine flag is present in the first syntax structure and the third affine flag is not present in the second syntax structure.

13. The electronic device of claim 10, wherein, The plurality of instructions, when executed by the at least one processor, further cause the at least one processor to: disable the one of the plurality of affine tools for the particular one of the one or more regions when the third affine flag is equal to one; and reconstruct the particular one of the one or more regions based on a plurality of second candidate modes, wherein the one of the plurality of affine tools is excluded from the plurality of first candidate modes to generate the plurality of second candidate modes.

14. The electronic device of claim 10, wherein: the first affine flag is an affine PROF enable flag that indicates whether the affine PROF mode is enabled when reconstructing the at least one image frame associated with the first syntax structure; and the second affine flag is an affine PROF present flag that indicates whether the affine PROF disable flag is included in the second syntax structure.

15. The electronic device of claim 14, wherein, The plurality of instructions, when executed by the at least one processor, further cause the at least one processor to: disable the affine PROF mode for the at least one image frame associated with the first syntax structure when the affine PROF enable flag is equal to zero; and reconstruct the at least one image frame based on a plurality of second candidate modes, wherein the affine PROF mode is excluded from the plurality of first candidate modes to generate the plurality of second candidate modes.

16. A method of decoding, by an electronic device, a bitstream, the method comprising: receiving, as part of the bitstream, encoded data of at least one image frame, wherein each of the at least one image frame includes one or more regions; when affine mode is enabled in the at least one picture frame, determining a first affine flag from a first syntax structure associated with the at least one picture frame, wherein the first syntax structure is included in the coded data and the affine mode includes a plurality of affine tools; determining whether a second affine flag is present in the first syntax structure based on the first affine flag; determining whether a third affine flag is present in a second syntax structure associated with a particular one of the one or more regions in a particular one of the at least one picture frame based on the second affine flag, wherein: the second syntax structure is included in the coded data, and the third affine flag corresponds to one of the plurality of affine tools, and the one of the plurality of affine tools is an affine prediction refinement with optical flow (PROF) mode; and when the third affine flag is equal to zero, reconstructing the particular one of the one or more regions based on a plurality of first candidate modes, the plurality of first candidate modes including the one of the plurality of affine tools, wherein the third affine flag is an affine PROF disable flag that indicates whether the affine PROF mode is disabled when reconstructing the particular one of the one or more regions associated with the second syntax structure.

17. The method of claim 16, further comprising: when the first affine flag is equal to one, determining that the second affine flag is present in the first syntax structure; and when the first affine flag is equal to zero, determining that the second affine flag is not present in the first syntax structure and inferring that the second affine flag is equal to zero.

18. The method of claim 16, further comprising: when the second affine flag is equal to one, determining that the third affine flag is present in the second syntax structure; and when the second affine flag is equal to zero, determining that the third affine flag is not present in the second syntax structure.

19. The method of claim 16, wherein: the first syntax structure is one of a video parameter set, a sequence parameter set, and a picture parameter set; and the second syntax structure is one of a picture header and a slice header.

20. The method of claim 16, further comprising: when the first affine flag is equal to zero, disabling the one of the plurality of affine tools for the at least one picture frame associated with the first syntax structure; and reconstructing the at least one picture frame based on a plurality of second candidate modes, wherein the affine PROF mode is excluded from the plurality of first candidate modes to generate the plurality of second candidate modes, wherein the first affine flag is an affine prediction refinement with optical flow (PROF) enable flag that indicates whether the affine PROF mode is enabled when reconstructing the at least one picture frame associated with the first syntax structure.

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