Clock domain conversion method, verification system and storage medium designed

Abstract

Embodiments of the present disclosure provide a clock domain conversion method, a verification system and a storage medium. The method is used for converting a design from a first clock domain to a second clock domain. The first clock domain is associated with a first clock signal, and the second clock domain is associated with a second clock signal. The frequency of the second clock signal is higher than that of the first clock signal. The method comprises: obtaining a description of a register of the design; generating an enable signal based on the first clock signal, the enable signal being used for enabling the register of the design; and updating the design to apply the enable signal to an enable end of the register. Embodiments of the present disclosure can ensure the behavior consistency of the design when converting from the first clock domain to the second clock domain.

Description

Technical Field

[0001] This disclosure relates to the field of logic system design technology, and in particular to a clock domain conversion method, verification system, and storage medium for a design. Background Technology

[0002] Logic system design (or simply design) refers to the design of circuits such as ASICs (Application Specific Integrated Circuits) and SOCs (System-On-Chip). Design is generally accomplished using specialized HDLs (Hardware Description Languages). HDLs allow for layer-by-layer specification of the design, enabling complex circuit structures to be represented using a series of modules.

[0003] As designs become increasingly powerful, they often employ multiple clock domains to meet the operational requirements of their modules, which involves clock domain transformations. Therefore, when validating a design, it is essential to ensure consistent behavior across different clock domains. Summary of the Invention

[0004] This disclosure presents a clock domain conversion method, a verification system, and a storage medium.

[0005] In a first aspect, embodiments of this disclosure provide a clock domain conversion method for a design, the method being used to convert the design from a first clock domain to a second clock domain, wherein the first clock domain is associated with a first clock signal, and the second clock domain is associated with a second clock signal, the frequency of the second clock signal being higher than the frequency of the first clock signal, the method comprising:

[0006] Obtain the description of the registers in the design;

[0007] An enable signal is generated based on the first clock signal; this enable signal is used to enable the registers in the design.

[0008] Update the design to apply an enable signal to the enable pin of the register.

[0009] In a second aspect, embodiments of this disclosure provide a verification system configured to perform a clock domain conversion method as described in the first aspect above.

[0010] Thirdly, embodiments of this disclosure provide a storage medium that stores at least one set of instructions, which, when executed, cause a verification system to perform the clock domain conversion method designed as described in the first aspect above.

[0011] The clock domain conversion method provided in this disclosure can be used to convert a design from a first clock domain to a second clock domain, wherein the first clock domain is associated with a first clock signal, and the second clock domain is associated with a second clock signal. Since the frequency of the second clock signal is higher than that of the first clock signal, the register behavior of the design will be advanced when converting from the first clock domain to the second clock domain (i.e., the register behavior in the first clock domain is delayed compared to the second clock domain), causing inconsistencies between the design behavior in the second clock domain and the behavior in the first clock domain. Based on this, this disclosure can obtain a description of the design's registers when converting the design from the first clock domain to the second clock domain; generate an enable signal for enabling the register based on the first clock signal in the first clock domain, so that the register reads data and stores processed data. Furthermore, after the register stores the processed data, the register is enabled to output the processed data based on the second clock signal in the second clock domain. In other words, the registers are enabled to read and store processed data based on the first clock signal, and the registers are enabled to output processed data based on the second clock signal, thereby balancing the behavioral delay time of the registers in the first and second clock domains and ensuring the consistency of the design's behavior when converting from the first clock domain to the second clock domain. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0013] Figure 1 A schematic diagram of the host structure provided in an embodiment of this disclosure.

[0014] Figure 2 A schematic diagram of a verification system provided in an embodiment of this disclosure.

[0015] Figure 3A A schematic diagram to verify the system based on the user clock signal enable register.

[0016] Figure 3B The waveform diagram of the system based on the user clock signal enable register is used to verify the system.

[0017] Figure 4A A schematic diagram to verify the system based on the system clock signal enable register.

[0018] Figure 4B The diagram shows a waveform of the verification system provided in this disclosure verifying a design based on an enable signal.

[0019] Figure 5 A flowchart illustrating an exemplary method for clock domain conversion according to an embodiment of the present disclosure is shown. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the embodiments of this disclosure will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0021] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which these embodiments pertain. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0022] Validating a design essentially involves simulating the design on the host machine running the validation system.

[0023] Figure 1 A schematic diagram of a host 100 according to an embodiment of the present disclosure is shown. The host 100 may be an electronic device running a verification system. Figure 1 As shown, the host 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. The processor 102, memory 104, network interface 106, and peripheral interface 108 are interconnected within the host via the bus 110.

[0024] Processor 102 may be a Central Processing Unit (CPU), a graphics processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 can be used to perform functions related to the techniques described in the embodiments of this disclosure. In some embodiments, processor 102 may also include multiple processors integrated as a single logic component. Figure 1 As shown, processor 102 may include multiple processors 102a, 102b and 102c.

[0025] Memory 104 can be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In the design field, a verification system used for simulation verification can be a computer program stored in memory 104. Figure 1 As shown, the data stored in the memory may include program instructions (e.g., program instructions for implementing the technical solutions of the embodiments of this disclosure) and data to be processed (e.g., the memory may store temporary code generated during the compilation process). The processor 102 may also access the program instructions and data stored in the memory and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include random access memory (RAM), read-only memory (ROM), optical disk, magnetic disk, hard disk, solid-state drive (SSD), flash memory, memory stick, etc.

[0026] Network interface 106 can be configured to provide communication with other external devices to host 100 via a network. This network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, Near Field Communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It is understood that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0027] The peripheral interface 108 can be configured to connect the host 100 to one or more peripheral devices to enable information input and output. For example, peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, and various sensors, as well as output devices such as displays, speakers, vibrators, and indicator lights.

[0028] Bus 110 can be configured to transfer information between various components of host 100 (e.g., processor 102, memory 104, network interface 106, and peripheral interface 108), such as internal buses (e.g., processor-memory bus), external buses (USB port, PCI-E bus), etc.

[0029] It should be noted that although the above host architecture only shows processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110, in specific implementations, this host architecture may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above host architecture may only include the components necessary for implementing the embodiments of this disclosure, and does not necessarily include all the components shown in the figures.

[0030] In the design field (such as chip design), verification systems can be used to verify designs.

[0031] Figure 2 A schematic diagram of a verification system 200 according to an embodiment of the present disclosure is shown. (As shown) Figure 2 As shown, the verification system 200 may include a compiler 210 and a verification tool 220.

[0032] The compiler 210 can generate target code based on the computer code to be compiled. The computer code to be compiled can also be called source code, such as a written design. Typically, the source language used to write the source code is a high-level programming language. High-level programming languages ​​can be, for example, software programming languages ​​such as C++ and Java, or hardware description languages ​​such as VHDL, Verilog, and SystemVerilog. In the disclosed embodiments, the design can be described using, for example, Verilog. The target code can be, for example, assembly code, machine code, gate-level netlists, etc. In this disclosed embodiment, the target code is described using a gate-level netlist as an example; however, those skilled in the art should understand that the gate-level netlist in this disclosed embodiment can be replaced by other types of target code. Typically, the compiler 210 can store... Figure 1 The design is stored in memory 104 and executed by processor 102 to compile it into object code.

[0033] Verification tool 220 can perform simulation verification based on the target code and output verification results. Sometimes, verification tool 220 may include an emulator or prototyping. In some embodiments, verification tool 220 may include one or more field-programmable gate arrays (FPGAs) for implementing the target code on verification tool 220. For example, a gate-level netlist can be loaded into the FPGA of verification tool 220, enabling verification tool 220 to implement some or all of the design's functionality. By simulating some or all of the design's functionality on verification tool 220, corresponding signals (e.g., intermediate signals during operation or final output signals) can be read. By analyzing the read signals, engineers can determine whether the design is correct and perform appropriate debugging if the design is incorrect.

[0034] In some embodiments, the design can be a verification environment written in SystemVerilog, such as a Universal Verification Methodology (UVM) environment. By verifying the design using verification system 200, a UVM environment can be constructed, and a device under test (DUT) can be verified within this UVM environment. The design description (e.g., HDL description) can be compiled into a simulation program. This simulation program can then be used as the DUT within the UVM environment.

[0035] In some embodiments, during simulation verification, the verification tool 220 can enable registers in the design based on a user clock within the user clock domain to achieve simulation verification of the design. A clock domain refers to an area in a circuit design controlled by the same clock signal. Signals crossing clock domains require special handling to ensure correct signal transmission. The user clock domain can be user-defined, and the user clock can be a user-defined clock.

[0036] During simulation verification, to accelerate the verification process, slower user clocks can be replaced with faster system clocks (sometimes called root clocks) in some or all modules of the design. In other words, the verification system 200 can replace the slower user clock domain with a faster system clock domain provided by the verification system 200. Typically, the system clock frequency is at least twice that of the user clock. In digital circuit design, circuit operation is usually triggered by clock transitions (e.g., rising or falling edges). Understandably, due to the frequency difference, transitions in the system clock domain arrive faster than in the user clock domain. That is, the behavior of the design will change due to the clock domain replacement. Since the purpose of simulation verification is to realistically mimic the behavior of the design, it is necessary to avoid discrepancies between the simulation verification process and the actual circuit behavior.

[0037] Verification systems typically analyze delay information across all data paths in the design to determine how many cycles the signal should be delayed in the system clock domain. However, this approach is extremely labor-intensive, and with the increasing scale of circuit designs, there is an urgent need to find a new way to quickly synchronize the behavior between different clock domains.

[0038] This disclosure provides a clock domain conversion method, a verification system, and a storage medium.

[0039] Figure 3A A schematic diagram of the verification system based on the user clock signal enable register is shown. (Reference) Figure 3AAs shown, the verification system 200 can acquire the user clock signal 310. The user clock signal 310 can have rising and falling edges. Based on the changes in the rising and falling edges of the user clock signal 310, the verification system 200 can generate high and low level enable signals 330. The verification system 200 transmits the high and low level enable signals 330 to the enable terminal of the register 301 of the design 300, thereby enabling the register 301 in different states.

[0040] In some embodiments, the duration of the high level of the enable signal 330 can be determined by the system clock signal. For example, the duration of the high level of the enable signal 330 can be one cycle of the system clock signal.

[0041] It is understood that register 301 here can refer to the registers in design 300 related to clock domain switching. In some embodiments, register 301 can be all registers in design 300.

[0042] Register 301 can have different states: an on state and an off state. In the on state, design 300 can read and output data via register 301. In the off state, design 300 cannot read or output data, even if it has already processed the data. Thus, by controlling the on and off states of register 301, the output transmission and output of design 300 can be controlled. For example, during the process of enabling register 301 based on the user clock signal 310, register 301 is in the off state, preventing data reading and output, thereby achieving control over the design.

[0043] The switching between different states of register 301 can be triggered by a high-level or low-level enable signal. The high-level enable signal enables the register to be in the on state, and the low-level enable signal enables the register to be in the off state. When the register is in the on state, the verification system 200 performs simulation verification on the design 300.

[0044] Figure 3B The waveform diagram of the verification system based on the user clock signal enable register is shown. Combined with... Figure 3A and Figure 3BWhen the rising edge 311 of the first clock cycle of the user clock signal 310 arrives, the enable signal 330 of the verification system 200 transitions to a high level state 331, thereby enabling register 301 to enter the conduction state. In the conduction state, register 301 processes data by varying the rising or falling edge of the high-level enable signal, reading data Din at the rising edge of the first clock cycle of the enable signal. When the rising edge 312 of the second clock cycle of the user clock signal 310 arrives, the enable signal 330 of the verification system 200 transitions from a low level state 332 to a high level state 333, thereby enabling register 301 to enter the conduction state. Register 301 outputs data Dout at the rising edge of the second clock cycle of the enable signal.

[0045] As mentioned above, since the user clock domain is typically a low-frequency clock domain, the clock period of the user clock signal is usually relatively long. Therefore, controlling the state changes of the enable signal based on the user clock signal to enable the register to be in different operating states will result in a long clock interval between the register's on-state and output state. Based on this, the design can be shifted from the low-frequency user clock domain to the high-frequency system clock domain, thereby shortening the clock interval between the register's on-state and output state by increasing the frequency of the clock signal.

[0046] During simulation verification, design 300 can switch from the user clock domain to the system clock (root clock) domain provided by the verification system, thereby converting the design from a low-frequency clock domain to a high-frequency clock domain. Consequently, the verification system can also enable registers in the design based on the system clock signal in the system clock domain to achieve simulation verification of the design. The system clock can be generated by verification system 200. Figure 4A The diagram illustrates the register enable functionality of the verification system when it transitions from the user clock domain to the system clock domain.

[0047] Combination Figure 4A As shown, the verification system 200 can acquire the system clock signal 320. The system clock signal 320 can have rising and falling edges. Based on the changes in the rising and falling edges of the system clock signal 320, the verification system 200 can generate high-level and low-level enable signals. The verification system 200 transmits high-level and low-level enable signals to the enable terminal of the designed register, thereby enabling the register 301 in different states.

[0048] In the system clock domain, the state of register 301 in design 300 can also include an on state and an off state. When register 301 is on, design 300 can read and output data via register 301. When register 301 is off, design 300 cannot read or output data.

[0049] Figure 4B A waveform diagram 400 is shown illustrating the verification system provided in this embodiment of the present disclosure verifying a design based on an enable signal.

[0050] Waveform diagram 400 includes a first clock domain 401 under the user clock and a second clock domain 402 under the system clock.

[0051] like Figure 4B As shown, in the first clock domain 401, the user clock signal 310 may include rising edges 311, 312, and 313. In some embodiments, design 300 may read input Din 41 at rising edge 311 and output Dout 44 at the next rising edge 312. Similarly, design 300 may read input Din 42 at rising edge 312 and output Dout 45 at the next rising edge 313. That is, design 300 reads data (e.g., Din 41) at the first rising edge, completes processing within one cycle, and outputs the processing result (e.g., Dout 44) at the next rising edge.

[0052] It is understandable that the above example is only used as an illustration of the working principle of the enable signal.

[0053] like Figure 4B As shown, in the second clock domain 402, after the clock domain replacement, the system clock signal 320 replaces the original user clock signal 310. To ensure that the behavior of design 300 in the new clock domain conforms to the design intent, an enable signal 330 is introduced. In some embodiments, the enable signal 330 is a high-level enable signal, meaning that the enable signal 330 includes both a high-level state and a low-level state. Specifically, the enable signal 330 is set to a high-level state in response to the rising edge of the user clock signal 310. That is, the period of the enable signal 330 can be set to be the same as that of the user clock signal 310. Specifically, the rising edge of the enable signal 330 corresponds to the rising edge of the user clock signal 310.

[0054] A high level of enable signal 330 can turn on register 301, allowing data to be transmitted, read, processed, or output via register 301. Conversely, a low level of enable signal 330 can turn off register 301, preventing data from being transmitted, read, processed, or output via register 301. In some embodiments, a high level of enable signal 330 can last for one cycle of system clock signal 320.

[0055] It is understandable that register 301 here refers to a register related to clock domain switching.

[0056] As described above, design 300 reads data (e.g., Din 41) on the first rising edge, completes processing within one cycle, and outputs the processing result (e.g., Dout 44) on the next rising edge. Therefore, when the system clock signal 320 replaces the original user clock signal 310, design 300 should have read input Din 41 after the first rising edge 321 and output Dout 44 after the second rising edge 322. However, because the enable signal 330 is low after a falling edge following the second rising edge 322, register 301 is in a cutoff state. At this time, Dout 44, which should have been output, is temporarily stored in register 301, waiting for the next high level.

[0057] The next high level of enable signal 330 is set to synchronize with the second rising edge 312 of the original user clock signal 310. Thus, when the next high level of enable signal 330 arrives, register 301 can correspondingly output Dout 44, which was previously temporarily stored in register 301. To distinguish between different signals, the output of register 301... Figure 4B The output is displayed as Dout_temp 46. It is worth noting that Dout_temp 46 is only the output of register 301, not the output of register 300.

[0058] The output of register 301 is then sampled by design 300 before being obtained by design 300. Design 300 will sample Dout_temp 46 in response to the rising edge (i.e., rising edge 323) of the next system clock signal 320 after register 301 outputs Dout_temp 46.

[0059] Therefore, design 300 will start outputting Dout48 at the moment corresponding to the rising edge 323 of the system clock signal 320. It can be understood that Dout48 and Dout44 have the same value.

[0060] Compared to design 300 driven by user clock signal 310, Dout 48 is delayed by one cycle of system clock signal 320 compared to Dout 44. However, since Dout 48 is read by the user clock signal 310 at the next clock signal (e.g., the rising edge 313 of user clock signal 310), from the perspective of user clock signal 310, the behavior of Dout 48 is consistent with that of Dout 44. That is, at the moment corresponding to the rising edge 313 of user clock signal 310, the behavior of design 300 is the same from an external perspective.

[0061] Therefore, by providing the enable signal 330 to register 301, design 300 can maintain the same behavior in the system clock domain (i.e., excited by the system clock signal 320) as in the user clock domain (i.e., excited by the user clock signal 310).

[0062] In some embodiments, the verification system 200 may include a digital signal processor (DSP) or a first-in-first-out (FIFO) memory. A DSP is a processor that processes signals using numerical calculations; a FIFO memory is a processor that processes signals in a first-in-first-out manner.

[0063] Figure 5 A flowchart illustrating an exemplary method 500 for clock domain conversion according to an embodiment of the present disclosure is shown. Method 500 can be performed by... Figure 2 The verification system 200 is implemented. Specifically, method 500 can be implemented by... Figure 2 The verification system 200 shown is implemented. The method 500 is used to verify designs (e.g., Figure 3A Design 300) from the first clock domain (e.g., Figure 4B The first clock domain 401) is switched to the second clock domain (e.g., Figure 4B The second clock domain 402). The first clock domain and the first clock signal (e.g., Figure 4B The user clock signal 310) is associated with the second clock domain, which is associated with the second clock signal (e.g., Figure 4B The system clock signal 320 is associated with the second clock signal, the frequency of which is higher than the frequency of the first clock signal. Method 500 may include the following steps.

[0064] In step S502, the verification system 200 obtains the design's registers (e.g., Figure 4A and 4B The description of register 301 in the database. By obtaining the description of the register, the verification system 200 can modify the design in subsequent steps (e.g., apply an enable signal to the register) to achieve signal domain conversion.

[0065] In step S504, the verification system 200 is based on a first clock signal (e.g., Figure 4B The user clock signal 310 (shown) generates an enable signal (e.g., Figure 4B The enable signal 330 is shown. The first clock signal includes a first transition edge and a second transition edge opposite to the first transition edge. For example, the first transition edge can be a rising edge, while the second transition edge can be a falling edge.

[0066] This enable signal is used to enable the registers in the design. In other words, the enable signal can put the registers in a conducting state. In some embodiments, the enable signal includes a first state (e.g., Figure 4B The high-level state shown) and the second state (e.g.) Figure 4B (As shown in the low-level state). The first state turns the register on, and the second state turns the register off. The register includes all registers related to transitioning the design from the first clock domain to the second clock domain.

[0067] In some embodiments, generating an enable signal based on a first clock signal further includes: in response to the arrival of a first transition edge of the first clock signal, setting the enable signal to a first state (e.g., ...). Figure 4B The high-level state shown); and in response to the first state lasting for a given time period, the enable signal is placed in the second state (e.g., Figure 4B The low-level state is shown. Where the given time period is one clock cycle of the second clock signal (e.g., ...). Figure 4B (This refers to one cycle of the system clock signal 320 shown).

[0068] The design may include a digital signal processor (DSP) or a first-in-first-out (FIFO) memory. A DSP is a processor that processes signals using numerical calculations; a FIFO memory is a processor that processes signals using a first-in-first-out (FIFO) method.

[0069] In step S506, the verification system 200 can update the design (e.g. Figure 4B Design 300 in the middle) to apply an enable signal (such as Figure 4B The enable signal 330 in the register is sent to the enable terminal of the register.

[0070] Understandably, the verification system 200 can run the updated design described above to simulate the design in the second clock domain (i.e., the system clock domain).

[0071] The clock domain conversion method provided in this disclosure enables the designed register to read and store processed data based on a first clock signal, and enables the register to output processed data based on a second clock signal, thereby balancing the behavioral delay time of the register in the first clock domain and the second clock domain, and ensuring the consistency of the design behavior when switching from the first clock domain to the second clock domain.

[0072] Based on the same inventive concept, corresponding to any of the above embodiments, this disclosure also provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform the methods of any of the above embodiments.

[0073] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0074] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to perform the method as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0075] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the embodiments of this disclosure (including the claims) is limited to these examples; under the concept of the embodiments of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of the different aspects of the embodiments of this disclosure as described above, which are not provided in the details for the sake of brevity.

[0076] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this disclosure, the provided drawings may or may not show well-known power / ground connections to integrated circuit (IC) chips and other components. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this disclosure, and this also takes into account the fact that the details of implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this disclosure will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of the embodiments of this disclosure, it will be apparent to those skilled in the art that the embodiments of this disclosure can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0077] Although embodiments of the present disclosure have been described in conjunction with specific examples thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0078] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A method of clock domain conversion for a logic system design, wherein, The method is used for converting a signal stimulating the design from a first clock domain to a second clock domain, the first clock domain is associated with a first clock signal, the second clock domain is associated with a second clock signal, a frequency of the second clock signal is higher than a frequency of the first clock signal, the method is performed by a verification system, and the method comprises: obtaining a description of a register of the design; the description is completed by a hardware description language; generating an enable signal based on the first clock signal, the enable signal is used for enabling the register of the design; and modifying the design based on the description of the register of the design to apply the enable signal to an enable end of the register.

2. The method of claim 1, wherein, The enable signal comprises a first state and a second state, the first clock signal comprises a first transition edge and a second transition edge opposite to the first transition edge, wherein the first state makes the register conductive, the second state makes the register non-conductive, and generating the enable signal based on the first clock signal further comprises: in response to the first transition edge of the first clock signal, setting the enable signal to the first state; and in response to the first state lasting for a given time period, setting the enable signal to the second state.

3. The method of claim 2, wherein, The given time period is one clock period of the second clock signal.

4. The method of claim 2, wherein, The first transition edge is a rising edge, the second transition edge is a falling edge, the first state is a high level, and the second state is a low level.

5. The method according to any one of claims 1 to 4, wherein, The design comprises a digital signal processor or a first-in-first-out memory.

6. The method of claim 1, wherein, Converting the design from the first clock domain to the second clock domain is used for verifying the design on the verification system.

7. The method of claim 6, wherein, The first clock domain is a user clock domain, and the first clock signal is a user-defined user clock signal; the second clock domain is a system clock domain, and the second clock signal is a system clock signal generated by the verification system.

8. The method of claim 1, wherein, The register comprises all registers related to converting the design from the first clock domain to the second clock domain.

9. A verification system wherein, The verification system comprises a compiler and a verification tool, and the verification system is configured to perform the clock domain conversion method of the design as claimed in any one of claims 1-8.

10. A storage medium, wherein, The storage medium stores at least one set of instructions, which when executed, causes the verification system to perform the clock domain conversion method of the design as claimed in any one of claims 1-8.

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