Automatic generation method and device for logic test cases based on control logic diagrams

Abstract

The present application discloses a method and apparatus for automatically generating logic test cases based on a control logic diagram. The method includes: obtaining a control logic diagram composed of basic algorithm blocks and a description file corresponding to the basic algorithm blocks; using a parsing function to parse the control logic diagram to generate a simulation task file; compiling the description file corresponding to the basic algorithm blocks into an algorithm function corresponding to the basic algorithm blocks and an algorithm block dynamic link library file for recording the storage address of the algorithm function; according to the call order recorded in the simulation task file and the storage address recorded in the algorithm block dynamic link library file, calling the algorithm function to perform simulation operations on the control logic diagram corresponding to the simulation task file; generating a test output result according to the test input and the control logic diagram simulation operation model, and finally generating a test case. This method and apparatus can automatically generate test cases according to the control logic diagram, effectively improving the construction speed of test cases and reducing errors caused by human factors.

Description

Technical Field

[0001] The present application relates to the technical field of digital instrument control systems, and particularly to a method and device for automatically generating logic test cases based on a control logic diagram. Background Art

[0002] Test cases are test cases written based on the logic diagram of the automatic control scheme of the nuclear power plant process during the engineering test process, and are used to verify whether the DCS (Digital Instrument & Control System) system of the nuclear power plant meets the requirements of the logic diagram.

[0003] In the related art, designers usually need to manually model according to the logic diagram. Due to the complexity of the DCS system technology of nuclear power plants and the huge workload, the work efficiency is low, and human error is easily introduced, resulting in incorrect expected results of the test cases. Summary of the Invention

[0004] The purpose of the present application is to solve at least one of the above technical problems to some extent.

[0005] To this end, the first object of the present application is to propose a method for automatically generating logic test cases based on a control logic diagram, which can automatically generate test cases according to the control logic diagram, effectively improve the construction speed of the test cases, and reduce errors caused by human factors.

[0006] The second object of the present application is to propose a device for automatically generating logic test cases based on a control logic diagram.

[0007] The third object of the present application is to propose a computer device.

[0008] The fourth object of the present application is to propose a non-transitory computer-readable storage medium.

[0009] To achieve the above object, the first aspect embodiment of the present application proposes a method for automatically generating logic test cases based on a control logic diagram, including:

[0010] Obtain a control logic diagram composed of basic algorithm blocks and a description file corresponding to the basic algorithm blocks;

[0011] Use an analysis function to analyze the control logic diagram to generate a simulation task file, and the simulation task file is used to determine the call order of the basic algorithm blocks in the control logic diagram;

[0012] Compile the description file corresponding to the basic algorithm block into an algorithm function corresponding to the basic algorithm block and an algorithm block dynamic link library file for recording the storage address of the algorithm function;

[0013] Call the algorithm functions in order according to the call order of the basic algorithm blocks recorded in the simulation task file and the storage addresses of the algorithm functions recorded in the algorithm block dynamic link library file, so as to perform simulation operations on the control logic diagram corresponding to the simulation task file;

[0014] Generate test outputs according to the test inputs and the simulation operations of the control logic diagram, and finally generate test cases.

[0015] Optionally, the control logic diagram includes the basic algorithm blocks and the connecting lines connecting the basic algorithm blocks. The parsing of the control logic diagram using the parsing function includes:

[0016] Parse the basic algorithm block elements corresponding to the basic algorithm blocks using the first parsing function, where the basic algorithm block elements include the basic algorithm block name, the shape appearance of the basic algorithm block, and the shape data of the basic algorithm block;

[0017] Parse the coordinate positions of the connecting lines using the second parsing function, and map the coordinate positions to the input point positions or output point positions of the basic algorithm blocks.

[0018] Optionally, the shape appearance corresponding to the basic algorithm block includes input point names and output point names. The simulation task file includes at least one test input point combination, and the test input point combination includes at least one input point name. Before calling the algorithm functions in order according to the call order of the basic algorithm blocks recorded in the simulation task file and the storage addresses of the algorithm functions recorded in the algorithm block dynamic link library file to perform simulation operations on the control logic diagram corresponding to the simulation task file, it further includes:

[0019] Obtain the test input point combination corresponding to the control logic diagram; or

[0020] Parse the control logic diagram according to the test coverage criterion to obtain the test input point combination corresponding to the control logic diagram.

[0021] Optionally, the test case file includes the test input point combination and the output point combination corresponding to each test input point combination after simulation operations.

[0022] Optionally, before calling the algorithm functions in order according to the call order of the basic algorithm blocks recorded in the simulation task file and the storage addresses of the algorithm functions recorded in the algorithm block dynamic link library file to perform simulation operations on the control logic diagram corresponding to the simulation task file, it further includes:

[0023] Generate a simulation data file according to at least one of the basic algorithm blocks recorded in the control logic diagram, where the simulation data file is used to store the basic algorithm block elements corresponding to the basic algorithm blocks;

[0024] After orderly calling the algorithm functions according to the call order of the basic algorithm blocks recorded in the simulation task file and the storage addresses of the algorithm functions recorded in the algorithm block dynamic link library file to perform simulation operations on the control logic diagram corresponding to the simulation task file, it further includes:

[0025] Write the operation result corresponding to each basic algorithm block to the corresponding position of the basic algorithm block in the simulation data file.

[0026] Optionally, the basic algorithm block is defined by a Visio stencil, the control logic diagram can be obtained by connecting the defined Visio stencils through lines, and the parsing function is a Visio parsing function.

[0027] The method for automatically generating logic test cases based on a control logic diagram according to an embodiment of the present application, after obtaining the control logic diagram, can automatically parse and simulate the control logic diagram using a parsing function, without manual participation, effectively improving the generation efficiency of logic test cases, reducing human errors, and improving the accuracy and reliability of test cases.

[0028] To achieve the above object, an embodiment of the second aspect of the present application proposes a device for automatically generating logic test cases based on a control logic diagram, including:

[0029] An acquisition module, configured to acquire a control logic diagram composed of basic algorithm blocks and a description file corresponding to the basic algorithm blocks;

[0030] A parsing module, configured to parse the control logic diagram using a parsing function to generate a simulation task file, where the simulation task file is used to determine the call order of each basic algorithm block in the control logic diagram;

[0031] A compilation module, configured to compile the description file corresponding to the basic algorithm block into an algorithm function corresponding to the basic algorithm block and an algorithm block dynamic link library file for recording the storage address of the algorithm function;

[0032] A simulation module, configured to orderly call the algorithm functions according to the call order of the basic algorithm blocks recorded in the simulation task file and the storage addresses of the algorithm functions recorded in the algorithm block dynamic link library file to perform simulation operations on the control logic diagram corresponding to the simulation task file;

[0033] A generation module for simulating operations based on test inputs and the control logic diagram to generate test outputs and finally generate test cases.

[0034] Optionally, the control logic diagram includes the basic algorithm blocks and the connecting lines connecting the basic algorithm blocks. The parsing module is further configured to:

[0035] Parse the basic algorithm block elements corresponding to the basic algorithm blocks by using a first parsing function. The basic algorithm block elements include the basic algorithm block name, the shape appearance of the basic algorithm block, and the shape data of the basic algorithm block;

[0036] Parse the coordinate positions of the connecting lines by using a second parsing function and map the coordinate positions to the input point positions or output point positions of the basic algorithm blocks.

[0037] Optionally, the shape appearance corresponding to the basic algorithm block includes input point names and output point names. The simulation task file includes at least one test input point combination, and the test input point combination includes at least one input point name. The simulation module is further configured to:

[0038] Obtain the test input point combination corresponding to the control logic diagram; or

[0039] Parse the control logic diagram according to the test coverage criterion to obtain the test input point combination corresponding to the control logic diagram.

[0040] Optionally, the test case file includes the test input point combination and the output point combination corresponding to each test input point combination after simulation operations.

[0041] Optionally, the simulation module is further configured to:

[0042] Generate a simulation data file according to at least one of the basic algorithm blocks recorded in the control logic diagram. The simulation data file is used to store the basic algorithm block elements corresponding to the basic algorithm blocks;

[0043] Write the operation result corresponding to each basic algorithm block to the corresponding position of the basic algorithm block in the simulation data file.

[0044] Optionally, the basic algorithm block is defined by a visio stencil, and the control logic diagram can be obtained by connecting the defined visio stencils with connecting lines. The parsing function is a visio parsing function.

[0045] The automatic generation device of logic test cases based on a control logic diagram according to the embodiments of the present application can automatically parse and simulate the control logic diagram by using a parsing function after obtaining the control logic diagram, without manual participation, effectively improving the generation efficiency of logic test cases, reducing human errors, and improving the accuracy and reliability of test cases.

[0046] To achieve the above object, an embodiment of the third aspect of the present application provides a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the method described in the embodiment of the first aspect is implemented.

[0047] To achieve the above object, an embodiment of the fourth aspect of the present application further provides a non-transitory computer-readable storage medium, on which a computer program is stored. The computer program, when executed by a processor, implements the method described in the embodiment of the first aspect.

[0048] Additional aspects and advantages of the present application will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present application. Description of the Drawings

[0049] The schematic diagrams of the drawings forming a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0050] Figure 1 is a schematic diagram of the generation principle of a test case in the related art;

[0051] Figure 2 is a schematic diagram of the generation principle of another test case in the related art;

[0052] Figure 3 is a flowchart of the automatic generation method of logic test cases based on a control logic diagram according to an embodiment of the present application;

[0053] Figure 4 is a schematic diagram of the appearance of the shape of a basic algorithm block according to an embodiment of the present application;

[0054] Figure 5 is a schematic diagram of the data parameters of the shape of a basic algorithm block according to an embodiment of the present application;

[0055] Figure 6 is a schematic diagram of a control logic diagram according to an embodiment of the present application;

[0056] Figure 7 is a schematic diagram of the description file of a basic algorithm block according to an embodiment of the present application;

[0057] Figure 8 It is a schematic diagram of the principle of the simulation process in an embodiment of the present application;

[0058] Figure 9 It is a schematic diagram of a test case file in an embodiment of the present application;

[0059] Figure 10 It is a schematic structural diagram of a logic test case automatic generation device based on a control logic diagram in an embodiment of the present application. Specific embodiments

[0060] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0061] The following further describes the present application in detail with specific embodiments, and these embodiments should not be construed as limiting the scope claimed by the present application.

[0062] The digital control system (DCS system) of a nuclear power plant is the nerve center of the nuclear power plant, and a large number of complex logical operations are performed internally to complete the control of the process equipment and function regulation of the entire nuclear power plant. Therefore, it is crucial to ensure the correctness of the logical operations.

[0063] In the related art, nuclear power plant designers draw the process automation control scheme into a control logic diagram according to the standardized drawing principle, and this control logic diagram is a standardized formal language. The nuclear power plant DCS engineering designers perform software configuration according to the control logic diagram, compile and download it to the hardware, and then form the nuclear power DCS system. The nuclear power DCS system engineering testers write and execute test cases according to the control logic diagram to verify whether the DCS system meets the requirements.

[0064] Specifically, as Figure 1 shown, the design of traditional test cases is all performed manually. The test cases include the names of test input points, the names of test output points, test input combinations, and test output combinations. In application, testers first extract the names of test input points and test output points according to the control logic diagram, then perform principle analysis on the control logic diagram, design several signals simulating the operating conditions of on-site equipment and their changes according to the control logic diagram to obtain test input combinations, and finally, according to the logical relationships recorded in the control logic diagram, manually calculate the test output combinations under the test input combinations, that is, manually calculate the test results, and use the manually calculated results as test cases.

[0065] Alternatively, as shown in [2], the research on the design method of the reactor protection system function logic test based on MATLAB introduces a logic test design method for the reactor protection system based on simulation software. By using the graphical modeling, simulation, and analysis functions of Simulink in MATLAB software, testers can model and simulate in Simulink according to the control logic diagram of the reactor protection system, which helps the test designers deduce the test output combinations of the reactor protection system and design test cases.

[0066] However, due to the large number of on-site devices and complex processes in nuclear power plants, the control logic diagrams reflecting the automatic control schemes of nuclear power plant processes are very complex, making it difficult and inaccurate to determine the test output combinations based on the control logic diagrams.

[0067] Based on this, the present application proposes a method and device for automatically generating logic test cases based on a control logic diagram, which can automatically generate test cases according to the control logic diagram, effectively improve the construction speed of test cases, and reduce errors caused by human factors.

[0068] The following describes the method and device for automatically generating logic test cases based on a control logic diagram according to the embodiments of the present application with reference to the accompanying drawings.

[0069] Figure 3 is a flowchart of a method for automatically generating logic test cases based on a control logic diagram according to an embodiment of the present application.

[0070] As Figure 3 shown, the method includes the following steps:

[0071] S1, obtain a control logic diagram composed of basic algorithm blocks and a description file corresponding to the basic algorithm blocks.

[0072] It should be noted that the control logic diagram is a logic diagram drawn by test designers according to the design requirements of the DCS system of a nuclear power plant and based on standardized drawing principles.

[0073] In one or more embodiments, the control logic diagram is formed by connecting multiple basic algorithm blocks through wires. Optionally, the basic algorithm blocks can be defined by visio software to standardize the basic algorithm blocks. For example, when constructing the basic algorithm blocks, the names, shapes, and shape data of the basic algorithm blocks are specified.

[0074] For example, as Figure 4 and Figure 5As shown in the figure, when standardizing the ON-delay basic algorithm block, first use the basic shapes (such as rectangles, texts, etc.) of Visio software to draw the shape appearance of the basic algorithm block, and clearly mark the input point positions and output point positions on the appearance. Then, define the shape data of the basic algorithm block, including but not limited to the unique encoding, delay time, function classification, etc. of the basic algorithm block. Finally, generate a Visio stencil file according to the set shape appearance and shape data of the basic algorithm block, and name the stencil file to obtain the name of the basic algorithm block.

[0075] Further, as Figure 6 shown in the figure, materialize the defined shape appearance of the basic algorithm block, and connect the input points and output points in the shape appearance of the basic algorithm block according to the design requirements to obtain a control logic diagram.

[0076] The description file corresponding to the basic algorithm block describes the function of the basic algorithm block, the definition of input connection points, the definition of output connection points, the parameters of the basic algorithm block, and special instructions. The function of the basic algorithm block is usually described in the form of text or input / output waveform diagrams. Taking the above ON-delay basic algorithm block as an example, the description file of the ON-delay basic algorithm block is the waveform diagram as Figure 7 shown in the figure, where x is the input waveform, y is the input waveform, and T is the delay parameter.

[0077] Optionally, the obtained control logic diagram and description file can be extensible markup language files, such as XML files, etc.

[0078] S2. Use the parsing function to parse the control logic diagram to generate a simulation task file, and the simulation task file is used to determine the call order of each basic algorithm block in the control logic diagram.

[0079] It should be understood that since the control logic diagram includes basic algorithm blocks and the wires connecting the basic algorithm blocks, therefore, the parsing of the control logic diagram is actually the parsing of the basic algorithm blocks and the wires, including but not limited to the parsing of the names, parameters, and functions of the basic algorithm blocks, as well as the input points, output points, and connection order of at least two basic algorithm blocks connected by the wires. Based on this, through the parsing of the control logic diagram, a simulation task file for determining the call order of each basic algorithm block in the control logic diagram can be obtained by parsing the basic algorithm blocks and the wires.

[0080] Further, using the parsing function to parse the control logic diagram includes: using the first parsing function to parse the basic algorithm block elements corresponding to the basic algorithm block, and the basic algorithm block elements include the basic algorithm block name, the shape appearance of the basic algorithm block, and the shape data of the basic algorithm block; using the second parsing function to parse the coordinate positions of the wires, and mapping the coordinate positions to the input point positions or output point positions of the basic algorithm block.

[0081] Among them, the first parsing function can be the first Visio parsing function, that is, the first Visio parsing function can be used to parse the basic algorithm blocks in the control logic diagram, and parse out the name, static attributes, and dynamic attributes set for the basic algorithm blocks when defining the basic algorithm blocks. Among them, the static attributes include but are not limited to the shape appearance of the basic algorithm blocks, and the dynamic attributes include but are not limited to the shape data of the basic algorithm blocks.

[0082] The second parsing function can also be the second Visio parsing function, that is, the second Visio parsing function can be used to parse the connection lines in the control logic diagram, parse out the coordinates corresponding to the starting position and the coordinates corresponding to the ending position of the connection line, and then, according to the input point position coordinates and output point coordinate positions of each basic algorithm block in the control logic diagram, determine at least two basic algorithm blocks connected by the connection line and the logical order between at least two basic algorithm blocks.

[0083] It should be understood that before parsing the basic algorithm blocks and connection lines in the control logic diagram by using the first parsing function and the second parsing function respectively, it is necessary to first identify the basic algorithm blocks and connection lines in the control logic diagram, that is, extract the basic algorithm blocks and connection lines from the control logic diagram, and then use the first parsing function and the second parsing function for parsing respectively.

[0084] Thus, when the basic algorithm blocks are defined using Visio software in this application, using the Visio parsing function to parse them can quickly and accurately achieve the purpose of parsing the control logic diagram, without the need for manual analysis by test designers, effectively improving the parsing efficiency for subsequent automatic test case generation. At the same time, it effectively reduces human errors and improves the quality guarantee for the subsequently automatically generated test cases.

[0085] S3. Compile the description file corresponding to the basic algorithm block into an algorithm function corresponding to the basic algorithm block and an algorithm block dynamic link library file for recording the storage address of the algorithm function.

[0086] It should be noted that a dynamic link library enables a process to call functions that do not belong to its executable code. The executable code of the function is located in a DLL file, and this DLL contains one or more functions that have been compiled, linked, and stored separately from the process using them. That is to say, in this application, by compiling the description file corresponding to the basic algorithm block into an executable function and storing it in the DLL file, and generating an algorithm dynamic link library for recording the function address corresponding to the basic algorithm block, the functions corresponding to each basic algorithm block can be called from the storage file during simulation operation.

[0087] Optionally, the description file corresponding to the basic algorithm block can be compiled according to the execution language of the simulation run. For example, when the language of the simulation run is Microsoft Visual C++, the description file corresponding to the basic algorithm block is compiled into an algorithm function in Microsoft Visual C++ language.

[0088] Specifically, a compilation template can be written according to the types of multiple basic algorithm blocks in the nuclear power DCS system, and then, according to the parsing results of the basic algorithm blocks, information such as input type, output type, delay time, and function classification is filled into the compilation template to obtain the algorithm function corresponding to the basic algorithm block. Finally, the algorithm functions compiled from the description files corresponding to all the basic algorithm blocks in the control logic diagram are summarized and stored in a DLL file, and an algorithm block dynamic link library is generated according to the storage addresses of the algorithm functions in the storage file.

[0089] S4. According to the call order of the basic algorithm blocks recorded in the simulation task file and the storage addresses of the algorithm functions recorded in the algorithm block dynamic link library file, the algorithm functions are called in an orderly manner to perform a simulation operation on the control logic diagram corresponding to the simulation task file.

[0090] Among them, the test case and the simulation task file can have a one-to-one correspondence relationship, that is, the call order of the basic algorithm blocks recorded in a simulation task file corresponds to the simulation order of a test case.

[0091] Specifically, as Figure 8 shown, when performing the simulation, first determine the order of executing the basic algorithm blocks according to the simulation task file obtained by parsing the connections in the control logic diagram. Then, when it comes to executing the algorithm function corresponding to a certain basic algorithm block, the algorithm function of this basic algorithm block is called according to the storage location of the algorithm function recorded in the algorithm block dynamic link library. In this way, it goes straight from the first basic algorithm block in the simulation task file to the last basic algorithm block, completing the simulation run of the simulation task file and obtaining the test result.

[0092] In one or more embodiments, the shape and appearance corresponding to the basic algorithm block include input point names and output point names. The simulation task file includes at least one test input point combination, and the test input point combination includes at least one input point name. Before performing the simulation run of the test case according to the simulation task file and calling the algorithm function in an orderly manner according to the algorithm block dynamic link library to obtain the test result, it further includes: obtaining the test input point combination corresponding to the control logic diagram, or parsing the control logic diagram according to the test coverage criterion to obtain the test input point combination corresponding to the control logic diagram.

[0093] It should be understood that the operation of the DCS system in a nuclear power plant is usually not in a static environment, that is, the operating state may change the operating logic according to different complex requirements and other conditions. Therefore, although the control logic diagram gives a complete operating diagram, during specific operation, it is still easy to have a state of variable input operation. Therefore, the test of the control logic diagram also needs to be carried out in an environment of variable input point combinations.

[0094] Among them, when the test input point combination of the DCS system in a nuclear power plant is a fixed combination, for example, the input situation of the control logic diagram is a specific one or more combination ranges, at this time, the test designer can directly input the test input point combination corresponding to the control logic diagram, reduce redundant simulation operations, and improve the overall simulation efficiency.

[0095] Or, when the test input point combination of the DCS system in a nuclear power plant is uncertain, the control logic diagram can be parsed according to the test coverage criterion to obtain the test input point combination corresponding to the control logic diagram, that is, the input points in the control logic diagram can be arranged and combined to obtain multiple test input point combinations. Optionally, the initial input points in the control logic diagram can be identified, that is, the total input points in the control logic diagram, or the output points corresponding to the first basic algorithm block, and then the initial input points are arranged and combined to obtain the input point combination.

[0096] Specifically, obtain the control logic diagram composed of basic algorithm blocks and the corresponding description file of the basic algorithm blocks, then use the parsing function to parse the control logic diagram to obtain the call order of each basic algorithm block in the control logic diagram, and determine at least one set of test input point combinations from the control logic diagram according to the test coverage criterion, and obtain the call logic of the basic algorithm blocks corresponding to the test input point combination based on the test input point combination and the call order of each basic algorithm block. Among them, the call logic of the basic algorithm blocks corresponding to the test input point combination is a test case. According to the call logic of the basic algorithm blocks corresponding to the test input point combination, the algorithm functions are called in turn according to the algorithm block dynamic link library to realize the simulation operation of the test case and obtain the test result.

[0097] S5, perform simulation operations according to the test input and the control logic diagram, generate test outputs, and finally generate test cases.

[0098] Among them, the test input includes but is not limited to the control strategy for the test input points, such as the on or off state of the switch, etc.

[0099] It should be noted that as Figure 9 shown, the test case file includes the test input point combination and the output point combination corresponding to each test input point combination after simulation operation.

[0100] That is to say, the test case file is used to store and express the output conditions obtained by executing the control logic diagram under various combinations of input points, where the output conditions are expressed by combinations of output points.

[0101] In one or more embodiments, before the simulation operation of the test case is implemented by sequentially calling algorithm functions according to the simulation task file and the algorithm block dynamic link library file to obtain test results, it further includes: generating a simulation data file according to at least one basic algorithm block recorded in the control logic diagram, where the simulation data file is used to store basic algorithm block elements corresponding to the basic algorithm blocks; after the simulation operation of the test case is implemented by sequentially calling algorithm functions according to the simulation task file and the algorithm block dynamic link library file to obtain test results, it further includes: writing the operation result corresponding to each basic algorithm block to the corresponding position of the basic algorithm block in the simulation data file.

[0102] That is to say, in order to facilitate the test designer to correct the control logic diagram, the operation results of each basic algorithm block can also be saved and stored in the storage position of the basic algorithm block elements corresponding to the basic algorithm blocks.

[0103] Specifically, obtain the control logic diagram composed of basic algorithm blocks and the description file corresponding to the basic algorithm blocks, use the parsing function to parse the control logic diagram to obtain the basic algorithm block elements corresponding to the basic algorithm blocks, save the basic algorithm block elements as a simulation data file, perform simulation by sequentially calling algorithm functions according to the simulation task file and the algorithm block dynamic link library file, and write the operation result obtained after each basic algorithm block is called and executed to the corresponding position of the basic algorithm block in the simulation data, so that the test designer can correct the basic algorithm block according to the basic algorithm block elements and operation results of each basic algorithm block, that is, correct the control logic diagram.

[0104] The method for automatically generating logical test cases based on a control logic diagram according to an embodiment of the present application can automatically parse and simulate the control logic diagram using a parsing function after obtaining the control logic diagram, without manual participation, effectively improving the generation efficiency of logical test cases, reducing human errors, and improving the accuracy and reliability of test cases.

[0105] To implement the above embodiments, the present application also proposes a device for automatically generating logical test cases based on a control logic diagram.

[0106] Figure 10 It is a structural schematic diagram of a device for automatically generating logical test cases based on a control logic diagram according to an embodiment of the present application.

[0107] As Figure 10 shown, the device 10 for automatically generating logical test cases based on a control logic diagram includes:

[0108] An acquisition module 11, configured to acquire a control logic diagram composed of basic algorithm blocks and a description file corresponding to the basic algorithm blocks;

[0109] An analysis module 12, configured to analyze the control logic diagram by using an analysis function to generate a simulation task file, where the simulation task file is used to determine the call sequence of each basic algorithm block in the control logic diagram;

[0110] A compilation module 13, configured to compile the description file corresponding to the basic algorithm block into an algorithm function corresponding to the basic algorithm block and an algorithm block dynamic link library file for recording the storage address of the algorithm function;

[0111] A simulation module 14, configured to sequentially call the algorithm functions according to the call sequence of the basic algorithm blocks recorded in the simulation task file and the storage address of the algorithm functions recorded in the algorithm block dynamic link library file, so as to perform a simulation operation on the control logic diagram corresponding to the simulation task file;

[0112] A generation module 15, configured to generate a test output according to the test input and the simulation operation of the control logic diagram, and finally generate a test case.

[0113] Optionally, the control logic diagram includes basic algorithm blocks and connection lines connecting the basic algorithm blocks. The analysis module 12 is further configured to:

[0114] Analyze the basic algorithm block elements corresponding to the basic algorithm blocks by using a first analysis function, where the basic algorithm block elements include the basic algorithm block name, the shape appearance of the basic algorithm block, and the shape data of the basic algorithm block;

[0115] Analyze the coordinate positions of the connection lines by using a second analysis function, and map the coordinate positions to the input point positions or output point positions of the basic algorithm blocks.

[0116] Optionally, the shape appearance of the basic algorithm block includes an input point name and an output point name. The simulation task file includes at least one test input point combination, and the test input point combination includes at least one input point name. The simulation module 14 is further configured to:

[0117] Acquire a test input point combination corresponding to the control logic diagram; or

[0118] Analyze the control logic diagram according to a test coverage criterion to obtain a test input point combination corresponding to the control logic diagram.

[0119] Optionally, the test case file includes a test input point combination and an output point combination corresponding to each test input point combination that has undergone a simulation operation.

[0120] Optionally, the simulation module 14 is further configured to:

[0121] Generate a simulation data file according to at least one basic algorithm block recorded in the control logic diagram. The simulation data file is used to store the basic algorithm block elements corresponding to the basic algorithm blocks;

[0122] Write the operation result corresponding to each basic algorithm block to the corresponding position of the basic algorithm block in the simulation data file.

[0123] Optionally, the basic algorithm block is defined by a Visio stencil, and the control logic diagram can be obtained by connecting the defined Visio stencils through wires. The parsing function is a Visio parsing function.

[0124] The automatic generation device of logic test cases based on the control logic diagram according to the embodiments of the present application can automatically parse and simulate the control logic diagram by using the parsing function after obtaining the control logic diagram, without manual participation, effectively improving the generation efficiency of logic test cases, reducing human errors, and improving the accuracy and reliability of test cases.

[0125] To implement the above embodiments, the present application also proposes a computer device.

[0126] The computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the method according to the embodiments of the first aspect is implemented.

[0127] To implement the above embodiments, the present application also proposes a non-transitory computer-readable storage medium.

[0128] The non-transitory computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, the method according to the embodiments of the first aspect is implemented.

[0129] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0130] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a definitional sequence list of executable instructions for implementing logical functions, and can be embodied specifically in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, a system including a processor, or other systems that can fetch instructions from and execute the instructions of the instruction execution system, apparatus, or device. As used in this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection portion having one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable medium on which a program can be printed, as the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering, or otherwise processing it as appropriate, and then storing it in a computer memory.

[0131] It should be understood that various parts of the present application can be implemented by hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGA), field programmable gate arrays (FPGA), etc.

[0132] It should be noted that in the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

Claims

1. An automatic generation method for logic test cases based on a control logic diagram, characterized in that, It includes the following steps: Obtain a control logic diagram composed of basic algorithm blocks and a description file corresponding to the basic algorithm blocks; Use a parsing function to parse the control logic diagram to generate a simulation task file, and the simulation task file is used to determine the call order of each of the basic algorithm blocks in the control logic diagram; Compile the description file corresponding to the basic algorithm block into an algorithm function corresponding to the basic algorithm block and an algorithm block dynamic link library file for recording the storage address of the algorithm function; According to the call order of the basic algorithm blocks recorded in the simulation task file and the storage address of the algorithm function recorded in the algorithm block dynamic link library file, orderly call the algorithm functions to perform simulation operations on the control logic diagram corresponding to the simulation task file; Perform simulation operations according to the test input and the control logic diagram to generate a test output, and finally generate a test case; The shape appearance corresponding to the basic algorithm block includes an input point name and an output point name, the simulation task file includes at least one test input point combination, and the test input point combination includes at least one input point name. Before orderly calling the algorithm functions according to the call order of the basic algorithm blocks recorded in the simulation task file and the storage address of the algorithm function recorded in the algorithm block dynamic link library file to perform simulation operations on the control logic diagram corresponding to the simulation task file, it further includes: Obtain a test input point combination corresponding to the control logic diagram; Or Parse the control logic diagram according to a test coverage criterion to obtain a test input point combination corresponding to the control logic diagram; The test case includes the test input point combination and an output point combination corresponding to each test input point combination that has undergone simulation operations.

2. The method according to claim 1, wherein The control logic diagram includes the basic algorithm blocks and the connection lines connecting the basic algorithm blocks. Using a parsing function to parse the control logic diagram includes: Use a first parsing function to parse the basic algorithm block elements corresponding to the basic algorithm blocks, and the basic algorithm block elements include a basic algorithm block name, a basic algorithm block shape appearance, and basic algorithm block shape data; Use a second parsing function to parse the coordinate positions of the connection lines and map the coordinate positions to the input point positions or output point positions of the basic algorithm blocks.

3. The method according to claim 1, characterized in that, Before orderly calling the algorithm functions according to the call order of the basic algorithm blocks recorded in the simulation task file and the storage address of the algorithm function recorded in the algorithm block dynamic link library file to perform simulation operations on the control logic diagram corresponding to the simulation task file, it further includes: Generate a simulation data file according to at least one of the basic algorithm blocks recorded in the control logic diagram, and the simulation data file is used to store the basic algorithm block elements corresponding to the basic algorithm blocks; After orderly calling the algorithm functions according to the call order of the basic algorithm blocks recorded in the simulation task file and the storage address of the algorithm function recorded in the algorithm block dynamic link library file to perform simulation operations on the control logic diagram corresponding to the simulation task file, it further includes: Write the operation result corresponding to each of the basic algorithm blocks to the corresponding position of the basic algorithm block in the simulation data file.

4. The method according to any one of claims 1 to 3, characterized in that, The basic algorithm blocks are defined by Visio stencils, the control logic diagram can be obtained by connecting the defined Visio stencils through wires, and the parsing function is a Visio parsing function.

5. An automatic generation device for logic test cases based on a control logic diagram, characterized in that It includes: An acquisition module for acquiring a control logic diagram composed of basic algorithm blocks and a description file corresponding to the basic algorithm blocks; A parsing module for parsing the control logic diagram using a parsing function to generate a simulation task file, where the simulation task file is used to determine the call order of each of the basic algorithm blocks in the control logic diagram; A compilation module for compiling the description file corresponding to the basic algorithm blocks into an algorithm function corresponding to the basic algorithm blocks and an algorithm block dynamic link library file for recording the storage address of the algorithm function; A simulation module for sequentially calling the algorithm functions according to the call order of the basic algorithm blocks recorded in the simulation task file and the storage address of the algorithm function recorded in the algorithm block dynamic link library file to perform a simulation operation on the control logic diagram corresponding to the simulation task file; A generation module for performing a simulation operation according to test inputs and the control logic diagram to generate test outputs and finally generate test cases; The shape appearance corresponding to the basic algorithm block includes an input point name and an output point name, the simulation task file includes at least one test input point combination, the test input point combination includes at least one input point name, and the simulation module is further configured to: Acquire a test input point combination corresponding to the control logic diagram; or Parse the control logic diagram according to a test coverage criterion to obtain a test input point combination corresponding to the control logic diagram; The test case includes the test input point combination and an output point combination corresponding to each of the test input point combinations obtained through simulation operation.

6. The device according to claim 5, characterized in that, The control logic diagram includes the basic algorithm blocks and wires connecting the basic algorithm blocks, and the parsing module is further configured to: Parse the basic algorithm block elements corresponding to the basic algorithm blocks using a first parsing function, where the basic algorithm block elements include a basic algorithm block name, a basic algorithm block shape appearance, and basic algorithm block shape data; Parse the coordinate positions of the wires using a second parsing function and map the coordinate positions to the input point positions or output point positions of the basic algorithm blocks.

7. A computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, when the processor executes the computer program, implementing the method according to any one of claims 1-4.

8. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the method according to any one of claims 1-4.

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