System on chip and method for voltage and frequency regulation

Abstract

Provided are a system on chip and a method for adjusting voltage and frequency. The system on chip includes: a processing unit for generating configuration instructions and frequency modulation instructions; a sensor component for acquiring detection data; an AVFS controller coupled to the sensor component, configured to configure at least one frequency according to the configuration instruction, and when the target frequency of the frequency modulation instruction matches the first frequency of at least one frequency, determine the clock frequency of the system on chip based on the first frequency adjustment, and determine and adjust the power supply voltage of the system on chip based on the detection data; an on-chip bus coupling the processing unit and the AVFS controller. Based on the embodiment of the present disclosure, the AVFS controller configures at least one frequency to limit the allowable value range of the system's clock frequency. If the adjustment of the clock frequency by the frequency modulation instruction is within the allowable value range, the frequency and voltage modulation operation can be performed normally, and if it is outside the allowable value range, it is rejected, thereby improving the safety of the frequency and voltage modulation operation.

Description

Technical Field

[0001] The present disclosure relates to the field of chips, and in particular to a system on chip and a method for adjusting voltage and frequency. Background Art

[0002] The trend of miniaturization of integrated circuits has made processor manufacturers enthusiastic about how to reduce power consumption. Adaptive Voltage Frequency Scaling (AVFS) is one of the ways to reduce power consumption of processors. Adaptive Voltage Frequency Scaling determines the supply voltage by measuring the detection data in real time through sensors.

[0003] In the AVFS system, the application can initiate frequency modulation instructions through the system interface, and the AVFS controller modifies the processor's clock frequency and power supply voltage according to the frequency modulation instructions. Malicious attack software takes advantage of this and brings security issues to the system. For example, malicious attack software can initiate a frequency modulation and voltage modulation request containing a large frequency. If the clock frequency is set to this frequency, it may cause the system to crash. Summary of the invention

[0004] In view of this, an object of the present disclosure is to provide a system on chip and a method for adjusting voltage and frequency, so as to improve the safety of frequency and voltage regulation operations of the system on chip.

[0005] In a first aspect, an embodiment of the present disclosure provides a system on chip, including:

[0006] A processing unit, used for generating configuration instructions and frequency modulation instructions;

[0007] A sensor component for acquiring detection data;

[0008] an AVFS controller, coupled to the sensor component, configured to configure at least one frequency according to the configuration instruction, and when a target frequency of the frequency modulation instruction matches a first frequency among the at least one frequency, determine a clock frequency of the system on chip based on the first frequency, and determine a supply voltage of the system on chip based on the detection data;

[0009] An on-chip bus couples the processing unit and the AVFS controller.

[0010] Optionally, the AVFS controller generates an alarm signal when the target frequency does not match any frequency of the at least one frequency.

[0011] Optionally, the AVFS controller further configures a plurality of voltage table entries corresponding to the at least one frequency according to the configuration instruction, and the AVFS controller further comprises a voltage determination unit for determining a first voltage from the plurality of voltage table entries as a power supply voltage of the system on chip based on the detection data.

[0012] Optionally, the AVFS controller further includes a voltage determination unit, configured to calculate a power supply voltage of the system on chip according to the first frequency and the detection data based on a predefined voltage calculation rule.

[0013] Optionally, the processing unit includes a secure environment and a non-secure environment divided in hardware, and the processing unit generates the configuration instruction in the secure environment and generates the frequency modulation instruction in the non-secure environment.

[0014] Optionally, the processing unit switches between a user state and a kernel state, and generates the configuration instruction in the kernel state, and generates the frequency modulation instruction in the user state.

[0015] Optionally, the configuration instruction includes an indication bit, and the indication bit is used to indicate whether the processing unit generates the configuration instruction in a secure environment, and the AVFS controller configures the at least one frequency only when it is determined based on the indication bit that the configuration instruction is generated in a secure environment.

[0016] Optionally, the sensor component includes at least one of a temperature sensor component, a process sensor component and a voltage sensor component.

[0017] In a second aspect, an embodiment of the present disclosure provides a method for adjusting voltage and frequency, including:

[0018] Generate configuration instructions and frequency modulation instructions;

[0019] configuring at least one frequency according to the configuration instruction;

[0020] Acquire detection data through sensor components;

[0021] comparing the target frequency in the frequency modulation instruction with the at least one frequency;

[0022] In a case where the target frequency matches a first frequency among the at least one frequency, a clock frequency of the system on chip is determined according to the first frequency, and a power supply voltage of the system on chip is determined based on the detection data.

[0023] Optionally, the method further includes: generating an alarm signal and performing alarm processing when the target frequency does not match any frequency of the at least one frequency.

[0024] Optionally, the method also includes: configuring multiple voltage table items corresponding to the at least one frequency according to the configuration instruction, and determining the power supply voltage of the system on chip based on the detection data includes: determining a first voltage from the multiple voltage table items as the power supply voltage of the system on chip based on the detection data.

[0025] Optionally, determining the supply voltage of the system on chip based on the detection data includes: calculating the supply voltage of the system on chip according to the first frequency and the detection data based on a predefined voltage calculation rule.

[0026] Optionally, the configuration instruction is generated in a secure environment of the processing unit, and the frequency modulation instruction is generated in a non-secure environment.

[0027] Optionally, the configuration instruction includes an indication bit, and the indication bit is used to indicate whether the processing unit generates the configuration instruction in a secure environment. The method further includes: configuring at least one frequency only when it is determined based on the indication bit that the configuration instruction is generated in a secure environment.

[0028] In a third aspect, an embodiment of the present disclosure provides a computing device, including:

[0029] The system on chip as described in any one of the above items;

[0030] bus;

[0031] a storage device coupled to the system on chip via the bus;

[0032] A power management circuit is coupled to the AVFS controller in the system on chip.

[0033] According to an embodiment of the present disclosure, the AVFS controller configures at least one frequency to limit the allowable range of values ​​of the system's clock frequency. If the frequency modulation instruction adjusts the clock frequency within the allowable range, the frequency and voltage modulation operations can proceed normally. If it is outside the allowable range, it will be refused to execute, thereby improving the safety of the frequency and voltage modulation operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other objects, features and advantages of the present disclosure will become more apparent through the description of the embodiments of the present disclosure with reference to the following drawings, in which:

[0035] Figure 1 is a schematic diagram of the structure of a system on a chip provided by an embodiment of the present disclosure;

[0036] Figure 2 is a schematic diagram of an exemplary structure of an AVFS controller;

[0037] Figure 3is another exemplary structural diagram of an AVFS controller;

[0038] Figure 4 is a flow chart of a method for adjusting voltage and frequency provided by an embodiment of the present disclosure;

[0039] Figure 5 is a schematic diagram of the structure of a general computer system used in the embodiments of the present disclosure;

[0040] Figure 6 It is a schematic diagram of the structure of the embedded system used in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] The present disclosure is described below based on embodiments, but the present disclosure is not limited to these embodiments. In the detailed description of the present disclosure below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present disclosure without the description of these details. In order to avoid confusing the essence of the present disclosure, well-known methods, processes, and procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0042] The system on chip of the present disclosure

[0043] Figure 1 Schematic diagram of the structure of the system on chip 100 used in the embodiment of the present disclosure.

[0044] As shown in the reference figure, the on-chip bus 102 couples various components to the processing unit 101. The on-chip bus 102 is, for example, an AXI bus. The AXI bus is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 and above protocols proposed by ARM. It is an on-chip bus oriented to high performance, high bandwidth, and low latency. The AIX bus separates the address / control and data phases, supports unaligned data transmission, and supports burst transmission and out-of-order transmission, thereby meeting the requirements of ultra-high performance and complex on-chip system design.

[0045] As shown in the figure, the AVFS controller 103 and the high-speed memory 104 are coupled to the processing unit 101 via the on-chip bus 102. The AVFS controller 103 is coupled to the clock management unit 105, the sensor 106, and the power management circuit 211 located outside the chip.

[0046] In some embodiments, the power management circuit 211 may also be located inside the system on chip 100. One or more sensors 106 are used to obtain detection data of the system on chip in real time. The system on chip 100 may also include an interface circuit not shown, which is coupled to an external device outside the chip through the interface circuit. The external device may be, for example, an input / output device for text, audio and video and various other memories. The system on chip 100 may access the external device outside the chip through the interface circuit. Unlike the high-speed memory 104 provided in the system on chip, the memory outside the chip may have a larger capacity but a slower speed and a lower cost. In some implementations, the high-speed memory 104 may be a static random access memory (SRAM), while the memory outside the chip is a DRAM (dynamic random access memory) and a flash memory. Designers may also configure the system on chip so that the communication between the various components in the system on chip is secure.

[0047] As shown in the figure, basic software (such as embedded control system 121) and application programs (such as application program AN) are embedded in system on chip 100. Other application programs not shown can be stored in a memory outside system on chip 100, and these application programs can be copied to high-speed memory 104 in system on chip 100 through interface circuits for execution, or access resources on system on chip 100 through interface circuits.

[0048] When the AVFS controller 103 is working, it receives a configuration instruction and a frequency modulation instruction from the on-chip bus 102. The configuration instruction includes at least one frequency. The frequency modulation instruction includes a target frequency, that is, the on-chip system 100 is to be adjusted from the current frequency to the target frequency. The AVFS controller 103 reads at least one frequency from the configuration instruction and stores it in the AVFS controller 103. At the same time, the AVFS controller 103 obtains the target frequency from the frequency modulation instruction, and compares the target frequency with each frequency in the configuration table 1031. When a certain frequency matches the target frequency, it indicates that the target frequency is a legal frequency. Then, the target frequency and the detection data of the system on chip 100 are used to determine the power supply voltage provided to the system on chip 100, and a voltage adjustment signal REGV is generated according to the power supply voltage, and sent to the power management circuit 211. The power management circuit 211 thus provides the power supply voltage VCPU to the system on chip 100. At the same time, the AVFS controller 103 generates a frequency modulation signal REGF and sends it to the clock management unit 105, and the clock management unit 105 adjusts the clock frequency FCPU of the system on chip 100. The AVFS controller 103 also refuses frequency adjustment when the target frequency does not match any frequency in the at least one frequency, and generates an alarm signal ALARM.

[0049] The processing unit 101 generates configuration instructions and frequency modulation instructions. For example, the configuration instructions may be generated when the boot program is executed. The boot program is used to load the embedded control system 121 after the machine is powered on. That is, during the period from when the machine is powered on to when the embedded control system 121 is working normally, the configuration instructions are generated when the boot program is executed. The advantage of this is that since various interface circuits may not work normally when the boot program is running, it is not easy for external attack software to attack the configuration instructions. For another example, the processing unit 101 generates frequency modulation instructions when executing executable code from the embedded control system 121. Specifically, the embedded control system 121 executes the following computer code every time period T (for example, 20ms): first, collect signals related to the system load and calculate the current system load; then, based on the current load of the system, predict the performance required by the system in the next time period; then convert the predicted performance into the required frequency, and then call the system interface to modify the system clock frequency to the required frequency. The system interface is an interface provided by the embedded control system for calling the underlying hardware unit. When the processing unit 101 decodes and executes the above computer code, it generates a frequency modulation instruction sent to the hardware AVFS controller by calling the system interface.

[0050] It should be noted that the at least one frequency specified by the configuration instruction is a verified frequency that enables the system on chip 100 to operate normally.

[0051] In summary, the system on chip provided by the embodiment of the present disclosure is configured with at least one frequency to limit the allowable value range of the system's clock frequency. If the modification of the clock frequency by the frequency modulation instruction is within the allowable value range, the frequency and voltage modulation operations can be carried out normally. If it is outside the allowable value range, an alarm is performed to improve the safety of the frequency and voltage modulation operations.

[0052] In one implementation, the system on chip 100 includes a static storage unit, which contains a plurality of frequencies that enable the system on chip 100 to operate normally, and at least one frequency specified in the configuration instruction is included in the plurality of frequencies.

[0053] In a further implementation, the execution environment of the computer instructions of the processing unit 101 can be divided into a secure environment 1011 and a non-secure environment 1012 based on hardware. The secure environment 1011 is a more trusted instruction execution environment than the non-secure environment 1012. For example, the secure environment 1011 cannot be accessed from the outside, and the non-secure environment 1012 is accessible from the outside. The secure environment includes a hardware protection mechanism at the input and output interfaces, and the hardware protection mechanism is, for example, a register for filtering authenticated or unauthenticated data, and communication with the secure environment can be based on an encryption algorithm, etc. Optionally, the processing unit 101 generates a configuration instruction in the secure environment 1011 and generates a frequency modulation instruction in the non-secure environment 1012.

[0054] In a further implementation, the execution environment of the processing unit 101 for computer instructions can be divided into user state and kernel state based on software. User state and kernel state come from the multi-user management mode. The multi-user management mode includes at least two types of users: ordinary privilege users and highest privilege users. Based on the multi-user management mode, the addressing space of the memory is divided into kernel space and user space in software logic. For example, for the Linux operating system, the highest 1G bytes (from virtual address 0xC0000000 to 0xFFFFFFFF) are used as kernel space, and the lower 3G bytes (from virtual address 0x00000000 to 0xBFFFFFFF) are used as user space. If an application is executed by an ordinary user, the code and data of the application will be loaded into the user space for execution. If an application is executed by the highest privilege user, the code and data of the application will be loaded into the kernel space for execution. Thus, when the processor processes the code in the kernel space, its working mode is called kernel state, and when the processor processes the code in the user space, its working mode is called user state. Optionally, the processing unit 101 generates a configuration instruction in kernel mode and generates a frequency modulation instruction in user mode.

[0055] Under normal circumstances, the processing unit 101 only generates configuration instructions in a secure environment or kernel mode, and only generates frequency modulation instructions in a non-secure environment or user mode, thereby improving the security of frequency and voltage modulation operations. However, an attack program can still destroy the generation process of configuration instructions, for example, through illegal computer instructions, the processing unit 101 generates frequency instructions in a non-secure environment and tampering with the frequency in the configuration instructions.

[0056] To this end, in a further implementation, the configuration instruction includes an indicator bit, which is used to indicate the state information of the processing unit 101 when the configuration instruction is generated. For example, when it is 0, it indicates that the processing unit 101 is in a secure environment, when it is 1, it indicates that the processing unit 101 is in a non-secure environment, or when it is 0, it indicates that the processing unit 101 is in a kernel state, and when it is 1, it indicates that the processing unit 101 is in a user state. Thus, the AVFS controller 103 can determine whether the processing unit 101 generates the configuration instruction in the correct state (i.e., the secure environment or the kernel state) by detecting the indicator bit. If the AVFS controller 103 determines that the processing unit 101 generates the configuration instruction in the correct state according to the indicator bit, the frequency configuration is performed. If the AVFS controller 103 determines that the processing unit 101 generates the configuration instruction in the wrong state according to the indicator bit, the frequency configuration is refused to be executed and an alarm signal is given, and then the alarm processing unit performs an alarm processing according to the alarm signal. In this way, even if the attack program can destroy the generation process of the configuration instruction, the AVFS controller 103 cannot complete the frequency configuration.

[0057] In summary, generating configuration instructions in a secure environment makes it difficult for attack software to easily destroy the generation process of configuration instructions, so that the frequency in the configuration instructions will not be tampered with in most cases. Therefore, the security of frequency configuration is guaranteed, and the security of frequency and voltage regulation operations is also guaranteed.

[0058] Furthermore, even if the attack software can make the processing unit generate configuration instructions in a non-secure environment, since the configuration instructions include an indication bit, if the AVFS controller determines that the configuration instruction is generated in a non-secure environment based on the indication bit, the AVFS controller will not perform frequency configuration. Therefore, the attack software cannot configure illegal frequencies into the AVFS controller. Therefore, the security of the frequency configuration is guaranteed, and thus the security of the frequency and voltage regulation operations is also guaranteed.

[0059] Figure 2 is a schematic diagram of an exemplary structure of an AVFS controller.

[0060] As shown in the figure, the AVFS controller 103 includes a register group for storing a configuration table 1031 , a voltage determination unit 202 , a frequency conversion control unit 206 , and a plurality of different sensor components for measuring detection data.

[0061] The configuration table 1031 includes a plurality of frequencies, which are generated by the AVFS controller 103 according to the configuration instruction. For example, the AVFS controller 103 reads the plurality of frequencies from the one-time programmable storage unit according to the configuration instruction and stores them in the AVFS controller 103. The voltage determination unit 202 or the frequency conversion control unit 206 determines whether the target frequency is included in the configuration table 1031. If yes, it indicates that the target frequency is legal. If not, it indicates that the target frequency is illegal.

[0062] When the target frequency is legal, the voltage determination unit 202 calculates the power supply voltage of the system on chip 100 based on the detection data measured in real time by the sensor component and the target frequency, and generates a voltage regulation signal REGV based on the power supply voltage. When the target frequency is legal, the frequency conversion control unit 206 generates a frequency modulation signal REGF according to the target frequency. When the target frequency is illegal, the frequency conversion control unit 206 does not generate a frequency modulation signal, and the voltage determination unit 202 does not generate a voltage regulation signal. Optionally, the AVFS controller 103 may also include an alarm unit (not shown) for performing alarm processing when the target frequency is illegal or other abnormalities occur.

[0063] As shown in the figure, the multiple different sensor components include a temperature sensor component, a process sensor component and a voltage sensor component. The temperature sensor component includes a temperature sensor controller 203 and a temperature sensor 206. The process sensor component includes a process sensor controller 204 and a process sensor 207. The voltage sensor component includes a voltage sensor controller 205 and a voltage sensor 208. The temperature sensor 206, the process sensor 207 and the voltage sensor 208 respectively collect analog signals of the real-time temperature, process deviation and real-time voltage of the system on chip 100, and convert the analog signals into digital signals. The temperature sensor controller 203, the process sensor controller 204 and the voltage sensor controller 205 respectively control the temperature sensor 206, the process sensor 207 and the voltage sensor 208, for example, to control the start and stop of the sensor to collect detection data. Among them, the process sensor component is used to calculate the process deviation, which will have an impact when determining the power supply voltage.

[0064] The voltage determination unit 202 calculates the supply voltage based on the target frequency and the real-time temperature of the system 100 and the process deviation according to the predefined voltage calculation rules, or first calculates the supply voltage based on the target frequency and the real-time temperature of the system 100 according to the predefined voltage calculation rules, and then biases the supply voltage according to the process deviation. The voltage determination unit 202 can also receive the real-time voltage obtained by the voltage sensor 208, and compare the real-time voltage with the supply voltage to determine whether the previous voltage adjustment operation is successful. If it is unsuccessful, for example, the voltage value difference between the real-time voltage and the supply voltage is too large, the voltage calculation rules can be adjusted accordingly in the subsequent voltage calculation.

[0065] Figure 3 1 is another exemplary structural diagram of the AVFS controller. As shown in the figure, the AVFS controller 103 includes a register group for storing a configuration table 1032, a voltage determination unit 212, a frequency conversion control unit 206, and a plurality of different sensor components for measuring detection data.

[0066] in, Figure 3 The AVFS controller shown is Figure 2 The AVFS controller shown has the following differences. First, the configuration table 1032 stores multiple frequencies 1-n and voltage table items 1-k corresponding to each frequency in the multiple frequencies 1-n, and k is a positive integer greater than or equal to 1, wherein the data of the configuration table 1032 is generated by the AVFS controller 103 according to the configuration instruction, and the data can be burned in a one-time programmable storage medium in advance, and the data is transferred to the AVFS controller 103 when the system is powered on. Secondly, the voltage determination unit 202 determines the supply voltage by a table lookup method. Specifically, the voltage determination unit 202 selects a voltage table item from multiple voltage table items corresponding to the target frequency as the supply voltage of the system on chip based on the detection data collected by multiple sensor components.

[0067] certainly Figure 2 and 3 The structure of the AVFS controller is only exemplary, and those skilled in the art may also conceive of other structures of the AVFS controller, all of which are within the protection scope of the embodiments of the present disclosure.

[0068] Method for adjusting voltage and frequency according to the embodiment of the present disclosure

[0069] Figure 4 The flowchart of the method for adjusting voltage and frequency according to the embodiment of the present disclosure is shown. The method can be implemented by a software program, or by a software program and a hardware module. As shown in the figure, the method includes the following steps.

[0070] In step S400 , a configuration instruction is generated in a secure environment. This step is completed by the processing unit 101 .

[0071] In step S401, at least one frequency is configured according to the configuration instruction. This step can be completed by the AVFS controller. The AVFS controller receives the configuration instruction, reads at least one frequency therefrom, and stores the at least one frequency in a specific register group. The specific register group is dedicated to storing the at least one frequency. If the AVFS controller has processed the configuration instruction before, the specific register group will store the previously configured frequency, and after this step, it is equivalent to using the latest frequency to update the previously configured frequency.

[0072] In step S402, a frequency modulation instruction is generated in a non-secure environment. This step is performed by a processing unit, which generates a frequency modulation instruction when executing a computer instruction. The computer instruction usually comes from an application or an embedded control system.

[0073] In step S403, the target frequency in the frequency modulation instruction is compared with at least one frequency. This step can be performed by the AVFS controller. The target frequency is compared with at least one frequency obtained in step S401 by a comparator.

[0074] In step S404, it is determined whether the target frequency matches the first frequency. The first frequency is any one of the at least one frequency. If the target frequency matches the first frequency, step S405 is executed, otherwise step S406 is executed.

[0075] In step S405, a clock frequency is determined according to the first frequency.

[0076] In step S406, detection data is obtained from the sensor component, and the supply voltage is determined according to the detection data and the target frequency. This step is performed by the AVFS controller, and the supply voltage can be determined in a variety of ways, such as the AVFS controller substituting the detection data and the target frequency into a predefined voltage calculation rule to determine the supply voltage provided to the system on chip, and for another example, the AVFS controller also configures multiple voltage table items corresponding to at least one frequency according to the configuration instruction, and then selects a voltage table item from the multiple voltage table items based on the detection data to determine the supply voltage provided to the system on chip.

[0077] In step S406, an alarm signal is generated and an alarm process is performed. This step is also performed by the AVFS controller, and is used to generate an alarm signal and perform an alarm process when the target frequency does not match any frequency stored in the AVFS controller.

[0078] Furthermore, the alarm signal generated in step S406 may be an interrupt signal, a reset signal or a bus error signal. Different alarm signals are processed differently. For example, an interrupt processing routine in an embedded control system may be used to process interrupt signals and reset signals.

[0079] As an implementation method, configuration instructions and frequency modulation instructions are generated in different modes of the processor (including central processing unit, microprocessor, digital signal processing unit), for example, the operation of generating configuration instructions in kernel mode and the operation of generating frequency modulation instructions in user mode.

[0080] As an implementation, the configuration instruction includes an indication bit, which is used to indicate whether the processing unit generates the configuration instruction in a secure environment, and the AVFS controller performs the configuration operation only when it is determined based on the indication bit that the configuration instruction is generated in a secure environment.

[0081] Specific Applications of System-on-Chip

[0082] Figure 5The general computer architecture used in the embodiments of the present disclosure is shown. As shown in the figure, the computer system 500 may include one or more processors 12 and a memory 14. The system on chip provided in the above embodiments may be used as the processor 12.

[0083] The memory 14 in the computer system 500 may be a main memory (hereinafter referred to as main memory or internal memory), which is used to store instruction information and / or data information represented by data signals, such as storing data (such as calculation results) provided by the processor 12, and may also be used to implement data exchange between the processor 12 and an external storage device 16 (also referred to as auxiliary memory or external memory).

[0084] In some cases, the processor 12 may need to access the memory 14 to obtain data in the memory 14 or modify the data in the memory 14. Since the access speed of the memory 14 is slow, in order to alleviate the speed gap between the processor 12 and the memory 14, the computer system 300 also includes a cache memory 18 coupled to the bus 11, and the cache memory 18 is used to cache some program data or message data in the memory 14 that may be repeatedly called. The cache memory 18 is implemented by a storage device of the type of static random access memory (SRAM) for example. The cache memory 18 can be a multi-level structure, such as a three-level cache structure with a first-level cache (L1Cache), a second-level cache (L2Cache) and a third-level cache (L3Cache), or a cache structure of more than three levels or other types of cache structures. In some embodiments, a portion of the cache memory 18 (such as a first-level cache, or a first-level cache and a second-level cache) can be integrated inside the processor 12 or integrated with the processor 12 in the same system on a chip.

[0085] Based on this, the processor 12 may include an instruction execution unit 121, a memory management unit 122, and other parts. The instruction execution unit 121 initiates a write access request when executing some instructions that need to modify the memory. The write access request specifies the write data and the corresponding physical address that need to be written into the memory; the memory management unit 122 is used to translate the virtual addresses specified by these instructions into the physical addresses mapped by the virtual addresses. The physical address specified by the write access request may be consistent with the physical address specified by the corresponding instruction.

[0086] The information exchange between the memory 14 and the cache memory 18 is usually organized in blocks. In some embodiments, the cache memory 18 and the memory 14 can be divided into data blocks according to the same spatial size, and the data block can be used as the minimum unit of data exchange between the cache memory 18 and the memory 14 (including one or more data of a preset length). For the sake of simplicity and clarity, the data blocks in the cache memory 18 are referred to as cache blocks (which can be called cache lines or cache lines), and different cache blocks have different cache block addresses; the data blocks in the memory 14 are referred to as memory blocks, and different memory blocks have different memory block addresses. The cache block address includes, for example, a physical address tag for locating the data block.

[0087] Due to space and resource limitations, the cache memory 18 cannot cache all the contents in the memory 14, that is, the storage capacity of the cache memory 18 is usually smaller than that of the memory 14, and the cache block addresses provided by the cache memory 18 cannot correspond to all the memory block addresses provided by the memory 14. When the processor 12 needs to access the memory, it first accesses the cache memory 18 via the bus 11 to determine whether the content to be accessed has been stored in the cache memory 18. If so, the cache memory 18 hits, and the processor 12 directly calls the content to be accessed from the cache memory 18; if the content that the processor 12 needs to access is not in the cache memory 18, the cache memory 18, the processor 12 needs to access the memory 14 via the bus 11 to find the corresponding information in the memory 14. Because the access rate of the cache memory 18 is very fast, when the cache memory 18 hits, the efficiency of the processor 12 can be significantly improved, thereby improving the performance and efficiency of the entire computer system 300.

[0088] In addition, the computer system 300 may also include input / output devices such as a storage device 16, a display device 13, an audio device 19, and a mouse / keyboard 15. The storage device 16 is, for example, a hard disk, an optical disk, a flash memory, and other devices for information access coupled to the bus 11 through a corresponding interface. The display device 13 is, for example, coupled to the bus 11 through a corresponding graphics card, and is used to display according to a display signal provided by the bus 11.

[0089] The computer system 500 also typically includes a communication device 17, so that it can communicate with a network or other devices in various ways. The communication device 17 may include, for example, one or more communication modules. As an example, the communication device 17 may include a wireless communication module suitable for a specific wireless communication protocol. For example, the communication device 17 may include a WLAN module for implementing Wi-FiTM communication that complies with the 802.11 standard established by the Institute of Electrical and Electronics Engineers (IEEE); the communication device 17 may also include a WWAN module for implementing wireless wide area communication that complies with cellular or other wireless wide area protocols; the communication device 17 may also include a communication module that uses other protocols, such as a Bluetooth module, or other custom types of communication modules; the communication device 17 may also be a port for serial transmission of data.

[0090] Of course, the structure of different computer systems may vary according to the motherboard, operating system and instruction set architecture. For example, many computer systems are currently provided with an input / output control center connected between the bus 11 and various input / output devices, and the input / output control center can be integrated into the processor 12 or independent of the processor 12.

[0091] Figure 6 601 is a structural diagram of an embedded system used in the embodiment of the present disclosure. The system on chip provided in the above embodiment can be used as the processor 601.

[0092] Although embedded systems are highly similar to computer systems in hardware structure, the characteristics of embedded system applications make them quite different from general computer systems in hardware composition and implementation.

[0093] First, in order to meet the requirements of the embedded system 600 in terms of speed, volume and power consumption, the operating system, application software, special data and other data that need to be stored for a long time usually do not use storage media such as disks with large capacity and slow speed, but mostly use random access memory 602 or flash memory (Flash Memory) 603.

[0094] In addition, in the embedded system 600, an A / D (analog / digital conversion) interface 605 and a serial interface 606 are required for the needs of measurement and control, which are rarely used in general-purpose computers. The A / D interface 605 mainly completes the conversion of analog signals to digital signals and the conversion of digital signals to analog signals required in the test. When the embedded system 600 is applied to industrial production, it often needs to be tested. Since the single-chip microcomputer generates digital signals, it needs to be converted into analog signals for testing during testing. Therefore, unlike general-purpose computers, an A / D (analog / digital conversion) interface 605 is required to complete the relevant conversion. In addition, in industry, multiple embedded systems are often required to be connected in series to complete relevant functions, so a serial interface 606 is required for connecting multiple embedded systems in series, which is mostly not required in general-purpose computers.

[0095] In addition, as a basic processing unit, the embedded system 600 often needs to connect multiple embedded systems 600 into a network in industrial design, so a network interface 607 is needed to connect the embedded system 600 to the network. This is also not needed in general-purpose computers. In addition, according to the actual application and scale, some embedded systems 600 need to use external buses 604. With the rapid expansion of the application field of embedded systems 600, embedded systems 600 are becoming more and more personalized, and the types of buses used according to their own characteristics are also increasing. In addition, in order to test the internal circuits of the embedded processor 601, the processor chip generally adopts boundary scan test technology. In order to adapt to this test, a debug interface 608 is adopted.

[0096] With the rapid development of very large scale integration (VLSI) and semiconductor technology, part or all of the above embedded systems can be implemented on a silicon chip, namely, an embedded system on chip (SoC).

[0097] The commercial value of the disclosed embodiments

[0098] The system-on-chip provided by the embodiment of the present disclosure reduces the system power consumption on the basis of ensuring the safety of frequency and voltage regulation operations, and can form a computing device used in a variety of scenarios, such as a large number of cloud servers in a data center. In this scenario, by reducing the power consumption of the processor, the power consumption of each cloud server is reduced, thereby reducing the operating costs of each cloud server and the entire data center; for example, electronic devices used in daily life, including terminal devices such as notebooks and mobile phones, and certain consumer electronic products, can improve the system life of electronic devices by reducing power consumption, thereby improving user experience. It can be seen that the system-on-chip of the embodiment of the present disclosure and the computing device constructed by the system-on-chip have commercial value and economic value on the basis of practical value.

[0099] Those skilled in the art will appreciate that the present disclosure may be implemented as systems, methods, and computer program products. Therefore, the present disclosure may be specifically implemented in the following forms, namely complete hardware, complete software (including firmware, resident software, microcode), and may also be implemented in the form of a combination of software and hardware. In addition, in some embodiments, the present disclosure may also be implemented in the form of a computer program product in one or more computer-readable media, which contains computer-readable program code.

[0100] Any combination of one or more computer-readable media may be used. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example but not limited to, an electrical, magnetic, optical, electromagnetic, infrared or semiconductor system, device or device, or any combination thereof. More specific examples of computer-readable storage media include: an electrical connection of one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this article, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by a processing unit, a device or a device, or used in combination with the program.

[0101] Computer readable signal media may include data signals propagated in baseband or as part of a chopped wave, which carry computer readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any other suitable combination. Computer readable signal media may also be any computer readable medium other than a computer readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction system, apparatus, or device.

[0102] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., and any suitable combination of the foregoing.

[0103] The computer program code for executing the disclosed embodiments may be written in one or more programming languages ​​or combinations. The programming languages ​​include object-oriented programming languages, such as JAVA, C++, and may also include conventional procedural programming languages, such as C. The program code may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet).

[0104] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A system on chip, comprising: A processing unit, used for generating configuration instructions and frequency modulation instructions; A sensor component for acquiring detection data; an AVFS controller, coupled to the sensor component, configured to configure at least one frequency according to the configuration instruction, and when a target frequency of the frequency modulation instruction matches a first frequency among the at least one frequency, determine a clock frequency of the system on chip based on the first frequency, and determine a supply voltage of the system on chip based on the detection data; an on-chip bus coupling the processing unit and the AVFS controller; The configuration instruction includes an indication bit, and the indication bit is used to indicate whether the processing unit generates the configuration instruction in a secure environment. When it is determined based on the indication bit that the configuration instruction is generated in a secure environment, the AVFS controller configures the at least one frequency; when it is determined based on the indication bit that the configuration instruction is generated in a non-secure environment, the AVFS controller refuses to execute the frequency configuration.

2. The system on chip according to claim 1, wherein: The AVFS controller generates an alarm signal when the target frequency does not match any frequency of the at least one frequency.

3. The system on chip according to claim 1, wherein: The AVFS controller also configures multiple voltage table items corresponding to the at least one frequency according to the configuration instruction, and the AVFS controller also includes a voltage determination unit for determining a first voltage from the multiple voltage table items as a power supply voltage of the system on chip based on the detection data.

4. The system on chip according to claim 1, wherein: The AVFS controller further includes a voltage determination unit configured to calculate a supply voltage of the system on chip according to the first frequency and the detection data based on a predefined voltage calculation rule.

5. The system on chip according to claim 1, wherein: The processing unit includes a secure environment and a non-secure environment divided in hardware. The processing unit generates the configuration instruction in the secure environment and generates the frequency modulation instruction in the non-secure environment.

6. The system on chip according to claim 1, wherein: The processing unit switches between the user state and the kernel state, and generates the configuration instruction in the kernel state and generates the frequency modulation instruction in the user state.

7. The system on chip according to claim 1, wherein: The sensor assembly includes at least one of a temperature sensor assembly, a process sensor assembly and a voltage sensor assembly.

8. A method for voltage and frequency regulation, comprising: Generate configuration instructions and frequency modulation instructions; configuring at least one frequency according to the configuration instruction; Acquire detection data through sensor components; comparing the target frequency in the frequency modulation instruction with the at least one frequency; In a case where the target frequency matches a first frequency among the at least one frequency, determining a clock frequency of the system on chip according to the first frequency, and determining a power supply voltage of the system on chip based on the detection data; The configuration instruction includes an indication bit, and the indication bit is used to indicate whether the processing unit generates the configuration instruction in a secure environment. The method also includes: configuring at least one frequency when it is determined based on the indication bit that the configuration instruction is generated in a secure environment, and refusing to execute frequency configuration when it is determined based on the indication bit that the configuration instruction is generated in a non-secure environment.

9. The method according to claim 8, further comprising: In the case that the target frequency does not match any frequency of the at least one frequency, an alarm signal is generated and an alarm process is performed.

10. The method according to claim 8, further comprising: Configuring multiple voltage table items corresponding to the at least one frequency according to the configuration instruction, and determining the supply voltage of the system on chip based on the detection data includes: determining a first voltage from the multiple voltage table items as the supply voltage of the system on chip based on the detection data.

11. The method according to claim 8, wherein: Determining the supply voltage of the system on chip based on the detection data includes: calculating the supply voltage of the system on chip according to the first frequency and the detection data based on a predefined voltage calculation rule.

12. The method according to claim 8, wherein: The configuration instruction is generated in a secure environment of the processing unit, and the frequency modulation instruction is generated in a non-secure environment.

13. A computing device comprising: The system on chip according to any one of claims 1 to 7; bus; a storage device coupled to the system on chip via the bus; A power management circuit is coupled to the AVFS controller in the system on chip.

Images