Apparatus and method for controlling a display panel

Abstract

The present application relates to an apparatus and method for controlling a display panel. A display driver includes a control circuit and a signal supply circuit. The control circuit is configured to store a first setting table for a first frame rate and a second setting table for a second frame rate. The control circuit is further configured to generate an interpolated control parameter by interpolation of a first control parameter obtained from the first setting table and a second control parameter obtained from the second setting table in response to adjusting a frame rate of the display device from the first frame rate to the second frame rate. The signal supply circuit is configured to generate at least one first signal to be supplied to the display panel based on the interpolated control parameter.

Description

TECHNICAL FIELD

[0001] The disclosed technology relates generally to an apparatus and a method for controlling a display panel. BACKGROUND

[0002] A display apparatus can be configured such that a frame rate (also referred to as a frame frequency) is adjustable. An increased frame rate improves image quality, while a decreased frame rate reduces power consumption. In view of this, the frame rate can be controlled depending on content (e.g., a video, a still image, etc.) of a display image. For example, the frame rate can be set to 60 Hz in normal operation, and increased up to 90 Hz or higher during a game. SUMMARY

[0003] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0004] In one or more embodiments, a display driver is provided. The display driver includes a control circuit and a signal supply circuit. The control circuit is configured to store a first setting table for a first frame rate and a second setting table for a second frame rate. The control circuit is further configured to generate an interpolated control parameter by interpolation of a first control parameter obtained from the first setting table and a second control parameter obtained from the second setting table in response to adjusting a frame rate of the display apparatus from the first frame rate to the second frame rate. The signal supply circuit is configured to generate at least one first signal to be supplied to a display panel based on the interpolated control parameter.

[0005] In one or more embodiments, a display apparatus is provided. The display apparatus includes a display panel and a display driver. The display driver includes a control circuit and a signal supply circuit. The control circuit is configured to store a first setting table for a first frame rate and a second setting table for a second frame rate. The control circuit is further configured to generate an interpolated control parameter by interpolation of a first control parameter obtained from the first setting table and a second control parameter obtained from the second setting table in response to adjusting a frame rate of the display apparatus from the first frame rate to the second frame rate. The signal supply circuit is configured to generate at least one first signal to be supplied to the display panel based on the interpolated control parameter.

[0006] In one or more embodiments, a method for controlling a display panel is provided. The method includes storing a first setting table for a first frame rate and a second setting table for a second frame rate. The method also includes determining an interpolated control parameter by interpolation of a first control parameter obtained from the first setting table and a second control parameter obtained from the second setting table in response to adjusting a frame rate of a display device from the first frame rate to the second frame rate. The method further includes generating at least one first signal to be supplied to the display panel based on the interpolated control parameter.

[0007] Other aspects of embodiments will be apparent on review of the following description and the appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order that the above mentioned and other features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, can be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only example embodiments and therefore are not to be considered as limiting the scope of the disclosure as it can admit to other equally effective embodiments.

[0009] Figure 1 An example configuration of a display device is illustrated in accordance with one or more embodiments.

[0010] Figure 2 An example setting table stored in a storage circuit is illustrated in accordance with one or more embodiments.

[0011] Figure 3 An example frame rate control is illustrated in accordance with one or more embodiments.

[0012] Figure 4 An example control of image processing is illustrated in accordance with one or more embodiments.

[0013] Figure 5 An example generation of a gamma curve by interpolation is illustrated in accordance with one or more embodiments.

[0014] Figure 6 An example change of a gamma curve for gamma conversion is illustrated in accordance with one or more embodiments.

[0015] Figure 7 An example waveform of a vertical synchronization signal and an example change of a gamma curve are schematically illustrated in accordance with one or more embodiments.

[0016] Figure 8 An example method for controlling a signal supply circuit is illustrated in accordance with one or more embodiments.

[0017] To facilitate an understanding of this description, like reference characters are used to identify like elements throughout the discussion. It is intended that elements disclosed in one embodiment can be utilized in other embodiments without specific recitation. A suffix can be appended to a reference character to distinguish between like elements having the same reference character. The drawings referred to herein are not intended to be drawn to scale unless specifically indicated. Also, to the extent that the drawings illustrate shapes of certain elements, these shapes are merely exemplary and there is no intent to be limited to the particular shapes disclosed. The drawings and the discussion herein make use of common notations of the electrical arts to describe and teach various principles. DETAILED DESCRIPTION

[0018] The following detailed description is merely exemplary in nature and is not intended to limit the disclosure or the application and uses of the disclosure. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding background, the summary, or the following detailed description.

[0019] Variable frame rate (or variable frame frequency) is a method for providing improved image quality with reduced power consumption. In one implementation, moving pictures (e.g., during a game) can be displayed at an increased frame rate (e.g., 90 Hz or higher) to improve image quality. Still images or low frame rate videos, which are less sensitive to frame rate reduction, can be displayed at a reduced frame rate (e.g., 60 Hz or lower) to reduce power consumption.

[0020] Changing frame rate can cause changes in display characteristics of a display device. In one implementation, the change in frame rate can cause a change in gamma characteristics (or input-output properties) of the display device and / or a change in display brightness level (e.g., brightness level of the entire display image). The changes in display characteristics can be visually perceptible, for example, in the form of undesirable flicker of the displayed image.

[0021] The present disclosure provides various techniques to mitigate undesirable effects of changes in display characteristics potentially caused by changes in frame rate. In one or more embodiments, a display driver includes a control circuit and a signal supply circuit. The control circuit is configured to store a first setting table for a first frame rate and a second setting table for a second frame rate. The control circuit is further configured to generate an interpolated control parameter by interpolation of a first control parameter obtained from the first setting table and a second control parameter obtained from the second setting table in response to adjusting the frame rate of the display device from the first frame rate to the second frame rate. The signal supply circuit is configured to generate at least one first signal to be supplied to a display panel based on the interpolated control parameter. Using the interpolated control parameter can suppress effects of changes in display characteristics, thereby improving image quality.

[0022] In one implementation, the first control parameter can be used to define a first gamma curve for a first frame rate, and the second control parameter can be used to define a second gamma curve for a second frame rate. In such an implementation, the interpolation can provide a smooth change in the gamma curve, thereby mitigating undesirable effects (e.g., flicker) that can potentially be caused by a sudden change in the gamma curve.

[0023] Figure 1 An example configuration of a display device 100 is illustrated in accordance with one or more embodiments. In the illustrated embodiment, the display device 100 is configured to display an image corresponding to input image data Din received from a host 200. Examples of the host 200 can include an application processor, a central processing unit (CPU), or other processor. The display device 100 includes a display panel 1 and a display driver 2. The display panel 1 can include a self-emissive display panel, such as an organic light-emitting diode (OLED) display panel and a micro light-emitting diode (LED) display panel. In other embodiments, the display panel 1 can be a liquid crystal display panel or a different type of display panel. In the illustrated embodiment, the display panel 1 includes a display area 3 and a scan driver circuit 4. The display area 3 includes pixel circuits 5, N gate scan lines SC[1] to SC[N], N emission lines EM[1] to EM[N], and M data lines D[1] to D[M]. The gate scan lines SC[1] to SC[N] and the N emission lines EM[1] to EM[N] are coupled to the scan driver circuit 4, while the data lines D[1] to D[M] are coupled to the display driver 2. The gate scan lines SC[1] to SC[N] and the emission lines EM[1] to EM[N] extend in a horizontal direction of the display panel 1, while the data lines D[1] to D[M] extend in a vertical direction. Each pixel circuit 5 is coupled to a corresponding gate scan line SC, emission line EM, and data line D.

[0024] The pixel circuits 5 are each configured to be programmed or updated with a gamma voltage received from the display driver 2. In one or more embodiments, programming or updating a pixel circuit 5 connected to a gate scan line SC[i], an emission line EM[i], and a data line D[j] can be achieved by asserting the gate scan line SC[i] in a state in which the emission line EM[i] is deasserted and the gamma voltage is supplied to the data line D[j]. The pixel circuits 5 are each also configured to emit light having a luminance level corresponding to the gamma voltage. Light emission from the pixel circuits 5 is controlled by the emission lines EM[1] to EM[N]. The pixel circuits 5 connected to the emission line EM[i] are configured to emit light when the emission line EM[i] is asserted and not to emit light when the emission line EM[i] is deasserted.

[0025] The scan driver circuit 4 is configured to select the pixel circuits 5 to be programmed or updated by the gate scan lines SC[1] to SC[N] and the emission lines EM[1] to EM[N]. The scan driver circuit 4 is configured to activate the gate scan line SC[i] while deactivating the emission line EM[i] when the pixel circuits 5 connected to the gate scan line SC[i] and the emission line EM[i] are programmed or updated. The scan driver circuit 4 is configured to sequentially activate the gate scan lines SC to program or update the pixel circuits 5 of the display area 3. The activation and deactivation of the gate scan lines SC[1] to SC[N] can be controlled based on a gate scan control signal GSTV synchronized with a pair of gate clocks GCK1 and GCK2, where the gate scan control signal GSTV and the gate clocks GCK1 and GCK2 are received from the display driver 2.

[0026] The scan driver circuit 4 is further configured to control the light emission from the pixel circuits 5 by the emission lines EM[1] to EM[N]. When displaying an image, a selected emission line among the emission lines EM[1] to EM[N] is activated to allow the pixel circuits 5 connected thereto to emit light, and the selection of the activated emission line EM is sequentially shifted over the array of emission lines EM in synchronization with the emission clocks ECK1 and ECK2 received from the display driver 2. The activation and deactivation of the emission lines EM[1] to EM[N] are controlled based on an emission control signal ESTV received from the display driver 2.

[0027] In one or more embodiments, the emission control signal ESTV is generated as a pulse width modulation (PWM) signal and the display brightness level of the display device 100 is controlled by the duty cycle of the emission control signal ESTV. The display brightness level can be the brightness level of the entire image being displayed on the display panel 1. The duty cycle of the emission control signal ESTV can correspond to the ratio of the period during which the emission control signal ESTV is activated to one cycle period of the emission control signal ESTV. In one or more embodiments, when the duty cycle of the emission control signal ESTV increases, the ratio of the number of activated emission lines EM to the total number of emission lines EM increases, and the ratio of the pixel circuits 5 emitting light to the total number of pixel circuits 5 also increases, resulting in an increase in the display brightness level of the display device 100.

[0028] In one or more embodiments, the display driver 2 is configured to control the display panel 1 to display an image corresponding to the input image data Din on the display panel 1 based on the input image data Din and control data Dctrl received from the host 200. The input image data Din can include grayscale values associated with the pixel circuits 5 of the display panel 1. The control data can include a display brightness value (DBV) and a frame rate command f FRMThe DBV can specify a desired display luminance level of the display device 100. The frame rate command f FRM The DBV can specify a desired display luminance level of the display device 100. The frame rate command f

[0029] In one or more embodiments, the interface circuit 11 is configured to receive the input image data Din and the control data Dctrl from the host 200. The interface circuit 11 can also be configured to forward the input image data Din to the GRAM 12 and the control data Dctrl to the control circuit 14. In other embodiments, the interface circuit 11 can be configured to process the input image data Din and send the processed input image data Din to the GRAM 12.

[0030] The GRAM 12 is configured to temporarily store the input image data Din received from the interface circuit 11 and forward the input image data Din to the signal supply circuit 13. In other embodiments, the GRAM 12 can be omitted and the input image data Din can be directly transferred from the interface circuit 11 to the signal supply circuit 13.

[0031] The signal supply circuit 13 is configured to supply various signals to the display panel 1 under the control of the control circuit 14. The signals supplied to the display panel 1 can include a gamma voltage (at which the pixel circuits 5 are programmed or updated), a gate scan control signal GSTV, gate clocks GCK1, GCK2, an emission control signal ESTV, emission clocks ECK1 and ECK2. The signal supply circuit 13 can include an image processing circuit 15, a grayscale voltage generator 16, a data driver circuit 17, and a panel interface (I / F) circuit 18.

[0032] In one or more embodiments, the image processing circuit 15 is configured to process the input image data Din received from the GRAM 12 to generate output voltage data Dout. The output voltage data Dout can include voltage values specifying voltage levels of gamma voltages at which the respective pixel circuits 5 of the display panel 1 are programmed or updated.

[0033] The processing performed by the image processing circuit 15 includes a gamma conversion to convert a gray scale value to a voltage value. The gamma conversion can be controlled based on a set of gamma parameters Para_Gamma received from the control circuit 14, where the gamma parameters Para_Gamma define a gamma curve according to which the gamma conversion is performed. The gamma curve represents a correlation between a gray scale value and a voltage value. The processing performed by the image processing circuit 15 can also include one or more other processes (e.g., color adjustment, image scaling, etc.) that can be implemented before and / or after the gamma conversion.

[0034] The gray scale voltage generator 16 is configured to supply (m+1) gray scale voltages Vo to Vm to the data driver circuit 17. In various embodiments, the (m+1) gray scale voltages Vo to Vm have voltage levels that are different from each other. In embodiments where the gray scale voltage Vo is the highest gray scale voltage and the gray scale voltage Vm is the lowest gray scale voltage, the gray scale voltage generator 16 can be configured to generate the highest gray scale voltage Vo and the lowest gray scale voltage Vm and further generate the intermediate gray scale voltages Vi to V(m-i) by voltage division of the gray scale voltages Vo and Vm. In such embodiments, the highest gray scale voltage Vo and the lowest gray scale voltage Vm can control the display brightness level, as the display brightness level of the display device 100 depends on the range of the gamma voltages supplied to the pixel circuits 5.

[0035] The voltage level of the highest gray scale voltage Vo can be specified by a top voltage command value Vtop* received from the control circuit 14, and the voltage level of the lowest gray scale voltage Vm can be specified by a bottom voltage command value Vbottom*. In such embodiments, the range of the gamma voltages, i.e., the display brightness level of the display device 100, can be controlled based at least in part on the top voltage command value Vtop* and the bottom voltage command value Vbottom*.

[0036] The data driver circuit 17 is configured to generate the gamma voltage to be supplied to each of the pixel circuits 5 of the display panel 1 based on the output voltage data Dout received from the image processing circuit 15 and the gray scale voltages Vo to Vm received from the gray scale voltage generator 16. The data driver circuit 17 can be configured to select the gray scale voltages Vo to Vm based on the voltage values of the output voltage data Dout of each of the pixel circuits 5 and output the selected gray scale voltage as the gamma voltage to be supplied to each of the pixel circuits 5. In one implementation, the range of the gamma voltage to be supplied to each of the pixel circuits 5 is from Vm to Vo, and increases as the corresponding voltage value of the output voltage data Dout increases.

[0037] The panel interface circuit 18 is configured to generate a gate scan control signal GSTV, gate clocks GCK1, GCK2, an emission control signal ESTV, and emission clocks ECK1 and ECK2 to control the scan driver circuit 4 of the display panel 1. In one or more embodiments, the panel interface circuit 18 is configured to control a duty cycle of the emission control signal ESTV based on an emission command Emission* received from the control circuit 14. The emission command Emission* can specify a desired duty cycle of the emission control signal ESTV. In embodiments in which a display brightness level of the display device 100 is controllable with the emission control signal ESTV, the display brightness level is controllable with the emission command Emission*.

[0038] In one or more embodiments, the control circuit 14 is configured to control the operation of the signal supply circuit 13 based on control data Dctrl received from the host 200 via the interface circuit 11. In embodiments in which the control data Dctrl includes a display brightness value (DBV), the control circuit 14 can be configured to control a display brightness level of the display device 100 based on the DBV. The DBV can be generated based on user operation. For example, when an instruction for adjusting a brightness of an image displayed on the display device 100 is manually input to an input device (not shown), the host 200 can generate the DBV based on the instruction to adjust the display brightness level. The input device can include a touch panel provided on at least a portion of the display panel 1, a cursor control device, and mechanical and / or non-mechanical buttons.

[0039] The control circuit 14 can also be configured to control a frame rate (or frame frequency) of the display device 100. In embodiments in which the control data Dctrl includes a frame rate command f FRM , the control circuit 14 can be configured to control a frame rate as specified by the frame rate command f FRM . In one or more embodiments, the control circuit 14 includes a timing controller (TCON) 21, a storage (STR) circuit 22, a seamless frame rate controller (SFC) 23, and a brightness controller (BRC) 24.

[0040] The timing controller 21 is configured to control an operation timing of the display device 100 based on the control data Dctrl. The operation timing control can include specifying a frame rate of the display device 100. In some embodiments, the timing controller 21 can be configured to specify the frame rate as specified by the frame rate command f FRM . In embodiments in which the timing controller 21 fails to receive the frame rate command f FRM , the timing controller 21 can be configured to specify the frame rate by itself.

[0041] The timing controller 21 can also be configured to generate vertical synchronization periods to achieve the frame rate so specified. A vertical synchronization signal can define a frame period (or a vertical synchronization period) by being asserted at the beginning of each frame period (or each vertical synchronization period). The signal supply circuit 13 can be configured to operate in synchronization with the vertical synchronization signal. In one implementation, the vertical synchronization periods can be generated such that each frame period has a duration that is an inverse number of the specified frame rate.

[0042] The storage circuit 22 is configured to store a plurality of setting tables 25, each setting table 25 including information for controlling the signal supply circuit 13. The plurality of setting tables 25 are respectively associated with (or defined for) a plurality of predetermined frame rates. Each setting table 25 can include control parameters for controlling the signal supply circuit 13. The term table refers to any storage mechanism related to a set of values. The set of tables can be a single storage structure or multiple structures. Each setting table is defined for a corresponding frame rate and relates control parameters to DBV. In one implementation, the control parameters included in each setting table 25 can include a set of gamma parameters Para_Gamma, emission command values Emission*, top voltage command values Vtop*, and / or bottom voltage command values Vbottom*.

[0043] Figure 2 An example setting table 25 stored in the storage circuit 22 is illustrated in accordance with one or more embodiments. In the illustrated embodiment, the setting tables 25 stored in the storage circuit 22 include four setting tables 251, 252, 253, and 254 defined for frame rates of 60, 90, 120, and 144 Hz, respectively. These setting tables 251, 252, 253, and 254 can be collectively referred to by the numeral 25. Setting tables 25 can be defined for different frame rates. The number of setting tables 25 stored in the storage circuit 22 is not limited to four. In some embodiments, only two or three setting tables 25 can be stored in the storage circuit 22. In other embodiments, five or more setting tables 25 can be stored in the storage circuit 22.

[0044] Each of the settings tables 251 to 254 includes multiple sub-tables associated with different DBV ranges. In the illustrated embodiment, each of the settings tables 251 to 254 includes 18 sub-tables #0 to #17 associated with DBV ranges #0 to #17, respectively. In the embodiment where DBV is defined as a 12-bit value from 0 to 4095, DBV ranges #0 to #17 are defined to cover the range from 0 to 4095. In the illustrated embodiment, DBV range #0 is defined as the range between 0 and 227 (inclusive), and DBV range #1 is defined as the range between 228 and 455 (inclusive). Other DBV ranges can be defined similarly. Sub-table #i includes one or more control parameters for DBV range #i, where i is an integer from 0 to 17. The control parameters for each sub-table #i may include a set of gamma parameters Para_Gamma, a transmit command value Emission*, a top voltage command value Vtop* and / or a bottom voltage command value Vbottom* for DBV range #i.

[0045] The storage circuit 22 can also be configured to store one or more setting tables defined for one or more different frame rates, each setting table including multiple sub-tables associated with multiple DBV ranges.

[0046] Return to reference Figure 1 SFC 23 is configured to retrieve the first setting table from a plurality of setting tables stored in storage circuit 22 (e.g., ...). Figure 2 The first sub-table selected from the 60Hz setting table 251 illustrated in the figure, and the second sub-table selected from a second setting table (e.g., the 90Hz setting table 252) among multiple setting tables, are forwarded to BRC 24. In embodiments where the storage circuit 22 is configured to store three or more setting tables, the first and second setting tables can be selected based on the specified frame rate as described above, such that the specified frame rate is between the frame rates corresponding to the first and second setting tables. The selection of the first sub-table from the first setting table and the selection of the second sub-table from the second setting table can be based on DBV. Setting tables 251 to 254 are stored as shown in the figure. Figure 2 In the embodiment of the storage circuit 22 shown in the figure, when DBV is in the DBV range #i, the sub-table #i of the first and second setting tables selected from setting tables 251 to 254 can be selected as the first and second sub-tables and forwarded to BRC24.

[0047] SFC 23 is also configured to determine (e.g., calculate) one or more interpolation coefficients for interpolating the control parameters contained in the first and second sub-tables based on the frame rate specified as described above. The determined interpolation coefficients can include one or more interpolation coefficients for the gamma parameter Para_Gamma, the top voltage command value Vtop*, the bottom voltage command value Vbottom*, and / or the emission command value Emission*.

[0048] BRC 24 is configured to generate control parameters for controlling the signal supply circuit 13 by interpolating the control parameters contained in the first and second sub-tables selected by SFC 23 based on the interpolation coefficients determined by SFC 23. BRC 24 can be configured to generate the gamma parameter Para_Gamma to be used by the image processing circuit 15 by interpolating those contained in the first and second sub-tables based on the interpolation coefficients determined for the gamma parameter Para_Gamma. BRC 24 can also be configured to generate the emission command value Emission* to be used by the panel interface circuit 18 by interpolating those contained in the first and second sub-tables based on the interpolation coefficients determined for the emission command value Emission*. BRC 24 can also be configured to generate the top voltage command value Vtop* and the bottom voltage command value Vbottom* to be used by the grayscale voltage generator 16 by interpolating those contained in the first and second sub-tables based on the interpolation coefficients determined for the top voltage command value Vtop* and the bottom voltage command value Vbottom*, respectively.

[0049] The control parameters thus generated are provided to the signal supply circuit 13 to control the operation of the signal supply circuit 13. The image processing circuit 15 of the signal supply circuit 13 can be configured to process the input image data Din based on the gamma parameter Para_Gamma thus generated to generate the output voltage data Dout. The panel interface circuit 18 can be configured to generate the emission control signal ESTV based on the emission control value Emission* thus generated. The grayscale voltage generator 16 can be configured to generate the highest grayscale voltage Vo based on the top voltage command value Vtop* and the lowest grayscale voltage Vm based on the bottom voltage command value Vbottom*, and to generate the grayscale voltages Vo to Vm by voltage division of the grayscale voltages Vo and Vm.

[0050] Figure 3 An example frame rate control according to one or more embodiments is illustrated. In the illustrated embodiment, a target frame rate is specified by the host 200 or the timing controller 21, and the frame rate of the display device 100 is adjusted to follow the target frame rate. In one embodiment, the target frame rate is specified by a frame rate command f FRM*Specified. In other embodiments, the target frame rate may be specified by the timing controller 21 instead. In the illustrated embodiment, the target frame rate is initially set to 60Hz, which is the frame rate for normal operation, and the frame rate of the display device 100 is set to 60Hz during the frame period prior to time t1.

[0051] At time t l The target frame rate is changed to 90Hz. In one implementation, this change may be intended to improve image quality during gameplay or video display. In response to the change in the target frame rate, the frame rate of the display device 100 gradually increases toward 90Hz during a first dimming period beginning at time t1. The first dimming period may include a specified number of frame periods, for example, tens to thousands of frame periods. The timing controller 21 specifies the frame rate for each frame period during the first dimming period, such that the specified frame rate gradually increases. At time t2, the specified frame rate reaches 90Hz. The frame rate is then maintained at 90Hz during the frame period between time t2 and time t3.

[0052] At time t3, the target frame rate changes to 60Hz. In response to the change in the target frame rate, the frame rate of the display device 100 gradually decreases towards 60Hz during a second dimming period beginning at time t3. The second dimming period may include a specified number of frame periods, for example, tens to thousands of frame periods. The timing controller 21 specifies the frame rate in each frame period during the second dimming period, such that the specified frame rate gradually decreases. At time t4, the frame rate reaches 60Hz. Thereafter, the frame rate is maintained at 60Hz.

[0053] In other embodiments, the frame rate command f FRM *Can be directly specified in t l The frame rate during each frame period between t2 and t3 and between t4. In other embodiments, the timing controller 21 can be independent of the frame rate command f. FRM *Specify the frame rate for each frame period during the first and second dimming periods.

[0054] Figure 4 The illustration depicts a frame rate that is variably adjusted (e.g., as shown in one or more embodiments). Figure 3 Example control of image processing (e.g., gamma transform) in an embodiment (illustrated in the figure). In some embodiments, host 200 specifies the frame rate for the current frame period in step 401-1. In other embodiments, timing controller 21 may alternatively specify the frame rate for the current frame period in step 401-2. The frame rate can be based on a target frame rate specified by host 200 (e.g., by a frame rate command f). FRM The frame rate for the current frame period is specified using the asterisk (*).Figure 3 As described.

[0055] In step 402, SFC 23 obtains control parameters (e.g., gamma parameters) from two settings tables 25 stored in storage circuitry 22 based on a specified frame rate and / or DBV. In one embodiment, SFC 23 selects two settings tables 25 based on a specified frame rate for the current frame period, and further selects a sub-table from each of the two selected settings tables 25 based on DBV. In one embodiment, when DBV is in the DBV range #i, SFC 23 selects sub-table #i from each of the two selected settings tables 25. In such an embodiment, SFC 23 obtains controller parameters from each sub-table #i of the two selected settings tables 25. In embodiments where storage circuitry 22 stores only two settings tables 25, SFC 23 can obtain controller parameters from each sub-table #i of the two settings tables 25.

[0056] In step S403, SFC 23 determines one or more interpolation coefficients based on the frame rate specified for the current frame rate. In step S404, BRC 24 generates control parameters to be used by the image processing circuit 15 by interpolating control parameters obtained from two selected setting tables 25 (e.g., from sub-table #i of the two selected setting tables 25) based on the interpolation coefficients. The image processing circuit 15 processes the input image data based on the control parameters generated by BRC 24.

[0057] In one implementation, the control parameters generated by BRC 24 include a set of gamma parameters Para_Gamma, which are used to generate or determine a gamma curve, and the image processing circuit 15 performs a gamma transformation based on the gamma curve. Figure 5 and 6 The diagram illustrates the process of... Figure 4 Example generation of the interpolated gamma curve described.

[0058] exist Figure 5 In the embodiment illustrated, in response to the frame rate being specified between a first frame rate (e.g., 60Hz) and a second frame rate (e.g., 90Hz) for the current frame period, a setting table 25 for the first frame rate (e.g., setting table 251 for 60Hz) and a setting table 25 for the second frame rate (e.g., setting table 252 for 90Hz) are selected.

[0059] In one embodiment, when the DBV is in the DBV range #i, the gamma parameter Para_Gamma for the gamma conversion in the image processing circuit 15 is generated by interpolation of the corresponding gamma parameters contained in the sub-table #i of the setting tables 251 and 252. The interpolation coefficient for this interpolation is determined based on the frame rate designated for the current frame period. In an embodiment in which the interpolation coefficient for a first frame rate (e.g., 60 Hz) is a first value (e.g., 0) and the interpolation coefficient for a second frame rate (e.g., 90 Hz) is a second value (e.g., 255), when the designated frame rate is between the first frame rate and the second frame rate, the interpolation coefficient for the designated frame rate can be determined to be a value between the first value and the second value. The interpolation coefficient can be determined depending on the difference between the designated frame rate and the first frame rate divided by the difference between the second frame rate and the designated frame rate. In an embodiment in which the interpolation coefficient is determined to be a value between 0 and 255 inclusive, the interpolation coefficient Coef_int can be determined as follows:

[0060]

[0061] where f is the designated frame rate; f1 is the first frame rate; and f2 is the second frame rate.

[0062] In one embodiment, the gamma parameter Para_Gamma for the gamma conversion can be determined as a weighted sum of the corresponding gamma parameters contained in the selected sub-table #i of the setting table 25 for the first and second frame rates, the weighting factors depending on the interpolation coefficient. In an embodiment in which the interpolation coefficient is determined to be a value between 0 and 255 inclusive, each gamma parameter Para_Gamma[k] can be determined according to the following expression, as discussed above:

[0063] Para_Gamma[k] = w1 · Para_Gamma1[k] + w2 · Para_Gamma2[k],

[0064] where Para_Gamma1[k] is the corresponding gamma parameter contained in the selected sub-table #i of the setting table 25 corresponding to the first frame rate; Para_Gamma2[k] is the corresponding gamma parameter contained in the selected sub-table #i of the setting table 25 corresponding to the second frame rate; and the weighting factors w1 and w2 are determined as follows:

[0065] w1 = 1 - Coef_int / 255, and

[0066] w2 = Coef_int / 255.

[0067] Figure 6 An example change in the gamma curve for the gamma conversion in the image processing circuit 15 is illustrated. In the example of FIG. 17, the gamma curve for the gamma conversion in the image processing circuit 15 is changed from the gamma curve for the gamma conversion in the image processing circuit 15 in the case of the first frame rate (e.g., 60 Hz) to the gamma curve for the gamma conversion in the image processing circuit 15 in the case of the second frame rate (e.g., 90 Hz) by interpolation of the corresponding gamma parameters contained in the sub-table #i of the setting tables 251 and 252. Figure 6In some embodiments, the gamma curve defined by the gamma parameters included in the setting table 25 for the first, second and third frame rates (e.g., 60, 90 and 120 Hz) is illustrated by the solid line and dots. The above-described interpolation-based scheme allows the gamma curve to change smoothly (or seamlessly) as the frame rate gradually changes (e.g., from the first frame rate to the third frame rate). This can effectively suppress potentially undesirable effects (e.g., flicker) caused by the change in the frame rate. Figure 7 An example waveform of the vertical synchronization signal Vsync and example changes of the gamma curve are schematically illustrated. The gamma curve is smoothly changed or modified while increasing the frame rate by reducing the periodicity of the vertical synchronization signal (i.e., the length of the frame period).

[0068] In some embodiments, in addition to or instead of the gamma parameters Para_Gamma, the top voltage command value Vtop* and / or the bottom voltage command value Vbottom* can be generated by interpolation in a similar manner. In such embodiments, the control parameters included in each sub-table (e.g., sub-tables #0 to #17 in the setting table 25) of the setting table 25 can include the top voltage command value and / or the bottom voltage command value corresponding to the frame rate of the setting table 25. Figure 2

[0069] Referring back to Figure 1 , the SFC 23 can be configured to obtain the top voltage command value and / or the bottom voltage command value from two of the setting tables 25 stored in the storage circuit 22 based on the specified frame rate and / or the DBV. The SFC 23 can be configured to select the two of the setting tables 25 based on the specified frame rate of the current frame period, and further select a sub-table #i from each of the selected two setting tables 25 when the DBV is in the DBV range #i. In such embodiments, the SFC 23 can be configured to obtain the top voltage command value and / or the bottom voltage command value from each sub-table #i of the selected two setting tables 25. The SFC 23 can be further configured to determine the interpolation coefficient based on the specified frame rate for the current frame rate.

[0070] ​The BRC 24 can be configured to generate a top voltage command value Vtop* and / or a bottom voltage command value Vbottom* to be used by the grayscale voltage generator 16 by interpolating the top voltage command value and / or the bottom voltage command value obtained from two selected setting tables 25 (e.g., from sub-tables #i of the two selected setting tables 25) based on interpolation coefficients. The grayscale voltage generator 16 can be configured to generate a highest grayscale voltage Vo as indicated by the top voltage command value Vtop* and to generate a lowest grayscale voltage Vm as indicated by the bottom voltage command value Vbottom*. Generating the top voltage command value Vtop* and / or the bottom voltage command value Vbottom* by interpolation can smoothly (or seamlessly) achieve a change in the range of gamma voltages provided to the pixel circuit 5. This can effectively suppress an undesirable image quality degradation (e.g., flicker) potentially caused by a change in the frame rate.

[0071] In other embodiments, in addition to or instead of the gamma parameter Para_Gamma, the top voltage command value Vtop*, and / or the bottom voltage command value Vbottom*, an emission command value Emission* can be generated by interpolation in a similar manner. It should be noted that the emission command value specifies a duty cycle of the emission control signal ESTV to control a ratio of the pixel circuit 5 that emits light to a total number of pixel circuits 5 in the display panel 1 as described above with respect to Figure 1 In such embodiments, the control parameters included in each sub-table (e.g., sub-tables #0 to #17 in Figure 2 of each setting table 25 can include an emission command value corresponding to the frame rate of the setting table 25.

[0072] In one implementation, the SFC 23 can be configured to obtain an emission command value from two of the setting tables 25 stored in the storage circuit 22 based on the specified frame rate and / or the DBV. The SFC 23 can be configured to select two of the setting tables 25 based on the specified frame rate for the current frame period and to further select a sub-table #i from each of the two selected setting tables 25 when the DBV is in the DBV range #i. In such embodiments, the SFC 23 can be configured to obtain an emission command value from each sub-table #i of the two selected setting tables 25. The SFC 23 can be further configured to determine interpolation coefficients based on the specified frame rate for the current frame rate.

[0073] The BRC 24 can be configured to generate an emission command value Emission* to be used by the panel interface circuit 18 by interpolating the emission command values obtained from two selected setting tables 25 (e.g., from sub-tables #i of the two selected setting tables 25) based on the interpolation coefficients. The panel interface circuit 18 can be configured to generate an emission control signal ESTV having a duty cycle indicated by the emission command value Emission*. Generating the emission command value Emission* by interpolation can smoothly (or seamlessly) implement a change in the duty cycle of the emission control signal ESTV, which controls the display brightness level of the display device 100 by controlling the ratio of the number of pixel circuits 5 that emit light to the total number of pixel circuits 5. This can effectively suppress undesirable image quality degradation (e.g., flicker) that can be caused by a change in the frame rate.

[0074] Figure 8 The method 800 illustrates steps for controlling a display panel 1 (as illustrated in FIG. 1) while a frame rate of the display device 100 is adjusted from a first frame rate (e.g., 60 Hz) to a second frame rate (e.g., 90 Hz) according to one or more embodiments. It should be noted that the order of the steps can be changed from the illustrated order. Figure 1

[0075] At step 801, a frame rate for a current frame period is specified by the host 200 or the timing controller 21. At step 802, control parameters (e.g., gamma parameters, top voltage command values, bottom voltage command values, and emission control commands) are obtained from two of the setting tables 25 stored in the storage circuit 22 based on the specified frame rate and / or the DBV. In one implementation, the two setting tables 25 can be selected based on the frame rate specified for the current frame period, and a sub-table is selected from each of the selected two setting tables 25 based on the DBV. In one implementation, when the DBV is in the DBV range #i, a sub-table #i is selected from each of the selected two setting tables 25. In such an embodiment, the controller parameters can be selected from each sub-table #i of the selected two setting tables 25. In embodiments where the storage circuit 22 stores only two setting tables 25, the controller parameters can be obtained from each sub-table #i of the two setting tables 25.

[0076] ​At step 803, one or more interpolation coefficients are determined based on the frame rate specified for the current frame rate. At step 804, one or more interpolated parameters to be supplied to the signal supply circuit 13 are generated by interpolating the corresponding control parameters obtained from two selected setting tables 25 (e.g., from sub-tables #i of two selected setting tables 25) based on the interpolation coefficients. The one or more interpolated parameters thus generated can include a set of gamma parameters Para_Gamma, top voltage command values Vtop*, bottom voltage command values Vbottom*, and / or emission command values Emission*. At step 805, one or more signals to be supplied to the display panel 1 (e.g., gamma voltages and emission control signals ESTV to be supplied to the pixel circuits 5) are generated by the signal supply circuit 13 based on the interpolated control parameters supplied to the signal supply circuit 13.

[0077] While a number of embodiments have been described, those skilled in the art will appreciate that other embodiments can be devised without departing from the scope. Accordingly, the scope of the present application should be limited only by the appended claims.

Claims

1. A display driver comprising: a control circuit configured to: store a first setting table for a first frame rate and a second setting table for a second frame rate; in response to adjusting a frame rate of a display device from the first frame rate to the second frame rate, generate an interpolated control parameter by interpolation of a first control parameter obtained from the first setting table and a second control parameter obtained from the second setting table; set the frame rate of the display device to the first frame rate during a first frame period; set the frame rate of the display device to the second frame rate during a second frame period after the first frame period; and set the frame rate of the display device to a third frame rate between the first frame rate and the second frame rate during a third frame period between the first frame period and the second frame period, wherein an interpolation coefficient of the interpolation is determined based on the third frame rate specified for the third frame period; and a signal supply circuit configured to generate at least one first signal to be supplied to a display panel based on the interpolated control parameter.

2. The display driver according to claim 1, wherein the control circuit is configured to: select the first setting table and the second setting table from a plurality of setting tables based on a specified frame rate.

3. The display driver according to claim 2, wherein the specified frame rate is specified by a host external to the display driver.

4. The display driver according to claim 1, wherein the control circuit is configured to: select the first control parameter from the first setting table based on a display luminance value; and select the second control parameter from the second setting table based on the display luminance value.

5. A display driver comprising: a control circuit configured to: store a first setting table for a first frame rate and a second setting table for a second frame rate; in response to adjusting a frame rate of a display device from the first frame rate to the second frame rate, generate an interpolated control parameter by interpolation of a first control parameter obtained from the first setting table and a second control parameter obtained from the second setting table, wherein an interpolation coefficient of the interpolation is determined based on a frame rate specified for a current frame period; and a signal supply circuit configured to generate at least one first signal to be supplied to a display panel based on the interpolated control parameter, wherein the at least one first signal includes a gamma voltage supplied to a pixel circuit of the display panel, wherein the signal supply circuit includes: an image processing circuit configured to generate output voltage data specifying voltage levels of the gamma voltage based on the interpolated control parameter defined for the pixel circuit and input image data; and a driver circuit configured to generate the gamma voltage based on the output voltage data.

6. The display driver according to claim 5, wherein the first control parameter includes a first gamma parameter for defining a first gamma curve of the first frame rate, 7. The display driver according to claim 5, wherein the second control parameter includes a second gamma parameter for defining a second gamma curve of the second frame rate. ​ ​ wherein the second control parameter comprises a second gamma parameter defining a second gamma curve for the second frame rate.

7. The display driver of claim 6, wherein the interpolated control parameter comprises a third gamma parameter defining a third gamma curve for generating the gamma voltages.

8. The display driver of claim 5, wherein the control circuit is configured to: select a first gamma parameter from the first settings table based on the DBV; and select a second gamma parameter from the second settings table based on the DBV.

9. The display driver of claim 5, wherein the control circuit is configured to: set the frame rate of the display device to the first frame rate during a first frame period; set the frame rate of the display device to the second frame rate during a second frame period after the first frame period; and set the frame rate of the display device to a third frame rate between the first frame rate and the second frame rate during a third frame period between the first frame period and the second frame period, wherein the interpolation of the first control parameter and the second control parameter comprises an interpolation of a first gamma parameter and a second gamma parameter based on the third frame rate during the third frame period.

10. The display driver of claim 5, wherein the signal supply circuit further comprises: a grayscale voltage supply circuit configured to supply a plurality of grayscale voltages to the driver circuit, wherein the first control parameter specifies a first voltage level of a highest one of the plurality of grayscale voltages for the first frame rate, wherein the second control parameter specifies a second voltage level of the highest one of the plurality of grayscale voltages for the second frame rate, and wherein the interpolated control parameter specifies the highest one of the plurality of grayscale voltages for a specified frame rate between the first frame rate and the second frame rate.

11. The display driver of claim 5, wherein the signal supply circuit further comprises: a grayscale voltage supply circuit configured to supply a plurality of grayscale voltages to the driver circuit, wherein the first control parameter specifies a first voltage level of a lowest one of the plurality of grayscale voltages for the first frame rate, wherein the second control parameter specifies a second voltage level of the lowest one of the plurality of grayscale voltages for the second frame rate, and wherein the interpolated control parameter specifies the lowest one of the plurality of grayscale voltages for a specified frame rate between the first frame rate and the second frame rate.

12. A display driver, comprising: a control circuit configured to: store a first settings table for a first frame rate and a second settings table for a second frame rate; in response to adjusting a frame rate of a display device from the first frame rate to the second frame rate, generate an interpolated control parameter by an interpolation of a first control parameter obtained from the first settings table and a second control parameter obtained from the second settings table, wherein an interpolation factor of the interpolation is determined based on a frame rate specified for a current frame period; and and a signal supply circuit configured to generate at least one first signal to be supplied to the display panel based on the interpolated control parameter, wherein the at least one first signal includes an emission control signal that controls a ratio of a number of pixel circuits that emit light to a total number of pixel circuits of the display panel.

13. The display driver of claim 12, wherein the first control parameter includes a first emission command value that controls a first ratio of a number of pixel circuits that emit light to the total number of the pixel circuits of the display panel for the first frame rate, and wherein the second control parameter includes a second emission command value that controls a second ratio of a number of pixel circuits that emit light to the total number of the pixel circuits of the display panel for the second frame rate.

14. The display driver of claim 13, wherein the interpolated control parameter includes a third emission command value generated by interpolation of the first emission command value and the second emission command value, the emission control signal being generated based on the third emission command value.

15. A display device, comprising: a display panel; and a display driver, comprising: a control circuit configured to: store a first setting table for a first frame rate and a second setting table for a second frame rate; and in response to adjusting a frame rate of the display device from the first frame rate to the second frame rate, generate an interpolated control parameter by interpolation of a first control parameter obtained from the first setting table and a second control parameter obtained from the second setting table, wherein an interpolation coefficient of the interpolation is determined based on a frame rate specified for a current frame period; and a signal supply circuit configured to generate at least one first signal to be supplied to the display panel based on the interpolated control parameter, wherein the at least one first signal includes a gamma voltage to be supplied to a pixel circuit of the display panel, wherein the signal supply circuit includes: an image processing circuit configured to generate output voltage data that specifies a voltage level of the gamma voltage based on the interpolated control parameter defined for the pixel circuit and input image data; and a driver circuit configured to generate the gamma voltage based on the output voltage data.

16. The display device of claim 15, wherein the first control parameter defines a first gamma curve for the first frame rate, wherein the second control parameter defines a second gamma curve for the second frame rate, and wherein the interpolated control parameter defines a third gamma curve for generating the gamma voltage.

17. A method, comprising: in response to adjusting a frame rate of a display device from a first frame rate to a second frame rate, determining an interpolated control parameter by interpolation of a first control parameter obtained from a first setting table for the first frame rate and a second control parameter obtained from a second setting table for the second frame rate, wherein an interpolation coefficient of the interpolation is determined based on a frame rate specified for a current frame period, wherein the first control parameters comprise first gamma parameters for defining a first gamma curve of the first frame rate, wherein the second control parameters comprise second gamma parameters for defining a second gamma curve of the second frame rate; and generating at least one first signal to be supplied to a display panel based on the interpolated control parameters.

Images