Semiconductor device and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a manufacturing method thereof, which relates to the field of semiconductor technology. The manufacturing method comprises: providing a substrate, forming a film layer stacking structure on the substrate; etching the film layer stacking structure to form a first region containing a through hole exposing the substrate and a second region containing a hole segment not exposing the substrate; patterning and etching the second region to remove the film layer stacking structure in the second region. The manufacturing method of the semiconductor device disclosed in the present disclosure can prevent capacitor failure and improve capacitor stability.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high integration and fast transmission speed. Capacitors are the core components of dynamic random access memory and are mainly used to store charges.

[0003] Usually, in the process of manufacturing capacitors, it is necessary to form overlapping support layers and sacrificial layers on the substrate, etch the support layers and sacrificial layers to form a hole-shaped structure for accommodating the capacitor, and then remove the sacrificial layer after the capacitor is formed. However, due to the limitations of the preparation process, the etching depth of the film layer in different etching areas is different. After removing the sacrificial layer, some capacitors fail due to being suspended.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to overcome the deficiencies in the above-mentioned prior art and to provide a semiconductor device and a manufacturing method thereof, which can prevent capacitor failure and improve capacitor stability.

[0006] According to one aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, characterized by comprising:

[0007] Providing a substrate, and forming a film layer stacking structure on the substrate;

[0008] Etching the film layer stack structure to form a first region including a through hole exposing the substrate and a second region including a hole segment not exposing the substrate;

[0009] The second region is pattern-etched to remove the film layer stack structure in the second region.

[0010] In an exemplary embodiment of the present disclosure, etching the film layer stack structure to form a first region including a through hole exposing the substrate and a second region including a hole segment not exposing the substrate includes:

[0011] forming a mask material layer on a side of the film layer stack structure facing away from the substrate;

[0012] forming a photoresist layer on a surface of the mask material layer facing away from the substrate;

[0013] Exposing and developing the photoresist layer to form a plurality of development areas, each of the development areas exposing the mask material layer;

[0014] etching the mask material layer in the developing area to form a mask pattern;

[0015] The film layer stack structure is anisotropically etched according to the mask pattern, and the substrate is used as an etching stop layer to form the through hole in the film layer stack structure located in the first area and the hole segment in the film layer stack structure located in the second area.

[0016] In an exemplary embodiment of the present disclosure, the patterned etching of the second region to remove the film layer stack structure in the second region includes:

[0017] forming a photoresist layer on the surface of the first region;

[0018] Etching the film layer stack structure in the second region and the substrate facing the second region;

[0019] The photoresist layer is removed.

[0020] In an exemplary embodiment of the present disclosure, the etching of the film layer stack structure of the second region and the substrate facing the second region includes:

[0021] The film layer stack structure in the second region is dry-etched using an etching gas along a direction perpendicular to the film layer stack structure.

[0022] In an exemplary embodiment of the present disclosure, the etching gas includes at least one of carbon tetrafluoride gas or sulfur hexafluoride gas.

[0023] In an exemplary embodiment of the present disclosure, the first region is a central region of the film layer stacking structure, and the second region is an edge region of the film layer stacking structure.

[0024] In an exemplary embodiment of the present disclosure, it is characterized in that there are a plurality of through holes, the substrate facing the first region includes a plurality of storage node contact plugs, and each of the through holes can expose each of the storage node contact plugs in a one-to-one correspondence.

[0025] In an exemplary embodiment of the present disclosure, the manufacturing method further includes:

[0026] A capacitor array is formed in each of the through holes.

[0027] In an exemplary embodiment of the present disclosure, the film layer stack structure includes a support layer and a sacrificial layer overlapped and arranged in a direction perpendicular to the substrate, and the capacitor array is formed in each of the through holes, including:

[0028] forming a lower electrode layer in each of the through holes, wherein the lower electrode layer is in contact with the storage node contact plug;

[0029] removing each of the sacrificial layers;

[0030] forming a capacitor dielectric layer on the surface of the structure formed by the lower electrode layer and the support layer;

[0031] forming an upper electrode layer on a surface of the capacitor dielectric layer away from the lower electrode layer;

[0032] A conductive layer covering the upper electrode layer is formed, and the conductive layer fills the through hole and the gap between two adjacent capacitors.

[0033] According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device is manufactured by any of the above-mentioned methods for manufacturing a semiconductor device.

[0034] The semiconductor device and its manufacturing method disclosed in the present invention will not form a capacitor in the hole segment after removing the hole segment in the second region, so there will be no suspended capacitor after removing the sacrificial layer, thereby preventing the capacitor from failing due to being suspended, and also preventing the suspended capacitor from collapsing due to lack of support at the bottom, thereby preventing short circuits between adjacent capacitors. In addition, the through hole in the first region is retained, so that the capacitor formed subsequently can be connected to the substrate through the through hole, and the charge of the capacitor can be stored in the substrate, thereby realizing capacitor storage; at the same time, the bottom of the capacitor can be supported by the substrate to prevent the capacitor from collapsing, which can improve the stability of the capacitor.

[0035] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0037] Figure 1 The present invention is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0038] Figure 2 It is a schematic diagram after completing step S110 of the manufacturing method disclosed in the present invention.

[0039] Figure 3 It is a schematic diagram after completing step S120 of the manufacturing method disclosed in the present invention.

[0040] Figure 4 for Figure 1 Flowchart of step S120 in FIG.

[0041] Figure 5 It is a schematic diagram after completing step S1203 of the manufacturing method disclosed in the present invention.

[0042] Figure 6 It is a schematic diagram after completing step S1204 of the manufacturing method disclosed in the present invention.

[0043] Figure 7 It is a schematic diagram after completing step S130 of the manufacturing method disclosed in the present invention.

[0044] Figure 8 for Figure 1 Flowchart of step S130 in FIG.

[0045] Fig. 9 It is a schematic diagram after completing step S1301 of the manufacturing method disclosed in the present invention.

[0046] Fig.10 It is a schematic diagram after completing step S1303 of the manufacturing method disclosed in the present invention.

[0047] Fig.11 It is a schematic diagram after completing step S140 of the manufacturing method disclosed in the present invention.

[0048] Fig.12 for Figure 1 Flowchart of step S140 in FIG.

[0049] Fig.13 It is a schematic diagram after completing step S1401 of the manufacturing method disclosed in the present invention.

[0050] Fig.14 It is a schematic diagram after completing step S1402 of the manufacturing method disclosed in the present invention.

[0051] Fig.15 It is a schematic diagram after completing step S1404 of the manufacturing method disclosed in the present invention.

[0052] In the figure: 1. substrate; 11. storage node contact plug; 2. film layer stack structure; 211. through hole; 221. hole segment; 201. first sacrificial layer; 202. first supporting layer; 203. second sacrificial layer; 204. second supporting layer; 3. mask material layer; 31. polymer layer; 32. oxide layer; 33. hard mask layer; 4. photoresist layer; 5. columnar capacitor; 51. lower electrode layer; 52. capacitor dielectric layer; 53. upper electrode layer; 6. bottom supporting layer; 7. conductive layer; A. first region; B. second region. DETAILED DESCRIPTION

[0053] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0054] The features, structures or characteristics described above may be combined in one or more embodiments in any suitable manner, and if possible, the features discussed in each embodiment are interchangeable. In the above description, many specific details are provided to provide a full understanding of the embodiments of the present invention. However, those skilled in the art will appreciate that the technical solution of the present invention may be practiced without one or more of the specific details, or other methods, materials, etc. may be adopted. In other cases, known structures, materials or operations are not shown or described in detail to avoid blurring various aspects of the present invention.

[0055] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0056] The terms "a", "an", "the", "said", "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc. The terms "first" and "second" are used only as labels and are not intended to limit the quantity of their objects.

[0057] The present disclosure provides a method for manufacturing a semiconductor device, such as Figure 1 As shown, the manufacturing method may include:

[0058] Step S110, providing a substrate, and forming a film layer stacking structure on the substrate;

[0059] Step S120, etching the film layer stack structure to form a first region including a through hole exposing the substrate and a second region including a hole segment not exposing the substrate;

[0060] Step S130 , pattern-etching the second region to remove the film layer stacking structure in the second region.

[0061] The manufacturing method of the semiconductor device disclosed in the present invention will not form a capacitor in the hole segment after removing the hole segment in the second region, so there will be no suspended capacitor after removing the sacrificial layer, thereby preventing the capacitor from failing due to being suspended, and also preventing the suspended capacitor from collapsing due to lack of support at the bottom, thereby preventing short circuits between adjacent capacitors. In addition, the through hole in the first region is retained, so that the capacitor formed subsequently can be connected to the substrate through the through hole, and the charge of the capacitor can be stored in the substrate, thereby realizing capacitor storage; at the same time, the bottom of the capacitor can be supported by the substrate to prevent the capacitor from collapsing, which can improve the stability of the capacitor.

[0062] The following is a detailed description of each step of the method for manufacturing a semiconductor device according to an embodiment of the present disclosure:

[0063] In step S110 , a substrate is provided, and a film layer stacking structure is formed on the substrate.

[0064] The substrate may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be silicon or other semiconductor materials. The shape and material of the substrate are not particularly limited here.

[0065] The substrate may include a base 1 and a bottom supporting layer 6 formed on the surface of the base 1, wherein a plurality of storage node contact plugs 11 distributed in an array are formed in the bottom supporting layer 6. The storage node contact plugs 11 may be a ring structure and may be made of a conductor or semiconductor material, for example, tungsten, copper or polysilicon.

[0066] For example, the bottom support layer 6 may be provided with a plurality of vias distributed in an array, each of which may be a through hole, and a storage node contact plug 11 may be formed in the via. For example, the storage node contact plug 11 may be formed in the via by vacuum evaporation, magnetron sputtering or chemical vapor deposition. Of course, the storage node contact plug 11 may also be formed by other methods, which are not listed here one by one.

[0067] like Figure 2 As shown, a film layer stacking structure 2 may be formed on the substrate, and the film layer stacking structure 2 may include a single film layer or a multi-layer film layer, which is not particularly limited herein. In one embodiment, the film layer stacking structure 2 may include a multi-layer film layer, for example, it may include overlapping support layers and sacrificial layers, for example, it may include a first sacrificial layer 201, a first support layer 202, a second sacrificial layer 203, and a second support layer 204 stacked in sequence, wherein the first sacrificial layer 201 may be formed on the surface of the bottom support layer 6.

[0068] The first sacrificial layer 201, the first supporting layer 202, the second sacrificial layer 203 and the second supporting layer 204 can be formed on the surface of the bottom supporting layer 6 by vacuum evaporation or magnetron sputtering. Of course, the first sacrificial layer 201, the first supporting layer 202, the second sacrificial layer 203 and the second supporting layer 204 can also be formed in a stacked manner by other methods, which are not specifically limited here.

[0069] The first sacrificial layer 201 may be formed on the surface of the bottom support layer 6, and its material may be SiO 2 ; The first supporting layer 202 may be a thin film formed on the side of the first sacrificial layer 201 away from the substrate, and its material may be silicon nitride or SiCN; the second sacrificial layer 203 may be formed on the side of the first supporting layer 202 away from the first sacrificial layer 201, and may be made of the same material and have the same thickness as the first sacrificial layer 201; the second supporting layer 204 may be formed on the side of the second sacrificial layer 203 away from the first supporting layer 202, and may be made of the same material as the first supporting layer 202. The thickness of the first supporting layer 202 and the second supporting layer 204 may be the same or different, and no special limitation is made herein.

[0070] In step S120 , the film layer stack structure is etched to form a first region including a through hole exposing the substrate and a second region including a hole segment not exposing the substrate.

[0071] like Figure 2 As shown, the film stack structure 2 may have a first region A and a second region B arranged side by side, and the first region A and the second region B may be arranged adjacent to each other. There may be two second regions B, and the two second regions B may be located on both sides of the first region A, for example, the first region A may be the central region of the film stack structure 2, and the second region B may be the edge region of the film stack structure 2.

[0072] The film layer stack structure 2 can be etched to form a capacitor hole for depositing capacitors. The capacitor hole can extend in a direction perpendicular to the substrate, and its cross-sectional shape can be circular or rectangular, etc., or an irregular shape. No special limitation is made to the shape of the capacitor hole.

[0073] During the etching process, due to the limitation of the etching process, capacitor holes with different etching depths appear in different regions of the film layer stack structure 2, that is, a through hole 211 exposing the substrate can be formed in the first region A, and a hole segment 221 not exposing the substrate can be formed in the second region B. In the embodiment of the manufacturing method disclosed in the present invention, the structure after completing step S120 is as follows Figure 3 shown.

[0074] In one embodiment, there may be a plurality of through holes 211, and the plurality of through holes 211 may be distributed in an array. At the same time, the substrate opposite to the first area A may include a plurality of storage node contact plugs 11 distributed in an array. It should be noted that the number of through holes 211 may be equal to the number of storage node contact plugs 11, and each through hole 211 can expose each storage node contact plug 11 one by one.

[0075] In one embodiment of the present disclosure, Figure 4 As shown, step S120 may include steps S1201 to S1205, wherein:

[0076] Step S1201 , forming a mask material layer on a side of the film layer stack structure facing away from the substrate.

[0077] The mask material layer can be formed on the side of the film stack structure 2 away from the substrate by chemical vapor deposition, vacuum evaporation, atomic layer deposition or other methods. The mask material layer can have multiple layers or a single layer structure, and its material can be a polymer, SiO 2 , at least one of SiN, poly and SiCN. Of course, it can also be other materials, which are not listed here one by one.

[0078] In one embodiment, if Figure 5 As shown, the mask material layer 3 may be a multilayer, which may include a polymer layer 31, an oxide layer 32 and a hard mask layer, wherein the polymer layer 31 may be formed on the surface of the film layer stacking structure 2 away from the substrate, and the oxide layer 32 may be located between the hard mask layer and the polymer layer 31. The polymer layer 31 may be formed on the surface of the film layer stacking structure 2 away from the substrate by a chemical vapor deposition process, the oxide layer 32 may be formed on the surface of the polymer layer 31 away from the film layer stacking structure 2 by a vacuum evaporation process, and the hard mask layer may be formed on the surface of the oxide layer 32 away from the polymer layer 31 by an atomic layer deposition process.

[0079] Step S1202, forming a photoresist layer on the surface of the mask material layer facing away from the substrate.

[0080] The photoresist layer 4 can be formed on the surface of the mask material layer 3 facing away from the substrate by spin coating or other methods. The material of the photoresist layer 4 can be positive photoresist or negative photoresist, which is not particularly limited here.

[0081] Step S1203, exposing and developing the photoresist layer to form a plurality of development areas, each of which exposes the mask material layer.

[0082] The photoresist layer 4 may be exposed using a mask, and the pattern of the mask may match the pattern required by the film layer stack structure 2. Subsequently, the exposed photoresist layer 4 may be developed to form a plurality of development areas, each of which may expose the mask material layer 3, and the pattern of the development area may be the same as the pattern required by the film layer stack structure 2, and the width of the development area may be the same as the size of the required capacitor hole. In the embodiment of the manufacturing method disclosed in the present invention, the structure after completing step S1203 is as follows: Figure 5 shown.

[0083] Step S1204: etching the mask material layer in the developing area to form a mask pattern.

[0084] The mask material layer 3 can be etched in the developing area by a plasma etching process, and the etched area can expose the film layer stacking structure 2, thereby forming a desired mask pattern on the mask material layer 3. It should be noted that when the mask material layer 3 is a single-layer structure, a single etching process can be used to form the mask pattern, and when the mask material layer 3 is a multi-layer structure, each film layer can be etched in layers, that is, one etching process can be used to etch one layer, and multiple etching processes can be used to etch through the mask layer to form a mask pattern.

[0085] It should be noted that after completing the above etching process, the photoresist layer 4 can be removed by cleaning with a cleaning solution or by ashing or other processes, so that the mask material layer 3 is no longer covered by the photoresist layer 4, and the formed mask layer is exposed to obtain a hard mask structure. Figure 6 The structure after step S1204 in the embodiment of the manufacturing method disclosed herein is shown.

[0086] Step S1205, performing anisotropic etching on the film layer stack structure according to the mask pattern, and using the substrate as an etching stop layer, forming the through hole in the film layer stack structure located in the first area, and forming the hole segment in the film layer stack structure located in the second area.

[0087] The film stack structure 2 can be anisotropically etched according to the mask pattern. For example, the film stack structure 2 can be etched in the development area of ​​the mask pattern by a dry etching process, and the substrate is used as an etching stop layer to form multiple capacitor holes in the film stack structure 2. In this process, due to the limitation of the manufacturing process, the etching depths in different areas of the film stack structure 2 are different, so that multiple through holes 211 are formed in the film stack structure 2 located in the first area A, and one or more hole segments 221 are formed in the film stack structure 2 located in the second area B, and the open end of each hole segment 221 facing away from the substrate can be flush with the open end of the through hole 211 facing away from the substrate, and its end close to the substrate can be located in any sacrificial layer. For example, its end close to the substrate is located in the first sacrificial layer 201.

[0088] When the first region A is the central region of the film stack structure 2, and the second region B is the edge region of the film stack structure 2, a plurality of hole segments 221 that do not expose the substrate may be formed at the edge of the film stack structure 2, and a plurality of through holes 211 distributed in an array may be formed at the center of the film stack structure 2. For example, each through hole 211 may be arranged in one-to-one correspondence with each storage node contact plug 11 located in the first region A, and the open end of each through hole 211 close to the substrate side may contact the surface of the storage node contact plug 11 corresponding thereto, so that after a capacitor is formed in the through hole 211, the charge in the capacitor is stored through the storage node contact plug 11. Figure 3 The structure after step S1205 in the embodiment of the manufacturing method disclosed herein is shown.

[0089] In step S130 , the second region is pattern-etched to remove the film layer stack structure in the second region.

[0090] The second region B can be patterned and etched by a photolithography process to remove the film stack structure 2 in the second region B, and only retain the film stack structure of the first region A, so as to prevent the formation of a capacitor in the hole section 221, and to prevent the capacitor from being suspended after the sacrificial layer is removed, and the stored electricity cannot be stored in the storage node contact plug 11, resulting in capacitor failure; at the same time, it also avoids the collapse of the capacitor due to suspension, and prevents short circuits between adjacent capacitors. In the embodiment of the manufacturing method disclosed in the present invention, the structure after completing step S130 is as follows: Figure 7 shown.

[0091] In one embodiment of the present disclosure, Figure 8 As shown, step S130 may include steps S1301 to S1303, wherein:

[0092] Step S1301, forming a photoresist layer on the surface of the first region.

[0093] like Fig. 9As shown, a photoresist layer 4 can be formed on the surface of the hard mask layer 33 away from the substrate by spin coating, coating, chemical vapor deposition or other methods, and the photoresist layer 4 can be arranged opposite to the first area A of the film layer stack structure 2 to prevent the first area A from being etched. The material of the photoresist layer 4 can be positive photoresist or negative photoresist, which is not particularly limited here.

[0094] Step S1302 is to etch the film layer stack structure in the second region and the substrate facing the second region.

[0095] The film stack structure 2 and the substrate may be etched in the second region B by a plasma etching process to remove the hole segments 221. For example, the film stack structure 2 and the substrate may be etched by an etching gas. For example, the film stack structure 2 in the second region B may be dry-etched in a direction perpendicular to the film stack structure 2, and the film stack structure 2 in the second region B may be removed by chemically reacting the etching gas with the material of the film stack structure 2. The etching gas may be a single gas or a mixture of multiple gases, which is not particularly limited herein.

[0096] For example, the etching gas may include at least one of carbon tetrafluoride gas or sulfur hexafluoride gas. For example, it may be carbon tetrafluoride gas, sulfur hexafluoride gas, or a mixture of carbon tetrafluoride gas and sulfur hexafluoride gas. Of course, the etching gas may also be other gases that can be used to etch the film layer stack structure 2 and the substrate, which are not listed one by one here.

[0097] Step S1303, removing the photoresist layer.

[0098] After the above etching process is completed, the photoresist layer 4 can be removed by cleaning with a cleaning solution or by ashing or other processes, so that the first area A is no longer covered by the photoresist layer 4, and the hard mask layer 33 is removed to expose the formed film layer stacking structure 2. Fig.10 The structure after completing step S1303 of the manufacturing method disclosed in the present invention is shown.

[0099] like Figure 1 As shown, the manufacturing method of the present disclosure may also include:

[0100] Step S140: forming a capacitor array in each of the through holes.

[0101] The capacitor array can be formed in each through hole 211 of the first area A by vacuum evaporation, magnetron sputtering, chemical vapor deposition or atomic layer deposition, such as Fig.11As shown, the capacitor array may include a plurality of spaced-apart columnar capacitors 5 and a conductive layer 7 covering the surface of each capacitor array. Each columnar capacitor 5 may be respectively contacted and connected to each storage node contact plug 11. When in use, a plurality of capacitors may be charged and discharged simultaneously, thereby increasing the capacitance. The conductive layer 7 may be in contact with the capacitor array to electrically lead out the capacitor.

[0102] Each columnar capacitor 5 may include a lower electrode layer 51, a capacitor dielectric layer 52 and an upper electrode layer 53, wherein the lower electrode layer 51 is in a strip shape, which may be formed on the hole wall and bottom of the through hole 211, and may be located on the side of the storage node contact plug 11 away from the substrate, the lower electrode layer 51 may be in contact with the storage node contact plug 11, and may extend in a direction perpendicular to the storage node contact plug 11 to the side of the storage node contact plug 11 away from the substrate, so as to form a columnar capacitor 5. The capacitor dielectric layer 52 is located between the lower electrode layer 51 and the upper electrode layer 53, and may form a double-sided capacitor, so as to increase the capacitance. Each supporting layer may be coated on the periphery of the lower electrode layer 51, and may provide lateral support to the lower electrode layer 51, increase the lateral stability of the lower electrode layer 51, and prevent the lower electrode layer 51 from lateral deformation.

[0103] In one embodiment of the present disclosure, a capacitor array is formed in each of the through holes 211, that is, step S140 may include steps S1401 to S1404, such as Fig.12 As shown, where:

[0104] Step S1401 , forming a lower electrode layer in each of the through holes, wherein the lower electrode layer is in contact with the storage node contact plug.

[0105] The through hole 211 can be used as a capacitor hole, and a lower electrode layer 51 can be formed on the side wall of the through hole 211. Specifically, a lower electrode layer 51 that conforms to the bottom and side wall surfaces of the capacitor hole can be formed in the capacitor hole. For the convenience of the process, the lower electrode layer 51 can be formed in the capacitor hole and on the top surface at the same time. Then, the lower electrode layer 51 on the top surface of the capacitor hole can be removed, and only the lower electrode layer 51 on the bottom and side wall is retained. The structure of the finally formed lower electrode layer 51 is as follows: Fig.13 In addition, the lower electrode layer 51 can be in contact with the storage node contact plug 11 through the capacitor hole, so that the electricity stored in the lower electrode layer 51 is input to the storage dielectric contact plug, thereby realizing capacitor storage.

[0106] For example, a chemical vapor deposition process can be used to form a lower electrode layer 51 in the capacitor hole. Of course, the lower electrode layer 51 can also be formed by other processes. The material of the lower electrode layer 51 can be titanium nitride. Of course, it can also be other materials that can be used as electrodes. No special restrictions are made on the material and formation process of the lower electrode layer 51.

[0107] Step S1402, removing each of the sacrificial layers.

[0108] like Fig.14 As shown, after forming the lower electrode layer 51, the sacrificial layers in the first area A can be removed, while the supporting layers are retained, which can not only increase the capacitor storage density, but also support the lower electrode layer 51 to prevent the lower electrode layer 51 from deforming outward and reduce the risk of short circuit.

[0109] Step S1403, forming a capacitor dielectric layer on the surface of the structure formed by the lower electrode layer and the support layer.

[0110] like Fig.15 As shown, a capacitor dielectric layer 52 can be formed on the lower electrode layer 51 in the capacitor hole of the first region A. For example, the capacitor dielectric layer 52 can be a thin film formed on the surface of the lower electrode layer 51. The capacitor dielectric layer 52 can be formed by processes such as vacuum evaporation or magnetron sputtering. Of course, the capacitor dielectric layer 52 can also be formed by other processes, which are not listed here. The capacitor dielectric layer 52 can be a single-layer film structure composed of the same material, or a mixed film layer structure composed of film layers of different materials. For example, it may include a material with a higher dielectric constant, for example, it can be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide or a mixture thereof. Of course, it can also be other materials, which are not listed here.

[0111] Step S1404: forming an upper electrode layer on a surface of the capacitor dielectric layer away from the lower electrode layer.

[0112] The upper electrode layer 53 can be formed on the outer surface of the capacitor dielectric layer 52 by chemical vapor deposition process. Of course, the upper electrode layer 53 can also be formed by other processes, which are not specifically limited here. The material of the upper electrode layer 53 can be titanium nitride, and of course, it can also be other materials, which are not listed here one by one. In the embodiment of the manufacturing method disclosed in the present invention, the structure after completing step S1404 is as follows Fig.15 shown.

[0113] Step S1405, forming a conductive layer covering the upper electrode layer, wherein the conductive layer fills the capacitor hole and the gap between two adjacent capacitors.

[0114] like Fig.11As shown, a conductive layer 7 can be formed on the surface of the upper electrode layer 53 by vacuum evaporation process, so that the charge is fully in contact with the upper electrode layer 53, which helps to improve the capacitor charging efficiency. The conductive layer 7 can cover the surface of the upper electrode layer 53 and can fill the through hole 211 and the gap between two adjacent capacitors, which can not only lead out the capacitors electrically, but also enhance the stability of each capacitor in the capacitor array. The conductive layer 7 can be composed of silicon material, metal material or metal compound, for example, it can be silicon, germanium silicon, tungsten, titanium silicide, titanium oxide or tungsten oxide, etc., without special limitation here.

[0115] The present disclosure also provides a semiconductor device, which can be manufactured by the method for manufacturing a semiconductor device of any of the above embodiments.

[0116] The specific details and manufacturing process of each part of the above-mentioned semiconductor device have been described in detail in the manufacturing method of the corresponding semiconductor device, so they are not repeated here. The semiconductor device can be a memory chip, for example, DRAM (Dynamic Random Access Memory), of course, it can also be other semiconductor devices, which are not listed here one by one. The beneficial effects of the semiconductor device can refer to the beneficial effects of the above-mentioned hard mask structure, which are not repeated here.

[0117] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, and forming a film layer stacking structure on the substrate; Etching the film layer stack structure to form a first region including a through hole exposing the substrate and a second region including a hole segment not exposing the substrate; Graphically etching the second region to remove the film layer stack structure in the second region; The step of patterning and etching the second region to remove the film layer stack structure in the second region includes: forming a photoresist layer on the surface of the first region; Etching the film layer stack structure in the second region and the substrate facing the second region; The photoresist layer is removed.

2. The manufacturing method according to claim 1, characterized in that: The etching of the film layer stack structure to form a first region including a through hole exposing the substrate and a second region including a hole segment not exposing the substrate comprises: forming a mask material layer on a side of the film layer stack structure facing away from the substrate; forming a photoresist layer on a surface of the mask material layer facing away from the substrate; Exposing and developing the photoresist layer to form a plurality of development areas, each of the development areas exposing the mask material layer; etching the mask material layer in the developing area to form a mask pattern; The film layer stack structure is anisotropically etched according to the mask pattern, and the substrate is used as an etching stop layer to form the through hole in the film layer stack structure located in the first area and the hole segment in the film layer stack structure located in the second area.

3. The manufacturing method according to claim 1, characterized in that: The etching of the film layer stack structure of the second region and the substrate facing the second region comprises: The film layer stack structure in the second region is dry-etched using an etching gas along a direction perpendicular to the film layer stack structure.

4. The manufacturing method according to claim 3, characterized in that: The etching gas includes at least one of carbon tetrafluoride gas and sulfur hexafluoride gas.

5. The manufacturing method according to claim 1, characterized in that: The first region is a central region of the film layer stacking structure, and the second region is an edge region of the film layer stacking structure.

6. The manufacturing method according to any one of claims 1 to 5, characterized in that: There are a plurality of through holes, and the substrate facing the first region includes a plurality of storage node contact plugs, and each of the through holes can expose each of the storage node contact plugs in a one-to-one correspondence.

7. The manufacturing method according to claim 6, characterized in that: The manufacturing method further comprises: A capacitor array is formed in each of the through holes.

8. The manufacturing method according to claim 7, characterized in that: The film layer stack structure includes a support layer and a sacrificial layer overlapped and arranged in a direction perpendicular to the substrate, and the capacitor array is formed in each of the through holes, including: forming a lower electrode layer in each of the through holes, wherein the lower electrode layer is in contact with the storage node contact plug; removing each of the sacrificial layers; forming a capacitor dielectric layer on the surface of the structure formed by the lower electrode layer and the support layer; forming an upper electrode layer on a surface of the capacitor dielectric layer away from the lower electrode layer; A conductive layer covering the upper electrode layer is formed, and the conductive layer fills the through hole and the gap between two adjacent capacitors.

9. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 8.

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