semiconductor devices

Abstract

An embodiment provides a semiconductor device capable of connecting multiple chips while reducing its area when viewed from above. The semiconductor device includes: a first chip having a first electrode and a second electrode provided on a first surface, and a third electrode provided on a second surface opposite to the first surface; a second chip having a fourth electrode and a fifth electrode provided on a third surface, and a sixth electrode provided on a fourth surface opposite to the third surface, the second chip being arranged such that the third surface faces the first surface; a first connector arranged between the first electrode and the fourth electrode and connected to the first and fourth electrodes; and a second connector arranged between the second electrode and the fifth electrode and connected to the second and fifth electrodes.

Description

[0001] Related applications

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2020-154924 (filing date: September 15, 2020), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a semiconductor device. Background Art

[0004] In order to output a large current while suppressing on-resistance, power semiconductor chips such as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) are sometimes connected in parallel. Summary of the Invention

[0005] Embodiments provide a semiconductor device capable of connecting a plurality of chips while reducing the area in a plan view.

[0006] A semiconductor device of an embodiment includes: a first chip, having a first electrode and a second electrode on a first surface, and a third electrode on a second surface located opposite to the first surface; a second chip, having a fourth electrode and a fifth electrode on a third surface, and a sixth electrode on a fourth surface located opposite to the third surface, the second chip being arranged with the third surface facing the first surface; a first connector arranged between the first chip and the second chip and connected to the first electrode and the fourth electrode; and a second connector arranged between the first chip and the second chip and connected to the second electrode and the fifth electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a plan view showing the semiconductor device according to the first embodiment.

[0008] Figure 2 This is a plan view showing a substrate, first leads, second leads, and a first chip of the semiconductor device according to the first embodiment.

[0009] Figure 3 This is a plan view showing a substrate, first leads, second leads, a first chip, a first connector, and a second connector of the semiconductor device according to the first embodiment.

[0010] Figure 4 yes Figure 1 Cross-sectional view on line A-A'.

[0011] Figure 5 yes Figure 1 Cross-sectional view on line BB'.

[0012] Figure 6 (a) is Figure 1 Cross-sectional view on line C-C'. Figure 6 (b) is a plan view showing the lower surface of the first chip and the upper surface of the second chip of the semiconductor device according to the first embodiment.

[0013] Figure 7 (a) is a plan view showing a method for manufacturing a semiconductor device according to a first embodiment. Figure 7 (b) is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0014] Figure 8 (a) is a plan view showing a method for manufacturing a semiconductor device according to a first embodiment. Figure 8 (b) is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0015] Figure 9 (a) is a plan view showing a method for manufacturing a semiconductor device according to a first embodiment. Figure 9 (b) is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0016] Figure 10 (a) is a plan view showing a method for manufacturing a semiconductor device according to a first embodiment. Figure 10 (b) is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0017] Figure 11 (a) is a plan view showing a method for manufacturing a semiconductor device according to a first embodiment. Figure 11 (b) is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0018] Figure 12 (a) is a plan view showing a first connector of a semiconductor device according to a second embodiment. Figure 12 (b) is Figure 12 (a) Cross-sectional view on line D-D'.

[0019] Figure 13 It is a cross-sectional view showing a semiconductor device according to a second embodiment.

[0020] Figure 14 It is a cross-sectional view showing a semiconductor device according to a second embodiment.

[0021] Figure 15(a) is a plan view showing a first connector in a semiconductor device according to a third embodiment. Figure 15 (b) is Figure 15 (a) is a cross-sectional view on the EE' line.

[0022] Figure 16 It is a cross-sectional view showing a semiconductor device according to a fourth embodiment.

[0023] Figure 17 It is a cross-sectional view showing a semiconductor device according to a fifth embodiment.

[0024] Figure 18 It is a cross-sectional view showing a semiconductor device according to a sixth embodiment.

[0025] Figure 19 (a) is a cross-sectional view showing a modified example of the first connector, Figure 19 (b) is a cross-sectional view showing a modified example of the first connector.

[0026] Figure 20 (a) and (b) are plan views showing modified examples of the first chip and the second chip. DETAILED DESCRIPTION

[0027] <First embodiment>

[0028] First, the first embodiment will be described.

[0029] Figure 1 1 is a plan view showing the semiconductor device according to this embodiment.

[0030] Figure 2 This is a plan view showing a substrate, first leads, second leads, and a first chip of the semiconductor device according to this embodiment.

[0031] Figure 3 This is a plan view showing a substrate, first leads, second leads, a first chip, a first connector, and a second connector of the semiconductor device according to the present embodiment.

[0032] Figure 4 yes Figure 1 Cross-sectional view on line A-A'.

[0033] Figure 5 yes Figure 1 Cross-sectional view on line BB'.

[0034] Figure 6 (a) is Figure 1 Cross-sectional view on line C-C'. Figure 6 (b) is a plan view showing the lower surface of the first chip and the upper surface of the second chip of the semiconductor device of this embodiment.

[0035] Reference Figure 1 as well as Figure 5 The semiconductor device 100 of this embodiment is briefly described. The semiconductor device 100 includes a substrate 110, a first lead 120, a second lead 130, a first chip 140, a second chip 150, a first connector 160, a second connector 170, a third connector 180, and a resin member 190. Figure 1 In FIG. 1 , in order to facilitate understanding of the internal structure of the semiconductor device 100 , the resin member 190 is indicated by a two-dot chain line.

[0036] The following describes each component of the semiconductor device 100 in detail. For easier understanding, an XYZ orthogonal coordinate system is used. The direction from the first chip 140 toward the second chip 150 is referred to as the "Z direction." Furthermore, a direction perpendicular to the Z direction is referred to as the "X direction." Furthermore, a direction perpendicular to both the Z and X directions is referred to as the "Y direction." Furthermore, the Z direction is referred to as the "upward direction." The direction opposite to the upward direction is referred to as the "downward direction." The upward and downward directions are independent of the direction of gravity.

[0037] The substrate 110 is made of, for example, a metal material. Figure 2 As shown, the substrate 110 has a main body 111 and a plurality of extensions 112 connected to the main body 111 and extending along the Y direction. The main body 111 is substantially rectangular in shape when viewed from above. Figure 4 As shown, the upper surface 111a and the lower surface 111b of the main body 111 are flat surfaces and are substantially parallel to the directions X and Y. However, the shape of the substrate is not limited to the above.

[0038] The first lead 120 is made of, for example, a metal material. Figure 2 As shown, first lead 120 is separated from substrate 110. First lead 120 is positioned adjacent to substrate 110 in the Y direction. First lead 120 is flat. First lead 120 includes a first extension 121 extending in the X direction and a plurality of second extensions 122 connected to first extension 121 and extending in the Y direction. However, the position and shape of the first lead are not limited to those described above.

[0039] Second lead 130 is made of the same material as first lead 120. Second lead 130 is separate from substrate 110 and first lead 120. Second lead 130 is positioned adjacent to substrate 110 in the Y direction and adjacent to first lead 120 in the X direction. Second lead 130 is flat. Second lead 130 includes a first extension 131 extending in the X direction and a second extension 132 connected to first extension 131 and extending in the Y direction. However, the position and shape of the second lead are not limited to those described above.

[0040] The first chip 140 is arranged on the substrate 110. In this embodiment, the first chip 140 is a MOSFET. The withstand voltage of the first chip 140 is not particularly limited, for example, it is above 100V. The shape of the first chip 140 is flat. In this embodiment, the shape of the first chip 140 when viewed from above is approximately square. However, the shape of the first chip when viewed from above is not limited to the above. Figure 5 As shown, the surface of the first chip 140 includes an upper surface (first surface) 140 a and a lower surface (second surface) 140 b located on the opposite side of the upper surface 140 a .

[0041] A source electrode (first electrode) 141 and a gate electrode (second electrode) 142 are provided on the upper surface 140a. A drain electrode (third electrode) 143 is provided on the lower surface 140b. The drain electrode 143 is connected to the substrate 110 via a conductive bonding member 143a such as solder.

[0042] The source electrode 141, gate electrode 142, and drain electrode 143 are preferably each made of a metal material, such as copper (Cu), having a higher thermal conductivity than the bonding members 141a, 142a, and 143a described later. The thickness of the source electrode 141, gate electrode 142, and drain electrode 143 is preferably 5 μm or more and 20 μm or less. However, the materials and thicknesses of the source, gate, and drain electrodes are not limited to those described above.

[0043] like Figure 2 As shown, the source electrode 141, when viewed from above, has a shape similar to a quadrilateral with one corner cut off and the other corners rounded. The gate electrode 142, when viewed from above, has a generally rectangular shape. The gate electrode 142 is separated from the source electrode 141 and is located in the region where the corner of the source electrode 141 is cut off. However, the positions and shapes of the source and gate electrodes are not limited to those described above.

[0044] In this embodiment, the second chip 150 is a MOSFET. The withstand voltage of the second chip 150 is not particularly limited, and is, for example, 100V or more. The shape of the second chip 150 is a flat plate. The shape of the second chip 150 when viewed from above is as follows: Figure 6As shown in (b), in this embodiment, it is a substantially square shape. However, the shape of the second chip when viewed from above is not limited to the above. The second chip 150 is arranged so as to face the first chip 140. The surface of the second chip 150 includes a lower surface (third surface) 150a facing the upper surface 140a of the first chip 140, and an upper surface (fourth surface) 150b located on the opposite side of the lower surface 150a.

[0045] A source electrode (fourth electrode) 151 and a gate electrode (fifth electrode) 152 are provided on the lower surface 150a. Figure 5 As shown in FIG. 1 , a drain electrode (sixth electrode) 153 is provided on the upper surface 150b. The source electrode 151 is opposite to the source electrode 141 of the first chip 140. Figure 6 As shown in (b), the shape of the source electrode 151 is substantially the same as the shape of the source electrode 141 of the first chip 140. The area of ​​the source electrode 151 is substantially the same as the area of ​​the source electrode 141 of the first chip 140. Figure 5 As shown, the gate electrode 152 is opposite to the gate electrode 142 of the first chip 140. Figure 6 As shown in (b), the shape of the gate electrode 152 is substantially the same as the shape of the gate electrode 142 of the first chip 140. The area of ​​the gate electrode 152 is substantially the same as the area of ​​the gate electrode 142 of the first chip 140. Figure 5 As shown, the first chip 140 and the second chip 150 are generally symmetrical with respect to a plane P, which passes through the center of the gap between the first chip 140 and the second chip 150 and is parallel to the X and Y directions. However, the positions and shapes of the source and gate electrodes are not limited to the above. For example, the second chip and the first chip may also be asymmetrical with respect to plane P.

[0046] like Figure 5 As shown, the source electrode 151, gate electrode 152, and drain electrode 153 are preferably each made of a metal material such as copper (Cu) that has a higher thermal conductivity than the bonding members 151a, 152a, and 153a described later. Furthermore, the film thickness of the source electrode 151, gate electrode 152, and drain electrode 153 is preferably not less than 5 μm and not more than 20 μm. However, the materials and film thicknesses of the source electrode, gate electrode, and drain electrode are not limited to those described above.

[0047] like Figure 3 as well as Figure 4 As shown, the first connector 160 is connected to the source electrode 141 of the first chip 140, the source electrode 151 of the second chip 150, and the first lead 120. The first connector 160 is made of a metal material with high thermal conductivity, such as copper (Cu).

[0048] In this embodiment, the first connector 160 has: a first front end portion 161, which is arranged between the source electrode 141 of the first chip 140 and the source electrode 151 of the second chip 150; a first base end portion 162, which is arranged on the first lead 120; and a first middle portion 163, which is located between the first front end portion 161 and the first base end portion 162.

[0049] The first tip portion 161 is substantially flat and is connected to the source electrode 141 of the first chip 140 via a conductive bonding member 141a such as solder. Furthermore, the first tip portion 161 is connected to the source electrode 151 of the second chip 150 via a conductive bonding member 151a such as solder.

[0050] The first base end portion 162 is substantially in the shape of a flat plate and is connected to the first lead 120 via a conductive bonding member 123 such as solder.

[0051] The first intermediate portion 163 is L-shaped. Specifically, the first intermediate portion 163 includes a first portion 163a extending in the Y direction from the Y-direction end of the first distal end portion 161, and a second portion 163b extending in the Z direction, connected to the first portion 163a and the upper end of the first proximal end portion 162. However, the shape of the first connector is not limited to the above.

[0052] like Figure 3 as well as Figure 5 As shown, the second connector 170 is connected to the gate electrode 142 of the first chip 140, the gate electrode 152 of the second chip 150, and the second lead 130. The second connector 170 is made of the same material as the first connector 160.

[0053] The second connector 170 has: a second front end portion 171, which is arranged between the gate electrode 142 of the first chip 140 and the gate electrode 152 of the second chip 150; a second base end portion 172, which is arranged on the second lead 130; and a second middle portion 173, which is located between the second front end portion 171 and the second base end portion 172.

[0054] The second tip portion 171 is substantially flat and is connected to the gate electrode 142 of the first chip 140 via a conductive bonding member 142a such as solder. The second tip portion 171 is also connected to the gate electrode 152 of the second chip 150 via a conductive bonding member 152a such as solder.

[0055] The second base end portion 172 is substantially in the shape of a flat plate and is connected to the second lead 130 via a conductive bonding member 133 such as solder.

[0056] The second intermediate portion 173 is L-shaped. Specifically, the second intermediate portion 173 includes a first portion 173a extending in the Y direction from the Y-direction end of the first distal end portion 161, and a second portion 173b connecting the first portion 173a and the upper end of the second proximal end portion 172 and extending in the Z direction. However, the shape of the second connector is not limited to the above.

[0057] like Figure 6 As shown in FIG. 1 , the third connector 180 is connected to the drain electrode 153 of the second chip 150 and the substrate 110 . The third connector 180 is made of the same material as the first connector 160 .

[0058] The third connector 180 includes a third front end portion 181 disposed on the drain electrode 153 of the second chip 150 , a third base end portion 182 disposed on the substrate 110 , and a third intermediate portion 183 located between the third front end portion 181 and the third base end portion 182 .

[0059] The third tip portion 181 is substantially in the shape of a flat plate and is connected to the drain electrode 153 of the second chip 150 via a conductive bonding member 153 a such as solder.

[0060] The third base end portion 182 is substantially in the shape of a flat plate and is connected to the substrate 110 via a conductive bonding member 113 such as solder.

[0061] The third intermediate portion 183 is L-shaped and includes a first portion 183a extending in the X direction from the X-direction end of the third distal end portion 181 and a second portion 183b connected to the first portion 183a and the upper end of the third base end portion 182 and extending in the Z direction.

[0062] like Figures 4 to 6 As shown in FIG. 1 ( a ), the resin member 190 seals the first chip 140 , the second chip 150 , the first connector 160 , the second connector 170 , and the third connector 180 .

[0063] like Figure 1As shown, resin member 190 covers a portion of main body 111 of substrate 110 and each extension portion 112. Resin member 190 also covers a portion of first extension portion 121 and each second extension portion 122 of first lead 120. Resin member 190 also covers a portion of first extension portion 131 and second extension portion 132 of second lead 130. Resin member 190 exposes the remaining portions of each extension portion 112 of substrate 110, the remaining portions of each second extension portion 122 of first lead 120, and the remaining portions of each second extension portion 132 of second lead 130. Resin member 190 is made of a resin material such as, for example, a thermosetting resin.

[0064] Next, a method for manufacturing the semiconductor device 100 according to this embodiment will be described.

[0065] Figure 7 (a) is a top view showing a method for manufacturing a semiconductor device according to this embodiment. Figure 7 (b) is a cross-sectional view showing the method for manufacturing the semiconductor device according to this embodiment.

[0066] Figure 8 (a) is a top view showing a method for manufacturing a semiconductor device according to this embodiment. Figure 8 (b) is a cross-sectional view showing the method for manufacturing the semiconductor device according to this embodiment.

[0067] Figure 9 (a) is a top view showing a method for manufacturing a semiconductor device according to this embodiment. Figure 9 (b) is a cross-sectional view showing the method for manufacturing the semiconductor device according to this embodiment.

[0068] Figure 10 (a) is a top view showing a method for manufacturing a semiconductor device according to this embodiment. Figure 10 (b) is a cross-sectional view showing the method for manufacturing the semiconductor device according to this embodiment.

[0069] Figure 11 (a) is a top view showing a method for manufacturing a semiconductor device according to this embodiment. Figure 11 (b) is a cross-sectional view showing the method for manufacturing the semiconductor device according to this embodiment.

[0070] First, if Figure 7 As shown in (b), uncured solder 143aF is placed on the substrate 110. Next, the first chip 140 is placed so that the drain electrode 143 faces the substrate 110.

[0071] Next, uncured solder 141aF is placed on the source electrode 141 of the first chip 140, and uncured solder 142aF is placed on the gate electrode 142 of the first chip 140. Figure 7 As shown in FIG. 1 ( a ), uncured solder 123F is placed on the first lead 120 , and uncured solder 133F is placed on the second lead 130 .

[0072] Next, if Figure 8 (a) and Figure 8 As shown in (b), the first connector 160 is arranged on the first lead 120 and the source electrode 141 of the first chip 140 , and the second connector 170 is arranged on the second lead 130 and the gate electrode 142 of the first chip 140 .

[0073] Next, if Figure 8 As shown in FIG. 1 , uncured solder 151 aF is placed on the first distal end portion 161 of the first connector 160 , and uncured solder 152 aF is placed on the second distal end portion 171 of the second connector 170 .

[0074] Next, if Figure 9 As shown in (b), the second chip 150 is arranged on the first connector 160 and the second connector 170 so that the source electrode 151 faces the source electrode 141 of the first chip 140 and the gate electrode 152 faces the gate electrode 142 of the first chip 140 .

[0075] Next, if Figure 9 As shown in FIG. 1 ( a ), uncured solder 153 aF is placed on the drain electrode 153 of the second chip 150 . Also, uncured solder 113F is placed on the substrate 110 .

[0076] Next, if Figure 10 (a) and Figure 10 As shown in (b), the third connector 180 is configured on the second chip 150.

[0077] Next, the solders 141aF, 142aF, 143aF, 151aF, 152aF, 153aF, 113F, 123F, and 133F are solidified, thereby forming the bonding members 141a, 142a, 143a, 151a, 152a, 153a, 113, 123, and 133.

[0078] Next, if Figure 11 (a) and Figure 11As shown in FIG. 1 ( b ), the first chip 140 , the second chip 150 , the first connector 160 , the second connector 170 , and the third connector 180 are sealed with the resin member 190 .

[0079] Next, the effects of this embodiment will be described.

[0080] The first chip 140 and the second chip 150 are connected in parallel via the substrate 110, the first connector 160, the second connector 170, and the third connector 180. This allows the on-resistance of the semiconductor device 100 to be suppressed while increasing the current that can be output by the semiconductor device 100. In particular, in this embodiment, the withstand voltage of the first chip 140 and the second chip 150 is 100V or higher. The higher the withstand voltage of each chip 140 and 150, the higher the proportion of the on-resistance of the transistor to the total on-resistance of the semiconductor device 100. Therefore, the higher the withstand voltage of each chip 140 and 150, the more significant the effect of suppressing the on-resistance based on the parallel connection.

[0081] Furthermore, the first chip 140 and the second chip 150 are stacked. Therefore, it is possible to connect the first chip 140 and the second chip 150 while suppressing an increase in the area of ​​the semiconductor device 100 in a plan view.

[0082] On the other hand, because the first chip 140 and the second chip 150 are stacked, heat generated in the first chip 140 and the second chip 150 becomes difficult to dissipate from the space between them. The higher the temperature of the first chip 140 and the second chip 150, the lower the on-state voltage of the first chip 140 and the second chip 150. The lower the on-state voltage of the first chip 140 and the second chip 150, the higher the current flowing through the first chip 140 and the second chip 150. The higher the current flowing through the first chip 140 and the second chip 150, the higher the temperature of the first chip 140 and the second chip 150. This makes it difficult to dissipate heat generated in the first chip 140 and the second chip 150, potentially causing thermal runaway of the semiconductor device 100. In this embodiment, the first connector 160 and the second connector 170 enable efficient heat dissipation of heat generated in the first chip 140 and the second chip 150. This prevents thermal runaway of the first chip 140 and the second chip 150.

[0083] Furthermore, in this embodiment, the source electrodes 141, 151 and the gate electrodes 142, 152 are formed of a metal material with a higher thermal conductivity than the bonding members 141a, 151a, 142a, and 152a, and have a film thickness of 5 μm to 20 μm. Therefore, heat generated within the first chip 140 and the second chip 150 is easily transferred to the source electrodes 141, 151 and the gate electrodes 142, 152, thereby being dissipated. As a result, thermal runaway of the first chip 140 and the second chip 150 can be suppressed.

[0084] <Second embodiment>

[0085] Next, a second embodiment will be described.

[0086] Figure 12 (a) is a top view showing a first connector of the semiconductor device of this embodiment. Figure 12 (b) is Figure 12 (a) Cross-sectional view on line D-D'.

[0087] Figure 13 2 is a cross-sectional view showing a semiconductor device according to this embodiment.

[0088] Figure 14 2 is a cross-sectional view showing a semiconductor device according to this embodiment.

[0089] The semiconductor device 200 of the present embodiment differs from the semiconductor device 100 of the first embodiment in the shapes of the first tip portion 261 of the first connector 260 and the second tip portion 271 of the second connector 270 .

[0090] In addition, in the following description, only the differences from the first embodiment are described in principle. Except for the matters described below, the present invention is the same as the first embodiment.

[0091] like Figure 12 (a) and Figure 12 As shown in FIG. 2( b ), the substantially central portion of the first front end portion 261 of the first connector 260 is punched. Specifically, the first front end portion 261 includes a first portion 261 a , a second portion 261 b , and a third portion 261 c .

[0092] The first portion 261a is located approximately in the center of the first front end portion 261. When viewed from above, the first portion 261a is a quadrilateral with rounded corners. However, the shape of the first portion 261a is not limited to this. The top and bottom surfaces of the first portion 261a are approximately parallel to the X and Y directions.

[0093] The second portion 261b is located below the first portion 261a and is provided around the first portion 261a. The upper surface and the lower surface of the second portion 261b are substantially parallel to the X direction and the Y direction.

[0094] The third portion 261 c is connected to the first portion 261 a and the second portion 261 b and extends in a direction including the Z direction.

[0095] like Figure 13 As shown, a bonding member 241a is provided between the first tip portion 261 and the source electrode 141 of the first chip 140, and a bonding member 251a is provided between the first tip portion 261 and the source electrode 151 of the second chip 150. The bonding members 241a and 251a are formed by solidifying solder.

[0096] The distance D1 between the second portion 261b and the source electrode 141 of the first chip 140 is shorter than the distance D2 between the first portion 261a and the source electrode 141. Furthermore, the distance D3 between the second portion 261b and the source electrode 151 of the second chip 150 is longer than the distance D4 between the first portion 261a and the source electrode 151. This increases the gap between the first chip 140 and the second chip 150. As a result, during manufacturing, it is easier to retain uncured solder between the first chip 140 and the second chip 150. This prevents uncured solder from coming into contact with the drain electrodes 143 and 153 along the side surfaces of the chips 140 and 150, thereby preventing the source electrodes 141 and 151 from being electrically connected to the drain electrodes 143 and 153.

[0097] In addition, the first connector 260 has a first portion 261a and a second portion 261b, so that the area of ​​the first connector 260 connected to the source electrodes 141 and 151 can be increased. As a result, the resistance between the first connector 260 and the source electrodes 141 and 151 can be reduced. At this time, the area of ​​the upper surface of the first portion 261a is preferably approximately the same as the area of ​​the lower surface of the second portion 261b. As a result, the difference in resistance between the first connector 260 and the source electrode 141 of the first chip 140 and the resistance between the first connector 260 and the source electrode 151 of the second chip 150 can be reduced. As a result, the difference in current flowing into the first chip 140 and the current flowing into the second chip 150 can be suppressed. However, the size relationship between the area of ​​the upper surface of the first portion and the area of ​​the lower surface of the second portion is not limited to the above.

[0098] like Figure 14 As shown, the second front end portion 271 of the second connector 270 has a shape that is bent multiple times or rounded to form four bent portions 271 a , 271 b , 271 c , and 271 d .

[0099] A bonding member 242a is provided between the second tip portion 271 and the gate electrode 142 of the first chip 140, and a bonding member 252a is provided between the second tip portion 271 and the gate electrode 152 of the second chip 150. The bonding members 242a and 252a are formed by solidifying solder.

[0100] As described above, the second tip portion 271 of the second connector 270 includes the bent portions 271a, 271b, 271c, and 271d, thereby increasing the gap between the first chip 140 and the second chip 150. Consequently, during manufacturing, it is easier to retain uncured solder between the first chip 140 and the second chip 150. This prevents uncured solder from coming into contact with the drain electrodes 143 and 153 along the side surfaces of the chips 140 and 150, thereby preventing the gate electrodes 142 and 152 from electrically connecting to the drain electrodes 143 and 153.

[0101] As described above, in the semiconductor device 200 of this embodiment, the first tip portion 261 of the first connector 260 includes a first portion 261a and a second portion 261b disposed around the first portion 261a. The distance D1 between the second portion 261b and the source electrode 141 of the first chip 140 is shorter than the distance D2 between the first portion 261a and the source electrode 141. Furthermore, the distance D3 between the second portion 261b and the source electrode 151 of the second chip 150 is longer than the distance D4 between the first portion 261a and the source electrode 151. Therefore, the contact area between the first connector 260 and the source electrodes 141 and 151 can be increased, and electrical connection between the source electrodes 141 and 151 and the drain electrodes 143 and 153 can be suppressed.

[0102] Furthermore, the second distal end portion 271 of the second connector 270 includes bent portions 271 a , 271 b , 271 c , and 271 d , thereby preventing the gate electrodes 142 , 152 from being electrically connected to the drain electrodes 143 , 153 .

[0103] <Third embodiment>

[0104] Next, a third embodiment will be described.

[0105] Figure 15 (a) is a top view showing a first connector in the semiconductor device of this embodiment. Figure 15 (b) is Figure 15 (a) is a cross-sectional view on the EE' line.

[0106] The semiconductor device 300 of the present embodiment differs from the semiconductor device 100 of the first embodiment in the shape of a first tip portion 361 of a first connector 360 .

[0107] In the first front end portion 361 of the first connector 360, the portion other than the end portion 361c located on the side of the first intermediate portion 163 in the Y direction is bent in multiple places, for example, by stamping, and is bent into a wave shape. Thus, the first connector has a plurality of first portions 361a and a plurality of second portions 361b arranged alternately. However, the first front end portion may also be bent into a wave shape as a whole. In addition, Figure 15 In (a), the area where the second portion 361b is provided is indicated by a dot pattern.

[0108] The positions of the plurality of first portions 361a in the vertical direction are approximately the same as the positions of the end portion 361c and the first portion 163a of the first intermediate portion 163. The plurality of second portions 361b are located below the plurality of first portions 361a. In this embodiment, the plurality of first portions 361a and the plurality of second portions 361b extend along the Y direction. However, the plurality of first portions and the plurality of second portions may also extend along the X direction or in a direction oblique to the X and Y directions. Furthermore, the number of first portions may be one or more, and the number of second portions may be one or more.

[0109] The total area of ​​the top surfaces of the plurality of first portions 361a and the area of ​​the top surfaces of the end portions 361c is preferably approximately the same as the total area of ​​the bottom surfaces of the plurality of second portions 361b. This reduces the difference in resistance between the first connector 360 and the source electrode 141 of the first chip 140 and the resistance between the first connector 360 and the source electrode 151 of the second chip 150. Consequently, the difference in current flowing into the first chip 140 and the current flowing into the second chip 150 can be suppressed. However, the relationship between the total area of ​​the top surfaces of the plurality of first portions and the area of ​​the top surfaces of the end portions and the total area of ​​the bottom surfaces of the plurality of second portions is not limited to the above.

[0110] As described above, the first tip portion 361 of the first connector 360 in this embodiment has a wavy shape. This increases the contact area between the first connector 260 and the source electrodes 141 and 151. Furthermore, this increases the gap between the source electrodes 141 and 151, making it easier to retain uncured solder. This prevents solder from flowing along the sides of the chips 140 and 150, potentially causing electrical connection between the source electrodes 141 and 151 and the drain electrodes 143 and 153.

[0111] <Fourth embodiment>

[0112] Next, a fourth embodiment will be described.

[0113] Figure 16 2 is a cross-sectional view showing a semiconductor device according to this embodiment.

[0114] The semiconductor device 400 of this embodiment is different from that of the first embodiment in that a first chip 440 and a second chip 450 are arranged so that drain electrodes 443 and 453 face each other.

[0115] The substrate 410 includes an insulating layer 411, and a first wiring 412, a second wiring 413, and a third wiring 414 provided on the insulating layer 411. A first chip 440 is provided on the substrate 410.

[0116] A source electrode 441 and a gate electrode 442 are provided on the lower surface (first face) 440a of the first chip 440. The source electrode 441 is connected to the first wiring 412 via a bonding member 441a such as solder. The gate electrode 442 is connected to the second wiring 413 via a bonding member 442a such as solder.

[0117] A drain electrode 443 is provided on the upper surface (second surface) 440 b of the first chip 440 . The second chip 450 is provided above the first chip 440 so as to face the first chip 440 .

[0118] A source electrode 451 and a gate electrode 452 are provided on the upper surface (third surface) 450 a of the second chip 450 .

[0119] A drain electrode 453 is provided on the lower surface (fourth surface) 450 b of the second chip 450 . The drain electrode 453 faces the drain electrode 443 of the first chip 440 . A first connector 460 is provided between the first chip 440 and the second chip 450 .

[0120] The first connector 460 includes a front end portion 461 located between the first chip 440 and the second chip 450 , a base end portion 462 located on the third wiring 414 , and a middle portion 463 located between the front end portion 461 and the base end portion 462 .

[0121] In this embodiment, the tip portion 461 is flat and connected to the drain electrode 443 of the first chip 440 via a solder bonding member 443a. Furthermore, the tip portion 461 is connected to the drain electrode 453 of the second chip 450 via a solder bonding member 453a.

[0122] The base end portion 462 has a flat plate shape and is connected to the third wiring 414 of the substrate 410 via a bonding member 414a such as solder.

[0123] The intermediate portion 463 is connected to the end of the distal end portion 461 and the upper end of the proximal end portion 462 .

[0124] A second connector 470 is provided on the source electrode 451 of the second chip 450. The second connector 470 is connected to the source electrode 451 via a bonding member 451a such as solder. Furthermore, the second connector 470 is connected to the first wiring 412 of the substrate 410 via a bonding member 412a such as solder.

[0125] A third connector 480 is provided on the gate electrode 452 of the second chip 450. The third connector 480 is connected to the gate electrode 452 via a bonding member 452a such as solder. Furthermore, the third connector 480 is connected to the second wiring 413 of the substrate 410 via a bonding member 413a such as solder.

[0126] The first connector 460, the second connector 470, and the third connector 480 are separated from each other. The first connector 460, the second connector 470, and the third connector 480 are made of a metal material with high thermal conductivity, such as copper.

[0127] As described above, the first chip 440 and the second chip 450 can also be arranged so that the drain electrodes 443 and 453 face each other. In this case, the on-resistance of the semiconductor device 100 can be reduced while increasing the current that can be output by the semiconductor device 100. Furthermore, in this case, the first chip 440 and the second chip 450 are stacked. Therefore, an increase in the area of ​​the semiconductor device 400 when viewed from above can be suppressed.

[0128] <Fifth embodiment>

[0129] Next, a fifth embodiment will be described.

[0130] Figure 17 2 is a cross-sectional view showing a semiconductor device according to this embodiment.

[0131] The semiconductor device 500 of the present embodiment differs from the semiconductor device 400 of the fourth embodiment in the shape of the front end portion 561 of the first connector 560 .

[0132] In addition, in the following description, only the differences from the fourth embodiment will be described in principle. Except for the matters described below, the fourth embodiment is the same as the fourth embodiment.

[0133] The shape of the front end portion 561 of the first connector 560 is substantially the same as the first front end portion 261 of the first connector 260 in the second embodiment. Specifically, the front end portion 561 includes a first portion 561a, a second portion 561b disposed around the first portion 561a, and a third portion 561c disposed between the first portion 561a and the second portion 561b and connected to the first portion 561a and the second portion 561b.

[0134] The distance D5 between the second portion 561b and the drain electrode 443 of the first chip 440 is shorter than the distance D6 between the first portion 561a and the drain electrode 443. In addition, the distance D7 between the second portion 561b and the drain electrode 453 of the second chip 450 is longer than the distance D8 between the first portion 561a and the drain electrode 453.

[0135] As described above, in the front end portion 561 of the first connector 560 in this embodiment, the distance D5 between the second portion 561b and the drain electrode 443 of the first chip 440 is shorter than the distance D6 between the first portion 561a and the drain electrode 443. Furthermore, the distance D7 between the second portion 561b and the drain electrode 453 of the second chip 450 is longer than the distance D8 between the first portion 561a and the drain electrode 453. Consequently, the contact area between the first connector 560 and the drain electrodes 443, 453 can be increased, and electrical connection between the drain electrodes 443, 453 and the source electrodes 441, 451 and the gate electrodes 442, 452 can be suppressed.

[0136] <Sixth embodiment>

[0137] Next, a sixth embodiment will be described.

[0138] Figure 18 2 is a cross-sectional view showing a semiconductor device according to this embodiment.

[0139] The semiconductor device 600 of the present embodiment differs from the semiconductor device 400 of the fourth embodiment in the shape of a front end portion 661 of a first connector 660 .

[0140] The shape of the front end portion 661 of the first connector 660 is substantially the same as the first front end portion 361 of the first connector 360 in the third embodiment. Specifically, the front end portion 661 is bent at multiple locations, for example, by stamping, to have a wavy shape. This increases the contact area between the first connector 660 and the drain electrodes 443 and 453, and prevents the drain electrodes 443 and 453 from being electrically connected to the source electrodes 441 and 451 and the gate electrodes 442 and 452.

[0141] <Modification of the First Connector>

[0142] Figure 19 (a) is a cross-sectional view showing a modified example of the first connector, Figure 19 (b) is a cross-sectional view showing a modified example of the first connector.

[0143] The first connector 160 in the first embodiment and the first connector 460 in the fourth embodiment can also be used with Figure 19 (a) and Figure 19 The first connector 760 shown in (b) is replaced with the first connector 760. The front end 761 of the first connector 760 includes a flat portion 761a and one or more protrusions 761b provided on the flat portion 761a. Preferably, the number of protrusions 761b provided on the upper surface of the flat portion 761a is the same as the number of protrusions 761b provided on the lower surface of the flat portion 761a. However, the number of protrusions 761b is not particularly limited as long as it is one or more.

[0144] As described above, the front end 761 of the first connector 760 includes a protrusion 761b that protrudes toward the first chip 140 or the second chip 150. This configuration increases the contact area with the electrodes connected to the first connector 760. Furthermore, the gap between the first chip 140, 440 and the second chip 150, 450 can be increased. Consequently, the transfer of uncured solder to the sides of each chip 140, 150, 440, 450 can be suppressed.

[0145] <Modifications of the First and Second Chips>

[0146] Figure 20 It is a plan view showing a modified example of the first chip and the second chip.

[0147] In the first embodiment, an example is described in which the first chip 140 and the second chip 150 are square in shape and the first chip 140 and the second chip 150 are symmetrical with respect to the plane P.

[0148] However, if Figure 20 As shown in (a), the first chip 140 and the second chip 150 may also be rectangular in shape.

[0149] In addition, if Figure 20 As shown in (b), the first chip 140 can also be aligned with the second chip 150 relative to the plane P (refer to Figure 5 For example, the area of ​​the source electrode 141 of the first chip 140 may be larger than the area of ​​the source electrode 151 of the second chip 150. In addition, the area of ​​the source electrode of the first chip may be larger than the area of ​​the source electrode of the second chip.

[0150] As described above, there are no particular limitations on the specific shapes of the first chip and the second chip and the areas of the electrodes as long as the corresponding electrodes of the first chip and the second chip can be electrically connected to each other.

[0151] While the embodiments of the present invention have been described above, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their variations are included within the scope or gist of the invention and are included within the scope of the invention described in the claims and their equivalents.

Claims

1. A semiconductor device comprising: a first chip having a first electrode and a second electrode provided on a first surface, and a third electrode provided on a second surface opposite to the first surface; a second chip having a fourth electrode and a fifth electrode provided on a third surface, and a sixth electrode provided on a fourth surface opposite to the third surface, the second chip being arranged so that the third surface faces the first surface; a substrate being arranged so as to face the second surface of the first chip and connected to the third electrode; and a first connector being arranged between the first chip and the second chip, connected to the first electrode and the fourth electrode, and extending from between the first electrode and the fourth electrode in a first direction. a second connector, disposed between the first chip and the second chip, connected to the second electrode and the fifth electrode, and extending from between the second electrode and the fifth electrode along the first direction; and a third connector connected to the sixth electrode of the second chip and the substrate, and extending from a portion connected to the sixth electrode along a second direction perpendicular to the first direction.

2. The semiconductor device according to claim 1 , further comprising: a first lead connected to the first connector; and a second lead connected to the second connector, the first connector having: a first front end portion arranged between the first electrode and the fourth electrode; a first base end portion arranged on the first lead; and a first middle portion located between the first front end portion and the first base end portion, the second connector having: a second front end portion arranged between the second electrode and the fifth electrode; a second base end portion arranged on the second lead; and a second middle portion located between the second front end portion and the second base end portion, the third connector having: a third front end portion arranged on the sixth electrode; a third base end portion arranged on the substrate; and a third middle portion located between the third front end portion and the third base end portion, the width of the first base end portion being wider than the width of a boundary between the first middle portion and the first front end portion, the width of the second base end portion being wider than the width of a boundary between the second middle portion and the second front end portion, and the width of the third base end portion being wider than the width of a boundary between the third middle portion and the third front end portion. 3 . The semiconductor device according to claim 2 , wherein the first front end portion located between the first electrode and the fourth electrode in the first connector has a corrugated shape. 4 . The semiconductor device according to claim 2 , wherein the first tip portion of the first connector located between the first electrode and the fourth electrode has a protrusion protruding toward the first electrode or the fourth electrode.

5. A semiconductor device comprising: a first chip having a first electrode and a second electrode provided on a first surface, and a third electrode provided on a second surface opposite to the first surface; a second chip having a fourth electrode and a fifth electrode provided on a third surface, and a sixth electrode provided on a fourth surface opposite to the third surface, the second chip being arranged so that the third surface faces the first surface; a first connector arranged between the first chip and the second chip and connected to the first electrode and the fourth electrode; and a second connector arranged between the first chip and the second chip and connected to the second electrode and the fifth electrode, wherein a first front end portion of the first connector located between the first electrode and the fourth electrode comprises: a first portion; and a second portion provided around the first portion, wherein a distance between the second portion and the first electrode is shorter than a distance between the first portion and the first electrode, a distance between the second portion and the fourth electrode is longer than a distance between the first portion and the fourth electrode, and an area of ​​an upper surface of the first portion is equal to an area of ​​a lower surface of the second portion. 6 . The semiconductor device according to claim 5 , wherein the first front end portion located between the first electrode and the fourth electrode in the first connector has a corrugated shape. 7 . The semiconductor device according to claim 5 , wherein the first tip portion of the first connector located between the first electrode and the fourth electrode has a protrusion protruding toward the first electrode or the fourth electrode.

8. A semiconductor device comprising: a first chip having a first electrode and a second electrode provided on a first surface, and a third electrode provided on a second surface opposite to the first surface; a second chip having a fourth electrode and a fifth electrode provided on a third surface, and a sixth electrode provided on a fourth surface opposite to the third surface, the second chip being arranged such that the fourth surface faces the second surface; and a substrate arranged such that it faces the first surface of the first chip and having a first wiring connected to the first electrode and a second wiring connected to the second electrode; a first connector disposed between the third electrode and the sixth electrode, connected to the third electrode and the sixth electrode, and extending from between the third electrode and the sixth electrode along a first direction; a second connector connected to the fourth electrode of the second chip and the first wiring, and extending from a portion connected to the fourth electrode along a second direction different from the first direction; and a third connector connected to the fifth electrode of the second chip and the second wiring, and extending from a portion connected to the fifth electrode in a third direction different from the first direction and the second direction.

9. A semiconductor device comprising: a first chip, having a first electrode and a second electrode provided on a first surface, and a third electrode provided on a second surface located opposite to the first surface; a second chip, having a fourth electrode and a fifth electrode provided on a third surface, and a sixth electrode provided on a fourth surface located opposite to the third surface, the second chip being arranged with the fourth surface facing the second surface; and a first connector arranged between the third electrode and the sixth electrode and connected to the third electrode and the sixth electrode; a front end portion of the first connector located between the third electrode and the sixth electrode comprises: a first part; and a second part provided around the first part, a distance between the second part and the third electrode being shorter than a distance between the first part and the third electrode, a distance between the second part and the sixth electrode being longer than a distance between the first part and the sixth electrode, and an area of ​​an upper surface of the first part being equal to an area of ​​a lower surface of the second part.

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