Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same, wherein the semiconductor structure includes: a substrate having an interlayer dielectric layer thereon; a gate structure located on the substrate; source / drain doping layers located in the substrate on both sides of the gate structure; a first opening located in the interlayer dielectric layer, the first opening exposing the top of the gate structure; a first inner sidewall located on the sidewall of the first opening, with a first gap between the first inner sidewalls; a second opening located in the interlayer dielectric layer, the second opening exposing the top of the source / drain doping layers; a conductive layer located in the second opening, and the top surface of the conductive layer being lower than the top surface of the interlayer dielectric layer; a second inner sidewall located on the sidewall of the second opening exposed by the conductive layer, with a second gap between the second inner sidewalls. The semiconductor structure provided by the embodiments of the present invention avoids the short-circuit problems between the first interconnect layer and the conductive layer, and between the second interconnect layer and the gate structure, and improves the electrical performance and stability of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Over the past several decades, the scaling of feature sizes in integrated circuits has been the driving force behind the growing semiconductor industry. Scaling to smaller and smaller feature sizes enables increased density of functional units on the limited substrate area of ​​a semiconductor chip. For example, reducing transistor size allows an increased number of memory or logic devices to be included on a chip, resulting in the manufacture of products with increased capacity. But the drive for greater capacity is not without its problems. The necessity to optimize the performance of each device becomes increasingly apparent.

[0003] In the manufacture of integrated circuit devices, multi-gate transistors become more common as device dimensions continue to shrink. In conventional processes, multi-gate transistors are usually manufactured on a silicon substrate or a silicon-on-insulator substrate.

[0004] But shrinking the size of multi-gate transistors is not without its problems. As the size of these basic building blocks of microelectronic circuits decreases, and as the absolute number of basic building blocks manufactured in a given area increases, the constraints of the photolithography process used to form the building block patterns become difficult to overcome. The electrical performance of multi-gate transistors in the prior art still needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor structure.

[0006] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, having an interlayer dielectric layer on the substrate; a gate structure, located on the substrate, and the top surface of the gate structure is lower than the top surface of the interlayer dielectric layer; a source-drain doped layer, located in the substrate on both sides of the gate structure; a first opening, located in the interlayer dielectric layer, the first opening exposing the top surface of the gate structure; a first inner sidewall, located on the sidewall of the first opening, with a first gap between the first inner sidewalls; a second opening, located in the interlayer dielectric layer, the second opening exposing the top surface of the source-drain doped layer; a conductive layer, located in the second opening, and the top surface of the conductive layer is lower than the top surface of the interlayer dielectric layer; a second inner sidewall, located on the sidewall of the second opening exposed by the conductive layer, with a second gap between the second inner sidewalls.

[0007] Optionally, it further includes: a first interconnect layer located within the first void and on top of the gate structure; a second interconnect layer located within the second void and on top of the conductive layer.

[0008] Optionally, it further includes: a second dielectric layer located on the interlayer dielectric layer, and part of the first interconnect layer and part of the second interconnect layer are also located within the second dielectric layer.

[0009] Optionally, the material of the first sidewall includes silicon nitride, silicon carbonitride, or nitrogen-doped silicon carbide.

[0010] Optionally, the material of the second sidewall includes silicon nitride, silicon carbonitride, or nitrogen-doped silicon carbide.

[0011] Optionally, the material of the second dielectric layer is different from the material of the first sidewall and the material of the second sidewall, and the material of the second dielectric layer includes a low-k dielectric material, an ultra-low-k dielectric material, or silicon oxide.

[0012] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate having an interlayer dielectric layer, a gate structure within the interlayer dielectric layer, and source / drain doping layers within the substrate on both sides of the gate structure; etching the gate structure until the top surface of the gate structure is lower than the top surface of the interlayer dielectric layer to form a first opening within the interlayer dielectric layer; forming a first sidewall on the sidewalls of the first opening, and having a first void between the first sidewalls; forming a first dielectric layer within the first void; etching the interlayer dielectric layer on the source / drain doping layers until the top surface of the source / drain doping layers is exposed to form a second opening; forming a conductive layer within the second opening, and the top surface of the conductive layer is lower than the top surface of the interlayer dielectric layer; forming a second sidewall on the sidewalls of the second opening where the conductive layer is exposed, and having a second void between the second sidewalls.

[0013] Optionally, it further includes: forming a first interconnect layer within the first void, and the first interconnect layer is located on top of the gate structure; forming a second interconnect layer within the second void, and the second interconnect layer is located on top of the conductive layer.

[0014] Optionally, before forming the first interconnect layer and the second interconnect layer, it further includes: forming a second dielectric layer on the interlayer dielectric layer, and the second dielectric layer also fills the second void.

[0015] Optionally, the step of forming the first interconnect layer in the first gap includes: etching the second dielectric layer and the first dielectric layer in the first gap until the top of the gate structure is exposed, forming a third opening in the second dielectric layer; forming the first interconnect layer in the first gap and the third opening.

[0016] Optionally, the step of forming the second interconnect layer in the second gap includes: etching the second dielectric layer until the top of the conductive layer is exposed, forming a fourth opening in the second dielectric layer; forming the second interconnect layer in the second gap and the fourth opening.

[0017] Optionally, the method of forming the conductive layer in the second opening includes: forming an initial conductive layer in the second opening, the top surface of the initial conductive layer being flush with the top surface of the interlayer dielectric layer; etching the initial conductive layer until the top surface of the initial conductive layer is lower than the top surface of the interlayer dielectric layer to form the conductive layer.

[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0019] By forming a first inner sidewall on the sidewall of the first opening on the gate structure, there is a first gap between the first inner sidewalls, and the first gap provides space for forming the first interconnect layer on the gate structure later. Due to the existence of the first inner sidewall, the distance between the subsequently formed first interconnect layer and the conductive layer is increased, avoiding short - circuit between the first interconnect layer and the conductive layer; similarly, by forming a second inner sidewall on the sidewall of the second opening where the conductive layer is exposed, there is a second gap between the second inner sidewalls, and the second gap provides space for forming the second interconnect layer on the conductive layer later. After forming the second interconnect layer in the second gap subsequently, due to the existence of the second inner sidewall, the distance between the second interconnect layer and the gate structure is increased, avoiding short - circuit between the second interconnect layer and the gate structure, which is beneficial to improving the electrical performance of the semiconductor structure. Description of the Drawings

[0020] Figure 1 is a schematic cross - sectional structure diagram of a semiconductor structure in an embodiment;

[0021] Figure 2 is a schematic cross - sectional structure diagram of a semiconductor structure in another embodiment;

[0022] Figures 3 to 19 is a schematic structure diagram corresponding to each step in the formation process of a semiconductor structure in an embodiment of the present invention. Detailed Embodiment

[0023] In the prior art, the electrical performance of MOSFET with a COAG structure still needs to be improved. The following will be specifically described with reference to the drawings.

[0024] Figure 1 is a schematic cross-sectional structure diagram of a semiconductor structure in an embodiment.

[0025] Referring to Figure 1 , the semiconductor structure includes: a substrate 100; fins 101 located on the substrate 100; a gate structure 102 spanning across the fins 101; sidewalls 103 located on the sidewalls of the gate structure 102; source / drain doping layers 104 located within the fins 101 on both sides of the gate structure 102; a conductive layer 105 located on top of the source / drain doping layers 104; a first hard mask layer 106 located on the top surface of the gate structure 102; a second hard mask layer 107 located on top of the conductive layer 105 and also covering the top surface of the sidewalls 103; a dielectric layer 108 located on the first hard mask layer 106 and the second hard mask layer 107; a second interconnect layer 109 located within the second hard mask layer 107 and on top of the conductive layer 105.

[0026] The inventors found that in the above embodiment, after forming the second interconnect layer 109, due to the small distance between the second interconnect layer 109 and the gate structure 102 (refer to the dotted-line circle part in Figure 1 ), it is easy to have a short circuit between the second interconnect layer 109 and the gate structure 102 during the electrical connection process, thus affecting the performance of the semiconductor structure.

[0027] Another method for forming a semiconductor structure will be specifically described below with reference to the accompanying drawings.

[0028] Figure 2 is a schematic cross-sectional structure diagram of a semiconductor structure in another embodiment.

[0029] Referring to Figure 2 , the semiconductor structure includes: a substrate 200; fins 201 located on the substrate 200; a gate structure 202 spanning across the fins 201; sidewalls 203 located on the sidewalls of the gate structure 202, and the top of the sidewalls 203 is higher than the top of the gate structure 202; source / drain doping layers 204 located within the fins 201 on both sides of the gate structure 202; a conductive layer 205 located on top of the source / drain doping layers 204; a first hard mask layer 206 located on the top surface of the gate structure 202; a second hard mask layer 207 located on the top surface of the conductive layer 205; a dielectric layer 208 located on the first hard mask layer 206, the second hard mask layer 207, and the sidewalls 203; a first interconnect layer 209 located within the first hard mask layer 206 and on top of the gate structure 202 between the source / drain doping layers 204.

[0030] The inventors found that in the above embodiments, after the first interconnect layer 209 is formed, since the distance between the first interconnect layer 209 and the conductive layer 205 is small, a short circuit is likely to occur between the first interconnect layer 209 and the conductive layer 205 during the electrical connection process (refer to Figure 2 the dotted circle part in

[0031] ), thus affecting the performance of the semiconductor structure.

[0032] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure. A first inner wall is formed on the sidewalls of the first opening at the top of the gate structure, and there is a first gap between the first inner walls. A second inner wall is formed on the sidewalls of the second opening exposed at the top of the conductive layer, and there is a second gap between the second inner walls. Subsequently, a first interconnect layer is formed in the first gap, and a second interconnect layer is formed in the second gap. Since there is a first inner wall between the first interconnect layer and the conductive layer, the distance between the first interconnect layer and the conductive layer is increased, avoiding a short circuit between the first interconnect layer and the conductive layer. Similarly, since there is a second inner wall between the second interconnect layer and the gate structure, the distance between the second interconnect layer and the gate structure is increased, avoiding a short circuit between the second interconnect layer and the gate structure, thereby being beneficial to improving the electrical performance of the semiconductor structure.

[0032] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0033] Figures 3 to 19 It is a schematic structural diagram corresponding to each step in the process of forming a semiconductor structure in an embodiment of the present invention.

[0034] Refer to Figure 3 , and a substrate 300 is provided.

[0035] In this embodiment, the substrate 300 includes a substrate 301 and a plurality of fin portions 302 arranged separately on the substrate 301, and the fin portions 302 extend along the first direction X.

[0036] In other embodiments, the fin portions may not be formed on the substrate 301.

[0037] In this embodiment, the material of the substrate 301 is silicon.

[0038] In other embodiments, the material of the substrate 301 may also be a semiconductor material such as germanium, silicon germanide, gallium arsenide, silicon on insulator (SOI), germanium on insulator (GOI), etc.

[0039] In this embodiment, the material of the fin portions 302 is silicon; in other embodiments, the material of the fin portions 302 may also be a semiconductor material such as silicon germanium.

[0040] In this embodiment, the method for forming the fin 302 includes: forming a fin material film (not shown) on the substrate 301; forming a patterned layer (not shown) on the fin material film; etching the fin material film using the patterned layer as a mask until the surface of the substrate 301 is exposed to form the fin 302.

[0041] In this embodiment, an isolation structure 303 is further formed on the substrate 301, and the isolation structure 303 covers a part of the sidewalls of the fin 302.

[0042] In this embodiment, the material of the isolation structure 303 is silicon oxide; in other embodiments, the material of the isolation structure 303 may further include one or more combinations of materials such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxynitride (SiOCN), silicon carbonitride boron (SiCBN), etc.

[0043] In this embodiment, the method for forming the isolation structure 303 includes: forming an isolation structure film (not shown) covering the fin 302 on the substrate 301; and re-etching the isolation structure film to form the isolation structure 303.

[0044] The process for forming the isolation structure film is a deposition process, such as a fluid chemical vapor deposition process. Using the fluid chemical vapor deposition process to form the isolation structure film has better filling performance of the isolation structure film.

[0045] After forming the isolation structure 303, an interlayer dielectric layer, a gate structure, and source / drain doping layers in the fins 302 on both sides of the gate structure are formed on the substrate 301.

[0046] The specific steps for forming the interlayer dielectric layer, the gate structure, and the source / drain doping layers include:

[0047] Refer to Figure 4 , a dummy gate structure 304 is formed on the substrate 300.

[0048] In this embodiment, a dummy gate structure 304 spanning the fins 302 is formed on the substrate 301.

[0049] In this embodiment, the dummy gate structure 304 includes: a dummy gate dielectric layer 305 on the fin 302, a dummy gate layer 306 on the dummy gate dielectric layer 305, and a protective layer 307 on the dummy gate layer 306.

[0050] In this embodiment, the material of the dummy gate dielectric layer 305 is silicon oxide.

[0051] In this embodiment, the material of the dummy gate layer 306 is polysilicon.

[0052] In this embodiment, the material of the protective layer 307 includes: silicon nitride or silicon oxide; in other embodiments, the material of the protective layer 307 can also be one or a combination of materials such as silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxynitride (SiOCN), silicon carbonitride boron (SiCBN), etc.

[0053] In this embodiment, the protective layer 307 protects the dummy gate layer 306 during the subsequent formation of the source / drain doping layer, and at the same time serves as a stop layer for the subsequent planarization of the interlayer dielectric layer.

[0054] In this embodiment, a spacer 308 is also formed on the sidewalls of the dummy gate layer 306 and the protective layer 307.

[0055] In this embodiment, the material of the spacer 308 is silicon nitride; in other embodiments, the material of the spacer 308 can also be one or a combination of materials such as silicon oxide, silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxynitride (SiOCN), silicon carbonitride boron (SiCBN), etc.

[0056] The spacer 308 is used to define the position of the subsequently formed source / drain doping layer, and the spacer 308 serves to protect the sidewalls of the dummy gate layer 306 to prevent morphological defects from occurring in the subsequently formed gate layer and affecting the electrical performance of the semiconductor structure.

[0057] Reference Figure 5 , the source / drain doping layer 309 is formed in the substrate 300 on both sides of the dummy gate structure 304.

[0058] In this embodiment, the fins 302 on both sides of the dummy gate structure 304 are etched to form the source / drain doping layer 309 in the fins 302.

[0059] The source / drain doping layer 309 has source / drain doping ions.

[0060] The process of forming the source / drain doping layer 309 includes an epitaxial growth process; the process of doping source / drain doping ions in the source / drain doping layer is an in-situ doping process.

[0061] When the semiconductor device is a P-type device, the material of the source / drain doping layer 309 includes: silicon, germanium, or silicon germanium; the source / drain doping ions are P-type ions, including boron ions, BF 2-Ions or indium ions; when the semiconductor device is an N-type device, the material of the source / drain doping layer 309 includes: silicon, gallium arsenide, or indium gallium arsenide; the source / drain doping ions are N-type ions, including phosphorus ions or arsenic ions.

[0062] In this embodiment, the semiconductor device is a P-type device, the material of the source / drain doping layer 309 is silicon, and the source / drain doping ions are boron ions. In other embodiments, the semiconductor device is an N-type device, the material of the source / drain doping layer 309 is silicon, and the source / drain doping ions are phosphorus ions.

[0063] Reference Figure 6 , an interlayer dielectric layer 310 is formed on the substrate 300 and on the source / drain doping layer 309, and the interlayer dielectric layer 310 exposes the top surface of the dummy gate structure 304.

[0064] In this embodiment, the interlayer dielectric layer 310 is formed on the substrate 301 and on the source / drain doping layer 309. The interlayer dielectric layer 310 covers the sidewalls of the dummy gate structure 304 and exposes the top surface of the protective layer 307.

[0065] In this embodiment, the method for forming the interlayer dielectric layer 310 includes: forming an interlayer dielectric material layer (not shown) on the substrate 301 and on the source / drain doping layer 309, the interlayer dielectric material layer covering the top surface of the dummy gate structure 304; performing a planarization process on the interlayer dielectric material layer until the top surface of the protective layer 307 is exposed, to form the interlayer dielectric layer 310.

[0066] In this embodiment, the material of the interlayer dielectric layer 310 is silicon oxide; in other embodiments, the material of the interlayer dielectric layer 310 can also be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0067] In this embodiment, the formation process of the interlayer dielectric layer 310 is a chemical vapor deposition process; in other embodiments, the formation process of the interlayer dielectric layer 310 can also be one or a combination of a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0068] Reference Figure 7 , the dummy gate structure 304 is etched away until the surface of the substrate 300 is exposed, to form a gate opening 311.

[0069] In this embodiment, the protective layer 307, the dummy gate layer 306, and the dummy gate dielectric layer 305 are removed, and the gate opening 311 is formed between the sidewalls 308.

[0070] The process of removing the dummy gate structure 304 includes a dry etching process or a wet etching process.

[0071] Reference Figure 8 , a gate structure 312 is formed within the gate opening 311, and the top surface of the gate structure 312 is flush with the top surface of the interlayer dielectric layer 310.

[0072] In this embodiment, the gate structure 312 includes a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer.

[0073] In this embodiment, the material of the gate dielectric layer includes a high-K dielectric material, such as: oxides – Al2O3, HfO2, Ta2O5, TiO2, ZrO2, etc.

[0074] In other embodiments, the material of the gate dielectric layer may further include other dielectric materials with a dielectric constant higher than 3.9.

[0075] In this embodiment, the material of the gate layer is metal, and the metal material includes one or a combination of copper, tungsten, nickel, chromium, titanium, tantalum, and aluminum.

[0076] In this embodiment, the method of forming the gate structure 312 includes: forming the gate dielectric layer on the sidewalls and bottom of the gate opening 311, forming an initial gate material layer on the gate dielectric layer, and planarizing the initial gate material layer until the top surface of the gate material layer is flush with the top of the interlayer dielectric layer 310 to form the gate structure 312.

[0077] Reference Figure 9 , etching the gate structure 312 until the top surface of the gate structure 312 is lower than the top surface of the interlayer dielectric layer 310 to form a first opening 320 within the interlayer dielectric layer 310.

[0078] In this embodiment, the first opening 320 is formed between the sidewalls 308.

[0079] In this embodiment, the depth of the first opening 320 is 100 - 500 nm. If the depth of the first opening 320 is too deep, too much of the gate structure 312 will be etched away, resulting in a large resistance of the gate structure; if the depth of the first opening 320 is too shallow, the height of the first inner sidewall 321 formed on the sidewall of the first opening 320 will be too short to provide protection.

[0080] In this embodiment, the method of etching the gate structure 312 is dry etching.

[0081] ReferenceFigure 10 , after forming the first opening 320, a first inner wall 321 is formed on the sidewall of the first opening 320 (refer to Figure 9 ), and there is a first gap 322 between the first inner walls 321.

[0082] In this embodiment, the first gap 322 provides space for forming a first interconnect layer on the gate structure 312 subsequently.

[0083] In this embodiment, the material of the first inner wall 321 is silicon nitride; in other embodiments, the material of the first inner wall 321 can also be silicon carbonitride or nitrogen-doped silicon carbide.

[0084] In this embodiment, the method for forming the first inner wall 321 is chemical vapor deposition; in other embodiments, physical vapor deposition or atomic layer deposition can also be used to form the first inner wall 321.

[0085] In this embodiment, the thickness of the first inner wall 321 in the extending direction of the fin 302 is 2 - 15 nm. If the thickness of the first inner wall 321 is too small, it cannot effectively increase the distance between the subsequently formed first interconnect layer and the conductive layer, and short circuit between the first interconnect layer and the conductive layer will still occur; if the thickness of the first inner wall 321 is too large, the width of the first gap 322 between the first inner walls 321 in the extending direction of the fin 302 will be small, and the width of the first interconnect layer formed in the first gap 322 subsequently will be small, resulting in a large resistance of the interconnect structure. Therefore, the thickness range of the first inner wall 321 in the extending direction of the fin 302 is 2 - 15 nm.

[0086] In this embodiment, by forming the first inner wall 321 on the sidewall of the first opening 320 at the top of the gate structure 312, when forming the first interconnect layer in the first gap 322 between the first inner walls 321 subsequently, due to the existence of the first inner wall 321, the distance between the first interconnect layer and the conductive layer formed on the source-drain doping layer subsequently increases, reducing the possibility of short circuit, which is beneficial to improving the performance of the semiconductor structure.

[0087] Refer to Figure 11 , a first dielectric layer 323 is formed in the first gap 322.

[0088] In this embodiment, the material of the first dielectric layer 323 is silicon oxide.

[0089] In this embodiment, the method for forming the first dielectric layer 323 includes: filling the first void 322 with the first dielectric layer film (not shown), and the first dielectric layer film also covers the top surface of the interlayer dielectric layer 310, the sidewall 308, and the first inner sidewall 321; performing planarization on the first dielectric layer film until the top surface of the first dielectric layer film is flush with the top surface of the interlayer dielectric layer 310, and forming the first dielectric layer 323 in the first void 322.

[0090] In this embodiment, the method for forming the first dielectric layer film is chemical vapor deposition; in other embodiments, physical vapor deposition or atomic layer deposition may also be used to form the first dielectric layer film.

[0091] In this embodiment, chemical mechanical polishing process is used to planarize the first dielectric layer film.

[0092] Reference Figure 12 , etching the interlayer dielectric layer 310 on the source / drain doped layer 309 until the top surface of the source / drain doped layer 309 is exposed, and forming the second opening 330.

[0093] In this embodiment, the second opening 330 provides space for forming a conductive layer on the subsequent source / drain doped layer 309.

[0094] Reference Figure 13 , forming a conductive layer 331 in the second opening 330, and the top surface of the conductive layer 331 is lower than the top surface of the interlayer dielectric layer 310.

[0095] In this embodiment, the method for forming the conductive layer 331 includes: forming an initial conductive layer (not shown) in the second opening 330, and the top surface of the initial conductive layer is flush with the top surface of the interlayer dielectric layer 310; etching the initial conductive layer until the top surface of the initial conductive layer is lower than the top surface of the interlayer dielectric layer 310, and forming the conductive layer 331.

[0096] In this embodiment, the material of the conductive layer 331 is metal, including copper, tungsten, or aluminum.

[0097] In this embodiment, the process for forming the conductive layer 331 is electrochemistry plating; in other embodiments, physical vapor deposition may also be used to form the conductive layer 331.

[0098] The method for etching the initial conductive layer includes one or a combination of dry etching and wet etching processes.

[0099] In this embodiment, the function of the conductive layer 331 is to realize the electrical connection between the source / drain doped layer 309 and the outside subsequently.

[0100] Reference Figure 14 , a second inner wall 332 is formed on the sidewalls of the exposed second opening 330 (Reference Figure 13 ) of the conductive layer 331, and a second gap 333 is formed between the second inner walls 332.

[0101] In this embodiment, the second gap 333 provides space for subsequently forming a second interconnection layer on the conductive layer 331.

[0102] In this embodiment, the material of the second inner wall 332 is silicon nitride; in other embodiments, the material of the second inner wall 332 may also be silicon carbonitride or nitrogen-doped silicon carbide.

[0103] In this embodiment, the method for forming the second inner wall 332 is chemical vapor deposition; in other embodiments, physical vapor deposition or atomic layer deposition may also be used to form the second inner wall 332.

[0104] In this embodiment, the thickness of the second inner wall 332 in the extending direction of the fin 302 is 2 - 15 nm. If the thickness of the second inner wall 332 is too small, it cannot effectively increase the distance between the subsequently formed second interconnection layer and the gate structure, and short circuit between the second interconnection layer and the gate structure will still occur; if the thickness of the second inner wall 332 is too large, the width of the second gap 333 between the second inner walls 332 in the extending direction of the fin 302 will be smaller, and the width of the second interconnection layer formed in the second gap 333 subsequently will be smaller, resulting in a larger resistance of the interconnection structure. Therefore, the thickness range of the second inner wall 332 in the extending direction of the fin 302 is 2 - 15 nm.

[0105] In this embodiment, by forming the second inner wall 332 on the sidewalls of the second opening 330, when a second interconnection layer is subsequently formed in the second gap 333 between the second inner walls 332, since the second inner wall 332 exists between the second interconnection layer and the gate structure, the distance between the second interconnection layer and the gate structure is increased, reducing the possibility of short circuit, thereby being beneficial to improving the performance of the semiconductor structure.

[0106] Reference Figure 15 , after forming the second inner wall 332, a second dielectric layer 340 is formed on the interlayer dielectric layer 310, and the second dielectric layer 340 also fills the second gap 333.

[0107] In this embodiment, the second dielectric layer 340 also covers the top surfaces of the sidewall 308, the first dielectric layer 323, the first inner wall 321, and the second inner wall 332.

[0108] In this embodiment, the material of the second dielectric layer 340 is silicon oxide; in other embodiments, the material of the second dielectric layer 340 may also be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0109] In this embodiment, the material of the second dielectric layer 340 is the same as that of the first dielectric layer 323.

[0110] After forming the second dielectric layer 340, a third opening exposing the top of the gate structure 312 and a fourth opening exposing the top of the conductive layer 331 are formed in the second dielectric layer 340.

[0111] Specific methods for forming the third opening and the fourth opening include:

[0112] Referring to Figure 16 , a metal hard mask layer 350 and a patterned photoresist layer 360 are formed on the second dielectric layer 340, and the patterned photoresist layer 360 defines the positions and dimensions of the to-be-formed third opening and fourth opening.

[0113] Referring to Figure 17 , using the patterned photoresist layer 360 as a mask, the metal hard mask layer 350 is etched to form a patterned metal hard mask layer 351; the patterned photoresist layer 360 is removed.

[0114] Referring to Figure 18 , using the patterned metal hard mask layer 351 as a mask, the second dielectric layer 340 and the first dielectric layer 323 in the first void 322 are etched until the top of the gate structure 312 and the top of the conductive layer 331 are exposed, a third opening 341 is formed on the top of the gate structure 312, and a fourth opening 342 is formed on the top of the conductive layer 331.

[0115] In this embodiment, the bottom of the third opening 341 communicates with the top of the first void 322; the bottom of the fourth opening 342 communicates with the top of the second void 333.

[0116] In this embodiment, the process of etching the second dielectric layer 340 and the first dielectric layer 323 is a dry etching process; in other embodiments, a wet etching process may also be used to etch the second dielectric layer 340 and the first dielectric layer 323.

[0117] In this embodiment, the third opening 341 provides space for subsequent formation of the first interconnect layer; the second opening 342 provides space for subsequent formation of the second interconnect layer.

[0118] Reference Figure 19 A first interconnect layer 3411 is formed in the first gap 322 and the third opening 341; a second interconnect layer 3421 is formed in the second gap 333 and the fourth opening.

[0119] In this embodiment, the material of the first interconnect layer 3411 is metal, including aluminum, copper, nickel, etc.

[0120] In this embodiment, the function of the first interconnect layer 3411 is to connect different devices together to form a circuit, and at the same time, it can also transmit external electrical signals to different parts inside the semiconductor device, so as to form a semiconductor device with certain functions.

[0121] In this embodiment, the process for forming the first interconnect layer 3411 is an electrochemical plating process, because using the plating process can form the first interconnect layer 3411 with good density and high uniformity.

[0122] In this embodiment, due to the existence of the first inner sidewall 321, the distance between the first interconnect layer 3411 and the adjacent conductive layer 331 is increased, thus avoiding the short - circuit problem between the first interconnect layer 3411 and the conductive layer 331, and improving the electrical performance of the formed semiconductor structure.

[0123] In this embodiment, the material of the second interconnect layer 3421 is metal, including aluminum, copper, nickel, etc.

[0124] In this embodiment, the function of the second interconnect layer 3421 is to connect different devices together to form a circuit, and at the same time, it can also transmit external electrical signals to different parts inside the semiconductor device, so as to form a semiconductor device with certain functions.

[0125] In this embodiment, the process for forming the second interconnect layer 3421 is an electrochemical plating process, because using the plating process can form the second interconnect layer 3421 with good density and high uniformity.

[0126] In this embodiment, due to the existence of the second inner sidewall 332, the distance between the second interconnect layer 3421 and the adjacent gate structure 312 is increased, thus avoiding the short - circuit problem between the second interconnect layer 3421 and the gate structure 312, and improving the electrical performance of the formed semiconductor structure.

[0127] Correspondingly, the present invention also provides a semiconductor structure.

[0128] Reference Figure 18, the semiconductor structure includes: a substrate 300, on which an interlayer dielectric layer 310 is provided; a gate structure 312, located on the substrate 300, and the top surface of the gate structure 312 is lower than the top surface of the interlayer dielectric layer 310; source / drain doping layers 309, located in the substrate 300 on both sides of the gate structure 312; a first opening 320, located in the interlayer dielectric layer 310, and the first opening 320 exposes the top surface of the gate structure 312; a first inner sidewall 321, located on the sidewalls of the first opening 320, and there is a first gap 322 between the first inner sidewalls 321; a second opening 330, located in the interlayer dielectric layer 310, and the second opening 330 exposes the top surface of the source / drain doping layer 309; a conductive layer 331, located in the second opening 330, and the top surface of the conductive layer 331 is lower than the top surface of the interlayer dielectric layer 310; a second inner sidewall 332, located on the sidewalls of the second opening 330 exposed by the conductive layer 331, and there is a second gap 333 between the second inner sidewalls 332.

[0129] In this embodiment, the material of the first inner sidewall 321 is silicon nitride; in other embodiments, the material of the first inner sidewall 321 can also be silicon carbonitride or nitrogen-doped silicon carbide.

[0130] In this embodiment, the material of the second inner sidewall 332 is silicon nitride; in other embodiments, the material of the second inner sidewall 332 can also be silicon carbonitride or nitrogen-doped silicon carbide.

[0131] In this embodiment, the first gap 322 provides space for forming a first interconnect layer on the top of the gate structure 312. Since there are first inner sidewalls 321 on both sides of the first gap 322, the distance between the subsequently formed first interconnect layer and the conductive layer 331 is increased, avoiding short circuit between the first interconnect layer and the conductive layer 331, and improving the electrical performance of the formed semiconductor structure.

[0132] In this embodiment, the second gap 333 provides space for forming a second interconnect layer on the top of the conductive layer 331. Since there are second inner sidewalls 332 on both sides of the second gap 333, the distance between the subsequently formed second interconnect layer and the gate structure 312 is increased, avoiding short circuit between the second interconnect layer and the gate structure 312, and enhancing the electrical performance of the formed semiconductor structure.

[0133] Continue to refer to Figure 18 , the semiconductor structure further includes: a sidewall 308, located on the sidewalls of the gate structure 312, and the top surface of the sidewall 308 is flush with the top surface of the interlayer dielectric layer 310.

[0134] Continue to refer toFigure 18 The semiconductor structure further includes: a second dielectric layer 340 located on the interlayer dielectric layer 310; a third opening 341 within the second dielectric layer 340 and exposing the top of the gate structure 312; and a fourth opening 342 within the second dielectric layer 340 and exposing the top of the conductive layer 331.

[0135] In this embodiment, the material of the second dielectric layer 340 is silicon oxide; in other embodiments, the material of the second dielectric layer 340 may also be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0136] In this embodiment, the material of the second dielectric layer 340 is different from the materials of the first inner sidewall 321 and the second inner sidewall 332, and there is an etching selectivity ratio when etching the second dielectric layer 340 later, thereby avoiding etching damage to the first inner sidewall 321 and the second inner sidewall 332, and ensuring the distance between the first interconnect layer and the conductive layer formed later, as well as the distance between the second interconnect layer and the gate structure.

[0137] Reference Figure 19 The semiconductor structure further includes: a first interconnect layer 3411 located in the first gap 322 and the third opening 341; and a second interconnect layer 3421 located in the second gap 333 and the fourth opening 342.

[0138] In this embodiment, the material of the first interconnect layer 3411 is metal, including aluminum, copper, nickel, etc.

[0139] In this embodiment, the material of the second interconnect layer 3421 is metal, including aluminum, copper, nickel, etc.

[0140] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate, on which an interlayer dielectric layer is provided; A gate structure, located on the substrate, and the top surface of the gate structure is lower than the top surface of the interlayer dielectric layer; Source / drain doping layers, located in the substrate on both sides of the gate structure; A first opening, located in the interlayer dielectric layer, and the first opening exposes the top surface of the gate structure; A first inner sidewall, located on the sidewalls of the first opening, and there is a first gap between the first inner sidewalls; A second opening, located in the interlayer dielectric layer, and the second opening exposes the top surface of the source / drain doping layers; A conductive layer, located in the second opening, and the top surface of the conductive layer is lower than the top surface of the interlayer dielectric layer; A second inner sidewall, located on the sidewalls of the second opening exposed by the conductive layer, and there is a second gap between the second inner sidewalls.

2. The semiconductor structure according to claim 1, wherein Further comprising: A first interconnect layer, located in the first gap and on the top of the gate structure; A second interconnect layer, located in the second gap and on the top of the conductive layer.

3. The semiconductor structure according to claim 2, wherein, Further comprising: A second dielectric layer, the second dielectric layer is located on the interlayer dielectric layer, and part of the first interconnect layer and part of the second interconnect layer are also located in the second dielectric layer.

4. The semiconductor structure according to claim 1, characterized in that, The material of the first inner sidewall includes silicon nitride, silicon carbonitride or nitrogen-doped silicon carbide.

5. The semiconductor structure according to claim 1, wherein The material of the second inner sidewall includes silicon nitride, silicon carbonitride or nitrogen-doped silicon carbide.

6. The semiconductor structure according to claim 3, wherein, The material of the second dielectric layer is different from the material of the first inner sidewall and different from the material of the second inner sidewall, and the material of the second dielectric layer includes a low-k dielectric material, an ultra-low-k dielectric material or silicon oxide.

7. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, on which an interlayer dielectric layer, a gate structure located in the interlayer dielectric layer and source / drain doping layers located in the substrate on both sides of the gate structure are provided; Etching the gate structure until the top surface of the gate structure is lower than the top surface of the interlayer dielectric layer, and forming a first opening in the interlayer dielectric layer; Forming a first inner sidewall on the sidewalls of the first opening, and there is a first gap between the first inner sidewalls; Forming a first dielectric layer in the first gap; Etching the interlayer dielectric layer on the source / drain doping layers until the top surface of the source / drain doping layers is exposed, and forming a second opening; Forming a conductive layer in the second opening, and the top surface of the conductive layer is lower than the top surface of the interlayer dielectric layer; Forming a second inner sidewall on the sidewalls of the second opening exposed by the conductive layer, and there is a second gap between the second inner sidewalls.

8. The method for forming a semiconductor structure according to claim 7, wherein Further comprising: Forming a first interconnect layer in the first gap, and the first interconnect layer is located on the top of the gate structure; Forming a second interconnect layer in the second gap, and the second interconnect layer is located on the top of the conductive layer.

9. The method for forming a semiconductor structure according to claim 8, wherein, Before forming the first interconnect layer and the second interconnect layer, further comprising: forming a second dielectric layer on the interlayer dielectric layer, and the second dielectric layer also fills the second gap.

10. The method for forming a semiconductor structure according to claim 9, wherein, The step of forming the first interconnect layer in the first gap includes: Etch the second dielectric layer and the first dielectric layer in the first void until the top of the gate structure is exposed, and form a third opening in the second dielectric layer. Form a first interconnect layer in the first void and the third opening.

11. The method for forming a semiconductor structure according to claim 9, wherein, The step of forming a second interconnect layer in the second void includes: Etch the second dielectric layer until the top of the conductive layer is exposed, and form a fourth opening in the second dielectric layer. Form a second interconnect layer in the second void and the fourth opening.

12. The method for forming a semiconductor structure according to claim 7, wherein The method of forming a conductive layer in the second opening includes: Form an initial conductive layer in the second opening, and the top surface of the initial conductive layer is flush with the top surface of the interlayer dielectric layer. Etch the initial conductive layer until the top surface of the initial conductive layer is lower than the top surface of the interlayer dielectric layer to form the conductive layer.

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