Storage cell structure of static random access memory and memory

Abstract

The present invention provides a static random access memory (SRAM) memory cell structure, comprising interconnected transistor units and connection units. The transistor units include a first transmission transistor, a first common-gate complementary field-effect transistor, a second common-gate complementary field-effect transistor, and a second transmission transistor, arranged along a first direction. During manufacturing, a continuous fin structure can be used, eliminating the need to cut off the fin structure process, thereby reducing process risks and costs. The connection units include a word line, a first bit line, a second bit line, a first interconnect line, a second interconnect line, a first power line, and a second power line. The first and second bit lines are perpendicular to the first direction, while the word line, the first interconnect line, the second interconnect line, the first power line, and the second power line are parallel to the first direction. Combined with field-effect transistors, this greatly reduces the occupied area, improves integration, and further reduces costs. The present invention also provides a memory.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a storage unit structure of a static random access memory and a memory. Background Art

[0002] Static random-access memory (SRAM) is a type of random access memory. An SRAM cell typically consists of a pull-up transistor (PU), a pull-down transistor (PD), and a pass-gate transistor (PG). In practical applications, SRAM occupies a large circuit area, and its low integration density significantly increases chip cost.

[0003] Therefore, it is necessary to provide a novel static random access memory storage unit structure and memory to solve the above problems existing in the prior art. Summary of the Invention

[0004] The object of the present invention is to provide a storage unit structure of a static random access memory, thereby improving circuit integration and reducing manufacturing costs.

[0005] To achieve the above object, the memory cell structure of the static random access memory of the present invention includes a transistor unit and a connection unit connected to each other, wherein:

[0006] The transistor unit includes a first transmission tube, a first common-gate complementary field-effect transistor, a second common-gate complementary field-effect transistor, and a second transmission tube, which are sequentially arranged along a first direction, wherein a channel direction of the first transmission tube, a channel direction of the first common-gate complementary field-effect transistor, a channel direction of the second common-gate complementary field-effect transistor, and a channel direction of the second transmission tube are all parallel to the first direction;

[0007] The connection unit includes a word line, a first bit line, a second bit line, a first interconnection line, a second interconnection line, a first power line and a second power line. The word line is used to control the first transmission tube and the second transmission tube. The first bit line and the second bit line are used to realize signal transmission. The first interconnection line and the second interconnection line are used to realize internal connection of the transistor unit. The first power line and the second power line are used to supply power or ground the transistor unit. The first bit line and the second bit line are perpendicular to the first direction. The word line, the first interconnection line, the second interconnection line, the first power line, and the second power line are parallel to the first direction.

[0008] The beneficial effect of the storage cell structure of the static random access memory is that: the transistor unit includes a first transmission tube, a first common-gate complementary field-effect transistor, a second common-gate complementary field-effect transistor and a second transmission tube arranged in sequence along a first direction, and the channel direction of the first transmission tube, the channel direction of the first common-gate complementary field-effect transistor, the channel direction of the second common-gate complementary field-effect transistor and the channel direction of the second transmission tube are all parallel to the first direction, so that the storage cell structure of the static random access memory can use a continuous fin structure during manufacturing, without the need to cut off the fin structure process, thereby reducing process risks and costs, and the first bit line and the second bit line are perpendicular to the first direction, and the word line, the first interconnection line, the second interconnection line, the first power line and the second power line are parallel to the first direction. Combined with the field effect transistor, the occupied area is greatly reduced, the circuit integration is improved, and the cost is further reduced.

[0009] Optionally, the word line, the first interconnection line and the second interconnection line are metal interconnections on the top of the device, which has the beneficial effect of facilitating wiring and reducing process difficulty.

[0010] Optionally, the word line, the first interconnection line and the second interconnection line are located in the same or different metal interconnection layers on the top of the device. This has the beneficial effect of facilitating flexible wiring and avoiding wiring conflicts.

[0011] Optionally, the first power line and the second power line are metal interconnects on the top of the device or metal buried lines in the substrate. This has the beneficial effect of facilitating routing of the first power line and the second power line as metal interconnects on the top of the device, while facilitating routing of the first power line and the second power line as metal buried lines in the substrate reduces routing difficulty of the metal interconnects on the top of the device and avoids routing conflicts.

[0012] Optionally, the first bit line is disposed on a side of the first transmission transistor whose gate faces away from the first cascade complementary field-effect transistor, and the second bit line is disposed on a side of the second transmission transistor whose gate faces away from the second cascade complementary field-effect transistor. This advantageously reduces the wiring difficulty of the first and second bit lines and saves wiring space at the top of the device.

[0013] Optionally, the first common-gate complementary field-effect transistor includes a first N-type field-effect transistor and a first P-type field-effect transistor stacked together, and the second common-gate complementary field-effect transistor includes a second N-type field-effect transistor and a second P-type field-effect transistor stacked together. This has the beneficial effect of sharing a gate, reducing process difficulty and size, and greatly improving integration.

[0014] Optionally, the drain of the first N-type field-effect transistor and the drain of the first P-type field-effect transistor are both disposed on one side of the gate of the first cascade complementary field-effect transistor, and the source of the first N-type field-effect transistor and the source of the first P-type field-effect transistor are both disposed on the other side of the gate of the first cascade complementary field-effect transistor. This advantageously facilitates connection between the drain of the first N-type field-effect transistor and the drain of the first P-type field-effect transistor, greatly improving circuit integration while reducing process difficulty.

[0015] Optionally, the drain of the first N-type field-effect transistor and the drain of the first P-type field-effect transistor are both located on the side of the gate of the first cascade complementary field-effect transistor facing the first transmission transistor, and the source of the first N-type field-effect transistor and the source of the first P-type field-effect transistor are both located on the side of the gate of the first cascade complementary field-effect transistor facing the second cascade complementary field-effect transistor. This advantageously facilitates the connection between the drain of the first N-type field-effect transistor, the drain of the first P-type field-effect transistor, the source of the first transmission transistor, and the first interconnect, greatly improving circuit integration while reducing process difficulty.

[0016] Optionally, the drain of the second N-type field-effect transistor and the drain of the second P-type field-effect transistor are both arranged on one side of the gate of the second cascade complementary field-effect transistor, and the source of the second N-type field-effect transistor and the source of the second P-type field-effect transistor are both arranged on the other side of the gate of the second cascade complementary field-effect transistor. This has the beneficial effect of facilitating the connection between the drain of the second N-type field-effect transistor and the drain of the second P-type field-effect transistor, greatly improving circuit integration, and reducing process difficulty.

[0017] Optionally, the drain of the second N-type field-effect transistor and the drain of the second P-type field-effect transistor are both arranged on the side of the gate of the second commensurate complementary field-effect transistor facing the second transmission transistor, and the source of the second N-type field-effect transistor and the source of the second P-type field-effect transistor are both arranged on the side of the gate of the second commensurate complementary field-effect transistor facing the first commensurate complementary field-effect transistor. This advantageously facilitates the connection between the drain of the second N-type field-effect transistor, the drain of the second P-type field-effect transistor, the source of the second N-type field-effect transistor, and the second interconnect, greatly improving circuit integration while reducing process difficulty.

[0018] Optionally, the source of the first P-type field-effect transistor is arranged opposite to the source of the second P-type field-effect transistor, and the source of the first N-type field-effect transistor is arranged opposite to the source of the second N-type field-effect transistor. This advantageously facilitates connecting the source of the first P-type field-effect transistor and the source of the second P-type field-effect transistor to the second power line, and connecting the source of the first N-type field-effect transistor and the source of the second N-type field-effect transistor to the first power line, thereby greatly improving circuit integration and reducing process difficulty.

[0019] Optionally, the gate height of the first transmission transistor, the gate height of the first cascade complementary field-effect transistor, the gate height of the second cascade complementary field-effect transistor, and the gate height of the second transmission transistor are the same; the channel, source, and drain of the first P-type field-effect transistor and the second P-type field-effect transistor are at the same height; and the channel, source, and drain of the first N-type field-effect transistor and the second N-type field-effect transistor are at the same height. This advantageously allows for the same gate height to facilitate simultaneous formation of the gates of all transistors, significantly reducing process complexity.

[0020] Optionally, the heights of the channel, source and drain of the first transmission tube are the same as the heights of the channel, source and drain of at least one of the first P-type field effect transistor and the first N-type field effect transistor.

[0021] Optionally, the heights of the channel, source and drain of the second transmission transistor are the same as the heights of the channel, source and drain of at least one of the second P-type field effect transistor and the second N-type field effect transistor.

[0022] Optionally, the number of channels of the first transmission transistor, the second transmission transistor, the first N-type field effect transistor, the second N-type field effect transistor, the first P-type field effect transistor, and the second P-type field effect transistor is greater than or equal to 1. This has the beneficial effect of facilitating low power consumption or high speed.

[0023] Optionally, both the first transmission tube and the second transmission tube are field effect transistors.

[0024] Optionally, the first transmission tube and the second transmission tube are both N-type field effect transistors or P-type field effect transistors.

[0025] The present invention also provides a memory comprising at least one storage unit structure of the static random access memory.

[0026] The beneficial effect of the memory is that the memory cell structure of the static random access memory is applied, thereby improving the integration of the circuit and reducing the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a cross-sectional view of a memory cell structure of a static random access memory in some embodiments of the present invention;

[0028] Figure 2 for Figure 1 A top view of a memory cell structure of a static random access memory;

[0029] Figure 3 A top view of a memory in some embodiments of the present invention;

[0030] Figure 4 A circuit schematic diagram of a storage unit structure of a static random access memory in some embodiments of the present invention;

[0031] Figure 5 Schematic diagram of the structure of two-channel field effect transistors in some embodiments of the present invention;

[0032] Figure 6 sectional views of memory cell structures of static random access memories in some further embodiments of the present invention;

[0033] Figure 7 are cross-sectional views of memory cell structures of static random access memories in other embodiments of the present invention;

[0034] Figure 8 2 is a cross-sectional view of a memory cell structure of a static random access memory in some further embodiments of the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the common meanings understood by people with ordinary skills in the field to which the present invention belongs. The words "including" and similar words used in this article mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0036] In view of the problems existing in the prior art, an embodiment of the present invention provides a memory including at least one storage unit structure of a static random access memory.

[0037] In some embodiments, the memory cell structure of the static random access memory includes a transistor unit and a connection unit.

[0038] Figure 1 FIG1 is a cross-sectional view of a memory cell structure of a static random access memory in some embodiments of the present invention. Figure 1 The transistor unit includes a first transmission tube 101, a first common-gate complementary field-effect transistor 102, a second common-gate complementary field-effect transistor 103, and a second transmission tube 104 arranged in sequence along a first direction, and the channel direction of the first transmission tube 101, the channel direction of the first common-gate complementary field-effect transistor 102, the channel direction of the second common-gate complementary field-effect transistor 103, and the channel direction of the second transmission tube 104 are all parallel to the first direction.

[0039] In some embodiments, the first transmission transistor and the second transmission transistor are both field effect transistors. In some further embodiments, the first transmission transistor and the second transmission transistor are both N-type field effect transistors or P-type field effect transistors.

[0040] Reference Figure 1 The connection unit includes a word line 201, a first bit line 202, a second bit line 203, a first interconnect line 204, a second interconnect line (not shown), a first power line (not shown), and a second power line 205. The word line is used to control the first and second transmission transistors. The first and second bit lines are used for signal transmission. The first and second interconnect lines are used to achieve internal connections within the transistor unit. The first and second power lines are used to supply power or ground to the transistor unit. The first and second bit lines 202 and 203 are perpendicular to the first direction. The word line 201, the first and second interconnect lines 204, the second interconnect line, the first and second power lines 205 are parallel to the first direction. The first power line is grounded, and the second power line 205 is connected to an operating voltage.

[0041] Reference Figure 1The first bit line 202 is connected to the first end of the first transmission transistor 101, the second bit line 203 is connected to the first end of the second transmission transistor 104, the word line 201 is connected to the gate of the first transmission transistor 101 and the gate of the second transmission transistor 104 through a metal through-hole, the first interconnection line 204 is connected to the second end of the first transmission transistor 101, the two drains of the first common-gate complementary field-effect transistor 102, and the gate of the second common-gate complementary field-effect transistor 103 through a metal through-hole, and the second interconnection line (not shown in the figure) is connected to the second transmission transistor 101 through a metal through-hole. The second end of 104, the two drains of the second common-gate complementary field effect transistor 103 and the gate of the first common-gate complementary field effect transistor 102 are connected, the second power line 205 is connected to the source of the P-type field effect transistor of the first common-gate complementary field effect transistor 102 and the source of the P-type transistor of the second common-gate complementary field effect transistor 103 through a metal through-hole, and the first power line is connected to the source of the N-type field effect transistor of the first common-gate complementary field effect transistor 102 and the source of the N-type transistor of the second common-gate complementary field effect transistor 103 through a metal through-hole.

[0042] In some embodiments, the first transmission transistor and the second transmission transistor are both N-type field effect transistors. In some further embodiments, the first transmission transistor and the second transmission transistor are both P-type field effect transistors.

[0043] In some embodiments, the first end of the first transmission tube is a drain, and the second end of the first transmission tube is a source.

[0044] In some embodiments, the first end of the first transmission tube is a source, and the second end of the first transmission tube is a drain.

[0045] In some embodiments, the first end of the second transmission tube is a drain, and the second end of the second transmission tube is a source.

[0046] In some embodiments, the first end of the second transmission tube is a source, and the second end of the second transmission tube is a drain.

[0047] In some embodiments, the word line, the first interconnect line and the second interconnect line are metal interconnect lines on the top of the device, and the word line, the first interconnect line and the second interconnect line are located in the same or different metal interconnect layers on the top of the device.

[0048] In some embodiments, the first power line and the second power line are metal interconnects on the top of the device or buried metal lines in the substrate. When the first power line and the second power line are metal interconnects on the top of the device, the first power line, the word line, the first interconnect line, and the second interconnect line are located on the same or different metal interconnect layers on the top of the device, and the second power line, the word line, the first interconnect line, and the second interconnect line are located on the same or different metal interconnect layers on the top of the device. Optionally, when the first power line and the second power line are metal interconnects on the top of the device, the first power line, the second power line, the word line, the first interconnect line, and the second interconnect line are located on the same metal interconnect layer on the top of the device.

[0049] Reference Figure 1 The word line 201, the first interconnection line 204 and the second interconnection line (not shown in the figure) are located in the same metal interconnection layer at the top of the device, for example, the first metal interconnection layer at the top of the device, and the first power line and the second power line 205 are both metal buried lines in the substrate.

[0050] In some embodiments, the first common-gate complementary field-effect transistor includes a first N-type field-effect transistor and a first P-type field-effect transistor stacked together, and the second common-gate complementary field-effect transistor includes a second N-type field-effect transistor and a second P-type field-effect transistor stacked together.

[0051] In some embodiments, the first N-type field effect transistor of the first cascade complementary field effect transistor is stacked above the first P-type field effect transistor. In still other embodiments, the first P-type field effect transistor of the first cascade complementary field effect transistor is stacked above the first N-type field effect transistor.

[0052] In some embodiments, the second N-type field effect transistor of the second cascade complementary field effect transistor is stacked above the second P-type field effect transistor. In still other embodiments, the second P-type field effect transistor of the second cascade complementary field effect transistor is stacked above the second N-type field effect transistor.

[0053] In some embodiments, the first transmission tube, the first common-gate complementary field-effect transistor, the second common-gate complementary field-effect transistor and the second transmission tube share the same substrate, the gate height of the first transmission tube, the gate height of the first common-gate complementary field-effect transistor, the gate height of the second common-gate complementary field-effect transistor and the gate height of the second transmission tube are the same, the channel, source and drain of the first P-type field-effect transistor and the second P-type field-effect transistor are at the same height, and the channel, source and drain of the first N-type field-effect transistor and the second N-type field-effect transistor are at the same height.

[0054] In some embodiments, the heights of the channel, source, and drain of the first transmission transistor are the same as the heights of the channel, source, and drain of at least one of the first P-type field effect transistor and the first N-type field effect transistor.

[0055] In some embodiments, the heights of the channel, source, and drain of the second transmission transistor are the same as the heights of the channel, source, and drain of at least one of the second P-type field effect transistor and the second N-type field effect transistor.

[0056] Reference Figure 1 The gate height of the first transmission tube 101, the gate height of the first common-gate complementary field-effect transistor 102, the gate height of the second common-gate complementary field-effect transistor 103 and the gate height of the second transmission tube 104 are the same.

[0057] Reference Figure 1 The first transmission tube 101, the first N-type field effect transistor 1021, the second N-type field effect transistor 1031 and the second transmission tube 104 are located at the same height, and the first P-type field effect transistor 1022 and the second P-type field effect transistor 1032 are located at the same height.

[0058] Reference Figure 1 , the channels of all transistors are formed by the same fin structure.

[0059] In some embodiments, the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are both arranged on one side of the gate of the first common-gate complementary field effect transistor, and the source of the first N-type field effect transistor and the source of the first P-type field effect transistor are both arranged on the other side of the gate of the first common-gate complementary field effect transistor.

[0060] In some optional embodiments, the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are both arranged on the side of the gate of the first common-gate complementary field effect transistor facing the second common-gate complementary field effect transistor, and the source of the first N-type field effect transistor and the source of the first P-type field effect transistor are both arranged on the side of the gate of the first common-gate complementary field effect transistor facing the first transmission tube.

[0061] In some optional embodiments, the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are both arranged on the side of the gate of the first common-gate complementary field effect transistor facing the first transmission tube, and the source of the first N-type field effect transistor and the source of the first P-type field effect transistor are both arranged on the side of the gate of the first common-gate complementary field effect transistor facing the second common-gate complementary field effect transistor.

[0062] In some embodiments, the drain of the second N-type field effect transistor and the drain of the second P-type field effect transistor are both arranged on one side of the gate of the second common-gate complementary field effect transistor, and the source of the second N-type field effect transistor and the source of the second P-type field effect transistor are both arranged on the other side of the gate of the second common-gate complementary field effect transistor.

[0063] In some optional embodiments, the drain of the second N-type field effect transistor and the drain of the second P-type field effect transistor are both arranged on the side of the gate of the second common-gate complementary field effect transistor facing the first common-gate complementary field effect transistor, and the source of the second N-type field effect transistor and the source of the second P-type field effect transistor are both arranged on the side of the gate of the second common-gate complementary field effect transistor facing the second transmission tube.

[0064] In some optional embodiments, the drain of the second N-type field effect transistor and the drain of the second P-type field effect transistor are both arranged on the side of the gate of the second common-gate complementary field effect transistor facing the second transmission tube, and the source of the second N-type field effect transistor and the source of the second P-type field effect transistor are both arranged on the side of the gate of the second common-gate complementary field effect transistor facing the first common-gate complementary field effect transistor.

[0065] In some optional embodiments, the source of the first P-type field effect transistor is arranged opposite to the source of the second P-type field effect transistor, and the source of the first N-type field effect transistor is arranged opposite to the source of the second N-type field effect transistor.

[0066] In some embodiments, the first bit line is arranged on a side of the gate of the first transmission tube facing away from the first common-gate complementary field effect transistor, and the second bit line is arranged on a side of the gate of the second transmission tube facing away from the second common-gate complementary field effect transistor.

[0067] Reference Figure 1, the drain of the first N-type field effect transistor faces the source of the first transmission transistor 101, the drain of the first P-type field effect transistor and the drain of the first N-type field effect transistor are located on the same side of the gate of the first common-gate complementary field effect transistor, the drain of the second N-type field effect transistor faces the source of the second transmission transistor 104, the drain of the second P-type field effect transistor and the drain of the second N-type field effect transistor are located on the same side of the gate of the second common-gate complementary field effect transistor, the source of the first N-type field effect transistor faces the source of the second N-type field effect transistor, and the source of the first P-type field effect transistor faces the source of the second P-type field effect transistor.

[0068] Reference Figure 1 A gate dielectric layer 105 is provided between the channels and gates of the first transmission tube 101, the second transmission tube 104, the first N-type field effect transistor 1021, the first P-type field effect transistor 1022, the second N-type field effect transistor 1031 and the second P-type field effect transistor 1032.

[0069] Figure 2 for Figure 1 The top view of the memory cell structure of the static random access memory is shown. Figure 2 The word line 201 is located between the first interconnection line 204 and the second interconnection line 206 , and the first bit line 202 and the second bit line 203 are perpendicular to the word line 201 .

[0070] Figure 3 FIG. 1 is a top view of a memory in some embodiments of the present invention. Figure 2 and Figure 3 The memory cell structures of a row of the static random access memory share a word line 201 , and the memory cell structures of a column of the static random access memory share a first bit line 202 and a second bit line 203 .

[0071] In some embodiments, the number of channels of the first transmission tube, the second transmission tube, the first N-type field effect transistor, the second N-type field effect transistor, the first P-type field effect transistor and the second P-type field effect transistor is greater than or equal to 1.

[0072] Figure 4 FIG1 is a circuit diagram of a memory cell structure of a static random access memory in some embodiments of the present invention. Figure 4, field effect transistor PD1 is equivalent to the first N-type field effect transistor, field effect transistor PD2 is equivalent to the second N-type field effect transistor, field effect transistor PG1 is equivalent to the first transmission transistor, field effect transistor PG2 is equivalent to the second transmission transistor, field effect transistor PU1 is equivalent to the first P-type field effect transistor, P-type field effect transistor PU2 is equivalent to the second P-type field effect transistor, bit line BL is equivalent to the first bit line, and bit line BLB is equivalent to the second bit line.

[0073] In some embodiments, the first transmission tube, the second transmission tube, the first N-type field effect transistor, the second N-type field effect transistor, the first P-type field effect transistor and the second P-type field effect transistor can all be referred to as field effect transistors. When the number of channels of a field effect transistor is greater than or equal to 2, the sources of all channels are epitaxially grown together to form the source of the transistor, and the drains of all channels are epitaxially grown together to form the drain of the field effect transistor.

[0074] In some other embodiments, when the number of channels of a field effect transistor is greater than or equal to 2, the sub-sources of all channels are interconnected through metal to form the source of the transistor, and the sub-drains of all channels are interconnected through metal to form the drain of the field effect transistor.

[0075] Figure 5 Schematic diagram of the structure of two-channel field effect transistor in some embodiments of the present invention. Figure 5 The field effect transistor includes two channels 301, a gate 302, a source 303, a drain 304, a gate dielectric layer 105 and a substrate (not shown in the figure). The sub-source electrodes 3031 of the two channels are interconnected by a first metal 3032 to form the source 303 of the field effect transistor. The sub-drain electrodes 3041 of the two channels are interconnected by a second metal 3042 to form the drain 304 of the field effect transistor. The gate dielectric layer 105 is arranged between the channel 301 and the gate.

[0076] In some embodiments, the shape of the metal through hole is not limited, as long as it can achieve connection between the source, drain, gate, word line, first bit line, second bit line, first interconnection line, second interconnection line, first power line and second power line.

[0077] Figure 6 2 is a cross-sectional view of a memory cell structure of a static random access memory according to some other embodiments of the present invention. Figure 6 and Figure 1The difference is that the first transmission tube 101, the first P-type field effect transistor 1022, the second P-type field effect transistor 1032, and the second transmission tube 104 are located at the same height, the drain of the first P-type field effect transistor faces the source of the first transmission tube 101, the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are located on the same side of the gate of the first common-gate complementary field effect transistor, the drain of the second P-type field effect transistor faces the source of the second transmission tube 104, and the drain of the second N-type field effect transistor and the drain of the second P-type field effect transistor are located on the same side of the gate of the second common-gate complementary field effect transistor.

[0078] Figure 7 2 is a cross-sectional view of a memory cell structure of a static random access memory according to some other embodiments of the present invention. Figure 7 and Figure 1 The difference is that the first transmission tube 101, the first N-type field effect transistor 1021 and the second N-type field effect transistor 1031 are located at the same height, the second transmission tube 104, the first P-type field effect transistor 1022 and the second P-type field effect transistor 1032 are located at the same height, the drain of the second P-type field effect transistor faces the source of the second transmission tube 104, and the drain of the second N-type field effect transistor and the drain of the second P-type field effect transistor are located on the same side of the gate of the second common-gate complementary field effect transistor.

[0079] Figure 8 2 is a cross-sectional view of a memory cell structure of a static random access memory in some further embodiments of the present invention. Figure 8 and Figure 1 The difference is that the first transmission tube 101 has two channels, which are respectively located at the same height as the channel of the first N-type field effect transistor 1021 and the channel of the first P-type field effect transistor, and the sub-drains of the two channels of the first transmission tube 101 are connected in parallel through the third metal 1011 to form the drain of the first transmission tube 101, and the sub-sources of the two channels of the first transmission tube 101 are connected in parallel through the fourth metal 1012 to form the source of the first transmission tube 101. The second transmission tube 104 has two channels, which are respectively located at the same height as the channel of the second N-type field effect transistor 1031 and the channel of the second P-type field effect transistor 1032, and the sub-drains of the two channels of the second transmission tube 104 are connected in parallel through the fifth metal 1041 to form the drain of the second transmission tube 104, and the sub-sources of the two channels of the second transmission tube 104 are connected in parallel through the sixth metal 1042 to form the source of the second transmission tube 104.

[0080] While the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations of these embodiments are possible. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the claims. Furthermore, the invention described herein is susceptible to other embodiments and may be practiced or implemented in a variety of ways.

Claims

1. A memory cell structure of a static random access memory, characterized in that: It includes transistor units and connection units connected to each other, wherein, The transistor unit includes a first transmission tube, a first common-gate complementary field-effect transistor, a second common-gate complementary field-effect transistor, and a second transmission tube, which are sequentially arranged along a first direction, wherein a channel direction of the first transmission tube, a channel direction of the first common-gate complementary field-effect transistor, a channel direction of the second common-gate complementary field-effect transistor, and a channel direction of the second transmission tube are all parallel to the first direction; The connection unit includes a word line, a first bit line, a second bit line, a first interconnection line, a second interconnection line, a first power line and a second power line, the word line is used to control the first transmission transistor and the second transmission transistor, the first bit line and the second bit line are used to realize signal transmission, the first interconnection line and the second interconnection line are used to realize internal connection of the transistor unit, the first power line and the second power line are used to supply power or ground the transistor unit, the first bit line and the second bit line are perpendicular to the first direction, and the word line, the first interconnection line, the second interconnection line, the first power line, and the second power line are parallel to the first direction; The first bit line is connected to the first end of the first transmission transistor, the second bit line is connected to the first end of the second transmission transistor, the word line is connected to the gate of the first transmission transistor and the gate of the second transmission transistor through a metal through-hole, the first interconnection line is connected to the second end of the first transmission transistor, the two drains of the first cascade complementary field-effect transistor, and the gate of the second cascade complementary field-effect transistor through a metal through-hole, the second interconnection line is connected to the second end of the second transmission transistor, the two drains of the second cascade complementary field-effect transistor, and the gate of the first cascade complementary field-effect transistor through a metal through-hole, the second power line is connected to the source of the first cascade complementary field-effect transistor and the source of the second cascade complementary field-effect transistor through a metal through-hole, and the first power line is connected to the source of the first cascade complementary field-effect transistor and the source of the second cascade complementary field-effect transistor through a metal through-hole.

2. The memory cell structure of the static random access memory according to claim 1, wherein: The word line, the first interconnect line and the second interconnect line are device top metal interconnect lines.

3. The memory cell structure of the static random access memory according to claim 2, wherein: The word line, the first interconnect line and the second interconnect line are located on the same or different metal interconnect layers on the top of the device.

4. The memory cell structure of the static random access memory according to claim 1, wherein: The first power line and the second power line are metal interconnection lines on the top of the device or metal buried lines in the substrate.

5. The memory cell structure of the static random access memory according to claim 1, wherein: The first bit line is arranged on a side of the gate of the first transmission tube facing away from the first common-gate complementary field effect transistor, and the second bit line is arranged on a side of the gate of the second transmission tube facing away from the second common-gate complementary field effect transistor.

6. The memory cell structure of the static random access memory according to claim 1, wherein: The first common-gate complementary field-effect transistor includes a first N-type field-effect transistor and a first P-type field-effect transistor that are stacked, and the second common-gate complementary field-effect transistor includes a second N-type field-effect transistor and a second P-type field-effect transistor that are stacked.

7. The memory cell structure of the static random access memory according to claim 6, wherein: The drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are both arranged on one side of the gate of the first common-gate complementary field effect transistor, and the source of the first N-type field effect transistor and the source of the first P-type field effect transistor are both arranged on the other side of the gate of the first common-gate complementary field effect transistor.

8. The memory cell structure of the static random access memory according to claim 7, wherein: The drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are both arranged on the side of the gate of the first common-gate complementary field effect transistor facing the first transmission tube, and the source of the first N-type field effect transistor and the source of the first P-type field effect transistor are both arranged on the side of the gate of the first common-gate complementary field effect transistor facing the second common-gate complementary field effect transistor.

9. The memory cell structure of the static random access memory according to claim 6, wherein: The drain of the second N-type field effect transistor and the drain of the second P-type field effect transistor are both arranged on one side of the gate of the second common-gate complementary field effect transistor, and the source of the second N-type field effect transistor and the source of the second P-type field effect transistor are both arranged on the other side of the gate of the second common-gate complementary field effect transistor.

10. The memory cell structure of the static random access memory according to claim 9, wherein: The drain of the second N-type field effect transistor and the drain of the second P-type field effect transistor are both arranged on the side of the gate of the second common-gate complementary field effect transistor facing the second transmission tube, and the source of the second N-type field effect transistor and the source of the second P-type field effect transistor are both arranged on the side of the gate of the second common-gate complementary field effect transistor facing the first common-gate complementary field effect transistor.

11. The memory cell structure of the static random access memory according to claim 6, wherein: The source of the first P-type field effect transistor is arranged opposite to the source of the second P-type field effect transistor, and the source of the first N-type field effect transistor is arranged opposite to the source of the second N-type field effect transistor.

12. The memory cell structure of the static random access memory according to claim 6, wherein: The gate height of the first transmission tube, the gate height of the first common-gate complementary field-effect transistor, the gate height of the second common-gate complementary field-effect transistor and the gate height of the second transmission tube are the same; the channel, source and drain of the first P-type field-effect transistor and the second P-type field-effect transistor are at the same height; and the channel, source and drain of the first N-type field-effect transistor and the second N-type field-effect transistor are at the same height.

13. The memory cell structure of the static random access memory according to claim 12, wherein: The heights of the channel, source, and drain of the first transmission transistor are the same as the heights of the channel, source, and drain of at least one of the first P-type field effect transistor and the first N-type field effect transistor.

14. The memory cell structure of the static random access memory according to claim 12, wherein: The heights of the channel, source, and drain of the second transmission transistor are the same as the heights of the channel, source, and drain of at least one of the second P-type field effect transistor and the second N-type field effect transistor.

15. The memory cell structure of the static random access memory according to claim 6, wherein: The number of channels of the first transmission tube, the second transmission tube, the first N-type field effect transistor, the second N-type field effect transistor, the first P-type field effect transistor, and the second P-type field effect transistor is greater than or equal to 1.

16. The memory cell structure of the static random access memory according to claim 1, wherein: The first transmission tube and the second transmission tube are both field effect transistors.

17. The memory cell structure of the static random access memory according to claim 16, wherein: The first transmission tube and the second transmission tube are both N-type field effect transistors or P-type field effect transistors.

18. A memory, characterized in that: A storage cell structure comprising at least one static random access memory according to any one of claims 1 to 17.

Images