3D SONOS memory structure and process method

Abstract

The present invention discloses a 3D SONOS memory comprising a memory cell comprising a select transistor and a storage transistor. The select transistors of each two memory cells share a common source region. The select transistor gates of the select transistors in the memory cells are trench-type and extend deep into the semiconductor substrate. The depth of the trench-type select transistor gate determines the length of the select transistor channel. The select transistor gates are also elevated above the surface of the semiconductor substrate. The storage transistor gates are located on either side of the select transistor gate that is elevated above the semiconductor substrate, serving as the storage transistor gates of two adjacent memory cells. The bottom of the trench-type select gate serves as the source region of the select transistor, serving as a shared source region for the select transistors of the two adjacent memory cells. Drain regions for the storage transistors of the two adjacent memory cells are located in the substrate on either side of the storage transistor gate. The present invention also discloses a process for the 3D SONOS memory.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device design and manufacturing technology, and in particular to a 3D SONOS memory structure and process method. Background Art

[0002] With the rapid popularization of electronic products, flash memory has become a mainstream storage medium and has been rapidly promoted and popularized, and its technology has also developed rapidly. Non-volatile memory (NVM) technology mainly includes floating gate technology and SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) technology based on the storage medium, and mainly includes single-gate (1-transistor), split-gate (split-gate), and dual-gate (2-transistor) technologies based on the structure. Due to its long life, non-volatility, low price, and easy programming and erasing, Flash has been increasingly widely used in various embedded electronic products such as financial IC cards and automotive electronics. Increasing storage integration density helps save chip area and reduce manufacturing costs. With the development of mainstream process technologies and the increasing demand for Flash devices, split-gate Flash based on a split-gate structure has attracted widespread attention. Compared to traditional Flash, split-gate Flash memory, as a type of Flash memory, has attracted greater attention in both single- and embedded products due to its efficient programming speed and ability to completely avoid over-erase. Currently, split-gate Flash memory has been widely used in personal computers, digital devices, mobile terminals, smart cards, and other products. This novel split-gate Flash performs superiorly in terms of reliability and over-erase resistance. Moreover, due to its compact structure, more storage cells can be integrated into the same chip area, thus optimizing capacity. However, due to the rapid increase in data volume in the current information age, further optimizing memory structure to achieve higher capacity is a constant pursuit in the industry. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a process method for a 3D SONOS memory to form a memory unit with a more compact structure.

[0004] The process method of the 3D SONOS memory of the present invention comprises the following process steps:

[0005] The first step is to provide a semiconductor substrate, first form a pad oxide layer on the semiconductor substrate, and then form a silicon nitride hard mask layer on the surface of the pad oxide layer;

[0006] The second step is to photolithographically and etch the silicon nitride hard mask layer, open the silicon nitride hard mask layer and etch downward to form a trench, wherein the trench extends deep into the semiconductor substrate;

[0007] The third step is to form a first oxide layer inside the trench in the semiconductor substrate;

[0008] Step 4: forming a sacrificial dielectric layer on the entire surface of the semiconductor substrate, wherein the sacrificial dielectric layer also covers the interior of the trench;

[0009] The fifth step is to etch the sacrificial dielectric layer to remove the sacrificial dielectric layer on the surface of the semiconductor substrate, as well as the sacrificial dielectric layer and the oxide layer at the bottom of the trench; and then perform ion implantation to form a first implantation region at the bottom of the trench;

[0010] Step 6: removing the sacrificial dielectric layer;

[0011] Step 7: growing a first polysilicon layer and performing a grinding process;

[0012] Step 8: growing a second oxide layer on top of the polysilicon in the trench;

[0013] Step 9: removing the silicon nitride hard mask layer;

[0014] Step 10: growing an isolation oxide layer;

[0015] Step 11: etching and removing the isolation oxide layer and the pad oxide layer;

[0016] Step 12: forming an ONO layer on the entire surface of the semiconductor substrate;

[0017] Step 13: forming a second polysilicon layer on the entire surface of the semiconductor substrate;

[0018] In the fourteenth step, the formed second polysilicon layer is etched, and then the second implantation region is implanted; and the ONO layer is etched.

[0019] A further improvement is that in the second step, the silicon nitride hard mask layer and the liner oxide layer are etched away, and the depth of the trench determines the length of the select pipe channel.

[0020] A further improvement is that in the third step, the first oxide layer covers the inside of the trench, including the sidewalls and the bottom. The first oxide layer serves as the gate dielectric layer of the selection tube, and its thickness determines the thickness of the gate dielectric layer of the selection tube.

[0021] A further improvement is that, in the fourth step, the sacrificial dielectric layer is a silicon nitride layer or a silicon oxide layer.

[0022] A further improvement is that, in the fifth step, the first injection region is the source region of the selection transistor in the memory unit, and its doping type depends on the type of the memory.

[0023] A further improvement is that in the seventh step, the first polysilicon layer fills the trench and serves as the selection tube gate of the storage unit in the memory; the grinding process is a CMP process, and the first polysilicon layer grown on the surface of the silicon nitride hard mask layer is removed by the grinding process, and the grinding ends at the surface of the silicon nitride hard mask layer.

[0024] A further improvement is that, in the ninth step, the silicon nitride hard mask layer is removed by a wet etching process to remove the entire silicon nitride hard mask layer.

[0025] A further improvement is that, in the tenth step, the isolation oxide layer is grown on the entire surface of the semiconductor substrate, and at the same time, the side surfaces of the first polysilicon layer exposed after the silicon nitride hard mask layer is removed are wrapped.

[0026] A further improvement is that in the eleventh step, the isolation oxide layer and the liner oxide layer on the surface of the semiconductor substrate are completely removed, and only the sidewalls and top of the first polysilicon layer exposed on the surface of the semiconductor substrate retain a certain thickness of isolation oxide layer or second oxide layer.

[0027] A further improvement is that, in the twelfth step, the ONO layer serves as the charge storage layer of the storage tube.

[0028] A further improvement is that in the fourteenth step, the second polysilicon layer is etched to form a storage transistor gate of a storage unit in the memory; and the second injection region is a drain region of the storage transistor.

[0029] A further improvement is that the process method is suitable for producing P-type SONOS or N-type SONOS; for P-type SONOS, the injection type of the source region and the drain region is P-type; for N-type SONOS, the injection type of the source region and the drain region is N-type, and before performing the first step, it is necessary to perform P-type well injection to form a P well, and then manufacture devices in the formed P well.

[0030] The 3D SONOS memory structure of the present invention is composed of multiple memory cells. Each memory cell includes a select transistor and a storage transistor. The select transistors of each two adjacent memory cells share a common source region. The select transistor gates of the select transistors in each memory cell are trench-type, extending deep into the semiconductor substrate. The depth of the trench-type select transistor gate determines the length of the select transistor channel. The select transistor gate is also elevated above the surface of the semiconductor substrate. The storage transistor gates are located on either side of the select transistor gate that is elevated above the semiconductor substrate, serving as the storage transistor gates of the two adjacent memory cells. The bottom of the trench-type select gate serves as the source region of the select transistor, serving as the shared source region for the select transistors of the two adjacent memory cells. The substrate on either side of the storage transistor gate contains drain regions for the storage transistors of the two adjacent memory cells.

[0031] The 3D SONOS memory structure described in this invention consists of a selector and a storage gate, with the storage gates positioned horizontally and the selector vertically. The selector tubes of two adjacent storage cells share a source region, and the selector tubes are 3D structures extending deep into the silicon wafer. The erase and write operations of this memory are similar to those of traditional two-tube memories. During read operations, one storage tube can be turned off, and a voltage applied from the source terminal can be used to read the state of the other storage tube. In the manufacturing process, the channel length of the selector tube in this invention is defined by the etching depth in the longitudinal direction of the silicon wafer (i.e., the thickness direction), making it suitable for the manufacture of long-channel devices and facilitating area reduction. The width of a single storage tube is defined by self-aligned etching of the polysilicon gate, reducing the number of photomasks and process costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figures 1 to 14 Schematic diagram of the manufacturing process steps of the 3D SONOS memory structure of the present invention.

[0033] Figure 15 1 is a flow chart of the manufacturing process steps of the 3D SONOS memory structure described in the present invention.

[0034] Description of Reference Numerals

[0035] 1 is the silicon substrate, 2 is the pad oxide layer, 3 is the silicon nitride hard mask layer, 4 is the select tube oxide layer, 5 is the sacrificial dielectric layer, 6 is the source region, 7 is the select tube polysilicon gate, 8 is the select tube top oxide layer, 9 is the isolation oxide layer, 10 is the ONO charge storage layer, 11 is the storage tube polysilicon, 12 is the drain region, and 13 is the shallow trench isolation STI. DETAILED DESCRIPTION

[0036] The following is a specific embodiment of the present invention in conjunction with the accompanying drawings, which clearly and completely describes the technical solutions in the present invention, but the present invention is not limited to the following embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. According to the following description and claims, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the embodiments of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0037] It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed herein. On the contrary, providing these embodiments will make disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, for clarity, the sizes and relative sizes of layers and regions may be exaggerated, and the same reference numerals represent the same elements throughout. It should be understood that when an element or layer is referred to as "on ... ", "adjacent to ... ", "connected to " or "coupled to" other elements or layers, it can be directly on other elements or layers, adjacent to them, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ... ", "directly adjacent to ... ", "directly connected to " or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the teachings of the present invention, a first element, component, region, layer or section discussed below may be represented as a second element, component, region, layer or section.

[0038] The process method of the 3D SONOS memory of the present invention includes the following process steps: Figures 1 to 14 The instructions are as follows:

[0039] In the first step, a semiconductor substrate is provided, a pad oxide layer is first formed on the semiconductor substrate, and then a silicon nitride hard mask layer is formed on the surface of the pad oxide layer.

[0040] It should be noted that the process method described in the present invention is applicable to the production of P-type SONOS or N-type SONOS; for P-type SONOS, the injection type of the source region and the drain region is P-type; for N-type SONOS, the injection type of the source region and the drain region is N-type, and before performing the first step, it is necessary to perform P-type well injection to form a P well, and then manufacture devices in the formed P well.

[0041] The second step involves photolithography and etching the silicon nitride hard mask layer. The silicon nitride hard mask layer is opened and etched downward, including removing the silicon nitride hard mask layer and the pad oxide layer, and etching the semiconductor substrate to form a trench that extends deep into the semiconductor substrate. The depth of the trench determines the length of the select pipe channel.

[0042] In the third step, a first oxide layer is formed within the trench in the semiconductor substrate. The first oxide layer covers the interior of the trench, including the sidewalls and bottom. The first oxide layer serves as the gate dielectric layer of the select transistor, and its thickness determines the gate dielectric thickness of the select transistor.

[0043] In the fourth step, a sacrificial dielectric layer is formed on the entire surface of the semiconductor substrate, and the sacrificial dielectric layer also covers the interior of the trench. In this embodiment, the sacrificial dielectric layer is a silicon nitride layer. In other embodiments, the sacrificial dielectric layer can also be a silicon oxide layer.

[0044] In the fifth step, the sacrificial dielectric layer is etched to remove the sacrificial dielectric layer on the surface of the semiconductor substrate, as well as the sacrificial dielectric layer and oxide layer at the bottom of the trench. Ion implantation is then performed to form a first implantation region at the bottom of the trench. This first implantation region serves as the source region of the selector in the memory cell, and its doping type depends on the memory type. For example, when making a P-type SONOS memory, the source region is implanted with P-type implantation.

[0045] Step 6: Remove the sacrificial dielectric layer.

[0046] In the seventh step, a first polysilicon layer is grown and subjected to a grinding process. The first polysilicon layer fills the trench and serves as the gate of the selection tube of the storage unit in the memory. The grinding process is a CMP process, and the first polysilicon layer grown on the surface of the silicon nitride hard mask layer is removed by the grinding process, and the grinding ends at the surface of the silicon nitride hard mask layer.

[0047] In the eighth step, a second oxide layer is grown on top of the polysilicon in the trench.

[0048] In the ninth step, the entire silicon nitride hard mask layer is removed by etching.

[0049] The tenth step is to grow an isolation oxide layer. The isolation oxide layer grows on the entire surface of the semiconductor substrate and simultaneously covers the side surfaces of the first polysilicon layer exposed after the silicon nitride hard mask layer is removed. The isolation oxide layer is fused with the pad oxide layer.

[0050] In the eleventh step, the isolation oxide layer and the liner oxide layer on the surface of the semiconductor substrate are completely removed, and only the sidewalls and top of the first polysilicon layer exposed on the surface of the semiconductor substrate retain an isolation oxide layer or a second oxide layer of a certain thickness.

[0051] In the twelfth step, an ONO layer is formed on the entire surface of the semiconductor substrate as a charge storage layer of the storage tube.

[0052] In the thirteenth step, a second polysilicon layer is formed on the entire surface of the semiconductor substrate.

[0053] In step 14, the second polysilicon layer is etched to form the storage transistor gate, and then the second implant region is implanted to form the storage transistor drain region. The ONO layer on the surface of the semiconductor substrate is etched to remove the excess ONO layer. The device of the present invention is now fabricated.

[0054] The 3D SONOS memory structure of the present invention refers to Figure 14 The right side of the figure is a plan view of the 3D SONOS memory, that is, a top view. The storage unit includes a selection tube and a storage tube. The storage tube is located on both sides, and the selection tube is located in the center. Figure 14 The bold boxes in the figure represent the select transistors of two adjacent memory cells. The select transistors of each of the two adjacent memory cells share a source region 6. The gates of the select transistors in these memory cells are trench-type, extending deep into the semiconductor substrate, forming a three-dimensional structure, hence the 3D structure. Their channels are perpendicular to the substrate surface. The left side of the figure shows schematic cross-sectional views along the respective dissection lines on the right side. The depth of the trench-type select transistor gate 7 determines the length of the select transistor channel; the select transistor gate is also elevated above the semiconductor substrate surface. Storage transistor gates 11 are located on either side of the select transistor gate that is elevated above the semiconductor substrate, serving as the storage transistor gates for the two adjacent memory cells. An isolation oxide layer 9 is provided between the storage transistor gate 11 and the select transistor gate 7. The bottom of the trench of the trench-type select gate forms the select transistor source region 6, serving as the shared source region for the select transistors of the two adjacent memory cells. In the substrate on either side of the storage transistor gate are drain regions 12 for the respective storage transistors of the two adjacent memory cells.

[0055] The 3D SONOS memory structure described in this invention consists of a selector and a storage gate, with the storage gates arranged horizontally and the selector gates arranged vertically, forming a 3D structure. The selector gates of two adjacent storage cells share a common source region. The erase and write operations of this memory are similar to those of traditional two-gate memory. During read operations, one storage gate can be turned off, and a voltage applied from the source region to read the state of the other storage gate. In the manufacturing process, the channel length of the selector in this invention is defined by the etching depth in the longitudinal direction of the silicon wafer (i.e., the thickness direction), making it suitable for manufacturing long-channel devices and facilitating area reduction. The width of a single storage gate is defined by self-aligned etching of the polysilicon gate, reducing the number of photomasks and process costs.

[0056] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A process for producing a 3D SONOS memory device, characterized by: The process steps include: The first step is to provide a semiconductor substrate, firstly form a pad oxide layer on the semiconductor substrate, and then form a hard mask layer on the surface of the pad oxide layer; The second step is to photolithographically and etch the hard mask layer, open the hard mask layer and etch downward to form a trench, wherein the trench extends deep into the semiconductor substrate; The third step is to form a first oxide layer inside the trench in the semiconductor substrate; Step 4: forming a sacrificial dielectric layer on the entire surface of the semiconductor substrate, wherein the sacrificial dielectric layer also covers the interior of the trench; The fifth step is to etch the sacrificial dielectric layer to remove the sacrificial dielectric layer on the surface of the semiconductor substrate, as well as the sacrificial dielectric layer and the oxide layer at the bottom of the trench; Then, ion implantation is performed to form a first implantation region at the bottom of the trench; Step 6: removing the sacrificial dielectric layer; Step 7: growing a first polysilicon layer and performing a grinding process; Step 8: growing a second oxide layer on top of the polysilicon in the trench; Step 9: removing the hard mask layer; Step 10: growing an isolation oxide layer; Step 11: etching and removing the isolation oxide layer and the pad oxide layer; Step 12: forming an ONO layer on the entire surface of the semiconductor substrate; Step 13: forming a second polysilicon layer on the entire surface of the semiconductor substrate; Step 14: etching the formed second polysilicon layer, and then implanting the second implantation region; The ONO layer is etched.

2. The process for producing a 3D SONOS memory device according to claim 1, wherein: In the first step, the hard mask layer includes a silicon nitride layer.

3. The process for producing a 3D SONOS memory device according to claim 1, wherein: In the second step, the hard mask layer and the liner oxide layer are removed by etching. The depth of the trench determines the length of the select pipe channel.

4. The process for producing a 3D SONOS memory device according to claim 1, wherein: In the third step, the first oxide layer covers the inside of the trench, including the sidewalls and the bottom. The first oxide layer serves as the gate dielectric layer of the selection tube, and its thickness determines the thickness of the gate dielectric layer of the selection tube.

5. The process for producing a 3D SONOS memory device according to claim 1, wherein: In the fourth step, the sacrificial dielectric layer is a silicon nitride layer or a silicon oxide layer.

6. The process for producing a 3D SONOS memory device according to claim 1, wherein: In the fifth step, the first implantation region is the source region of the selector in the memory cell, and its doping type depends on the type of the memory.

7. The process for producing a 3D SONOS memory device according to claim 1, wherein: In the seventh step, the first polysilicon layer fills the groove and serves as the selection tube gate of the storage unit in the memory; the grinding process is a CMP process, and the first polysilicon layer grown on the surface of the silicon nitride hard mask layer is removed by the grinding process, and the grinding ends at the surface of the silicon nitride hard mask layer.

8. The process for producing a 3D SONOS memory device according to claim 1, wherein: In the ninth step, the silicon nitride hard mask layer is removed by a wet etching process to remove the entire silicon nitride hard mask layer.

9. The process for producing a 3D SONOS memory device according to claim 1, wherein: In the tenth step, the isolation oxide layer is grown on the entire surface of the semiconductor substrate, and at the same time, the side surfaces of the first polysilicon layer exposed after the silicon nitride hard mask layer is removed are wrapped.

10. The process for producing a 3D SONOS memory device according to claim 1, wherein: In the eleventh step, the isolation oxide layer and the liner oxide layer on the surface of the semiconductor substrate are completely removed, and only the sidewalls and top of the first polysilicon layer exposed on the surface of the semiconductor substrate retain a certain thickness of the isolation oxide layer or the second oxide layer.

11. The process for producing a 3D SONOS memory device according to claim 1, wherein: In the twelfth step, the ONO layer serves as a charge storage layer of the storage tube.

12. The process for producing a 3D SONOS memory device according to claim 1, wherein: In the fourteenth step, the second polysilicon layer is etched to form a storage transistor gate of a storage unit in the memory; the second injection region is a drain region of the storage transistor.

13. The process for producing a 3D SONOS memory device according to claim 1, wherein: The process method is suitable for manufacturing P-type SONOS or N-type SONOS; for P-type SONOS, the source and drain regions are implanted with P-type; for N-type SONOS, the source and drain regions are implanted with N-type, and before the first step, a P-type well implantation is required to form a P-well, and then devices are manufactured in the formed P-well.

14. A 3D SONOS memory structure manufactured using the process according to claim 1, characterized in that: The 3D SONOS memory is composed of multiple memory cells, each of which includes a selection tube and a storage tube. The selection tubes of every two adjacent memory cells share a source region. The selection tube gates of the selection tubes in the memory cells are trench-type and extend deep into the semiconductor substrate. The depth of the trench-type selection tube gate determines the length of the selection tube channel. The selection tube gate is also higher than the surface of the semiconductor substrate. The storage tube gates are located on both sides of the selection tube gate that is higher than the semiconductor substrate, serving as the storage tube gates of two adjacent memory cells. The bottom of the trench of the trench-type selection tube gate is the source region of the selection tube, serving as the source region shared by the selection tubes of the two adjacent memory cells. The substrate on both sides of the storage tube gate has drain regions for the storage tubes of the two adjacent memory cells.

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