Semiconductor devices and manufacturing methods thereof

Abstract

According to one embodiment, a semiconductor device includes: a substrate; and a multilayer film comprising multiple electrode layers and multiple insulating layers alternately disposed above the substrate. The device further includes: a first semiconductor layer disposed within the multilayer film; and a second semiconductor layer disposed within the multilayer film on the first semiconductor layer, and comprising a single-crystal semiconductor layer. The device also includes a wiring layer disposed on the multilayer film and the second semiconductor layer, and electrically connected to the second semiconductor layer.

Description

[0001] [Cross-reference to related applications]

[0002] This application asserts priority based on the priority of a prior Japanese patent application No. 2020-154035 filed on September 14, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Technology

[0004] In semiconductor memories such as 3D memory, it is desirable to improve the performance of semiconductor layers such as channel semiconductor layers. Summary of the Invention

[0005] According to one embodiment, a semiconductor device includes: a substrate; and a multilayer film comprising multiple electrode layers and multiple insulating layers alternately disposed above the substrate. The device further includes: a first semiconductor layer disposed within the multilayer film; and a second semiconductor layer disposed within the multilayer film on the first semiconductor layer, and comprising a single-crystal semiconductor layer. The device also includes a wiring layer disposed on the multilayer film and the second semiconductor layer, and electrically connected to the second semiconductor layer. Attached Figure Description

[0006] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0007] Figure 2 This is an enlarged cross-sectional view showing the structure of the columnar portion in the first embodiment.

[0008] Figure 3 This is an enlarged cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0009] Figure 4 This is an enlarged cross-sectional view showing the structure of the semiconductor device of the comparative example of the first embodiment.

[0010] Figure 5 (a) and (b) Figure 6 (a) and (b) Figure 7 (a) and (b) Figure 8 (a) and (b) Figure 9 (a) and (b) Figure 10 (a) and (b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment.

[0011] Figure 11(a) and (b) are cross-sectional views showing a method for manufacturing a semiconductor device according to a variation of the first embodiment.

[0012] Figure 12 This is a cross-sectional view showing the overall structure of the semiconductor device according to the first embodiment. Detailed Implementation

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Figures 1 to 12 In this context, identical components are marked with the same symbol, and repeated descriptions are omitted.

[0014] (First Embodiment)

[0015] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0016] The semiconductor device of this embodiment is, for example, a three-dimensional memory, which includes a circuit region 1 and an array region 2 disposed on the circuit region 1. For example, as described below, the semiconductor device of this embodiment is manufactured by bonding a circuit wafer containing the circuit region 1 and an array wafer containing the array region 2. Figure 1 The mating surface S of circuit region 1 (circuit wafer) and array region 2 (array wafer) is shown.

[0017] The semiconductor device of this embodiment includes a substrate 11, a transistor 12, and an interlayer insulating layer 13 in circuit region 1, and an interlayer insulating film 21, a multilayer film 22, an interlayer insulating film 23, and a plurality of pillars 24 in array region 2. The transistor 12 includes a gate insulating film 12a, a gate electrode 12b, and an insulating film 12c. The multilayer film 22 includes multiple electrode layers 22a and multiple insulating layers 22b. Each pillar 24 includes a memory insulating film 24a, a semiconductor layer 24b, a channel semiconductor layer 24c, and a core insulating film 24d. The channel semiconductor layer 24c is an example of a first semiconductor layer, and the semiconductor layer 24b is an example of a second semiconductor layer.

[0018] The semiconductor device of this embodiment further includes a contact plug 31, a wiring layer 32 containing one or more wires, an interlayer plug 33, a wiring layer 34 containing one or more wires, an interlayer plug 35, a wiring layer 36 containing one or more wires, an interlayer plug 37, and a metal pad 38 in the circuit region 1, and a metal pad 41, an interlayer plug 42, a wiring layer 43 containing one or more wires, a wiring layer 51, and a passivation film 52 in the array region 2. The wiring layer 51 includes a semiconductor layer 51a and a metal layer 51b. The semiconductor layer 51a is an example of a third semiconductor layer.

[0019] Figure 1The X, Y, and Z directions are shown as mutually perpendicular. In this specification, the +Z direction is considered the up direction, and the -Z direction is considered the down direction. The -Z direction may or may not align with the direction of gravity. The Z direction is an example of the first direction.

[0020] The substrate 11 is, for example, a semiconductor substrate such as a silicon substrate. The transistor 12 includes: a gate insulating film 12a formed on the substrate 11; a gate electrode 12b formed on the gate insulating film 12a; and an insulating film 12c formed on the side of the gate electrode 12b. The semiconductor device of this embodiment includes a plurality of transistors 12 on the substrate 11. Figure 1 One of these transistors 12 is shown. These transistors 12, for example, constitute a control circuit (logic circuit) that controls the operation of the semiconductor device of this embodiment. An interlayer insulating layer 13 is formed on the substrate 11 to cover these transistors 12.

[0021] An interlayer insulating film 21 is formed on the interlayer insulating layer 13. The stacked film 22 includes multiple electrode layers 22a and multiple insulating layers 22b alternately stacked on the interlayer insulating film 21. In this embodiment, these electrode layers 22a include multiple word lines, one or more source-side select lines, and one or more drain-side select lines, as described below. Each electrode layer 22a includes, for example, a metal layer such as a W (tungsten) layer. Each insulating layer 22b is, for example, a silicon oxide film. An interlayer insulating film 23 is formed on the stacked film 22.

[0022] Each columnar portion 24 has a columnar shape extending in the Z direction and is formed within the interlayer insulating film 21, the stacked film 22, and the interlayer insulating film 23. Each columnar portion 24 includes: a memory insulating film 24a, formed on the side of the interlayer insulating film 21, the stacked film 22, and the interlayer insulating film 23; a semiconductor layer 24b and a channel semiconductor layer 24c, formed on the side of the memory insulating film 24a; and a core insulating film 24d, formed on the side of the channel semiconductor layer 24c.

[0023] The memory insulating film 24a has a tubular shape extending in the Z direction and surrounds the semiconductor layer 24b and the channel semiconductor layer 24c. As described below, the memory insulating film 24a includes a barrier insulating film, a charge storage layer, and a tunnel insulating film.

[0024] The channel semiconductor layer 24c has a tubular shape extending in the Z direction, surrounding the core insulating film 24d. Specifically, the channel semiconductor layer 24c includes: a side portion P1 having a tubular shape extending in the Z direction; and a bottom portion P2 having a bottom shape disposed at the upper end of the tube. The channel semiconductor layer 24c is, for example, a polycrystalline semiconductor layer such as a polysilicon layer. The side portion P1 is an example of the first portion, and the bottom portion P2 is an example of the second portion. Furthermore, the channel semiconductor layer 24c may contain n-type impurity atoms or p-type impurity atoms, or may not contain either n-type or p-type impurity atoms.

[0025] Semiconductor layer 24b has a non-tubular shape extending in the Z direction and is formed on the bottom portion P2 of channel semiconductor layer 24c. The side portion P1 of channel semiconductor layer 24c has a tubular shape, i.e., a hollow columnar shape, while semiconductor layer 24b has a non-tubular shape, i.e., a solid columnar shape. Semiconductor layer 24b is, for example, a monocrystalline silicon layer or a single-crystal semiconductor layer. In this embodiment, semiconductor layer 24b has an upper surface at the same height as the upper surface of interlayer insulating film 23, and a lower surface at a height lower than the lower surface of interlayer insulating film 23. Details regarding the height of the lower surface of semiconductor layer 24b in this embodiment will be described below.

[0026] Semiconductor layer 24b contains, for example, n-type or p-type impurity atoms. The concentration of n-type or p-type impurity atoms in semiconductor layer 24b is, for example, 1.0 × 10⁻⁶. 19 cm -3 That's all. The semiconductor layer 24b in this embodiment contains a concentration of 1.0 × 10⁻⁶. 19 cm -3 Up to 5.0×10 19 cm -3 The P (phosphorus) atom.

[0027] The core insulating film 24d has a non-tubular shape extending in the Z direction and is formed within the side portion P1 of the channel semiconductor layer 24c. The core insulating film 24d is, for example, a silicon oxide film.

[0028] In each columnar section 24, a plurality of memory cell transistors or a plurality of selection transistors are formed by a memory insulating film 24a, a semiconductor layer 24b, a channel semiconductor layer 24c, and a core insulating film 24d. These memory cell transistors or selection transistors constitute a memory cell array of a three-dimensional memory.

[0029] Contact plugs 31, wiring layers 32, dielectric plugs 33, wiring layers 34, dielectric plugs 35, wiring layers 36, dielectric plugs 37, metal pads 38, metal pads 41, dielectric plugs 42, and wiring layers 43 are sequentially disposed on substrate 11 within interlayer insulating films 13 and 21. The semiconductor device of this embodiment includes multiple contact plugs 31, multiple dielectric plugs 33, multiple dielectric plugs 35, multiple dielectric plugs 37, multiple metal pads 38, multiple metal pads 41, and multiple dielectric plugs 42. Figure 1 A portion of these plugs and pads is shown. The control circuitry is electrically connected to the memory cell array via these plugs, pads, and wiring layers, and controls the operation of the memory cell array via these plugs, pads, and wiring layers.

[0030] Each metal pad 38, 41 includes, for example, a metal layer such as a Cu (copper) layer. In the semiconductor device of this embodiment, metal pads 38 and 41 are bonded to each other, and interlayer insulating film 13 and interlayer insulating film 21 are bonded to each other. In this embodiment, each columnar portion 24 is formed on the wiring layer 43, thereby electrically connecting the channel semiconductor layer 24c of each columnar portion 24 to the wiring layer 43.

[0031] The wiring layer 51 includes: a semiconductor layer 51a formed on the interlayer insulating film 23 and each pillar 24; and a metal layer 51b formed on the semiconductor layer 51a. In this embodiment, the semiconductor layer 51a is connected to the semiconductor layer 24b of each pillar 24, thereby electrically connecting the wiring layer 51 to the semiconductor layer 24b of each pillar 24. The semiconductor layer 51a is, for example, a polycrystalline silicon layer doped with P atoms.

[0032] A passivation film 52 is formed on the wiring layer 51. The passivation film 52 is, for example, an insulating film such as a silicon oxide film. The passivation film 52 may also include a silicon oxide film and other insulating films.

[0033] Figure 2 This is an enlarged cross-sectional view showing the structure of the columnar portion 24 in the first embodiment.

[0034] like Figure 2 As shown, the columnar portion 24 includes a memory insulating film 24a, a channel semiconductor layer 24c (side portion P1), and a core insulating film 24d sequentially formed within the stacked film 22. The memory insulating film 24a includes a barrier insulating film 61, a charge storage layer 62, and a tunnel insulating film 63 sequentially formed within the stacked film 22.

[0035] The barrier insulating film 61 is, for example, a silicon oxide film. The charge storage layer 62 is, for example, an insulating film such as a silicon nitride film, and has the function of storing signal charge. The charge storage layer 62 can also be a semiconductor layer such as a polysilicon layer. The tunnel insulating film 63 is, for example, a silicon oxide film. The barrier insulating film 61, the charge storage layer 62, and the tunnel insulating film 63 all have a tubular shape extending in the Z direction, surrounding the channel semiconductor layer 24c and the semiconductor layer 24b (see reference). Figure 1 ).

[0036] Figure 3 This is an enlarged cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0037] Figure 3 A multilayer film 22, which alternately comprises multiple electrode layers 22a and multiple insulating layers 22b, is shown, along with columnar portions 24 disposed within the multilayer film 22. These electrode layers 22a include: one or more drain-side select lines SGD; multiple word lines WL disposed above the drain-side select lines SGD; and one or more source-side select lines SGS disposed above the word lines WL. Figure 3 The electrode layers 22a shown include one drain-side selection line (SGD) and five source-side selection lines (SGS) as an example, but the number of drain-side selection lines (SGD) and source-side selection lines (SGS) is not limited to this. The drain-side selection line (SGD) is an example of the first selection line, and the source-side selection lines (SGS) are an example of the second selection line.

[0038] In this embodiment, the semiconductor layer 24b has an upper surface at the same height as the upper surface of the interlayer insulating film 23, and a lower surface at a lower height than the lower surface of the interlayer insulating film 23. For example, Figure 3 The lower surface of the semiconductor layer 24b shown is located at the height between the lower surface of the bottommost source-side selection line SGS and the upper surface of the topmost source-side selection line SGS. Here, it is located at the height between the lower surface and the upper surface of the third source-side selection line SGS from the bottom (= the third from the top).

[0039] When erasing the stored data in each memory cell of a certain column 24 (NAND (Not AND) string), the semiconductor device of this embodiment applies an erase voltage to a designated source-side select line (SGS) for that column 24. As a result, a GIDL (Gate-Induced Drain Leakage) current is generated in the designated select transistor of that column 24 and flows to each memory cell. The stored data in each memory cell is erased using this GIDL current.

[0040] In this embodiment, the designated source-side select lines SGS are the source-side select lines SGS facing the semiconductor layer 24b. Specifically, they are the first (topmost) source-side select line SGS, the second source-side select line SGS, and the third source-side select line SGS from the top. When an erase voltage is applied to these source-side select lines SGS, a GIDL current is generated in the select transistors corresponding to these source-side select lines SGS, more specifically, a GIDL current is generated in the semiconductor layer 24b. These source-side select lines SGS are referred to as GIDL generators.

[0041] In this embodiment, the semiconductor layer 24b is provided to promote the generation of the GIDL current. Therefore, as described above, the semiconductor layer 24b contains a high concentration of P atoms. According to this embodiment, by using the channel region of the selection transistor corresponding to the designated source-side selection line SGS (GIDL generator) as the semiconductor layer 24b, the GIDL current can be effectively generated.

[0042] Figure 4 This is an enlarged cross-sectional view showing the structure of the semiconductor device of the comparative example of the first embodiment.

[0043] Figure 4 A multilayer film 22, which alternately comprises multiple electrode layers 22a and multiple insulating layers 22b, is shown, along with columnar portions 24 disposed within the multilayer film 22. These electrode layers 22a include: one or more drain-side select lines SGD; multiple word lines WL disposed above the drain-side select lines SGD; and one or more source-side select lines SGS disposed above the word lines WL. Figure 4 The electrode layers 22a shown include one drain-side selection line (SGD) and four source-side selection lines (SGS) as an example.

[0044] In this comparative example, the columnar portion 24 does not include the semiconductor layer 24b. Therefore, in the channel semiconductor layer 24c of this comparative example, the side portion P1 extends to the lower surface of the wiring layer 51, and the bottom portion P2 is in contact with the lower surface of the wiring layer 51.

[0045] In this comparative example, the columnar portion 24 has an impurity diffusion layer 25 disposed within the channel semiconductor layer 24c instead of the semiconductor layer 24b. The impurity diffusion layer 25 is, for example, a polycrystalline silicon layer doped with P atoms. In this comparative example, the source-side selection line SGS, the uppermost source-side selection line SGS facing the impurity diffusion layer 25, functions as a GIDL generator. The GIDL current in this comparative example is generated within the impurity diffusion layer 25.

[0046] Here, will Figure 3 The semiconductor device of the first embodiment shown and Figure 4The semiconductor devices shown in the comparative examples are compared.

[0047] exist Figure 4 In the comparative example shown, for example, an impurity diffusion layer 25 is formed by implanting P atoms into the channel semiconductor layer 24c. In this case, the position of the impurity diffusion layer 25 varies depending on the position of the implanted P atoms. Generally, since it is desirable for the GIDL current generated in different pillars 24 to be close to the same value, it is ideal for the positions of the impurity diffusion layers 25 in different pillars 24 to be close to the same position. However, the positions of the implanted P atoms generally differ between different impurity diffusion layers 25, making it difficult to make the positions of the impurity diffusion layers 25 in different pillars 24 close to the same position. Furthermore, if the P atoms implanted into the channel semiconductor layer 24c are diffused by annealing, the differences in the positions of the P atoms may be even greater.

[0048] On the other hand, Figure 3 In the first embodiment shown, a GIDL current is generated using a separately formed semiconductor layer 24b, which is different from the channel semiconductor layer 24c, instead of the impurity diffusion layer 25 formed within the channel semiconductor layer 24c. Therefore, according to this embodiment, it is easy to make the positions of the semiconductor layers 24b of different pillars 24 approximately the same, thereby making the values ​​of the GIDL currents generated in different pillars 24 approximately the same. As described below, the semiconductor layer 24b in this embodiment is formed by epitaxial growth, so it is easy to make the positions of the semiconductor layers 24b of different pillars 24 approximately the same.

[0049] Figure 12 This is a cross-sectional view showing the overall structure of the semiconductor device according to the first embodiment.

[0050] Array region 2 includes: a memory cell array 111 containing multiple memory cells, a semiconductor layer 112 on the memory cell array 111, a back gate insulating film 113 on the semiconductor layer 112, and a back gate electrode 114 on the back gate insulating film 113. The back gate electrode 114 is used for electric field control of the semiconductor layer 112, similar to the select gate SG described below. Array region 2 also includes an interlayer insulating film 21a below the memory cell array 111 and an insulating film 21b below the interlayer insulating film 21a as an interlayer insulating film 21. The insulating film 21b is, for example, a silicon oxide film.

[0051] Circuit region 1 is disposed below array region 2. Circuit region 1 includes an insulating film 13a below insulating film 21b, an interlayer insulating film 13b below insulating film 13a, and a substrate 11 below interlayer insulating film 13b, which serves as interlayer insulating film 13. Insulating film 13a is, for example, a silicon oxide film. Substrate 11 is, for example, a semiconductor substrate such as a silicon substrate.

[0052] Array region 2 has multiple word lines WL and a select gate SG as electrode layers within the memory cell array 111. Figure 12 The stepped structure 121 of the memory cell array 111 is shown. The array region 2 also includes the back gate electrode 114 as an electrode layer outside the memory cell array 111. Figure 12 As shown, each word line WL is electrically connected to the word wiring layer 123 via contact plug 122, the back gate electrode 114 is electrically connected to the back gate wiring layer 125 via contact plug 124, and the select gate SG is electrically connected to the select gate wiring layer 127 via contact plug 126. The pillar-shaped portion 24 passing through the word line WL and the select gate SG is electrically connected to the bit line BL within the wiring layer 43 via contact plug 43', and is also electrically connected to the semiconductor layer 112. Furthermore, the word line WL corresponds to a specific example of the electrode layer 22a.

[0053] Circuit region 1 includes a plurality of transistors 12. Each transistor 12 includes: a gate electrode 12b, a gate insulating film 12a disposed on a substrate 11; and a source diffusion layer and a drain diffusion layer (not shown) disposed within the substrate 11. Circuit region 1 also includes: a plurality of contact plugs 31 disposed on the source diffusion layer or drain diffusion layer of these transistors 12; a wiring layer 32 disposed on these contact plugs 31 and including a plurality of wirings; and a plurality of dielectric plugs 35 disposed on the wiring layer 32. Circuit region 1 also includes: a wiring layer 36 disposed on these dielectric plugs 35 and including a plurality of wirings; a plurality of dielectric plugs 37 disposed on the wiring layer 36; and a plurality of metal pads 38 disposed on these dielectric plugs 37 within an insulating film 13a. The dielectric plugs 33 and wiring layer 34 are not shown in the diagram. Circuit region 1 functions as the control circuit (logic circuit) of control array region 2.

[0054] Array region 2 includes: a plurality of metal pads 41 disposed on metal pads 38 within an insulating film 21b; a plurality of dielectric plugs 42 disposed on the metal pads 41; and a wiring layer 131 disposed on these dielectric plugs 42 and comprising a plurality of wirings. Each word line WL or each bit line BL is electrically connected to the corresponding wiring in the wiring layer 131. Array region 2 also includes: a wiring layer 132 disposed on the wiring layer 131 and comprising a plurality of wirings; a wiring layer 133 disposed on the wiring layer 132 and comprising a plurality of wirings; and a dielectric plug 134 disposed on the wiring 133. Array region 2 further includes: a metal pad 135 disposed on the dielectric plug 134; and a passivation film 136 covering the metal pad 135 and the back gate electrode 114. The passivation film 136 is, for example, a silicon oxide film, having an opening P that exposes the upper surface of the metal pad 136. The metal pad 136 is Figure 12 External connection pads for semiconductor devices can be connected to mounting substrates or other devices via solder balls, metal bumps, bonding wires, etc.

[0055] Figures 5 to 10 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0056] First, a substrate 26 for array wafer 4 is prepared, and an interlayer insulating film 23, a multilayer film 22', and an insulating film 21a (which is part of the interlayer insulating film 21) are sequentially formed on the substrate 26. Figure 5 (a)). The substrate 26 is, for example, a semiconductor substrate such as a silicon substrate. The multilayer film 22' is formed in such a manner that it alternately includes multiple sacrificial layers 22a' and multiple insulating layers 22b. Each sacrificial layer 22a' is, for example, a silicon nitride film. The substrate 26 is an example of a first substrate. These sacrificial layers 22a' are examples of a first film, and these insulating layers 22b are examples of a second film.

[0057] These sacrificial layers 22a' are in the following steps ( Figure 8 In step (a), the electrode layer 22a is replaced by a multilayer electrode layer 22a. As a result, a multilayer film 22, which alternately contains multilayer electrode layers 22a and multilayer insulating layers 22b, is formed between the interlayer insulating film 23 and the insulating film 21a.

[0058] Secondly, multiple memory holes H1 are formed within the insulating film 21a, the laminated film 22', and the interlayer insulating film 23. Figure 5 (b)). As a result, the upper surface of substrate 26 is exposed within these memory holes H1. These memory holes H1 are examples of recesses.

[0059] Secondly, a memory insulating film 24a is formed on the entire surface of the substrate 26. Figure 6 (a) As a result, a memory insulating film 24a is formed on the upper surface of the substrate 26 inside the memory hole H1, the side surface of the insulating film 21a, the stacked film 22' and the interlayer insulating film 23 inside the memory hole H1, and the upper surface of the insulating film 21a outside the memory hole H1. The memory insulating film 24a is formed by sequentially forming a barrier insulating film 61, a charge storage layer 62 and a tunnel insulating film 63 on the entire surface of the substrate 26. Figure 2 It is formed by ).

[0060] Secondly, the memory insulating film 24a is removed from the upper surface of the substrate 26 inside the memory hole H1 and the upper surface of the insulating film 21a outside the memory hole H1 by dry etching. Figure 6 (b)). As a result, the upper surface of substrate 26 is exposed again within memory hole H1. In this way, memory insulating film 24a is processed into a tubular shape extending in the Z direction.

[0061] Secondly, a semiconductor layer 24b is formed on the upper surface of the substrate 26 within the memory hole H1 by epitaxial growth from the substrate 26. Figure 7(a)). Semiconductor layer 24b is, for example, a single-crystal silicon layer doped with P atoms. The concentration of P atoms in semiconductor layer 24b is, for example, 1.0 × 10⁻⁶. 19 cm -3 The preferred value is 1.0 × 10⁴. 19 cm -3 Up to 5.0×10 19 cm -3 In this way, the semiconductor layer 24b is processed into a non-tubular shape that extends in the Z direction.

[0062] in addition, Figure 7 The orientation of the vertical direction of the array wafer 4 shown in (a) is the same as... Figure 3 The vertical orientation of array region 2 shown is opposite. Therefore, Figure 7 The upper surface of semiconductor layer 24b shown in (a) is with Figure 3 The lower surface of the semiconductor layer 24b shown corresponds to this. In Figure 7 In step (a), the position is reached at the upper surface of semiconductor layer 24b. Figure 3 The semiconductor layer 24b is formed in the manner shown by positioning the lower surface of the semiconductor layer 24b. Therefore, Figure 7 The upper surface of semiconductor layer 24b shown in (a) is located at the topmost point. Figure 3 The source-side selection line SGS (bottom) is located on the upper surface and the bottom surface (middle). Figure 3 The height between the lower surface of the source-side selection line SGS (topmost) in the middle. However, in Figure 7 In the stage shown in (a), the sacrificial layer 22a' has not yet been replaced by the electrode layer 22, therefore, more precisely, Figure 7 The upper surface of the semiconductor layer 24b shown in (a) is the height between the upper surface of the sacrificial layer 22a' corresponding to the uppermost source-side selection line SGS and the lower surface of the sacrificial layer 22a' corresponding to the lowermost source-side selection line SGS.

[0063] Next, a channel semiconductor layer 24c and a core insulating film 24d are sequentially formed on the entire surface of the substrate 26, and the channel semiconductor layer 24c and the core insulating film 24d outside the memory hole H1 are removed. Figure 7(b) As a result, a channel semiconductor layer 24c is formed on the upper surface of the semiconductor layer 24b within the memory hole H1, the side surface of the stacked film 22' within the memory hole H1, and the side surface of the interlayer insulating film 23. Furthermore, a core insulating film 24d is formed on the upper surface and side surface of the channel semiconductor layer 24c within the memory hole H1. In this way, the channel semiconductor layer 24c is formed in a tubular shape extending in the Z direction, and the core insulating film 24d is formed in a non-tubular shape extending in the Z direction. Specifically, the channel semiconductor layer 24c is formed in a manner including a side portion P1 and a bottom portion P2, wherein the side portion P1 has a tubular shape extending in the Z direction, and the bottom portion P2 has a bottom shape disposed at the lower end of the tube. In this way, a plurality of columnar portions 24 are formed within the plurality of memory holes H1.

[0064] Secondly, the sacrificial layer 22a' is replaced with the electrode layer 22 ( Figure 8 (a) Specifically, slits are formed within the insulating film 21a and the stacked film 22', and the sacrificial layer 22a' is removed by wet etching using the slits. Multiple electrode layers 22 are embedded within the multiple recesses formed by removing the sacrificial layer 22a'. As a result, a stacked film 22 alternating between the interlayer insulating film 23 and the insulating film 21a is formed, comprising multiple electrode layers 22a and multiple insulating layers 22b. These electrode layers 22a, for example, include multiple word lines WL, one or more source-side select lines SDS, and one or more drain-side select lines SDG (see reference). Figure 3 ).

[0065] In addition, Figure 5 In step (a), instead of forming a multilayer film 22' that alternately comprises multiple sacrificial layers 22a' and multiple insulating layers 22b, a multilayer film 22 that alternately comprises multiple electrode layers 22a and multiple insulating layers 22b may be formed. In this case, it is not necessary to... Figure 8 In step (a), the sacrificial layer 22a' is replaced with the electrode layer 22a. In this case, the electrode layer 22a and the insulating layer 22b are examples of the first film and the second film.

[0066] Secondly, on the insulating film 21a and each columnar portion 24, an insulating film 21b, a wiring layer 43, a dielectric plug 42, and a metal pad 41, which are part of the interlayer insulating film 21, are formed. Figure 8 (a)). In this way, an array of wafers 4 are fabricated to become the object to be bonded. Figure 8 (a) shows the upper surface S2 of the array wafer 4, which becomes the bonding surface S of the array wafer 4.

[0067] Next, a substrate 11 for the circuit wafer 3 is prepared, and transistors 12, interlayer insulating film 13, contact plugs 31, wiring layers 32, dielectric plugs 33, wiring layers 34, dielectric plugs 35, wiring layers 36, dielectric plugs 37, and metal pads 38 are formed on the substrate 11. Figure 8 (b)). In this way, a circuit wafer 3 is manufactured to become the object to be bonded. Figure 8 (b) shows the upper surface S1 of the circuit wafer 3, which becomes the bonding surface S of the circuit wafer 3.

[0068] Next, the circuit wafer 3 is bonded to the array wafer 4, and the array wafer 4 is disposed on the circuit wafer 3. Figure 9 (a)). The circuit wafer 3 and the array wafer 4 are bonded together by sandwiching transistor 12, multilayer film 22, columnar portion 24, etc., between substrate 11 and substrate 26. Through this bonding, metal pad 38 and metal pad 41 are joined together, and interlayer insulating film 13 and interlayer insulating film 21 are bonded together.

[0069] Secondly, substrate 26 was removed by CPM (Chemical Mechanical Polishing). Figure 9 (b)). As a result, the semiconductor layer 24b of each columnar portion 24 is exposed.

[0070] Next, a semiconductor layer 51a of a wiring layer 51 is formed on the interlayer insulating film 23 and each columnar portion 24. Figure 10 (a) Figure 10 The semiconductor layer 51a formed in step (a) is, for example, an amorphous silicon layer doped with P atoms. The semiconductor layer 51a is formed in a manner that is connected to the semiconductor layer 24b of each pillar 24, thereby being electrically connected to the semiconductor layer 24b of each pillar 24.

[0071] Secondly, the semiconductor layer 51a is annealed by laser annealing. Figure 10 (b)). As a result, the semiconductor layer 51a, which is an amorphous silicon layer, becomes a polycrystalline silicon layer.

[0072] Subsequently, a metal layer 51b of the wiring layer 51 is formed on the semiconductor layer 51a, and a passivation film 52 is formed on the metal layer 51b (see reference). Figure 1 In this way, the semiconductor device of this embodiment is manufactured.

[0073] In addition, in manufacturing Figure 4 When using the semiconductor device of the comparative example shown, for example by... Figure 10The annealing in step (b) causes P atoms to diffuse from semiconductor layer 51a to channel semiconductor layer 24c, forming an impurity diffusion layer 25 within channel semiconductor layer 24c. However, this method makes it difficult to ensure that the positions of the impurity diffusion layers 25 on different pillars 24 are close to the same location. Furthermore, to suppress the adverse effects of annealing on metal pads 38 and 41, it is desirable to... Figure 10 The annealing in step (b) is performed for only a short time. This also becomes an obstacle to the diffusion of P atoms from semiconductor layer 51a to channel semiconductor layer 24c.

[0074] On the other hand, in this embodiment, a semiconductor layer 24b, different from the channel semiconductor layer 24c, is formed instead of forming an impurity diffusion layer 25 within the channel semiconductor layer 24c. This eliminates problems similar to those in the comparative example semiconductor device.

[0075] Figure 11 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a variation of the first embodiment.

[0076] First, in implementation Figure 5 (a)~ Figure 9 Following step (b), substrate 26 is removed by wet etching. Figure 11 (a)). As a result, the semiconductor layer 24b of each columnar portion 24 is exposed. Figure 11 In step (a), a portion of the interlayer insulating film 23 and the memory insulating film 24a may also be removed together with the substrate 26. In this case, as Figure 11 As shown in (a), a portion K1 of the semiconductor layer 24b of each columnar portion 24 protrudes from the interlayer insulating film 23 and the memory insulating film 24a.

[0077] Secondly, with Figure 10 The semiconductor layer 51a of the wiring layer 51 is formed on the interlayer insulating film 23 and each columnar portion 24, which is the same as step (a). Figure 11 (b)). As a result, semiconductor layer 51a is formed such that multiple portions K2 of semiconductor layer 51a protrude in the +Z direction. These portions K2 of semiconductor layer 51a are respectively formed in the +Z direction of portions K1 of semiconductor layer 24b of the corresponding columnar portion 24. Figure 11 In (b), part K1 protrudes into the semiconductor layer 51a.

[0078] Secondly, in implementation Figure 10 Following step (b), a metal layer 51b of the wiring layer 51 is formed on the semiconductor layer 51a, and a passivation film 52 is formed on the metal layer 51b (see reference). Figure 1Thus, the semiconductor device of this variation is manufactured. The structure of the semiconductor device of this variation differs from that of the semiconductor device of this embodiment in that it includes the aforementioned portions K1 and K2.

[0079] As described above, each pillar 24 of the semiconductor device in this embodiment includes a channel semiconductor layer 24c and a semiconductor layer 24b. Therefore, according to this embodiment, the performance of the semiconductor layers (channel semiconductor layer 24c and semiconductor layer 24b) in each pillar 24 can be improved. For example, according to this embodiment, the positions of the semiconductor layers 24b in different pillars 24 can be easily made close to the same position, thereby making it easy to make the values ​​of the GIDL current generated in different pillars 24 close to the same value.

[0080] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as set forth in the claims and their equivalents.

Claims

1. A semiconductor device comprising: Substrate; A multilayer film comprising multiple electrode layers and multiple insulating layers alternately disposed above the substrate; An interlayer insulating film is disposed on the laminated film; A first semiconductor layer is disposed within the laminated film; The second semiconductor layer is disposed within the interlayer insulating film on the first semiconductor layer and includes a single-crystal semiconductor layer; as well as A wiring layer is disposed on the interlayer insulating film and the second semiconductor layer, and is electrically connected to the second semiconductor layer; and The lower surface of the second semiconductor layer is located at a lower height than the upper surface of the uppermost electrode layer of the stacked film.

2. The semiconductor device according to claim 1, wherein The first semiconductor layer has a tubular shape extending in a first direction, which is the direction in which the stacked film is stacked; The second semiconductor layer has a non-tubular shape extending in the first direction.

3. The semiconductor device according to claim 2, wherein The first semiconductor layer includes a first portion and a second portion, the first portion having a tubular shape extending in the first direction, and the second portion having a bottom surface shape disposed at the upper end of the tube; The second semiconductor layer has a non-tubular shape extending in the first direction and is disposed on the second portion of the first semiconductor layer.

4. The semiconductor device according to claim 3, further comprising an insulating film disposed within the first portion of the first semiconductor layer.

5. The semiconductor device of claim 1, further comprising a charge storage layer having a tubular shape surrounding the first semiconductor layer and the second semiconductor layer.

6. The semiconductor device of claim 1, wherein the first semiconductor layer comprises a polycrystalline semiconductor layer.

7. The semiconductor device of claim 1, wherein the second semiconductor layer comprises n-type impurity atoms or p-type impurity atoms.

8. The semiconductor device of claim 7, wherein the concentration of the n-type impurity atoms or the p-type impurity atoms in the second semiconductor layer is 1.0 × 10⁻⁶. 19 cm -3 above.

9. The semiconductor device of claim 1, wherein the wiring layer comprises: A third semiconductor layer is disposed on the laminated film and the second semiconductor layer, and is in contact with the second semiconductor layer; and A metal layer is disposed on the third semiconductor layer.

10. The semiconductor device of claim 9, wherein the second semiconductor layer includes a portion protruding into the third semiconductor layer.

11. The semiconductor device of claim 1, wherein The multilayer electrode layer includes: one or more first selection lines; multiple word lines disposed above the first selection lines; and one or more second selection lines disposed above the word lines. The lower surface of the second semiconductor layer is positioned at a height between the lower surface of the lowest second selection line and the upper surface of the highest second selection line.

12. A method for manufacturing a semiconductor device, comprising the following steps: An interlayer insulating film is formed above the first substrate; A laminated film, which alternately comprises multiple first films and multiple second films, is formed on the interlayer insulating film, wherein the first film is an electrode layer; A recess is formed within the interlayer insulating film and the laminated film, so that the first substrate is exposed within the recess; A second semiconductor layer comprising a single-crystal semiconductor layer is formed on the first substrate within the recess; A first semiconductor layer is formed on the second semiconductor layer within the recess; The first substrate and the second substrate are bonded together with the multilayer film, the first semiconductor layer and the second semiconductor layer in between; After the first substrate and the second substrate are bonded together, the first substrate is removed to expose the second semiconductor layer; as well as A wiring layer is formed on the exposed second semiconductor layer, and the wiring layer is electrically connected to the second semiconductor layer; and The lower surface of the second semiconductor layer is located at a lower height than the upper surface of the first film, which is the uppermost layer of the stacked film.

13. The method of manufacturing a semiconductor device according to claim 12, wherein the second semiconductor layer is formed by epitaxial growth from the first substrate.

14. The method of manufacturing a semiconductor device according to claim 12, wherein The second semiconductor layer is formed in a non-tubular shape having an extension in a first direction, which is the direction of the stacked film stacking; The first semiconductor layer is formed in a tubular shape that extends in the first direction.

15. The method of manufacturing a semiconductor device according to claim 14, wherein the first semiconductor layer is formed in a manner comprising a first portion and a second portion, the first portion having a tubular shape extending in the first direction, and the second portion having a bottom surface shape disposed at the lower end of the tube.

16. The method for manufacturing a semiconductor device according to claim 15, further comprising the following step: An insulating film is formed within the first portion of the first semiconductor layer.

17. The method of manufacturing a semiconductor device according to claim 12, wherein the second semiconductor layer and the first semiconductor layer are respectively formed in the recess by a charge accumulation layer.

18. The method of manufacturing a semiconductor device according to claim 12, wherein the first semiconductor layer is formed in a manner comprising a polycrystalline semiconductor layer.

19. The method of manufacturing a semiconductor device according to claim 12, wherein the second semiconductor layer is formed in a manner comprising n-type impurity atoms or p-type impurity atoms.

20. The method for manufacturing a semiconductor device according to claim 19, wherein the concentration of the n-type impurity atoms or the p-type impurity atoms in the second semiconductor layer is 1.0 × 10⁻⁶. 19 cm -3 above.

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