Filter packaging structure and packaging method

Abstract

The present invention relates to a filter packaging structure, comprising pins on a filter chip, metal pads on the pins, interconnecting posts on the metal pads, an insulating layer on the outer sides of the interconnecting posts and the metal pads, a passivation layer on top of the insulating layer, a silicon substrate on top of the passivation layer, interconnecting holes on the silicon substrate, a first redistribution layer on the interconnecting posts, the lower end of the first redistribution layer being connected to the interconnecting posts, a second redistribution layer on the upper end of the first redistribution layer, and interconnecting bumps on the second redistribution layer. The present invention achieves electrical interconnection by forming interconnecting holes on the back side of the silicon substrate, and simultaneously forms a groove structure with an insulating layer to form a cavity structure, thereby forming the cavity structure required for a resonant device. The present invention has a simple manufacturing method, simple metal bonding operation, and good sealing properties, making it suitable for large-scale mass production.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit packaging, in particular to a packaging structure of a filter and a packaging method thereof. Background Art

[0002] With the advent of the 5G era, radio frequency (RF) front-end components, the core of wireless communications, are rapidly increasing in complexity to meet the demands of expanding RF frequency bands. Filters, which filter out signals outside a specific frequency band, can be categorized as SAW filters and BAW filters. SAW and TC-SAW filters are suitable for frequencies up to 1.5 GHz. Above 1.5 GHz, BAW filters offer significant performance advantages, shrinking in size as frequency increases, making them ideal for demanding 4G and 5G applications. Furthermore, even in high-bandwidth designs, BAW filters are insensitive to temperature fluctuations while offering extremely low loss and steep filter skirts. The basic BAW structure consists of a piezoelectric film sandwiched between two metal electrodes. Acoustic waves oscillate within the film, forming standing waves. To confine the acoustic waves within the film, sufficient isolation must be maintained between the oscillating structure and the external environment to minimize loss and maximize Q.

[0003] Research has shown that a package with the same chip bonded together is 40% larger than a flip-chip package. Consequently, as electronic products continue to miniaturize while maintaining superior performance, chip-scale packaging (CSP) has become widely used in filter packaging. In 2008, J. Tian et al. proposed a high-resistivity silicon capping system. This capping system incorporates through-substrate electrical vias and a cavity structure, which is flip-chip bonded to the device wafer at the wafer level, providing device protection and vertical electrical signal interconnection. While chip-scale packaging significantly reduces package size while maintaining excellent performance, the complex manufacturing process leads to high packaging costs. Summary of the Invention

[0004] The object of the present invention is to overcome the deficiencies in the prior art and to provide a filter packaging structure and packaging method thereof that have high sealing properties, can simplify processes and reduce costs.

[0005] According to the technical solution provided by the present invention, the packaging structure of the filter includes pins, a filter chip, a metal pad, a first redistribution layer, an insulating layer, an interconnection column, a silicon substrate, a second redistribution layer, a passivation layer, interconnection holes and interconnection bumps;

[0006] A pin is provided on the filter chip, a metal pad is provided on the pin, an interconnection column is provided on the metal pad, an insulating layer is provided on the outer side of the interconnection column and the metal pad, a passivation layer is provided above the insulating layer, a silicon substrate is provided above the passivation layer, an interconnection hole is opened on the silicon substrate, the passivation layer covers the inner wall of the interconnection hole, a first redistribution layer is provided on the interconnection column, the upper end portion of the first redistribution layer covers a portion of the upper surface of the silicon substrate, the middle end portion of the first redistribution layer is located in the interconnection hole and is surrounded by the passivation layer, the lower end portion of the first redistribution layer covers a portion of the lower surface of the passivation layer, the lower end portion of the first redistribution layer is connected to the interconnection column, a second redistribution layer is provided on the upper end portion of the first redistribution layer, and an interconnection bump is provided on the second redistribution layer;

[0007] The insulating layer, the passivation layer and the filter chip are combined to form a cavity structure corresponding to the chip working area.

[0008] Preferably, the interconnection column is offset from the interconnection hole.

[0009] Preferably, the diameter of the interconnected pores is 0.1 to 100 μm.

[0010] Preferably, the thickness of the passivation layer is 0.1-30 μm, and the material of the passivation layer is an inorganic material, a polymer material, or an organic and inorganic composite material.

[0011] Preferably, the thickness of the insulating layer is 1-50 μm, and the passivation layer is made of an inorganic material, a polymer material, or an organic and inorganic composite material.

[0012] Preferably, the height of the interconnection pillar is 0.5-30 μm, and the material of the interconnection pillar is one or more of Cu, Ti, TiW, V, Ni, W, Sn, Ag or Au.

[0013] Preferably, the thickness of the metal pad is 0.1-10 μm, and the material of the metal pad is one or more of Cu, Ti, TiW, V, Ni, W, Sn, Ag or Au.

[0014] The packaging method of the above filter comprises the following steps:

[0015] S1, taking a silicon substrate, and etching interconnect holes on the upper surface of the silicon substrate by a dry etching process;

[0016] S2, depositing a passivation layer on the upper surface of the silicon substrate;

[0017] S3, forming a first redistribution layer on the upper surface of the passivation layer corresponding to the interconnection hole position;

[0018] S4, forming an insulating layer on the upper surface of the first redistribution layer and the passivation layer;

[0019] S5. forming a first groove and a second groove in the insulating layer, wherein the first groove exposes a portion of the upper surface of the first redistribution layer on one side of the interconnection hole, and the second groove exposes a portion of the upper surface of the passivation layer between adjacent interconnection holes;

[0020] S6. Make an interconnection column in the first groove, wherein the height of the interconnection column is lower than the thickness of the insulating layer, and set aside;

[0021] S7. Take the filter chip and make metal pads on the pins outside the working area of ​​the chip;

[0022] S8, inverting the filter chip obtained in step S7 and the silicon substrate obtained in step S6 through a metal bonding process, and interconnecting them through metal pads and interconnection pillars to form a semi-finished package;

[0023] S9, exposing the bottom of the first redistribution layer in the interconnection hole through a grinding and dry etching process, thereby forming a semi-finished package;

[0024] S10. Continue to implement several layers of rewiring on the first rewiring layer using a rewiring process to form a second rewiring layer, make interconnect bumps on the second rewiring layer to electrically connect the second rewiring layer to the outside, and finally cut the completed package into single packaged chips.

[0025] Preferably, in step S6, the height difference between the interconnection pillar and the insulating layer is controlled to be 0.5-5 μm.

[0026] The present invention overcomes the difficulties of existing filter packaging solutions, such as the influence of substrate material properties on filter parameters, poor airtightness, strict bonding accuracy requirements and complex preparation process. Electrical interconnection is achieved by making TSV silicon through-holes on the back of the silicon substrate, and at the same time, an insulating layer is prepared to form a groove structure to prepare the cavity structure required for the resonant device. The production method is simple, the metal bonding operation is simple, the airtightness is good, and it is suitable for large-scale mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a structural diagram of the silicon substrate after being processed in step S1 of the present invention.

[0028] Figure 2 It is a structural diagram of the silicon substrate after being processed in step S2 of the present invention.

[0029] Figure 3 It is a structural diagram of the silicon substrate after being processed in step S3 of the present invention.

[0030] Figure 4 It is a structural diagram of the silicon substrate after being processed in step S4 of the present invention.

[0031] Figure 5 It is a structural diagram of the silicon substrate after being processed in step S5 of the present invention.

[0032] Figure 6 It is a structural diagram of the silicon substrate after being processed in step S6 of the present invention.

[0033] Figure 7 It is a structural diagram of the filter chip after being processed in step S7 of the present invention.

[0034] Figure 8 It is a structural diagram of the semi-finished package after being processed in step S8 of the present invention.

[0035] Figure 9 It is a structural diagram of the semi-finished package after being processed in step S9 of the present invention.

[0036] Figure 10 It is a structural diagram of the finished package after being processed in step S10 of the present invention. DETAILED DESCRIPTION

[0037] The present invention will be further described below with reference to specific embodiments.

[0038] The filter packaging structure of the present invention includes a pin 1, a filter chip 2, a metal pad 3, a first redistribution layer 4, an insulating layer 5, an interconnection column 6, a silicon substrate 7, a second redistribution layer 8, a passivation layer 9, an interconnection hole 10 and an interconnection bump 11;

[0039] A pin 1 is provided on the filter chip 2, a metal pad 3 is provided on the pin 1, an interconnection column 6 is provided on the metal pad 3, an insulating layer 5 is provided on the outer side of the interconnection column 6 and the metal pad 3, a passivation layer 9 is provided above the insulating layer 5, a silicon substrate 7 is provided above the passivation layer 9, an interconnection hole 10 is opened on the silicon substrate 7, the passivation layer 9 covers the inner wall of the interconnection hole 10, a first redistribution layer 4 is provided on the interconnection column 6, the upper end portion of the first redistribution layer 4 covers a portion of the upper surface of the silicon substrate 7, the middle end portion of the first redistribution layer 4 is located in the interconnection hole 10 and is surrounded by the passivation layer 9, the lower end portion of the first redistribution layer 4 covers a portion of the lower surface of the passivation layer 9, the lower end portion of the first redistribution layer 4 is connected to the interconnection column 6, a second redistribution layer 8 is provided on the upper end portion of the first redistribution layer 4, and an interconnection bump 11 is provided on the second redistribution layer 8;

[0040] The insulating layer 5 , the passivation layer 9 and the filter chip 2 are combined to form a cavity structure corresponding to the chip working area.

[0041] The packaging method of the above filter comprises the following steps:

[0042] S1. Take a silicon substrate 7 and etch interconnection holes 10 on the upper surface of the silicon substrate 7 by dry etching. At this time, the interconnection holes 10 are blind holes with a diameter of 0.1 to 100 μm. The number of interconnection holes 10 is determined by the number of device electrodes, such as Figure 1 As shown;

[0043] S2. Deposit a passivation layer 9 on the upper surface of the silicon substrate 7. The passivation layer 9 can be one or more inorganic materials, such as SiO2, SiC and Si3N4, or a passivation glue of a polymer material, including resin and polyimide materials, or an organic and inorganic composite material, such as dry film, bottom filler, epoxy molding compound (epoxy resin material), solder mask film (solder resist ink), etc. The thickness of the passivation layer 9 is 0.1~30, which meets the electrical connection requirements, such as Figure 2 As shown;

[0044] S3, forming a first rewiring layer 4 on the upper surface of the passivation layer 9 corresponding to the position of the interconnection hole 10, wherein the first rewiring layer 4 includes a rewiring layer portion located on the upper surface of the silicon substrate 7 and an interconnection wiring portion in the interconnection hole 10; Figure 3 As shown;

[0045] S4, using spraying, vacuum lamination, spin coating and other methods to make an insulating layer 5 on the upper surface of the first redistribution layer 4 and the passivation layer 9, the thickness of the insulating layer 5 is 1~50μm, the insulating layer 5 can be a polymer material, including resin and polyimide material, the insulating layer 5 can also be one or more inorganic materials, such as SiO2, SiC and Si3N4, etc., the insulating layer 5 can also be an organic and inorganic composite material, such as dry film, bottom filling material, epoxy resin material, solder resist ink, etc. Figure 4 As shown;

[0046] S5, forming a first groove and a second groove on the insulating layer 5 by exposure, development, etching, etc., wherein the first groove exposes a portion of the upper surface of the first redistribution layer 4 on one side of the interconnection hole 10, and the second groove exposes a portion of the upper surface of the passivation layer 9 between adjacent interconnection holes 10, as shown in FIG. Figure 5 As shown;

[0047] S6. Make an interconnection column 6 in the first groove by photolithography, physical vapor deposition, electroplating, chemical plating and other technologies. The height of the interconnection column 6 is 0.5~30μm. The material of the interconnection column 6 is one or more of Cu, Ti, TiW, V, Ni, W, Sn, Ag, Au, etc., and the height of the interconnection column 6 is slightly lower than the height of the insulating layer 5. The height difference should be 0.5~5μm. Figure 6 As shown;

[0048] S7, take the filter chip 2, make a metal pad 3 on the pin 1 outside the working area of ​​the chip, the thickness of the metal pad 3 is 0.1~10μm, the preparation process of the metal pad 3 includes one or more processes such as chemical plating, evaporation, electroplating, etc., and the material of the metal pad 3 is one or more of Cu, Ti, TiW, V, Ni, W, Sn, Ag, Au, etc. Figure 7 As shown;

[0049] S8, through the metal bonding process, the filter chip obtained in step S7 and the silicon substrate 7 obtained in step S6 are inverted and interconnected through the metal pads 3 and the interconnection pillars 6 to form a semi-finished package body, such as Figure 8 As shown;

[0050] S9, through the process of grinding and dry etching, the bottom of the first redistribution layer 4 in the interconnection hole 10 is exposed. At this time, the interconnection hole 10 becomes a through hole, forming a semi-finished package body, such as Figure 9 As shown;

[0051] S10, using the rewiring process to continue to realize several layers of rewiring on the first rewiring layer 4 to form a second rewiring layer 8, making interconnection bumps 11 on the second rewiring layer 8, and also using the ball planting process to replace the bumps, so that the second rewiring layer 8 is electrically connected to the outside, and finally the completed package is cut into single packaged chips, such as Figure 10 shown.

Claims

1. A filter packaging method, characterized in that The method comprises the following steps: S1, taking a silicon substrate (7), and etching interconnection holes (10) on the upper surface of the silicon substrate (7) by a dry etching process; S2, depositing a passivation layer (9) on the upper surface of the silicon substrate (7); S3, forming a first redistribution layer (4) on the upper surface of the passivation layer (9) at a position corresponding to the interconnection hole (10); S4, forming an insulating layer (5) on the upper surface of the first redistribution layer (4) and the passivation layer (9); S5. forming a first groove and a second groove on the insulating layer (5), wherein the first groove exposes a portion of the upper surface of the first redistribution layer (4) on one side of the interconnection hole (10), and the second groove exposes a portion of the upper surface of the passivation layer (9) between adjacent interconnection holes (10); S6, making an interconnection column (6) in the first groove, wherein the height of the interconnection column (6) is lower than the thickness of the insulating layer (5), and the interconnection column (6) is reserved; S7, take the filter chip (2), and make a metal pad (3) on the pin (1) outside the working area of ​​the chip; S8, inverting the filter chip obtained in step S7 and the silicon substrate (7) obtained in step S6 through a metal bonding process, and interconnecting them through the metal pads (3) and the interconnection pillars (6) to form a semi-finished package; S9, exposing the bottom of the first redistribution layer (4) in the interconnection hole (10) through a grinding and dry etching process, thereby forming a semi-finished package; S10, using the rewiring process to continue to realize several layers of rewiring on the first rewiring layer (4) to form a second rewiring layer (8), making interconnect bumps (11) on the second rewiring layer (8) to realize electrical connection between the second rewiring layer (8) and the outside, and finally cutting the completed package into single packaged chips.

2. The filter packaging method according to claim 1, wherein: In step S6, the height difference between the interconnection pillar (6) and the insulating layer (5) is controlled to be 0.5-5 μm.

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