ADC calibration circuit, control method thereof, and storage medium

Abstract

The present invention discloses an ADC calibration circuit, a control method, and a storage medium. The circuit includes a calibration sampling subcircuit and a compensation subcircuit. The calibration sampling subcircuit includes an analog-to-digital converter (ADC). The calibration sampling subcircuit is used to provide a first reference value, a second reference value, and a value to be calibrated to the compensation subcircuit via the ADC. The compensation subcircuit is used to calibrate the value to be calibrated based on the first and second reference values ​​to obtain a corresponding digital calibration value. This circuit uses dual-point sampling to provide the first and second reference values ​​for calibration and calibrate and compensate the value to be calibrated, effectively reducing the impact of offset and gain errors on ADC conversion accuracy and improving ADC conversion accuracy. The circuit is easy to implement and integrate in circuit design and is suitable for more complex application scenarios.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an ADC calibration circuit, a control method thereof, and a storage medium. Background Art

[0002] An analog-to-digital converter (ADC), also known as an A / D converter, is a circuit that converts analog signals into digital signals. It is typically integrated as a functional module into a system-on-a-chip (SoC) chip and is widely used in various chip applications. An ideal ADC has a fixed gain between its analog input voltage and digital output, meaning the relationship between the two is linear. However, in practice, due to factors such as process variations, circuit limitations, and environmental noise, ADCs suffer from several common defects, including offset error, gain error, and linearity error. These errors severely impact the ADC's conversion accuracy and practical application. Summary of the Invention

[0003] The present invention aims to at least partially address one of the technical problems in the related art. To this end, one object of the present invention is to provide an ADC calibration circuit that effectively reduces the effects of offset error and gain error on ADC conversion accuracy, effectively improving ADC conversion accuracy. The circuit also has the advantages of being easy to implement and integrate in circuit design and suitable for more complex application scenarios.

[0004] A second objective of the present invention is to provide a control method for an ADC calibration circuit.

[0005] A third object of the present invention is to provide a computer-readable storage medium.

[0006] To achieve the above-mentioned objectives, an embodiment of the first aspect of the present invention provides an ADC calibration circuit, comprising: a calibration sampling subcircuit and a compensation subcircuit; the calibration sampling subcircuit includes an analog-to-digital converter, and the calibration sampling subcircuit is used to provide a first reference value, a second reference value, and a value to be calibrated to the compensation subcircuit through the analog-to-digital converter; the compensation subcircuit is used to calibrate the value to be calibrated based on the first reference value and the second reference value to obtain a corresponding digital calibration value.

[0007] According to the ADC calibration circuit of an embodiment of the present invention, a first reference value and a second reference value for calibration are provided by dual fixed-point sampling, and calibration compensation is performed on the value to be calibrated, thereby effectively reducing the influence of offset error and gain error on the ADC conversion accuracy, effectively improving the ADC conversion accuracy, and having the advantages of being easy to implement and integrate in circuit design and being applicable to more complex application scenarios.

[0008] In addition, the ADC calibration circuit proposed in the above embodiment of the present invention may also have the following additional technical features:

[0009] According to one embodiment of the present invention, the calibration sampling subcircuit further includes: a dual fixed-point generation unit, the dual fixed-point generation unit including a first resistor, a second resistor, a third resistor and a fourth resistor connected in series, one end of the first resistor, the second resistor, the third resistor and the fourth resistor connected in series is used to connect to a low external reference voltage, and the other end is used to connect to a high external reference voltage, wherein the first reference end of the analog-to-digital converter is used to connect to the low external reference voltage, and the second reference end is used to connect to the high external reference voltage; a channel selector, the first input end of the channel selector is connected to the node between the first resistor and the second resistor, the second input end of the channel selector is connected to the node between the third resistor and the fourth resistor, the third input end of the channel selector is used to input the voltage to be sampled corresponding to the value to be calibrated, and the output end of the channel selector is connected to the input end of the analog-to-digital converter; a controller, the controller is respectively connected to the channel selector The controller is connected to a control end of the analog-to-digital converter, a control end of the analog-to-digital converter, and a control end of the calibration sub-circuit, and is configured to: when controlling the first input end of the channel selector to be connected to the output end, input a first reference voltage to the analog-to-digital converter, control the analog-to-digital converter to convert the first reference voltage into the first reference value, and control the calibration sub-circuit to store the first reference value; when controlling the second input end of the channel selector to be connected to the output end, input a second reference voltage to the analog-to-digital converter, control the analog-to-digital converter to convert the second reference voltage into the second reference value, and control the calibration sub-circuit to store the second reference value; when controlling the third input end of the channel selector to be connected to the output end, input the voltage to be sampled to the analog-to-digital converter, control the analog-to-digital converter to convert the voltage to be sampled into the value to be calibrated, and control the calibration sub-circuit to calibrate the value to be calibrated according to the first reference value and the second reference value.

[0010] According to one embodiment of the present invention, the compensation subcircuit includes: a first register, an input end of the first register is connected to the output end of the analog-to-digital converter, a control end of the first register is connected to the controller, and the first register is used to store the first reference value; a second register, an input end of the second register is connected to the output end of the analog-to-digital converter, a control end of the second register is connected to the controller, and the second register is used to store the second reference value; a logic operation unit, a first input end of the logic operation unit is connected to the output end of the first register, a second input end of the logic operation unit is connected to the output end of the second register, and a third input end of the logic operation unit is connected to the output end of the analog-to-digital converter, and the logic operation unit is used to perform a logic operation on the value to be calibrated based on the first reference value and the second reference value, and output a corresponding digital calibration value.

[0011] According to an embodiment of the present invention, the logic operation unit is specifically configured to perform gain calibration and offset calibration on the value to be calibrated according to the first reference value and the second reference value.

[0012] According to an embodiment of the present invention, the compensation sub-circuit further includes: a shaping unit, the input end of the shaping unit is connected to the output end of the logic operation unit, and is used to perform a shaping operation on the digital calibration value output by the logic operation unit.

[0013] According to one embodiment of the present invention, the logic operation unit is used to implement the following formula:

[0014]

[0015] Wherein, c" represents the calibration digital value, a represents the first reference value, b represents the second reference value, c represents the value to be calibrated, and n represents the conversion accuracy of the analog-to-digital converter. represents the calibration gain, Indicates a calibration error.

[0016] According to one embodiment of the present invention, the logic operation unit includes: a first multiplier, wherein the input end of the first multiplier is connected to the output end of the first register, and is used to multiply the first reference value by -1; a second multiplier, wherein the input end of the second multiplier is connected to the output end of the analog-to-digital converter, and is used to multiply the value to be calibrated by 2; a third multiplier, wherein the input end of the third multiplier is connected to the output end of the first multiplier, and is used to multiply the output value of the first multiplier by 3; a first full adder, wherein the first input end of the first full adder is connected to the output end of the first multiplier, the second input end of the first full adder is connected to the output end of the second register, and the first full adder is used to add the output value of the first multiplier to the output of the first multiplier. a second full adder, wherein the first input terminal of the second full adder is connected to the output terminal of the second register, the second input terminal of the second full adder is connected to the output terminal of the second multiplier, and the second full adder is used to add the second reference value to the output value of the second multiplier; a third full adder, wherein the first input terminal of the third full adder is connected to the output terminal of the third multiplier, the second input terminal of the second full adder is connected to the output terminal of the second full adder, and the third full adder is used to add the output value of the third multiplier to the output value of the second full adder; a fourth multiplier, wherein the input terminal of the fourth multiplier is connected to the output terminal of the third full adder, and the output value of the third full adder is added to the output value of the second full adder; n-2 Perform a multiplication operation; a divider, wherein a first input end of the divider is connected to the output end of the first full adder, a second input end of the divider is connected to the output end of the fourth multiplier, and the divider is used to perform a division operation on the output value of the fourth multiplier and the output value of the first full adder.

[0017] According to an embodiment of the present invention, the resistance values ​​of the first resistor, the second resistor, the third resistor, and the fourth resistor are equal.

[0018] To achieve the above-mentioned objectives, an embodiment of a second aspect of the present invention provides a control method for an ADC calibration circuit, wherein the ADC calibration circuit includes a calibration sampling subcircuit, and the calibration sampling subcircuit includes an analog-to-digital converter. The method includes: receiving a first reference value, a second reference value, and a value to be calibrated provided by the calibration sampling subcircuit via the analog-to-digital converter; and calibrating the value to be calibrated according to the first reference value and the second reference value to obtain a corresponding digital calibration value.

[0019] To achieve the above objectives, the third embodiment of the present invention proposes a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the control method of the ADC calibration circuit proposed in the second embodiment of the present invention is implemented.

[0020] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 1 is a schematic structural diagram of an ADC calibration circuit according to an embodiment of the present invention;

[0022] Figure 2 1 is a schematic diagram of linear transformation for gain calibration and offset calibration according to an embodiment of the present invention;

[0023] Figure 3 The figure is a flow chart of a control method of an ADC calibration circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0025] The following will be combined with the instructions Figure 1-3 The ADC calibration circuit and its control method and storage medium according to the embodiment of the present invention are described in detail in the specific implementation manner.

[0026] Figure 1 FIG. 1 is a schematic diagram of the structure of an ADC calibration circuit according to an embodiment of the present invention. Figure 1 As shown, the ADC calibration circuit includes a calibration sampling subcircuit and a compensation subcircuit.

[0027] The calibration sampling subcircuit includes an analog-to-digital converter, and is configured to provide a first reference value, a second reference value, and a value to be calibrated to the compensation subcircuit through the analog-to-digital converter.

[0028] Specifically, the first reference value and the second reference value are reference values ​​obtained after analog-to-digital conversion processing of two known reference voltages of the analog-to-digital converter (a first reference voltage and a second reference voltage, where the first reference voltage is less than the second reference voltage), and are used as reference values ​​of the value to be calibrated, so as to calibrate the value to be calibrated based on the first reference value and the second reference value.

[0029] In an embodiment of the present invention, Figure 1 As shown, the calibration sampling subcircuit may further include a dual fixed-point generation unit, a channel selector, and a controller.

[0030] As a specific implementation method, Figure 1 As shown, the dual fixed-point generation unit includes a first resistor, a second resistor, a third resistor, and a fourth resistor connected in series, one end of the first resistor, the second resistor, the third resistor, and the fourth resistor connected in series is used to connect to a low external reference voltage, and the other end is used to connect to a high external reference voltage, wherein the first reference end of the analog-to-digital converter is used to connect to the low external reference voltage, and the second reference end is used to connect to the high external reference voltage.

[0031] Specifically, the first resistor, the second resistor, the third resistor and the fourth resistor in the dual fixed-point generation unit play the role of a voltage divider. One end of the first resistor, the second resistor, the third resistor and the fourth resistor connected in series is connected to the low external reference voltage (VREFL) connected to the analog-to-digital converter, and the other end is connected to the high external reference voltage (VREFH) connected to the analog-to-digital converter, and is used to divide the low external and high external reference voltages connected to the analog-to-digital converter to obtain reference voltages (first reference voltage and second reference voltage) for calibration.

[0032] In an embodiment of the present invention, the first resistor, the second resistor, the third resistor, and the fourth resistor have equal resistance values. The resistance values ​​of the four resistors are selected according to specific application requirements and can be designed to be 1K-10K ohms or other suitable values.

[0033] In an embodiment of the present invention, Figure 1 As shown, the first input terminal of the channel selector is connected to the node between the first resistor and the second resistor, the second input terminal of the channel selector is connected to the node between the third resistor and the fourth resistor, the third input terminal of the channel selector is used to input the voltage to be sampled corresponding to the value to be calibrated, and the output terminal of the channel selector is connected to the input terminal of the analog-to-digital converter.

[0034] Specifically, a first input terminal of the channel selector is connected to a node between a first resistor and a second resistor for obtaining a first reference voltage. A second input terminal of the channel selector is connected to a node between a third resistor and a fourth resistor for obtaining a second reference voltage. The channel selector may include multiple third input terminals for receiving a plurality of voltages to be sampled corresponding to values ​​to be calibrated. An output terminal of the channel selector is connected to an input terminal of an analog-to-digital converter for inputting the first reference voltage, the second reference voltage, and the voltage to be sampled into the analog-to-digital converter.

[0035] For better effect, the first reference voltage and the second reference voltage input terminals can be connected to the internal input channels of the analog-to-digital converter to minimize line delay and isolate external interference.

[0036] It should be noted that the channel selector includes multiple input terminals. The input terminal connected to the node between the first resistor and the second resistor is not limited to being connected to the first input terminal of the channel selector, the input terminal connected to the node between the third resistor and the fourth resistor is not limited to being connected to the second input terminal of the channel selector, and the voltage to be sampled corresponding to the value to be calibrated is not limited to being input through the third input terminal of the channel selector. In other words, the input terminal connected to the node between the first resistor and the second resistor, the node between the third resistor and the fourth resistor, and the voltage to be sampled corresponding to the value to be calibrated can be any input terminal of the channel selector.

[0037] In an embodiment of the present invention, Figure 1 As shown, the controller is respectively connected to the control end of the channel selector, the control end of the analog-to-digital converter, and the control end of the calibration subcircuit. The controller is used to: when the first input end and the output end of the control channel selector are connected, input a first reference voltage to the analog-to-digital converter, control the analog-to-digital converter to convert the first reference voltage into a first reference value, and control the calibration subcircuit to store the first reference value; when the second input end and the output end of the control channel selector are connected, input a second reference voltage to the analog-to-digital converter, control the analog-to-digital converter to convert the second reference voltage into a second reference value, and control the calibration subcircuit to store the second reference value; when the third input end and the output end of the control channel selector are connected, input a voltage to be sampled to the analog-to-digital converter, control the analog-to-digital converter to convert the voltage to be sampled into a value to be calibrated, and control the calibration subcircuit to calibrate the value to be calibrated according to the first reference value and the second reference value.

[0038] In an embodiment of the present invention, the analog-to-digital converter includes ports such as conversion trigger (trig), conversion end (done), and conversion output (Q) and corresponding functions.

[0039] In an embodiment of the present invention, the controller supports functions such as external calibration trigger (trig) and calibration completion (done).

[0040] Specifically, the controller receives an external calibration trigger. After detecting the valid edge of the calibration trigger, the controller sequentially selects the channels connected to the first reference voltage and the second reference voltage as valid input channels of the ADC. The first reference voltage and the second reference voltage are sequentially input into the analog-to-digital converter, which performs analog-to-digital conversion on the first reference voltage and the second reference voltage, so that the analog-to-digital converter outputs a first reference value a corresponding to the first reference voltage and a second reference value b corresponding to the second reference voltage. Further specifically, the controller is further configured to control the compensation subcircuit to store the first reference value a and the second reference value b, so that when calibrating multiple voltages to be sampled using the ADC calibration circuit, only one calibration is required at the initial stage. After generating the first reference value a and the second reference value b, the controller controls the third input terminal of the channel selector to input the voltage to be sampled. The analog-to-digital converter completes the analog-to-digital conversion of the voltage to be sampled and outputs the calibration value c corresponding to the voltage to be sampled.

[0041] The compensation subcircuit is used to calibrate the value to be calibrated according to the first reference value and the second reference value to obtain a corresponding digital calibration value.

[0042] Specifically, the compensation subcircuit performs calibration compensation on the input value to be calibrated c (raw data output by the ADC) according to the stored first reference value a and second reference value b, so as to output a digital calibration value after calibration of the value to be calibrated (calibration data output by the ADC calibration circuit).

[0043] In an embodiment of the present invention, Figure 1 As shown, the compensation subcircuit may include a first register, a second register, and a logic operation unit. The first register has an input connected to the output of the analog-to-digital converter, a control connected to the controller, and is used to store a first reference value. The second register has an input connected to the output of the analog-to-digital converter, a control connected to the controller, and is used to store a second reference value. The logic operation unit has a first input connected to the output of the first register, a second input connected to the output of the second register, and a third input connected to the output of the analog-to-digital converter. The logic operation unit is used to perform a logic operation on a value to be calibrated based on the first and second reference values, and output a corresponding digital calibration value.

[0044] Specifically, the controller controls the first register to store the first reference value a and the second register to store the second reference value b. The controller also controls the input of the value to be calibrated c into the logic operation unit. The logic operation unit performs calibration compensation on the value to be calibrated c based on the received first reference value a and second reference value b according to internal logic operation rules.

[0045] In an embodiment of the present invention, Figure 1 As shown, the compensation sub-circuit further includes a shaping unit, the input end of the shaping unit is connected to the output end of the logic operation unit, and is used to perform a shaping operation on the digital calibration value output by the logic operation unit.

[0046] Specifically, the shaping unit performs a shaping operation on the digital calibration value output by the logic operation unit, and outputs the digital calibration value of the voltage to be sampled.

[0047] In an embodiment of the present invention, the logic operation unit is specifically configured to perform gain calibration and offset calibration on the value to be calibrated according to the first reference value and the second reference value.

[0048] Specifically, the present invention adopts a center segment linear calibration method to perform gain calibration and offset calibration on the calibration value c according to the first reference value a and the second reference value b, so as to cover most applications of ADC and improve the conversion accuracy of the analog-to-digital converter.

[0049] It should be noted that, in the embodiment of the present invention, the low external reference voltage VREFL and the high external reference voltage VREFH of the ADC can be equivalent to 0 and VREF, the external analog input quantity should be within the range of 0-VREF, and the digital output quantity should be within the range of 0-2n, where n represents the conversion accuracy of the ADC.

[0050] It should be noted that, in the embodiment of the present invention, the first reference value a is a 1 / 4 VREF reference value, and the second reference value b is a 3 / 4 VREF reference value.

[0051] In an embodiment of the present invention, the logic operation unit is used to implement the following formula:

[0052]

[0053] Wherein, c" represents the calibration digital value, a represents the first reference value, b represents the second reference value, c represents the value to be calibrated, and n represents the conversion accuracy of the analog-to-digital converter. represents the calibration gain, Indicates a calibration error.

[0054] In the embodiment of the present invention, since the commonly used analog-to-digital converter has offset error, gain error and linear error. Among them, the linear error is mostly concentrated at the two ends of the analog-to-digital converter conversion range, that is, the near 0 segment and the near reference voltage VREF segment, while the linear error in the middle part is smaller. Among them, the middle part is also the recommended linear working range for the analog-to-digital converter. Therefore, a dual fixed-point generation unit is used to provide a first reference value a and a second reference value b, and the first reference value a and the second reference value b are used as sampling calibration reference values. By corresponding these two reference values ​​to the ideal point 2 of the ideal conversion, the first reference value a and the second reference value b are used as sampling calibration reference values. n-2 and 3*2 n-2Performing linear fitting on gain and offset can eliminate the gain error and offset error of the ADC intermediate conversion to the greatest extent.

[0055] Specifically, if Figure 2 As shown in the figure, the gain calibration and offset calibration of the logic operation unit are described:

[0056] The ADC conversion from actual to ideal conversion goes through two processes. The first process is center translation. The center point of the actual conversion line is (a+b) / 2, which corresponds to the center point of the ideal conversion. n-1 , subtracting the two will give the direction and magnitude of the center translation (2 n-1 -(a+b) / 2). The second process is to fit the translation line with the ideal conversion line by rotating and stretching it with the center point as the circle center. After fitting, the 1 / 4 VREF reference value a should be consistent with the ideal conversion point 2 n-2 coincide with point a", and the 3 / 4VREF reference value b coincides with the ideal transition point 3*2 n-2 Therefore, the conversion point c of any ADC should be fitted to the point c" of the ideal conversion line. According to the proportional relationship, we can get:

[0057]

[0058] Right now:

[0059]

[0060] in, is the calibration gain, is the calibration offset.

[0061] In an embodiment of the present invention, the logic operations involved in the ADC compensation subcircuit should be able to select signed number operations with sufficient bits according to the maximum precision n of the ADC. Among them, the multiplication constant operation is implemented using complement, left shift and addition. This represents a full addition operation for signed numbers with sufficient bits. The only division operation can be implemented using a binary cyclic subtraction right shift. This requires a certain number of clock cycles, but the overall compensation operation time is much lower than the ADC conversion time, which does not affect the ADC conversion rate to a certain extent. The final shaping circuit is used to perform a shaping operation on the result c″, converting values ​​exceeding 2n to 2n and negative values ​​to 0.

[0062] It should be noted that Figure 2 a′ represents the first reference value after the center point offset calibration, b′ represents the second reference value after the center point offset calibration, and c′ represents the value to be calibrated after the center point offset calibration.

[0063] As a specific embodiment, the logic operation unit may include a first multiplier, a second multiplier, a third multiplier, a first full adder, a second full adder, a third full adder, a fourth multiplier, and a divider. The input end of the first multiplier is connected to the output end of the first register, and is used to multiply the first reference value by -1; the input end of the second multiplier is connected to the output end of the analog-to-digital converter, and is used to multiply the calibration value by 2; the input end of the third multiplier is connected to the output end of the first multiplier, and is used to multiply the output value of the first multiplier by 3; the first input end of the first full adder is connected to the output end of the first multiplier, the second input end of the first full adder is connected to the output end of the second register, and the first full adder is used to add the output value of the first multiplier to the second reference value. operation; the first input end of the second full adder is connected to the output end of the second register, the second input end of the second full adder is connected to the output end of the second multiplier, and the second full adder is used to add the second reference value and the output value of the second multiplier; the first input end of the third full adder is connected to the output end of the third multiplier, the second input end of the second full adder is connected to the output end of the second full adder, and the third full adder is used to add the output value of the third multiplier and the output value of the second full adder; the input end of the fourth multiplier is connected to the output end of the third full adder, and is used to add the output value of the third full adder to the output value of the second full adder. n-2 Perform multiplication operation; the first input end of the divider is connected to the output end of the first full adder, the second input end of the divider is connected to the output end of the fourth multiplier, and the divider is used to divide the output value of the fourth multiplier and the output value of the first full adder.

[0064] The ADC calibration circuit of the embodiment of the present invention samples and converts two internal known reference voltages as reference benchmarks through hardware self-calibration, and performs real-time center calibration compensation on the output data of the analog-to-digital converter through the compensation sub-circuit, effectively reducing the impact of offset error and gain error on the ADC conversion accuracy. Specifically, by using dual-fixed-point sampling and compensation, the gain error and offset error of the ADC center segment are effectively eliminated, and the ADC conversion accuracy is effectively improved. Moreover, the calibration and compensation are all completed by the internal hardware circuit, which can be recalibrated at any time and is suitable for more complex application scenarios. By completing the self-calibration and error compensation of the ADC through the hardware circuit, the resource overhead of the off-chip hardware and execution software for ADC calibration and error compensation is effectively reduced, thereby ensuring the effective conversion rate of the ADC. The dual-fixed-point generation unit can be realized by a resistor voltage divider, and the logic operation unit is a pure digital logic design, which is easy to implement and integrate in the circuit design.

[0065] In an embodiment of the present invention, the ADC self-calibration circuit provided by the embodiment of the present invention may be integrated into a chip design.

[0066] The present invention also provides a control method for an ADC calibration circuit.

[0067] The control method of the ADC calibration circuit is used to control the above-mentioned ADC calibration circuit, which includes a calibration sampling subcircuit, and the calibration sampling subcircuit includes an analog-to-digital converter. The control method of the ADC calibration circuit includes:

[0068] S1 , receiving a first reference value, a second reference value, and a value to be calibrated provided by a calibration sampling sub-circuit via an analog-to-digital converter.

[0069] S2, calibrating the value to be calibrated according to the first reference value and the second reference value to obtain a corresponding digital calibration value.

[0070] It should be noted that, for other specific implementations of the control method of the ADC calibration circuit according to the embodiment of the present invention, reference may be made to the specific implementations of the ADC calibration circuit according to the above embodiment of the present invention.

[0071] The control method of the ADC calibration circuit provided by the present invention provides a first reference value and a second reference value for calibration by means of dual fixed-point sampling, performs calibration compensation on the value to be calibrated, effectively reduces the influence of offset error and gain error on the ADC conversion accuracy, and effectively improves the ADC conversion accuracy.

[0072] The present invention also provides a computer-readable storage medium.

[0073] In this embodiment, a computer program is stored on a computer-readable storage medium. The computer program corresponds to the above-mentioned control method of the ADC calibration circuit. When the computer program is executed by a processor, the control method of the ADC calibration circuit proposed in the embodiment of the second aspect of the present invention is implemented.

[0074] It should be noted that the logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device), or in conjunction with such instruction execution system, apparatus, or device. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transmit a program for use by an instruction execution system, apparatus, or device, or in conjunction with such instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion having one or more wires (electronic device), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0075] It should be understood that various parts of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0076] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0077] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0078] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0079] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0080] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0081] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. An ADC calibration circuit, characterized in that: The circuit includes: a calibration sampling subcircuit and a compensation subcircuit; The calibration sampling subcircuit includes an analog-to-digital converter, and the calibration sampling subcircuit is used to provide a first reference value, a second reference value and a value to be calibrated to the compensation subcircuit through the analog-to-digital converter; The compensation subcircuit is used to calibrate the value to be calibrated according to the first reference value and the second reference value to obtain a corresponding digital calibration value; The compensation sub-circuit comprises: a first register, wherein an input end of the first register is connected to an output end of the analog-to-digital converter, a control end of the first register is connected to a controller, and the first register is used to store the first reference value; a second register, wherein an input end of the second register is connected to the output end of the analog-to-digital converter, a control end of the second register is connected to the controller, and the second register is used to store the second reference value; a logic operation unit, wherein a first input terminal of the logic operation unit is connected to the output terminal of the first register, a second input terminal of the logic operation unit is connected to the output terminal of the second register, and a third input terminal of the logic operation unit is connected to the output terminal of the analog-to-digital converter, and the logic operation unit is configured to perform a logic operation on the value to be calibrated according to the first reference value and the second reference value, and output a corresponding digital calibration value; The logic operation unit is specifically configured to perform gain calibration and offset calibration on the value to be calibrated according to the first reference value and the second reference value; The logic operation unit is used to implement the following formula: Wherein, c" represents the digital calibration value, a represents the first reference value, b represents the second reference value, c represents the value to be calibrated, and n represents the conversion accuracy of the analog-to-digital converter. represents the calibration gain, Indicates a calibration error.

2. The ADC calibration circuit according to claim 1, wherein: The calibration sampling subcircuit further includes: a dual fixed-point generation unit, the dual fixed-point generation unit comprising a first resistor, a second resistor, a third resistor, and a fourth resistor connected in series, wherein one end of the first resistor, the second resistor, the third resistor, and the fourth resistor connected in series is used to connect to a low external reference voltage, and the other end is used to connect to a high external reference voltage, wherein the first reference end of the analog-to-digital converter is used to connect to the low external reference voltage, and the second reference end is used to connect to the high external reference voltage; a channel selector, wherein a first input terminal of the channel selector is connected to a node between the first resistor and the second resistor, a second input terminal of the channel selector is connected to a node between the third resistor and the fourth resistor, the third input terminal of the channel selector is used to input a voltage to be sampled corresponding to the value to be calibrated, and an output terminal of the channel selector is connected to an input terminal of the analog-to-digital converter; A controller, the controller being connected to a control terminal of the channel selector, a control terminal of the analog-to-digital converter, and a control terminal of the compensation sub-circuit, respectively, and configured to: When the first input terminal and the output terminal of the channel selector are connected, a first reference voltage is input to the analog-to-digital converter, the analog-to-digital converter is controlled to convert the first reference voltage into the first reference value, and the compensation sub-circuit is controlled to store the first reference value. When the second input terminal of the channel selector is connected to the output terminal, a second reference voltage is input to the analog-to-digital converter, the analog-to-digital converter is controlled to convert the second reference voltage into a second reference value, and the compensation sub-circuit is controlled to store the second reference value. When the third input terminal and the output terminal of the channel selector are controlled to be connected, the voltage to be sampled is input into the analog-to-digital converter, the analog-to-digital converter is controlled to convert the voltage to be sampled into the value to be calibrated, and the compensation sub-circuit is controlled to calibrate the value to be calibrated according to the first reference value and the second reference value.

3. The ADC calibration circuit according to claim 1, wherein: The compensation sub-circuit further includes: A shaping unit, wherein the input end of the shaping unit is connected to the output end of the logic operation unit, and is used to perform a shaping operation on the digital calibration value output by the logic operation unit.

4. The ADC calibration circuit according to claim 1, wherein: The logic operation unit includes: a first multiplier, wherein an input terminal of the first multiplier is connected to an output terminal of the first register, and is configured to perform a multiplication operation on the first reference value and -1; a second multiplier, wherein an input terminal of the second multiplier is connected to an output terminal of the analog-to-digital converter, and is configured to perform a multiplication operation on the value to be calibrated and 2; a third multiplier, wherein an input terminal of the third multiplier is connected to an output terminal of the first multiplier, and is configured to perform a multiplication operation on an output value of the first multiplier and 3; a first full adder, wherein a first input terminal of the first full adder is connected to the output terminal of the first multiplier, a second input terminal of the first full adder is connected to the output terminal of the second register, and the first full adder is configured to perform an addition operation on the output value of the first multiplier and the second reference value; a second full adder, wherein a first input terminal of the second full adder is connected to the output terminal of the second register, a second input terminal of the second full adder is connected to the output terminal of the second multiplier, and the second full adder is used to perform an addition operation on the second reference value and the output value of the second multiplier; a third full adder, wherein a first input terminal of the third full adder is connected to the output terminal of the third multiplier, a second input terminal of the second full adder is connected to the output terminal of the second full adder, and the third full adder is configured to perform an addition operation on an output value of the third multiplier and an output value of the second full adder; A fourth multiplier, wherein the input end of the fourth multiplier is connected to the output end of the third full adder, and is used to multiply the output value of the third full adder by 2 n-2 Perform multiplication operations; A divider, wherein a first input end of the divider is connected to the output end of the first full adder, a second input end of the divider is connected to the output end of the fourth multiplier, and the divider is used to perform a division operation on the output value of the fourth multiplier and the output value of the first full adder.

5. The ADC calibration circuit according to claim 2, wherein: The resistance values ​​of the first resistor, the second resistor, the third resistor, and the fourth resistor are equal.

6. A control method for an ADC calibration circuit, characterized in that: For implementing the ADC calibration circuit according to any one of claims 1 to 5, the ADC calibration circuit comprising a calibration sampling subcircuit, the calibration sampling subcircuit comprising an analog-to-digital converter, the method comprising: receiving a first reference value, a second reference value, and a value to be calibrated provided by the calibration sampling subcircuit through the analog-to-digital converter; The value to be calibrated is calibrated according to the first reference value and the second reference value to obtain a corresponding digital calibration value.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the control method of the ADC calibration circuit according to claim 6 is implemented.

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