Predictive control using one or more neural networks

Abstract

Predictive control using one or more neural networks is disclosed, specifically systems and methods for cooling a computer environment. In at least one embodiment, one or more neural networks can be used to determine one or more temperature control settings associated with one or more servers.

Description

TECHNICAL FIELD

[0001] At least one embodiment relates to processing resources for performing and facilitating artificial intelligence. For example, at least one embodiment relates to a processor or computing system for training a neural network according to different novel techniques described herein. BACKGROUND

[0002] In computing environments such as data centers, control infrastructure is used to manage aspects such as power distribution and temperature control. Different sensors or monitoring components can be used to determine a current state of the computing environment, and this state information can be used to determine adjustments to be made to the control infrastructure. This can include adjusting power or temperature control devices based on detected power or thermal conditions. The purely reactive nature of these approaches can allow for undesirable occurrences such as excessive power draw or thermal events, which can result in damage to hardware or loss of data. While there are modeling approaches that help to better determine the state of such environments, the computational complexity of these approaches prevents them from being used in real-time to make dynamic adjustments. BRIEF DESCRIPTION OF DRAWINGS

[0003] Figure 1A , Figure 1B and Figure 1C shows a computing environment according to at least one embodiment;

[0004] Figure 2A and 2B shows a temperature distribution in a data center according to at least one embodiment;

[0005] Figure 3A and 3B shows a server rack with a neural network-enabled cooling system according to at least one embodiment;

[0006] Figure 4A and 4B shows a data center with a neural network-enabled cooling system according to at least one embodiment;

[0007] Figure 5A shows a process for adjusting environmental control in a computing environment according to at least one embodiment;

[0008] Figure 5B shows a process for determining temperature control settings according to at least one embodiment;

[0009] Figure 6 shows a distributed system according to at least one embodiment;

[0010] Figure 7 shows an example data center according to at least one embodiment;

[0011] Figure 8 A client-server network is shown in accordance with at least one embodiment;

[0012] Figure 9 A computer network is shown in accordance with at least one embodiment;

[0013] Figure 10A A networked computer system is shown in accordance with at least one embodiment;

[0014] Figure 10B A networked computer system is shown in accordance with at least one embodiment;

[0015] Figure 10C A networked computer system is shown in accordance with at least one embodiment;

[0016] Figure 11 One or more components of a system environment in which services can be provided as third party network services are shown in accordance with at least one embodiment;

[0017] Figure 12 A cloud computing environment is shown in accordance with at least one embodiment;

[0018] Figure 13 A set of functional abstraction layers offered by a cloud computing environment is shown in accordance with at least one embodiment;

[0019] Figure 14 A supercomputer at the chip level is shown in accordance with at least one embodiment;

[0020] Figure 15 A supercomputer at the rack module level is shown in accordance with at least one embodiment;

[0021] Figure 16 A supercomputer at the rack level is shown in accordance with at least one embodiment;

[0022] Figure 17 A supercomputer at the entire system level is shown in accordance with at least one embodiment;

[0023] Figure 18A Inference and / or training logic is shown in accordance with at least one embodiment;

[0024] Figure 18B Inference and / or training logic is shown in accordance with at least one embodiment;

[0025] Figure 19 Training and scheduling of neural networks is shown in accordance with at least one embodiment;

[0026] Figure 20 An architecture for a network system is shown in accordance with at least one embodiment;

[0027] Figure 21 An architecture of a network system is shown in accordance with at least one embodiment;

[0028] Figure 22 A control plane protocol stack is shown in accordance with at least one embodiment;

[0029] Figure 23 A user plane protocol stack is shown in accordance with at least one embodiment;

[0030] Figure 24 Components of a core network are shown in accordance with at least one embodiment;

[0031] Figure 25 Components of a system that supports network function virtualization (NFV) are shown in accordance with at least one embodiment;

[0032] Figure 26 A processing system is shown in accordance with at least one embodiment;

[0033] Figure 27 A computer system is shown in accordance with at least one embodiment;

[0034] Figure 28 A system is shown in accordance with at least one embodiment;

[0035] Figure 29 An exemplary integrated circuit is shown in accordance with at least one embodiment;

[0036] Figure 30 A computing system is shown in accordance with at least one embodiment;

[0037] Figure 31 An APU is shown in accordance with at least one embodiment;

[0038] Figure 32 A CPU is shown in accordance with at least one embodiment;

[0039] Figure 33 An exemplary accelerator integrated segment is shown in accordance with at least one embodiment;

[0040] Figures 34A-34B An exemplary graphics processor is shown in accordance with at least one embodiment;

[0041] Figure 35A A graphics core is shown in accordance with at least one embodiment;

[0042] Figure 35B A GPGPU is shown in accordance with at least one embodiment;

[0043] Figure 36AA parallel processor is shown in accordance with at least one embodiment;

[0044] Figure 36B A processing cluster is shown in accordance with at least one embodiment;

[0045] Figure 36C A graphics multiprocessor is shown in accordance with at least one embodiment;

[0046] Figure 37 A software stack of a programming platform is shown in accordance with at least one embodiment;

[0047] Figure 38 A CUDA implementation of the software stack of Figure 37 is shown in accordance with at least one embodiment;

[0048] Figure 39 A ROCm implementation of the software stack of Figure 37 is shown in accordance with at least one embodiment;

[0049] Figure 40 An OpenCL implementation of the software stack of Figure 37 is shown in accordance with at least one embodiment;

[0050] Figure 41 Software supported by a programming platform is shown in accordance with at least one embodiment; and

[0051] Figure 42 Compiling code to execute on a programming platform of Figures 37-40 is shown in accordance with at least one embodiment. DETAILED DESCRIPTION

[0052] In at least one embodiment, a computing environment can include various computing devices and control systems, such as Figure 1AThe data center 100 shown in FIG. 1. In at least one embodiment, the data center 100 can include one or more spaces 102 with racks 110 and ancillary equipment for housing one or more servers on one or more server trays. In at least one embodiment, the data center 100 is supported by a cooling tower 104 located outside of the data center 100. In at least one embodiment, the cooling tower 104 dissipates heat from within the data center 100 by acting on a primary cooling loop 106. In at least one embodiment, a cooling distribution unit (CDU) 112 is used between the primary cooling loop 106 and a secondary or secondary cooling loop 108 to enable heat to be extracted from the secondary or secondary cooling loop 108 to the primary cooling loop 106. In at least one embodiment, the secondary cooling loop 108 can access different tubes into the server trays as needed. In at least one embodiment, the loops 106, 108 are shown as line graphs, but one of ordinary skill will recognize that one or more piping features can be used. In at least one embodiment, flexible polyvinyl chloride (PVC) tubing can be used with associated piping to move fluid along each of the loops 106, 108. In at least one embodiment, one or more coolant pumps can be used to maintain a pressure differential within the loops 106, 108 to enable the coolant to move according to temperature sensors in different locations, including in the room, in one or more racks 110, and / or in server cabinets or server trays within these racks 110.

[0053] In at least one embodiment, the coolant in the primary cooling loop 106 and the secondary cooling loop 108 can be at least water and an additive, such as ethylene glycol or propylene glycol. In operation, in at least one embodiment, each of the primary cooling loop and the secondary cooling loop has its own coolant. In at least one embodiment, the coolant in the secondary cooling loop can be dedicated to the requirements of the components in the server trays or racks 110. In at least one embodiment, the CDU 112 is capable of complex control of the coolant in the loops 106, 108 independently or simultaneously. In at least one embodiment, the CDU can be adapted to control flow rates so that the coolant is appropriately distributed to extract heat generated within the racks 110. In at least one embodiment, more flexible tubing 114 is provided from the secondary cooling loop 108 to enter each server tray and provide coolant to electrical and / or computing components.

[0054] In at least one embodiment, electrical and / or computing components are used interchangeably to refer to heat-generating components that benefit from the present data center cooling system. In at least one embodiment, tubing 118 forming part of secondary cooling loop 108 can be referred to as a room manifold. Separately, in at least one embodiment, tubing 116 extending from tubing 118 can also be part of secondary cooling loop 108, but can be referred to as a row manifold. In at least one embodiment, tubing 114 enters a rack as part of secondary cooling loop 108, but can be referred to as a rack cooling manifold. In at least one embodiment, row manifold 116 extends along a row in data center 100 to all racks. In at least one embodiment, tubing of secondary cooling loop 108 including manifolds 118, 116, and 114 can be improved. In at least one embodiment, chillers 120 can be provided in a primary cooling loop within data center 102 to support cooling prior to a cooling tower. In at least one embodiment, to the extent that additional loops are present in a primary control loop, these additional loops provide cooling outside of the rack and outside of the secondary cooling loop; and can be combined with the primary cooling loop.

[0055] In at least one embodiment, in operation, heat generated within a server tray of rack 110 can be transferred via flexible tubing of row manifold 114 of secondary cooling loop 108 to coolant exiting rack 110. In at least one embodiment, secondary coolant from CDU 112 for cooling rack 110 (in secondary cooling loop 108) moves toward rack 110. In at least one embodiment, secondary coolant from CDU 112 is transferred from one side of room manifold having tubing 118 via row manifold 116 to one side of rack 110 and via tubing 114 through one side of the server tray. In at least one embodiment, used or returning secondary coolant (or secondary coolant exiting taking heat away from computing components) exits from another side of the server tray (such as entering a left side of the rack after circulating through the server tray or through components on the server tray and exiting a right side of the rack for the server tray). In at least one embodiment, used secondary coolant exiting the server tray or rack 110 comes out of a different side (such as an exhaust side) of tubing 114 and moves to a parallel but also to an exhaust side of row manifold 116. In at least one embodiment, from row manifold 116, used secondary coolant moves in a parallel portion of room manifold 118 to travel in an opposite direction from incoming secondary coolant (which can also be newer secondary coolant) and toward CDU 112.

[0056] In at least one embodiment, used secondary coolant exchanges its heat with primary coolant in primary cooling loop 106 via CDU 112. In at least one embodiment, used secondary coolant is refreshed (such as relatively cooled when compared to temperature of used secondary coolant phase) and ready to cycle back to these computing components through secondary cooling loop 108. In at least one embodiment, various flow and temperature control features in CDU 112 can control heat exchange from used secondary coolant or flow of secondary coolant into and out of CDU 112. CDU 112 can also control flow of primary coolant in primary cooling loop 106.

[0057] In at least one embodiment, operation of components within a data center can generate patterns of temperature variation and heat flow, as shown by flow pattern 150 in Figure 1B In at least one embodiment, a cooling system can utilize one or more fluids (e.g., liquid or air) to attempt to manage temperature variations and levels across such a computing environment. In at least one embodiment, fluid-based cooling of high-density servers can be used to manage sudden high heat variations caused by varying computing loads or other such factors. In at least one embodiment, due to varying or trending requirements between a minimum to a maximum range of different cooling requirements, these requirements must be satisfied using appropriate cooling systems in an economical manner. In at least one embodiment, for moderate to high cooling requirements, a liquid cooling system can be used. In at least one embodiment, different cooling requirements also reflect different thermal characteristics of this data center. In at least one embodiment, heat generated from these components, servers, and racks is collectively referred to as a thermal characteristic or cooling requirement, as this cooling requirement must fully address this thermal characteristic.

[0058] In at least one embodiment, temperature and airflow can also vary within a computing device, as shown for computing device 180 of Figure 1C In at least one embodiment, a pattern of air flow 182 can be determined inside a computing device, shown here as at least without a top cover to illustrate flow between various components inside the device. During operation, different modeling methods can be used to determine air flow, power distribution, temperature variations, and other such aspects of such a device.

[0059] In at least one embodiment, a cooling system is disclosed that addresses thermal features in associated computing or data center equipment, such as in a graphics processing unit (GPU), in a switch, in a dual in-line memory module (DIMM), or in a central processing unit (CPU). Further, in at least one embodiment, the associated computing or data center equipment can include a processing card with one or more GPUs, switches, or CPUs thereon. In at least one embodiment, each of these GPUs, switches, and CPUs can be a heat-generating feature of the computing equipment. In at least one embodiment, the GPU, CPU, or switch can have one or more cores, and each core can be a heat-generating feature.

[0060] In at least one embodiment, such a cooling system can utilize one or more neural networks having different systems, devices, components, boards, or cards within a computing environment to provide predictions of one or more future states of that environment. In at least one embodiment, this can involve using a neural network computational fluid dynamics (NNCFD) system that provides the ability to predict future states such as temperatures at one or more locations within a computing environment at one or more future time periods. In at least one embodiment, these predictions can be inferences made using data about performance of data center devices and information such as temperatures, air flow, and pressures at different locations throughout that environment. In at least one embodiment, a control device can include or execute a NNCFD application that is capable of collecting various thermal, fluid flow, power, and environmental data from different locations in an entire computing environment such as a data center, a group of data centers, a server rack or individual servers, and other devices and systems discussed and suggested herein. In at least one embodiment, a NNCFD can be trained that continues to learn over time to provide accurate predictive modeling with different agents running in devices across that environment. In at least one embodiment, this can include one or more types of individual agents such as boards or ASICs with built-in machine learning capabilities. In at least one embodiment, these individual agents can perform tasks that regulate multiple aspects such as cooling (e.g., fan speed control or liquid flow control), power distribution (e.g., power distribution units (PDUs) or uninterruptible power supplies (UPSs)), and infrastructure (e.g., chillers or cooling towers) control based at least in part on inferences from that predictive NNCFD to best anticipate any upcoming time-wise significant power or thermal events to navigate these events smoothly, in many cases, prevent these events from happening. In at least one embodiment, a NNCFD application can provide an intelligent, predictive data center building management system (BMS) or data center infrastructure management (DCIM). In at least one embodiment, such a system can be designed using specific hardware that can enable machine learning capabilities to be incorporated directly into different computing devices or systems such as Jetson boards from NVIDIA Corporation that can utilize one or more graphics processing units (GPUs) on a board to efficiently provide neural network-based inferences and predictions.

[0061] In at least one embodiment, sensors and other such devices can be used to measure aspects such as air flow and temperature changes. In at least one embodiment, data for these aspects can be used to model a current state of a computing environment such as Figure 2Aof data center 200. In at least one embodiment, there are several racks 202 or other groupings of computer servers that each include one or more fans or other such elements that can force air away from those servers. In at least one embodiment, this can be modeled as a pattern 204 of air flow and associated temperatures. In at least one embodiment, there can be different events that can cause an unacceptable condition, such as a period of abnormally high compute load or an external heat event, as illustrated in view 250 of the data center in Figure 2B In at least one embodiment, darker shaded areas can correspond to areas of higher temperature, and it can be seen that there is a concentration of high temperatures in certain areas of Figure 2B In at least one embodiment, this can result in temperatures that exceed a maximum operating temperature threshold, and thus can result in damage to at least some of these compute devices or related infrastructure. In at least one embodiment, using a neural network to dynamically predict such occurrences or events in near real-time can help reduce the occurrence or extent of such events, or at least reduce the impact of such events on these servers or related infrastructure, can help reduce the occurrence or extent of such events, or at least reduce the impact of such events on these servers or related infrastructure.

[0062] In at least one embodiment, a neural network can be trained to solve fluid mechanics and dynamics problems that might otherwise be solved using a complex set of equations. In at least one embodiment, such equations are given by:

[0063]

[0064] where the sum of the unstable and convective components equals the sum of the diffusion and generation components. In at least one embodiment, such equations are functions of, for example, continuity, momentum, and energy. In at least one embodiment, the purpose of solving such equations is to obtain fluid velocity (air or liquid), temperature, and pressure values at any point in a computational environment, at any current or future point in time. In at least one embodiment, a neural network based architecture can be used to solve such computational mechanics or physics problems. In at least one embodiment, this can be implemented using a point cloud representation for three-dimensional (3D) geometrical structures, and maintaining a multi-physics network with respect to governing partial differential equations (PDEs). In at least one embodiment, performance of such neural network based modeling can be optimized for different configurations, such as multi-node, multi-GPU, automatic mixed precision (AMP), or accelerated linear algebra (XLA) configurations, such as those provided by NVIDIA Corporation. In at least one embodiment, such neural networks can be trained using loss functions that take into account aspects such as partial differential equations (PDEs), boundary conditions (BCs), initial conditions (ICs), and environmental data. In at least one embodiment, such networks can be trained using unsupervised, physics driven approaches. In at least one embodiment, there can be one model trained for each type of device to be utilized, and updated network parameters obtained from further training on additional data over time can be utilized. In at least one embodiment, an appropriate type of neural network suitable for equation solving and physics based analysis can be used, as can include SIMNet from NVIDIA Corporation. In at least one embodiment, SIMNet provides a physics and machine learning based simulation toolkit. In at least one embodiment, SIMNet provides a framework for modeling partial differential equations (PDEs) along with boundary and initial conditions. In at least one embodiment, flow problems can be solved in part by modeling mass balance conditions as hard constraints along with global constraints, which can improve accuracy as well as convergence properties. In at least one embodiment, for multi-physics problems spanning multiple domains, separate networks for different physics with coupling at domain interfaces also provide acceptable performance.

[0065] In at least one embodiment, neural networks can be embedded in different devices to enable those devices to predict future states, and make active adjustments based at least in part on those predictions. In at least one embodiment, this can include neural network enabled devices installed directly in liquid cooled server racks 300, such as Figure 3Ashown. In at least one embodiment, rack 300 can include a plurality of liquid-cooled servers 302 or other such devices. In at least one embodiment, a neural network-enabled rack manifold 304 can be included in rack 300 to provide a flow of liquid into each liquid-cooled server 302 through inlet valves 308 and back out with heat removed from that server 302 through outlet valves 310. In at least one embodiment, rack manifold 304 can include a plurality of neural network-enabled second liquid distribution control boards 306. In at least one embodiment, each inlet valve 308 and outlet valve 310 for each server can have one such control board 306. In at least one embodiment, rack 300 can also include a neural network-enabled rack power distribution unit (PDU) 312, which can include a plurality of outlets designed to distribute power to computers or networking devices within rack 300. In at least one embodiment, there can be a neural network-enabled power distribution control board 314 associated with each outlet of PDU 312. In at least one embodiment, sensors can capture information about temperature, airflow, or other such aspects of the computing environment inside and / or outside of rack 300, including inside and / or outside of any individual servers 302 located therein. In at least one embodiment, fluid cooling can remove an amount of heat from servers 302, but due to factors such as varying loads and external temperature fluctuations, temperatures at different locations can change and can reach or exceed temperature limits at which these devices can continue to operate properly. In at least one embodiment, it can be attempted to ensure that temperatures at particular locations remain below acceptable limits, where these locations can relate to junction or core temperatures of processors (e.g., CPUs or GPUs), memory modules, or power supplies.

[0066] In at least one embodiment, a task of the neural networks in these control boards 306, 314 can be to predict values such as coolant flow or air flow and temperatures at these different locations at one or more future points in time. In at least one embodiment, predictions from these networks can be used by corresponding boards, manifolds, PDUs, or other such devices to make adjustments to ensure proper temperatures and flows and to keep this equipment operating properly. In at least one embodiment, these adjustments can include adjusting amounts of fluid or air flowing into or out of servers or devices and temperatures of that fluid or air. In at least one embodiment, this can also include adjusting amounts of power supplied to one or more of these devices. In at least one embodiment, these can include similar adjustments as would be made in other data centers, but can be made based on future predictions rather than observed states, such that such a system can be proactive rather than reactive. In at least one embodiment, such monitoring can occur continuously or at least at regular intervals in order to ensure proper continued operation.

[0067] In at least one embodiment, each neural network in each type of component can be trained specifically for that type of component, and can receive updated network parameters that can be generated as a result of further training or continued learning. In at least one embodiment, inferences generated by individual devices can also be shared with other devices in a data center, which can help make more accurate predictions. In at least one embodiment, each control board 306, 314 can be a neural network-enabled board, ASIC, or other such component. In at least one embodiment, a control board can have components of a general purpose computer, including at least one processor 1014 and memory 1016 with associated circuitry, as described for computing device 1002 in FIG. 11. In at least one embodiment, a Jetson board from NVIDIA Corporation can be used, which is a complete System on a Module (S PM) including CPU, GPU, PMIC, DRAM, and Flash. In at least one embodiment, such a module can also be extended to provide additional functionality or capabilities. In at least one embodiment, each such board can function as a small artificial intelligence (AI) or machine learning-enabled computer. In at least one embodiment, multiple such boards can be used in parallel, such as on a rack manifold 304, in order to process data from multiple high resolution sensors simultaneously. In at least one embodiment, these different neural networks can make predictions that can be shared across servers, racks, or data centers, for example, in order to provide accurate predictions for different locations at one or more future points in time. In at least one embodiment, appropriate adjustments can then be made in order to maintain temperatures and other parameters at appropriate levels or values. In at least one embodiment, liquid distribution control boards 306 can make predictions of controls for adjusting related flow values only, or can share these predictions so that other adjustments can also be made based at least in part on these predictions. In at least one embodiment, a control system for a data center can collect predictions from these different boards or networks in order to make adjustments that are more appropriate for an entire data center. In at least one embodiment, adjustments can then be made at a server, rack, pod, data center, or other such level. Figure 10A In at least one embodiment, similar methods can be used with air-cooled server racks 350 as shown in FIG. 12. In at least one embodiment, a neural network-enabled rack PDU 354 can include multiple neural network-enabled power distribution control boards 356 to control power distribution for multiple air-cooled servers 352. In at least one embodiment, local power distribution boards 356 can make local adjustments within a rack 350, while external components in a corresponding data center can make adjustments to overall airflow or other such aspects.

[0068] In at least one embodiment, similar methods can be used with air-cooled server racks 350 as shown in FIG. 12. In at least one embodiment, a neural network-enabled rack PDU 354 can include multiple neural network-enabled power distribution control boards 356 to control power distribution for multiple air-cooled servers 352. In at least one embodiment, local power distribution boards 356 can make local adjustments within a rack 350, while external components in a corresponding data center can make adjustments to overall airflow or other such aspects. Figure 3B In at least one embodiment, similar methods can be used with air-cooled server racks 350 as shown in FIG. 12. In at least one embodiment, a neural network-enabled rack PDU 354 can include multiple neural network-enabled power distribution control boards 356 to control power distribution for multiple air-cooled servers 352. In at least one embodiment, local power distribution boards 356 can make local adjustments within a rack 350, while external components in a corresponding data center can make adjustments to overall airflow or other such aspects.

[0069] In at least one embodiment, a neural network-enabled method for liquid cooling of racks at the data center tier can utilize... Figure 4A The components of system 400 shown are described. In at least one embodiment, an external cooling unit 402 may supply liquid at a defined temperature to a data center cooling distribution unit 404. In at least one embodiment, the unit 404 may include a set of neural network-enabled distribution unit control boards 406 capable of performing inference and making adjustments based on inferred future values. In at least one embodiment, this may include regulating the temperature of the liquid received from the external cooling unit 402, or regulating the flow of the liquid to and / or from the external unit 402. In at least one embodiment, this may also include regulating the flow of manifolds 408 into rows of liquid cooling racks 412 and the flow into and out of those racks, as may be determined at least in part based on inference from the neural network-enabled control boards 410 built into the manifolds 410. In at least one embodiment, different levels of inflow and outflow may exist for different liquid cooling racks. In at least one embodiment, different flows may also exist to the individual servers in the racks, as per [the specific context]. Figure 3A As described. In at least one embodiment, a similar method can be used for an air-cooled data center 450, such as... Figure 4B As shown. In at least one embodiment, the external cooling unit 452 can supply cooling air at a defined temperature to the cooling distribution unit 454, which may incorporate multiple neural network-enabled control boards 456, such as computer room air conditioners (CRAC), computer room air processors (CRAH), SCHX, or other control boards. In at least one embodiment, temperature and airflow can be measured, and predictions can be made for future values ​​at future times, such as 30 seconds, one minute, five minutes, or one hour. This then allows adjustments to air temperature, airflow, power distribution, and other such aspects to be made. In at least one embodiment, these predictions can be made using different types of input data, such as server load, current temperature, current pressure, flow rate, power consumption, and other relevant data from different locations within the data center.

[0070] In at least one embodiment, these neural network-enabled boards can control air flow, supply, and return at different locations, such as where air is blown into a raised air space under a server rack, the air flow passes through the servers and then returns over the servers. In at least one embodiment, these boards can be used to predict, control, and create optimal solutions for such data centers to maintain desired operating conditions without loss of equipment or downtime due to temperature issues or heat events. In at least one embodiment, this can be based on current and expected loads and measured or detected network conditions. In at least one embodiment, this approach can also be applied to other types of equipment, and can also include UPS power supplies. In at least one embodiment, any device with a logic board or component can have this small neural network code injected for these and other such purposes. In at least one embodiment, such a network can be divided into all devices available in a unit or installation, so that in a device such as a PDU, the board can completely adjust or cut power to a server node, for example in case of a detected or predicted leak, and if operation continues, the associated device can suffer damage. In at least one embodiment, operation can be smoothly terminated or power can be shut off in order to avoid damage. In at least one embodiment, an executing program can instead be terminated in order to at least avoid data loss.

[0071] In at least one embodiment, a neural network can predict our future fluid temperatures at different locations based on available information. In at least one embodiment, this can include a snapshot of current information, or can include at least some data from recent past. In at least one embodiment, these predictions can then be used to adjust a number of aspects, such as fluid temperature or flow rate. In at least one embodiment, a cooling distribution unit can adjust the flow of liquid or coolant temperature. In at least one embodiment, such a device can take these predictions and be proactive in order to prevent any undesirable events before they occur. In at least one embodiment, detection of an external event such as a forest fire can also be used to predict a future significant increase in temperature in a data center, which can cause this data center to smoothly shut down all equipment and save data, move data to another data center, or bring additional cooling systems online to provide additional cooling as needed to prevent excessive internal heat events. In at least one embodiment, this can all be done before any increase in internal temperature is detected.

[0072] In at least one embodiment, various sensors can provide information about a current state of a computing environment. In at least one embodiment, this can include using sensors, such as temperature sensors, load sensors, flow sensors, or pressure sensors, which can be collected instantaneously or historically. In at least one embodiment, predictions made based on data from these sensors can be compared to one or more thresholds, ranges, or other operational criteria to determine whether any changes should be made. In at least one embodiment, this can include making adjustments to prevent unacceptable temperature rises at particular locations within a data center or other such environment. In at least one embodiment, this can include shutting down valves or increasing coolant flow, adjusting coolant temperature, or sounding an alarm, among other such remedial measures.

[0073] In at least one implementation, as Figure 5A indicated, a process 500 for regulating one or more environmental control components can be performed. In at least one embodiment, environmental data for one or more locations in a computing environment is captured 502. In at least one embodiment, this can include data captured by sensors in racks, servers, cooling units, or other such devices. In at least one embodiment, at least some of this environmental data can be provided 504 as input to one or more neural networks, as can be utilized by a neural network-enabled board or device within or associated with one or more devices or systems in this environment. In at least one embodiment, one or more predictions can be received 506 from these neural networks, where these predictions relate to future values at one or more locations within this computing environment, where these values can relate to environmental aspects such as temperature, pressure, fluid flow, power, humidity, etc. In at least one embodiment, these future values can be compared 508 to one or more related thresholds or ranges. In at least one embodiment, other values can also be predicted and analyzed, and can influence operation of computing devices within this environment. A determination can be made 510 as to whether any of these predicted values exceed a maximum threshold or otherwise fall outside of an allowable or specified range. If not, the process can continue. If one or more predicted values exceed such a threshold, or fall outside of such a range, one or more environmental control components can be adjusted 512 to keep one or more of these future values below a related threshold, or within a related range. In at least one embodiment, the process can subsequently continue with adjustments made based at least in part on future predictions. In at least one embodiment, adjustments can be made even if a value such as temperature will not exceed such a threshold, but in an attempt to maintain a desired temperature or environmental condition.

[0074] In at least one embodiment, as Figure 5BAs shown, a process 550 for determining one or more temperature control settings can be performed. In at least one embodiment, input is received 552 relating to environmental parameters of one or more servers. In at least one embodiment, this input can include data relating to temperature, airflow, pressure, or other such values at one or more locations. In at least one embodiment, one or more neural networks can be utilized to predict 554 one or more future temperatures using this input, such as to predict temperatures at one or more future points in time in or near these servers. In at least one embodiment, these predicted future temperatures can then be used to determine 556 one or more temperature control settings for these one or more servers. In at least one embodiment, this can include adjusting fluid temperature or flow, or power settings, in order to maintain temperatures within a desired range and avoid, for example, predicted temperatures for one or more locations.

[0075] Servers and data centers

[0076] The following figures set forth, without limitation, example network server and data center based systems that can be used to implement at least one embodiment.

[0077] Figure 6 A distributed system 600 is shown, in accordance with at least one embodiment. In at least one embodiment, the distributed system 600 includes one or more client computing devices 602, 604, 606, and 608, which are configured to execute and operate a client application, such as a web browser, a proprietary client, and / or variations or combinations thereof. In at least one embodiment, server 612 can be communicatively coupled with remote client computing devices 602, 604, 606, and 608 via network 610.

[0078] In at least one embodiment, server 612 can be adapted to execute one or more software applications or services, such as services and applications that can manage session activity for single sign-on (SSO) access across multiple data centers. In at least one embodiment, server 612 can also provide other services, or software applications can include non-virtual and virtual environments. In at least one embodiment, these services can be provided as web-based services or cloud services, or under a software as a service (SaaS) model, to users of client computing devices 602, 604, 606, and / or 608. In at least one embodiment, users operating client computing devices 602, 604, 606, and / or 608 can in turn utilize one or more client applications to interact with server 612 to utilize services provided by these components.

[0079] In at least one embodiment, software components 618, 620, and 622 of system 600 are implemented on server 612. In at least one embodiment, one or more components of system 600 and / or the services provided by these components may also be implemented by one or more client computing devices 602, 604, 606, and / or 608. In at least one embodiment, a user operating a client computing device can then utilize one or more client applications to use the services provided by these components. In at least one embodiment, these components may be implemented using hardware, firmware, software, or a combination thereof. It should be understood that various different system configurations are possible and may differ from the distributed system 600. Therefore, Figure 6 The embodiments shown are at least one embodiment of a distributed system for implementing the system of the embodiments, and are not intended to be limiting.

[0080] In at least one embodiment, client computing devices 602, 604, 606, and / or 608 may include different types of computing systems. In at least one embodiment, the client computing device may include a portable handheld device (e.g., Cellular phone Computing tablets, personal digital assistants (PDAs), or wearable devices (e.g., Google) Head-mounted display), running software (such as Microsoft Windows) The device may run various mobile operating systems (such as iOS), including Windows Phone, Android, BlackBerry 10, Palm OS, and / or variants thereof. In at least one embodiment, the device may support different applications, such as various internet-related applications, email, short message service (SMS) applications, and may use various other communication protocols. In at least one embodiment, the client computing device may also include a general-purpose personal computer, which, by way of at least one embodiment, includes a computer running different versions of Microsoft... Apple Personal computers and / or laptops running Linux operating systems.

[0081] In at least one embodiment, the client computing device can be running a variety of commercially available operating systems. Or a workstation computer running any of the UNIX-like operating systems, including but not limited to various GNU / Linux operating systems such as Google Chrome OS. In at least one embodiment, the client computing device may further include electronic devices capable of communicating via one or more networks 610, such as thin client computers, internet-enabled gaming systems (e.g., with or without...). Microsoft Xbox game console) and / or personal messaging devices. Although Figure 6 Distributed system 600 in FIG. 1 is shown with four client computing devices, but any number of client computing devices can be supported. Other devices, such as devices with sensors, etc. can interact with server 612.

[0082] In at least one embodiment, network 610 in distributed system 600 can be any type of network in which systems can communicate with one another. In at least one embodiment, network 610 can be capable of supporting communication in accordance with any one or more of numerous different wired and / or any other wireless protocol), and / or any combination of these and / or other networks.

[0083] In at least one embodiment, server 612 can be made up of one or more general purpose computers, specialized server computers (including by way of at least one embodiment, PC (personal computer) servers, UNIX® servers, mid-range servers, mainframe computers, rack-mounted servers, etc.), server farms, server clusters, or any other arrangement and / or combination that is suitable. In at least one embodiment, server 612 can include one or more virtual machines running virtual operating systems, or other computing architectures involving virtualization. In at least one embodiment, one or more pools of flexible logical storage devices can be virtualized for use by servers. In at least one embodiment, virtual networks can be controlled by server 612 using software defined networking. In at least one embodiment, server 612 can be adapted to run one or more services or software applications.

[0084] In at least one embodiment, server 612 can run any operating system, and any commercially available server operating system. In at least one embodiment, server 612 can also run any of a variety of additional server applications and / or mid-tier applications, including HTTP (HyperText server, database server, and / or variations thereof. In at least one embodiment, example database servers include, without limitation, those available from Oracle, Microsoft, Sybase, IBM (International Business Machine) and / or variations thereof.

[0085] In at least one embodiment, server 612 can include one or more applications to analyze and correlate data feeds and / or event updates received from users of client computing devices 602, 604, 606, and 608. In at least one embodiment, data feeds and / or event updates can include, without limitation, Twitter® feeds, Facebook® updates, web feeds such as Rich Site Summary (RSS) feeds, and / or real-time updates such as provided over XMPP (Extensible Messaging and Presence Protocol) i feeds, updates or real-time updates that can include real-time events related to sensor data applications, financial quotes, network performance measurement tools (e.g., network monitoring and traffic management applications), clickstream analysis tools, automobile traffic monitoring, and / or variations thereof. In at least one embodiment, server 612 can also include one or more applications to display the data feeds and / or real-time events via one or more display devices of client computing devices 602, 604, 606, and 608.

[0086] In at least one embodiment, distributed system 600 can also include one or more databases 614 and 616. In at least one embodiment, a database can provide a mechanism for storing information such as user interaction information, usage pattern information, adaptation rule information, and other information. In at least one embodiment, databases 614 and 616 can reside in various locations. In at least one embodiment, one or more of databases 614 and 616 can reside on a non-transitory storage medium local to (and / or resident in) server 612. In at least one embodiment, databases 614 and 616 can be remote from server 612 and in communication with server 612 via a network- or dedicated-connection. In at least one embodiment, databases 614 and 616 can reside in a storage area network (SAN). In at least one embodiment, any necessary files for performing functions attributed to server 612 can be stored locally on server 612 and / or remotely when appropriate. In at least one embodiment, databases 614 and 616 can include a relational database such as one adapted to store, update, and retrieve data in response to SQL-formatted commands.

[0087] Figure 7 An example data center 700 is shown in accordance with at least one embodiment. In at least one embodiment, data center 700 includes, without limitation, a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0088] In at least one embodiment, such as Figure 7 As shown, the data center infrastructure layer 710 may include a resource coordinator 712, grouped computing resources 714, and node computing resources (“nodes CR”) 716(1)-716(N), where “N” represents any complete positive integer. In at least one embodiment, nodes CR 716(1)-716(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (“FPGAs”), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 716(1)-716(N) may be servers having one or more of the aforementioned computing resources.

[0089] In at least one embodiment, the grouped computing resources 714 may include individual groups (not shown) of node CRs housed in one or more racks, or a plurality of racks (also not shown) housed in data centers in various geographic locations. The individual groups of node CRs within the grouped computing resources 714 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0090] In at least one embodiment, resource coordinator 712 may configure or otherwise control one or more nodes CR716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource coordinator 712 may include a Software Design Infrastructure (“SDI”) management entity for data center 700. In at least one embodiment, resource coordinator 712 may include hardware, software, or some combination thereof.

[0091] In at least one embodiment, such as Figure 7As shown, framework layer 720 includes, without limitation, a job scheduler 732, a configuration manager 734, a resource manager 736, and a distributed file system 738. In at least one embodiment, framework layer 720 can include a framework that supports software 752 of software layer 730 and / or one or more applications 742 of application layer 740. In at least one embodiment, software 752 or applications 742 can include, respectively, web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 720 can be, without limitation, a type of free and open-source software web application framework such as Apache Spark™ (hereinafter “Spark”) that can utilize distributed file system 738 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 732 can include a Spark driver to facilitate scheduling workloads supported by various layers of data center 700. In at least one embodiment, configuration manager 734 can be capable of configuring different layers, such as software layer 730 and framework layer 720 including Spark and distributed file system 738 for supporting large-scale data processing. In at least one embodiment, resource manager 736 can be capable of managing clustered or grouped computing resources mapped to or allocated for supporting distributed file system 738 and job scheduler 732. In at least one embodiment, clustered or grouped computing resources can include grouped computing resources 714 on data center infrastructure layer 710. In at least one embodiment, resource manager 736 can coordinate with resource orchestrator 712 to manage these mapped or allocated computing resources.

[0092] In at least one embodiment, software 752 included in software layer 730 can include software used by at least portions of node C.R.s 716(1)-716(N), grouped computing resources 714, and / or distributed file system 738 of framework layer 720. One or more types of software can include, without limitation, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0093] In at least one embodiment, one or more applications 742 included in application layer 740 can include one or more types of applications used by at least portions of node C.R.s 716(1)-716(N), grouped computing resources 714, and / or distributed file system 738 of framework layer 720. At least one or more types of applications can include, without limitation, CUDA applications, 5G network applications, artificial intelligence applications, data center applications, and / or variations thereof.

[0094] In at least one embodiment, any of configuration manager 734, resource manager 736, and resource orchestrator 712 can implement any number and type of self-modifying actions based on any number and type of data acquired in any technically feasible manner. In at least one embodiment, self-modifying actions can relieve data center operators of data center 700 from making possibly poor configuration decisions and can avoid underutilization and / or poor performing portions of a data center.

[0095] Figure 8 A client-server network 804 formed of a plurality of network server computers 802 interconnected is shown, according to at least one embodiment. In at least one embodiment, each network server computer 802 stores data accessible by other network server computers 802 and by client computers 806 and networks 808 linked to a wide area network 804. In at least one embodiment, configuration of client-server network 804 can change over time as client computers 806 and one or more networks 808 connect and disconnect with network 804, and as one or more backbone server computers 802 are added or removed from network 804. In at least one embodiment, client-server network includes client computers 806 and networks 808 when they are connected with network server computers 802. In at least one embodiment, term computer includes any device or machine that is capable of accepting data, applying prescribed processes to data, and providing results of processes.

[0096] In at least one embodiment, client-server network 804 stores information accessible by network server computers 802, remote networks 808, and client computers 806. In at least one embodiment, network server computers 802 are formed of mainframe computers and / or microcomputers each having one or more processors. In at least one embodiment, server computers 802 are linked together by wired and / or wireless transmission media, such as conductive wires, fiber optic cables, and / or microwave transmission media, satellite transmission media, or other conductive, optical, or electromagnetic wave transmission media.

[0097] In at least one embodiment, client computers 806 access network server computers 802 through a similar wired or wireless transfer medium. In at least one embodiment, client computers 806 can link into client-server network 804 using a modem and standard telephone communication network. In at least one embodiment, alternative carrier systems, such as cable and satellite systems, can also be used to link into client-server network 804. In at least one embodiment, other private or time-shared carrier systems can be used. In at least one embodiment, network 804 is a global information network, such as the Internet. In at least one embodiment, the network is a private intranet using similar protocols as the Internet but with added security measures and restricted access control. In at least one embodiment, network 804 is a private or semi-private network using a proprietary communications protocol.

[0098] In at least one embodiment, client computers 806 are any end-user computer and can also be a mainframe computer, a minicomputer, or a microcomputer having one or more microprocessors. In at least one embodiment, server computers 802 can sometimes act as client computers accessing another server computer 802. In at least one embodiment, remote network 808 can be a local area network, a network added to a wide area network through an independent service provider (ISP) for the Internet, or another group of computers interconnected by wired or wireless transfer medium having a fixed or changing configuration over time. In at least one embodiment, client computers 806 can link into and access network 804 independently or through remote network 808.

[0099] Figure 9 A computer network 908 connecting one or more computers is shown, in accordance with at least one embodiment. In at least one embodiment, network 908 can be any type of electrically connected group of computers, including, for example, the following networks: the Internet, an intranet, a local area network (LAN), a wide area network (WAN), or an interconnected combination of these network types. In at least one embodiment, connections within network 908 can be a remote modem, Ethernet (IEEE 802.3), Token Ring (IEEE 802.5), Fiber Distributed Datalink Interface (FDDI), Asynchronous Transfer Mode (ATM), or any other communications protocol. In at least one embodiment, computing devices linked to the network can be desktops, servers, portable, handheld, set-top boxes, personal digital assistants (PDAs), terminals, or any other desired type or configuration. In at least one embodiment, network-connected devices can vary widely in processing power, internal memory, and other performance, depending on their functionality.

[0100] In at least one embodiment, communications within network and to or from computing devices connected to network can be wired or wireless. In at least one embodiment, network 908 can comprise, at least in part, the worldwide public Internet that typically connects multiple users according to a client-server model according to Transmission Control Protocol / Internet Protocol (TCP / IP) specifications. In at least one embodiment, a client-server network is a dominant model for communication between two computers. In at least one embodiment, a client computer (“client”) issues one or more commands to a server computer (“server”). In at least one embodiment, a server fulfills client commands by accessing available network resources and returning information to a client according to client commands. In at least one embodiment, client computer systems and network resources residing on network servers are assigned network addresses for identification during communications between elements of a network. In at least one embodiment, communications from other network-connected systems to a server will include a network address of a relevant server / network resource as part of a communication, so that an appropriate destination for data / requests is identified as a recipient. In at least one embodiment, when network 908 comprises the global Internet, network addresses are IP addresses in TCP / IP format, which can route data, at least in part, to an email account, website, or other Internet tool residing on a server. In at least one embodiment, information and services residing on network servers can be made available to web browsers of client computers through domain names (e.g., www.site.com) mapped to IP addresses of network servers.

[0101] In at least one embodiment, multiple clients 902, 904, and 906 are connected to network 908 via corresponding communication links. In at least one embodiment, each of these clients can access network 908 via any desired form of communication, such as via a dial-up modem connection, cable link, digital subscriber line (DSL), wireless or satellite link, or any other form of communication. In at least one embodiment, each client can communicate using any machine compatible with network 908 (e.g., a personal computer (PC), a workstation, a special purpose terminal, a personal data assistant (PDA), or other similar device). In at least one embodiment, clients 902, 904, and 906 can or can not be located in the same geographic region.

[0102] In at least one embodiment, multiple servers 910, 912, and 914 are connected to network 918 to serve clients in communication with network 918. In at least one embodiment, each server is typically a powerful computer or device that manages network resources and responds to client commands. In at least one embodiment, servers include computer-readable data storage media, such as hard drives and RAM memory, that store program instructions and data. In at least one embodiment, servers 910, 912, 914 run application programs that respond to client commands. In at least one embodiment, server 910 can run a web server application for responding to client requests for HTML pages, and can also run a mail server application for receiving and routing electronic mail. In at least one embodiment, other application programs can also run on server 910, such as an FTP server or media server for streaming audio / video data to clients. In at least one embodiment, different servers can be dedicated to performing different tasks. In at least one embodiment, server 910 can be a dedicated web server that manages resources related to a website for different users, while server 912 can be dedicated to providing electronic mail (email) management. In at least one embodiment, other servers can be dedicated to media (audio, video, etc.), file transfer protocol (FTP), or a combination of any two or more services typically available or provided over a network. In at least one embodiment, each server can be in the same or different location as other servers. In at least one embodiment, there can be multiple servers performing mirroring tasks for users, relieving congestion or minimizing traffic directed to and from a single server. In at least one embodiment, servers 910, 912, 914 are under the control of a web hosting provider that maintains and delivers third-party content over network 918.

[0103] In at least one embodiment, a web hosting provider delivers services to two different types of clients. In at least one embodiment, one type, which can be referred to as a browser, requests content from servers 910, 912, 914, such as web pages, email messages, video clips, etc. In at least one embodiment, a second type, which can be referred to as a user, hires the web hosting provider to maintain network resources, such as a website, and make them available to browsers. In at least one embodiment, users contract with the web hosting provider to make memory space, processor capacity, and communication bandwidth available to their desired network resources in accordance with an amount of server resources that the user desires to utilize.

[0104] In at least one embodiment, in order for the web hosting provider to service both clients, the application that manages the web resources hosted by the server must be properly configured. In at least one embodiment, the program configuration process involves defining a set of parameters that at least partially control the application's response to browser requests and also at least partially define the server resources available to a particular user.

[0105] In one embodiment, the intranet server 916 communicates with the network 908 via a communication link. In at least one embodiment, the intranet server 916 communicates with a server manager 918. In at least one embodiment, the server manager 918 includes a database of application configuration parameters used in the servers 910, 912, 914. In at least one embodiment, a user modifies the database 920 via the intranet 916, and the server manager 918 interacts with the servers 910, 912, 914 to modify the application parameters so that they match the contents of the database. In at least one embodiment, a user logs onto the intranet server 916 by connecting to the intranet 916 via the computer 902 and entering authentication information such as a user name and password.

[0106] In at least one embodiment, when a user wishes to register a new service or modify an existing service, the intranet server 916 authenticates the user and provides the user with an interactive screen display / control panel that allows the user to access the configuration parameters for a particular application. In at least one embodiment, the user is presented with a number of modifiable text boxes that describe aspects of the configuration of the user's website or other web resources. In at least one embodiment, if the user desires to increase the amount of memory space reserved on the server for their website, the user is provided with a field in which the user specifies the desired amount of memory space. In at least one embodiment, in response to receiving this information, the intranet server 916 updates the database 920. In at least one embodiment, the server manager 918 forwards this information to the appropriate server, and the new parameters are used during operation of the application. In at least one embodiment, the intranet server 916 is configured to provide a user with access to the configuration parameters for the hosted web resources (e.g., web pages, email, FTP sites, media sites, etc.) that the user has contracted with the web hosting service provider.

[0107] Figure 10AA networked computer system 1000A is shown in accordance with at least one embodiment. In at least one embodiment, networked computer system 1000A includes a plurality of nodes or personal computers ("PCs") 1002, 1018, 1020. In at least one embodiment, personal computers or nodes 1002 include a processor 1014, a memory 1016, a video camera 1004, a microphone 1006, a mouse 1008, a speaker 1010, and a monitor 1012. In at least one embodiment, PCs 1002, 1018, 1020 can each run one or more desktop servers for an internal network within a given company, or can be servers for a general purpose network not limited to a particular environment. In at least one embodiment, each PC node of a network has one server, such that each PC node of a network represents a particular network server with a particular network URL address. In at least one embodiment, each server has a default web page for a user of that server by default, which default web page can itself contain embedded URLs pointing to further sub-pages of that user on that server, or to other servers on the network or pages on other servers.

[0108] In at least one embodiment, nodes 1002, 1018, 1020 and other nodes of a network are interconnected via a medium 1022. In at least one embodiment, medium 1022 can be a communication channel such as an Integrated Services Digital Network ("ISDN"). In at least one embodiment, different nodes of a networked computer system can be connected by different communication media, including a Local Area Network ("LAN"), a plain old telephone line ("POTS"), sometimes referred to as the Public Switched Telephone Network ("PSTN"), and / or variants thereof. In at least one embodiment, different nodes of a network can also constitute computer system users interconnected via a network such as the Internet. In at least one embodiment, each server on a network (running from a particular node of a network in a given instance) has a unique address or identification within a network, which can be specified according to a URL.

[0109] In at least one embodiment, a plurality of multipoint conference units ("MCUs") can thus be used to transmit data to and from various nodes or "endpoints" of a conferencing system. In at least one embodiment, nodes and / or MCUs can be interconnected by ISDN links or by a Local Area Network ("LAN") in addition to various other communication media, such as nodes connected by the Internet. In at least one embodiment, nodes of a conferencing system can typically be connected directly to a communication medium such as a LAN or through an MCU, and a conferencing system can include other nodes or elements such as routers, servers, and / or variants thereof.

[0110] In at least one embodiment, processor 1014 is a general purpose programmable processor. In at least one embodiment, processors of networked computer system 1000A’s nodes can also be specialized video processors. In at least one embodiment, different peripheral devices and components of nodes, such as those of node 1002, can be different from those of other nodes. In at least one embodiment, nodes 1018 and 1020 can be configured similarly to or differently from node 1002. In at least one embodiment, nodes can be implemented on any suitable computer system, in addition to a PC system.

[0111] Figure 10B Networked computer system 1000B is shown, in accordance with at least one embodiment. In at least one embodiment, system 1000B shows a network, such as LAN 1024, which can be used to interconnect various nodes that can communicate with each other. In at least one embodiment, attached to LAN 1024 are a number of nodes, such as PC nodes 1026, 1028, 1030. In at least one embodiment, nodes can also connect to a LAN via a network server or other device. In at least one embodiment, system 1000B includes other types of nodes or elements, including routers, servers, and nodes, in at least one embodiment.

[0112] Figure 10C Networked computer system 1000C is shown, in accordance with at least one embodiment. In at least one embodiment, system 1000C shows a WWW system with communication across a backbone communication network, such as Internet 1032, which can be used to interconnect various nodes of a network. In at least one embodiment, the WWW is a set of protocols that operate over the Internet, and allows graphical interface systems to operate thereon to access information over the Internet. In at least one embodiment, attached to Internet 1032 in the WWW are a number of nodes, such as PCs 1040, 1042, 1044. In at least one embodiment, nodes interface with other nodes of the WWW through WWW HTTP servers, such as servers 1034, 1036. In at least one embodiment, PC 1044 can be a PC that forms a node of network 1032, and PC 1044 itself runs its server 1036, although PC 1044 and server 1036 are shown separately in Figure 10C for purposes of illustration.

[0113] In at least one embodiment, the WWW is a distributed type of application, characterized by WWW HTTP, the protocol of the WWW, which operates over the Transmission Control Protocol / Internet Protocol (“TCP / IP”) of the Internet. In at least one embodiment, the WWW can thus be characterized by a set of protocols (i.e., HTTP) that operate over the Internet as its “backbone.”

[0114] In at least one embodiment, a web browser is an application running on a node of a network that allows a user of a particular server or node to view such information in a WWW-type compatible network system, and thus allows the user to search for graphics and text-based files linked together using hypertext links embedded in documents or files available from servers on a network that understand HTTP. In at least one embodiment, when a user uses another server on a network such as the Internet to retrieve a given web page of a first server associated with a first node, the retrieved document can have different hypertext links embedded in it, and a local copy of the page is created locally at the user's machine. In at least one embodiment, when the user clicks on a hypertext link, the information stored locally related to the selected hypertext link is typically sufficient to allow the user's machine to open a connection through the Internet to the server indicated by the hypertext link.

[0115] In at least one embodiment, more than one user can be coupled to each HTTP server through a LAN such as LAN 1038 as shown with respect to WWW HTTP server 1034. In at least one embodiment, system 1000C can also include other types of nodes or elements. In at least one embodiment, a WWW HTTP server is an application running on a machine such as a PC. In at least one embodiment, each user can be considered to have a unique "server" as shown with respect to PC 1044. In at least one embodiment, a server can be considered to be a server such as WWW HTTP server 1034 that provides access to a network for a LAN or multiple nodes or multiple LANs. In at least one embodiment, there are multiple users, each with a desktop PC or node of a network, each desktop PC potentially setting up a server for its user. In at least one embodiment, each server is associated with a particular network address or URL that provides a default web page for that user when accessed. In at least one embodiment, the web page can contain further links (embedded URLs) that point to further sub-pages of that user on that server, or to other servers on the network or to pages on other servers on the network.

[0116] Cloud computing and services

[0117] The following figures set forth, but are not limited to, exemplary cloud-based systems that can be used to implement at least one embodiment.

[0118] In at least one embodiment, cloud computing is a style of computing in which dynamically scalable and often virtualized resources are provided as a service over the Internet. In at least one embodiment, users do not need to have knowledge, understanding or control over the technology infrastructure in the “cloud” that supports them, in at least one embodiment, cloud computing converges infrastructure, platform and software as a service with common themes that include reliability, scalability and management abstraction. In at least one embodiment, a typical cloud deployment, such as in a private cloud (e.g., enterprise network) or data center (DC) in a public cloud (e.g., Internet), can consist of thousands of servers (or alternatively, VMs), hundreds of Ethernet, Fibre Channel or Fibre Channel over Ethernet (FCoE) ports, switching and storage infrastructure, etc. In at least one embodiment, a cloud can also consist of network services infrastructure, such as IPsec VPN hubs, firewalls, load balancers, Wide Area Network (WAN) optimizers, etc. In at least one embodiment, remote subscribers can securely access cloud applications and services by connecting via a VPN tunnel, such as an IPsec VPN tunnel.

[0119] In at least one embodiment, cloud computing is a model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, and services) that can be rapidly provisioned and released with minimal management effort or service provider interaction.

[0120] In at least one embodiment, cloud computing is characterized by on-demand self-service, wherein consumers can unilaterally provision computing capabilities, such as server time and network storage, as needed automatically (without human interaction with each service provider). In at least one embodiment, cloud computing is characterized by broad network access, wherein capabilities are available over a network and accessed through standard mechanisms that promote the use of heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs). In at least one embodiment, cloud computing is characterized by resource pooling, wherein the provider’s computing resources are pooled to serve multiple consumers using a multi-tenant model, with different physical and virtual resources dynamically assigned and reassigned according to consumer demand. In at least one embodiment, there is a sense of location independence, as consumers generally have no control or knowledge over the exact location of the provided resources, but can be able to specify the location at a higher level of abstraction (e.g., country, state, or data center).

[0121] In at least one embodiment, resources include storage, processing, memory, network bandwidth, and virtual machines. In at least one embodiment, cloud computing is characterized by rapid elasticity, in which capability can be rapidly and elastically provisioned (in some cases automatically), in some cases with little or no management effort or interaction with provider. In at least one embodiment, for consumers, capability is available almost instantaneously, and in many cases automatically, when required, and in at least one embodiment, cloud computing is characterized by measured service, in which cloud systems automatically control and optimize resource use by leveraging utilization levels of resources on demand such that certain workloads can be served at optimal efficiency.

[0122] In at least one embodiment, cloud computing can be associated with different services. In at least one embodiment, cloud Software as a Service (SaaS) can refer to a paradigm for enabling on-demand access to software. In at least one embodiment, SaaS provides consumers with a complete solution at a fixed price, eliminating the need for additional capital outlays. In at least one embodiment, SaaS is typically deployed on a pay-per-use basis, which allows the total functional and operational capacity to be exactly matched with demand at a particular point in time.

[0123] In at least one embodiment, cloud Platform as a Service (PaaS) can refer to a paradigm for enabling developers to deploy their created applications onto a cloud infrastructure without managing the underlying cloud infrastructure including the networks, servers, operating systems, or storage. In at least one embodiment, PaaS is typically deployed on a pay-per-use basis, which allows the total functional and operational capacity to be exactly matched with demand at a particular point in time.

[0124] In at least one embodiment, cloud Infrastructure as a Service (IaaS) can refer to a paradigm for providing consumers with access to processing resources, storage, networks and other fundamental computing resources where the consumer is able to deploy and run arbitrary software, which can include operating systems and applications. In at least one embodiment, IaaS is typically deployed on a pay-per-use basis, which allows the total functional and operational capacity to be exactly matched with demand at a particular point in time.

[0125] In at least one embodiment, cloud computing provides a convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, and client data, etc.) that can be rapidly provisioned and released with minimal management effort or interaction with a provider of the service. In at least one embodiment, this cloud resource can include tools delivered as a service to users that allow for the creation of a custom operating system, applications, or specific

[0126] Figure 11 One or more components of a system environment 1100, in accordance with one or more embodiments, are shown in which services can be provided as third party network services. In at least one embodiment, a third party network can be referred to as a cloud, a cloud network, a cloud computing network, and / or variations thereof. In at least one embodiment, system environment 1100 includes one or more client computing devices 1104, 1106, and 1108, which can be used by users to interact with a third party network infrastructure system 1102 that provides third party network services, which can be referred to as cloud computing services. In at least one embodiment, third party network infrastructure system 1102 can include one or more computers and / or servers.

[0127] It is to be appreciated that the third party network infrastructure system 1102 depicted in Figure 11 In at least one embodiment, the third party network infrastructure system 1102 depicted in Figure 11 In at least one embodiment, an embodiment of a third party network infrastructure system is depicted. In at least one embodiment, third party network infrastructure system 1102 can have more or fewer components than those depicted in Figure 11 In at least one embodiment, the third party network infrastructure system 1102 depicted in

[0128] In at least one embodiment, client computing devices 1104, 1106, and 1108 can be configured to operate a client application such as a web browser that can be used by users of client computing devices to interact with third party network infrastructure system 1102 to use services provided by third party network infrastructure system 1102. In at least one embodiment, example system environment 1100 is shown with three client computing devices, but any number of client computing devices can be supported. In at least one embodiment, other devices such as devices with sensors, etc. can interact with third party network infrastructure system 1102. In at least one embodiment, network(s) 1110 can facilitate communications and exchange of data between client computing devices 1104, 1106, and 1108 and third party network infrastructure system 1102.

[0129] In at least one embodiment, services provided by third party network infrastructure system 1102 can include hosting of services provided on-demand to users of the third party network infrastructure system. In at least one embodiment, different services can also be provided including, but not limited to, online data storage and backup solutions, Web-based e-mail services, hosted office suites and document collaboration services, database management and processing, managed technical support services, and / or variations thereof. In at least one embodiment, services provided by a third party network infrastructure system can dynamically expand to meet the needs of its users.

[0130] In at least one embodiment, a particular instance of a service provided by third party network infrastructure system 1102 can be referred to as a “service instance.” In at least one embodiment, generally, any service available to a user from a third party network service provider system via a communications network, such as the Internet, is referred to as a “third party network service.” In at least one embodiment, in a public third party network environment, servers and systems that make up the third party network service provider system are different from a customer’s own on-premise servers and systems. In at least one embodiment, a third party network service provider system can host an application and users can order and use the application on-demand over a communications network, such as the Internet.

[0131] In at least one embodiment, a service in a computer network third party network infrastructure can include protected computer network access to storage, hosted databases, hosted network servers, software applications, or other services provided to a user by a third party network vendor. In at least one embodiment, a service can include password protected access to remote storage on a third party network over the Internet. In at least one embodiment, a service can include a web services based hosted relational database and scripting language middleware engine for private use by a networked developer. In at least one embodiment, a service can include access to an email software application hosted on a website of a third party network vendor.

[0132] In at least one embodiment, third party network infrastructure system 1102 can include a set of application, middleware, and database services delivered in a self-service, subscription-based, elastically scalable, reliable, highly available, and secure manner. In at least one embodiment, third party network infrastructure system 1102 can also provide “big data” related computational and analytical services. In at least one embodiment, the term “big data” is commonly used to refer to extremely large datasets that can be stored and manipulated by analysts and researchers to visualize large amounts of data, detect trends, and / or otherwise interact with the data. In at least one embodiment, big data and related applications can be hosted and / or manipulated by infrastructure system at many levels and at different scales. In at least one embodiment, tens, hundreds, or thousands of processors linked in parallel can act on such data to present the data or simulate an outside force on the data or what it represents. In at least one embodiment, these datasets can involve structured data such as structured data in a database or otherwise organized according to a structured model and / or unstructured data (e.g., emails, images, data blobs (binary large objects), web pages, complex event processing). In at least one embodiment, by leveraging capabilities of an embodiment to relatively quickly focus more (or less) computing resources on a target, a third party network infrastructure system can be better used to perform tasks on big data sets based on needs from businesses, government agencies, research organizations, private individuals, groups of individuals or organizations who like to be reminded, or other entities.

[0133] In at least one embodiment, third party network infrastructure system 1102 can be adapted to automatically provide, manage and track customer subscriptions for services provided by third party network infrastructure system 1102. In at least one embodiment, third party network infrastructure system 1102 can provide third party network services via different deployment models. In at least one embodiment, services can be provided under a public third party network model in which third party network infrastructure system 1102 is owned by an organization that sells third party network services and makes services available to the general public or different industry enterprises. In at least one embodiment, services can be provided under a private third party network model in which third party network infrastructure system 1102 operates for a single organization and can provide services for one or more entities within the organization. In at least one embodiment, third party network services can also be provided under a community third party network model in which third party network infrastructure system 1102 and the services provided by third party network infrastructure system 1102 are shared by several organizations in a related community. In at least one embodiment, third party network services can also be provided under a hybrid third party network model, which is a combination of two or more different models.

[0134] In at least one embodiment, services provided by third party network infrastructure system 1102 can include one or more services provided under a Software as a Service (SaaS) category, a Platform as a Service (PaaS) category, an Infrastructure as a Service (IaaS) category, or other categories of services including hybrid services. In at least one embodiment, a customer can order one or more services provided by third party network infrastructure system 1102 via a subscription order. In at least one embodiment, third party network infrastructure system 1102 then performs processing to provide services in customer’s subscription order.

[0135] In at least one embodiment, services provided by third party network infrastructure systems 1102 can include, without limitation, application services, platform services, and infrastructure services. In at least one embodiment, application services can be provided by third party network infrastructure systems via a SaaS platform. In at least one embodiment, a SaaS platform can be configured to provide third party network services that fall into the SaaS category. In at least one embodiment, a SaaS platform can provide the capability for customers to use applications, running on third party network infrastructure systems, that are built using an integrated development and deployment platform. In at least one embodiment, a SaaS platform can manage and control underlying software and infrastructure for providing the SaaS services. In at least one embodiment, by utilizing the services provided by a SaaS platform, customers can no longer have to worry about acquiring and managing the underlying hardware and software. In at least one embodiment, customers can obtain an application service without the need for customers to purchase, install, and manage software or hardware. In at least one embodiment, various different SaaS services can be provided. In at least one embodiment, this can include, without limitation, services for sales performance management, enterprise integration, and business flexibility that provide solutions for managing sales, aligning sales with customers, and improving business responsiveness, respectively.

[0136] In at least one embodiment, platform services can be provided by third party network infrastructure systems 1102 via a PaaS platform. In at least one embodiment, a PaaS platform can be configured to provide third party network services that fall into the PaaS category. In at least one embodiment, platform services can include, without limitation, services enabling organizations to combine existing applications with new applications built using the shared services provided by the platform, as well as the ability to establish new applications that leverage the shared services provided by the platform. In at least one embodiment, a PaaS platform can manage and control the underlying software and infrastructure for providing the PaaS services. In at least one embodiment, customers can obtain PaaS services provided by third party network infrastructure systems 1102 without the need for customers to purchase, install, and manage the underlying hardware and software.

[0137] In at least one embodiment, by utilizing the services provided by a PaaS platform, customers can use programming languages and tools supported by the third party network infrastructure system and also control deployed services. In at least one embodiment, platform services provided by a third party network infrastructure system can include database third party network services, middleware third party network services, and third party network services. In at least one embodiment, database third party network services can support a shared services deployment model that enables organizations to pool database resources and offer databases as a service to customers in the form of database third party networks. In at least one embodiment, middleware third party network services can provide customers with a platform to develop and deploy various business applications, and third party network services can provide customers with a platform to deploy applications in a third party network infrastructure system.

[0138] In at least one embodiment, various different infrastructure services can be provided by an IaaS platform in third party network infrastructure system. In at least one embodiment, infrastructure services facilitate the management and control of underlying computing resources, such as storage, networks, and other fundamental computing resources for customers utilizing services provided by SaaS and PaaS platforms.

[0139] In at least one embodiment, third party network infrastructure system 1102 can also include infrastructure resources 1130 for providing resources used to provide different services to customers of third party network infrastructure system. In at least one embodiment, infrastructure resources 1130 can include pre-integrated and optimized combinations of hardware, such as, for example, servers, storage, and networking resources to perform the services provided by PaaS and SaaS platforms, and other resources.

[0140] In at least one embodiment, resources in third party network infrastructure system 1102 can be shared by multiple users and dynamically re-allocated per demand. In at least one embodiment, resources can be allocated to users in different time zones. In at least one embodiment, third party network infrastructure system 1102 can enable a first set of users in a first time zone to utilize resources of third party network infrastructure system for a specified number of hours and subsequently enable reallocation of same resources to another set of users located in a different time zone, thereby maximizing resource utilization.

[0141] In at least one embodiment, a number of internal shared services 1132 can be provided that are shared by different components or modules of third party network infrastructure system 1102 to implement services provided by third party network infrastructure system 1102. In at least one embodiment, these internal shared services can include, but are not limited to, security and identity services, integration services, enterprise repository services, enterprise manager services, virus scanning and whitelist services, high availability, backup and recovery services, services for enabling third party network support, email services, notification services, file transfer services, and / or variations thereof.

[0142] In at least one embodiment, third party network infrastructure system 1102 can provide comprehensive management of third party network services (e.g., SaaS, PaaS, and IaaS services) in third party network infrastructure system. In at least one embodiment, third party network management functionality can include the ability to provision, manage and track subscriptions of customers received by third party network infrastructure system 1102, and / or variations thereof.

[0143] In at least one embodiment, as Figure 11As shown, the third party network management functionality can be provided by one or more modules, such as an order management module 1120, an order coordination module 1122, an order provisioning module 1124, an order management and monitoring module 1126, and an identity management module 1128. In at least one embodiment, these modules can include or use one or more computers and / or servers, which can be general purpose computers, special purpose server computers, server farms, server clusters, or any other appropriate arrangement and / or combination.

[0144] In at least one embodiment, at step 1134, a customer, using a client device, such as client computing devices 1104, 1106, or 1108, can interact with the third party network infrastructure system 1102 by placing an order for one or more services provided by the third party network infrastructure system 1102 and for a subscription to one or more services provided by the third party network infrastructure system 1102. In at least one embodiment, a customer can access third party network user interfaces (UIs), such as third party network UI 1112, third party network UI 1114, and / or third party network UI 1116, and place an order via these UIs. In at least one embodiment, order information received by the third party network infrastructure system 1102 in response to a customer placing an order can include information identifying the customer and one or more services provided by the third party network infrastructure system 1102 that the customer wants to subscribe to.

[0145] In at least one embodiment, at step 1136, order information received from a customer can be stored in an order database 1118. In at least one embodiment, if this is a new order, a new record can be created for the order. In at least one embodiment, the order database 1118 can be one of several databases operated by the third party network infrastructure system 1118 and in conjunction with other system elements.

[0146] In at least one embodiment, at step 1138, the order information can be forwarded to an order management module 1120, which can be configured to perform billing and accounting functions related to an order, such as validating an order and, upon validation, provisioning an order.

[0147] In at least one embodiment, at step 1140, information about the order can be transmitted to an order coordination module 1122 configured to coordinate the provisioning of services and resources for orders placed by customers. In at least one embodiment, the order coordination module 1122 can use the services of an order provisioning module 1124 for provisioning. In at least one embodiment, the order coordination module 1122 enables management of business processes associated with each order and applies business logic to determine whether an order should proceed to provisioning.

[0148] In at least one embodiment, at step 1142, upon receiving a new subscription order, the order coordination module 1122 sends a request to the order provisioning module 1124 to allocate resources and configure resources needed to fulfill the subscription order. In at least one embodiment, the order provisioning module 1124 implements resource allocation for services ordered by customers. In at least one embodiment, the order provisioning module 1124 provides an abstraction level between third-party network services offered by the third-party network infrastructure system 1100 and physical implementation layers for resources to be applied to provision the requested services. In at least one embodiment, this enables the order coordination module 1122 to be isolated from implementation details such as whether services and resources are provisioned in real-time or pre-provisioned and only allocated / assigned upon request.

[0149] In at least one embodiment, at step 1144, once services and resources are provisioned, a notification can be sent to the subscribing customer indicating that the requested services are now ready for use. In at least one embodiment, information (e.g., a link) can be sent to the customer that enables the customer to begin using the requested services.

[0150] In at least one embodiment, at step 1146, a customer’s subscription order can be managed and tracked by an order management and monitoring module 1126. In at least one embodiment, the order management and monitoring module 1126 can be configured to collect usage statistics about customer usage of the subscription services. In at least one embodiment, statistics can be collected for amounts of storage used, amounts of data transferred, numbers of users, and amounts and / or changes in system up times and system down times.

[0151] In at least one embodiment, third party network infrastructure system 1100 can include an identity management module 1128 configured to provide identity services such as access management and authorization services in third party network infrastructure system 1100. In at least one embodiment, identity management module 1128 can control information about customers who wish to utilize services provided by third party network infrastructure system 1102. In at least one embodiment, such information can include information to authenticate identities of such customers and information describing what actions those customers are authorized to perform with respect to different system resources (e.g., files, directories, applications, communication ports, memory segments, etc.). In at least one embodiment, identity management module 1128 can also include managing descriptive information about each customer and descriptive information about how and by whom the descriptive information can be accessed and modified.

[0152] Figure 12 A cloud computing environment 1202 is shown in accordance with at least one embodiment. In at least one embodiment, cloud computing environment 1202 includes one or more computer systems / servers 1204, such as computing devices of a personal digital assistant (PDA) or cellular telephone 1206A, a desktop computer 1206B, a laptop computer 1206C, and / or a computer system 1206N of an automobile that communicate with the one or more computer systems / servers 1204. In at least one embodiment, this allows infrastructure, platforms, and / or software to be offered as services available from and through cloud computing environment 1202, so as to allow the clients to utilize such resources without needing to individually maintain such resources. As should be appreciated, the types of computing devices 1206A-N shown are intended to be illustrative only and that cloud computing environment 1202 can communicate with any type of computerized devices over any type of network and / or network addressable connection (e.g., using a web browser). Figure 12 The types of computing devices 1206A-N shown in FIG. 12 are intended to be illustrative only and that cloud computing environment 1202 can communicate with any type of computerized devices over any type of network and / or network addressable connection (e.g., using a web browser).

[0153] In at least one embodiment, computer system / server 1204 can be operational with numerous other general purpose or special purpose computing system environments or configurations. Examples of computing systems, environments, and / or configurations that can be suitable for use with computer system / server 1204 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, hand-held or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices, and / or variants thereof.

[0154] In at least one embodiment, computer system / server 1204 can be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. In at least one embodiment, program modules include routines, programs, objects, components, logic, data structures, and / or the like that perform particular tasks or implement particular abstract data types. In at least one embodiment, exemplary computer system / server 1204 can be practiced in distributed cloud computing environments with remote processing devices that are linked through a communications network. In at least one embodiment, in a distributed cloud computing environment, program modules can be located in both local and remote computer system storage media including memory storage devices.

[0155] Figure 13 A set of functional abstraction layers provided by cloud computing environment 1202 (FIG. 13) is shown. It should be understood that Figure 12 ) are intended to be illustrative only and that in no way limit the scope of components, layers, and functionality. Figure 13

[0156] In at least one embodiment, hardware and software layer 1302 includes hardware and software components. In at least one embodiment, hardware components include mainframes, various RISC (Reduced Instruction Set Computer) architecture-based servers, desktop computers, laptop computers, various computer system architectures, supercomputers, storage devices, networks, networking components, and / or the like. In at least one embodiment, software components include network application server software, various application server software, various database software, and / or the like.

[0157] In at least one embodiment, virtualization layer 1304 provides an abstraction layer from which the following exemplary virtual entities can be provided: virtual servers; virtual storage; virtual networks, including virtual private networks; virtual applications and virtual clients; and / or the like.

[0158] ​In at least one embodiment, management layer 1306 provides the tools, metrics, applications, and interfaces for computing environment management. In at least one embodiment, management layer 1306 provides central nervous system-like functionality for the data center, such as

[0159] In at least one embodiment, workload layer 1308 provides functionality for utilization of resources by customers. In at least one embodiment, workloads and functionality provided at this layer can include: map and navigation, software development and management, enterprise resource planning, data analytics processing, transaction processing, and execution of applications that require high performance and / or high reliability.

[0160] Supercomputing

[0161] The following figures set forth, without limitation, exemplary supercomputer-based systems that can be used to implement at least one embodiment.

[0162] In at least one embodiment, a supercomputer can refer to a hardware system that exhibits substantial parallelism and includes at least one chip, where chips in the system are interconnected by a network and placed in a hierarchically organized enclosure. In at least one embodiment, a large hardware system that fills a machine room with several racks, each containing several board / rack modules, each containing several chips all interconnected by a scalable network, is at least one embodiment of a supercomputer. In at least one embodiment, a single rack of such a large hardware system is at least one other embodiment of a supercomputer. In at least one embodiment, a single chip that exhibits substantial parallelism and contains several hardware components can also be considered a supercomputer, as the amount of hardware that can be incorporated in a single chip can also increase as feature sizes can decrease.

[0163] Figure 14A supercomputer at the chip level is shown, according to at least one embodiment. In at least one embodiment, within an FPGA or ASIC chip, primary computation is performed within finite state machines (1404) called thread units. In at least one embodiment, a task and synchronization network (1402) connects finite state machines and is used to dispatch threads and perform operations in correct order. In at least one embodiment, a memory network (1406, 1410) is used to access a multi-level partitioned on-chip cache hierarchy (1408, 1412). In at least one embodiment, a memory controller (1416) and off-chip memory network (1414) is used to access off-chip memory. In at least one embodiment, an I / O controller (1418) is used for cross-chip communication when a design does not fit on a single logic chip.

[0164] Figure 15 A supercomputer at the rock module level is shown, according to at least one embodiment. In at least one embodiment, within a rack module, there are multiple FPGA or ASIC chips (1502) connected to one or more DRAM units (1504) that make up a main accelerator memory. In at least one embodiment, each FPGA / ASIC chip is connected to its neighboring FPGA / ASIC chip using a wide bus on board with differential high-speed signaling (1506). In at least one embodiment, each FPGA / ASIC chip is also connected to at least one high-speed serial communication cable.

[0165] Figure 16 A supercomputer at the rack level is shown, according to at least one embodiment. Figure 17 A supercomputer at the entire system level is shown, according to at least one embodiment. In at least one embodiment, see Figure 16 and Figure 17Between rack modules in a rack and across the racks of an entire system, a scalable, possibly incomplete hypercube network is implemented using high-speed serial optical or copper cables (1602, 1702). In at least one embodiment, one of the FPGA / ASIC chips of an accelerator is connected to a host system through a PCI-Express connection (1704). In at least one embodiment, the host system includes a host microprocessor (1708) on which software portions of an application run, and a memory consisting of one or more host memory DRAM units (1706) that are kept coherent with the memory on the accelerator. In at least one embodiment, the host system can be a separate module on one of the racks, or can be integrated with one of the modules of a supercomputer. In at least one embodiment, a cubic connection circulant topology provides communication links to create a hypercube network for a large supercomputer. In at least one embodiment, a small group of FPGA / ASIC chips on a rack module can act as a single hypercube node, such that the total number of external links per group is increased compared to a single chip. In at least one embodiment, one group contains chips A, B, C, and D on a rack module, which has an internal wide differential bus connecting A, B, C, and D in a ring organization. In at least one embodiment, there are 12 serial communication cables that connect the rack module to the outside world. In at least one embodiment, chip A on a rack module is connected to serial communication cables 0, 1, 2. In at least one embodiment, chip B is connected to cables 3, 4, 5. In at least one embodiment, chip C is connected to 6, 7, 8. In at least one embodiment, chip D is connected to 9, 10, 11. In at least one embodiment, the entire group {A, B, C, D} making up a rack module can form a hypercube node within a supercomputer system, with up to 212= 4096 rack modules (16384 FPGA / ASIC chips). In at least one embodiment, in order for chip A to send a message out on link 4 of the group {A, B, C, D}, the message must first be routed to chip B with an on-board differential wide bus connection. In at least one embodiment, a message arriving on link 4 destined for the group {A, B, C, D} of chips (i.e., to B) must also first be routed to the correct destination chip (A) inside the group {A, B, C, D}. In at least one embodiment, other sizes of parallel supercomputer systems can also be implemented.

[0166] Artificial intelligence

[0167] The following figures illustrate, but are not limited to, example artificial intelligence-based systems that can be used to implement at least one embodiment.

[0168] Figure 18AInference and / or training logic 1815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 1815 are provided below in conjunction with FIGS. 6 and 7. Figure 18A And / or 18B provides details regarding inference and / or training logic 1815.

[0169] In at least one embodiment, inference and / or training logic 1815 can include, without limitation, code and / or data storage 1801 for storing forward and / or output weight and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, training logic 1815 can include or be coupled to code and / or data storage 1801 to store graphics code or other software to control timing and / or sequence in which weight and / or other parameter information is to be loaded to configure logic, including integer and / or floating point units (collectively, arithmetic logic unit(s) (ALU(s))).

[0170] In at least one embodiment, any portion of code and / or data storage 1801 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data storage 1801 can be cache memory, dynamic random addressable memory (“DRAM”), static random addressable memory (“SRAM”), non-volatile memory (e.g., Flash), or other storage. In at least one embodiment, whether code and / or code and / or data storage 1801 is internal or external to a processor, or includes DRAM, SRAM, Flash, or some other storage type, can depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data being used in inferencing and / or training of a neural network, or some combination of these and / or other factors.

[0171] In at least one embodiment, inference and / or training logic 1815 can include, without limitation, code and / or data storage 1805 for storing backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network being trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 1805 stores weight parameters and / or input / output data of each layer of a neural network that is trained in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments. In at least one embodiment, training logic 1815 can include or be coupled to code and / or data storage 1805 to store graphics code or other software to control timing and / or sequence in which weights and / or other parameter information will be loaded to configure logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs)).

[0172] In at least one embodiment, code such as graphics code causes weight or other parameter information to be loaded into processor ALUs based on an architecture of a neural network to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 1805 can be included with other on-chip or off-chip data storage, including a processor’s L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 1805 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 1805 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., Flash memory), or other storage devices. In at least one embodiment, a choice of whether code and / or data storage 1805 is internal or external to a processor, or includes DRAM, SRAM, Flash, or some other storage type, can depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0173] In at least one embodiment, code and / or data storage 1801 and code and / or data storage 1805 can be separate storage structures. In at least one embodiment, code and / or data storage 1801 and code and / or data storage 1805 can be combined into a single storage structure. In at least one embodiment, code and / or data storage 1801 and code and / or data storage 1805 can be partially combined and partially separate. In at least one embodiment, any portion of code and / or data storage 1801 and code and / or data storage 1805 can be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory.

[0174] In at least one embodiment, inference and / or training logic 1815 can include, without limitation, one or more arithmetic logic units (“ALUs”), including integer and / or floating-point units, to perform logic and / or mathematical operations based, at least in part, on or indicated by training and / or inference code (e.g., graph code) whose results can produce activations (e.g., output values from layers or neurons within a neural network) stored in activation storage 1820 as a function of input / output and / or weight parameter data stored in code and / or data storage 1801 and / or code and / or data storage 1805. In at least one embodiment, in response to executing instructions or other code, activations stored in activation storage 1820 are generated in accordance with linear algebra and / or matrix-based mathematics performed by ALUs 1810, where weight values stored in code and / or data storage 1805 and / or data storage 1801 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which can be stored in code and / or data storage 1805 or code and / or data storage 1801 or another storage on-chip or off-chip.

[0175] In at least one embodiment, one or more ALUs 1810 are included within one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 1810 may be external to the processor or other hardware logic devices or circuits (e.g., coprocessors) that use them. In at least one embodiment, ALUs 1810 may be included within an execution unit of a processor or otherwise within an ALU stack accessible by the execution unit of the processor, which may be within the same processor or distributed among different types of processors (e.g., central processing unit, graphics processing unit, fixed-function unit, etc.). In at least one embodiment, code and / or data storage devices 1801, 1805, and activation storage device 1820 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits, or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of the activated storage device 1820 may be included together with other on-chip or off-chip data storage devices, including the processor's L1, L2, or L3 cache or system memory. Furthermore, inference and / or training code may be stored together with other code accessible to the processor or other hardware logic or circuitry, and may be acquired and / or processed using the processor's fetch, decode, schedule, execute, de-fetch, and / or other logic circuitry.

[0176] In at least one embodiment, the active storage device 1820 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage device. In at least one embodiment, the active storage device 1820 may be wholly or partially located within or outside one or more processors or other logic circuits. In at least one embodiment, the selection of whether the active storage device 1820 is inside or outside the processor, or including DRAM, SRAM, flash memory, or some other storage type in at least one embodiment, may depend on the available on-chip storage relative to off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of data used in the inference and / or training of the neural network, or some combination of these factors.

[0177] In at least one embodiment, Figure 18A The inference and / or training logic 1815 shown can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as those from Google. Processing unit, from Graphcore TM Inference processing unit (IPU), or from Intel Corporation (For example, a "Lake Crest" processor. In at least one embodiment, Figure 18A The inference and / or training logic 1815 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware such as field programmable gate array (“FPGA”)).

[0178] Figure 18B Inference and / or training logic 1815 according to at least one embodiment is illustrated. In at least one embodiment, the inference and / or training logic 1815 may include, but is not limited to, hardware logic in which computational resources are dedicated or otherwise exclusively used in conjunction with weight values ​​or other information corresponding to one or more neuron layers within a neural network. In at least one embodiment, Figure 18B The inference and / or training logic 1815 shown can be combined with an application-specific integrated circuit (ASIC) (such as those from Google). Processing unit, from Graphcore TM Inference processing unit (IPU), or from Intel Corporation (For example, a "lake tooth" processor) is used. In at least one embodiment, Figure 18B The inference and / or training logic 1815 shown can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field-programmable gate array (FPGA). In at least one embodiment, the inference and / or training logic 1815 includes, but is not limited to, code and / or data storage devices 1801 and 1805, which can be used to store code (e.g., graphical code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 18B In at least one embodiment described herein, each of code and / or data storage devices 1801 and 1805 is associated with dedicated computing resources (e.g., computing hardware 1802 and computing hardware 1806). In at least one embodiment, each of computing hardware 1802 and computing hardware 1806 includes one or more ALUs that perform mathematical functions (such as linear algebraic functions) on information stored in code and / or data storage devices 1801 and 1805, respectively, with the results stored in active memory 1820.

[0179] In at least one embodiment, each code and / or data memory 1801 and 1805 and corresponding compute hardware 1802 and 1806, respectively, correspond to different layers of a neural network, such that resulting activations from a code one store / compute pair 1801 / 1802 and / or data store 1801 and compute hardware 1802 are provided as input to a next code store / compute pair 1805 / 1806 and / or data store 1805 and compute hardware 1806, in order to reflect a conceptual organization of a neural network. In at least one embodiment, each of store / compute pairs 1801 / 1802 and 1805 / 1806 can correspond to more than one neural network layer. In at least one embodiment, additional store / compute pairs (not shown) subsequent to or in parallel with store / compute pairs 1801 / 1802 and 1805 / 1806 can be included in inference and / or training logic 1815.

[0180] Figure 19 Training and deployment of a deep neural network is shown, in accordance with at least one embodiment. In at least one embodiment, an untrained neural network 1906 is trained using a training dataset 1902. In at least one embodiment, training framework 1904 is a PyTorch framework, while in other embodiments, training framework 1904 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, training framework 1904 trains untrained neural network 1906 and enables it to train using processing resources described herein to generate a trained neural network 1908. In at least one embodiment, weights can be chosen randomly or by pre-training using a deep belief network. In at least one embodiment, training can be performed in a supervised, partially supervised, or unsupervised manner.

[0181] In at least one embodiment, an untrained neural network 1906 is trained using supervised learning, where a training dataset 1902 includes inputs paired with desired outputs for inputs, or where a training dataset 1902 includes inputs with known outputs and outputs of the neural network 1906 are manually graded. In at least one embodiment, an untrained neural network 1906 is trained in a supervised manner and inputs from a training dataset 1902 are processed and resulting outputs are compared to a set of expected or desired outputs. In at least one embodiment, errors then propagate back through the untrained neural network 1906. In at least one embodiment, a training framework 1904 adjusts weights that control the untrained neural network 1906. In at least one embodiment, a training framework 1904 includes tools to monitor how well an untrained neural network 1906 is converging towards a model, such as a trained neural network 1908, that is suitable to generate correct answers, such as results 1914, based on input data, such as a new dataset 1912. In at least one embodiment, a training framework 1904 repeatedly trains an untrained neural network 1906 while using a loss function and adjustment algorithm, such as stochastic gradient descent, to adjust weights to refine outputs of the untrained neural network 1906. In at least one embodiment, a training framework 1904 trains an untrained neural network 1906 until the untrained neural network 1906 achieves a desired accuracy. In at least one embodiment, a trained neural network 1908 can then be deployed to implement any number of machine learning operations.

[0182] In at least one embodiment, an untrained neural network 1906 is trained using unsupervised learning, where an untrained neural network 1906 attempts to train itself using unlabeled data. In at least one embodiment, an unsupervised learning training dataset 1902 will include input data without any associated output data or “ground truth” data. In at least one embodiment, an untrained neural network 1906 can learn groupings within a training dataset 1902 and can determine how individual inputs relate to the untrained dataset 1902. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in a trained neural network 1908 that is capable of performing operations useful in reducing a dimensionality of a new dataset 1912. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for identification of data points in a new dataset 1912 that deviate from a normal pattern of the new dataset 1912.

[0183] In at least one embodiment, semi-supervised learning can be used, which is a technique where a mix of labeled and unlabeled data is included in a dataset 1902 in training. In at least one embodiment, training framework 1904 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables a trained neural network 1908 to adapt to new datasets 1912 without forgetting knowledge dripped within trained neural network 1408 during initial training.

[0184] 5G network

[0185] The following figures illustrate, but are not limited to, an exemplary 5G network-based system that can be used to implement at least one embodiment.

[0186] Figure 20 A framework of a system 2000 of a network is illustrated in accordance with at least one embodiment. In at least one embodiment, system 2000 is illustrated as including a user equipment (UE) 2002 and UE 2004. In at least one embodiment, UEs 2002 and 2004 are illustrated as smartphones (e.g., handheld touchscreen mobile computing devices connectable to one or more cellular networks), but can also include any mobile or non-mobile computing device, such as a Personal Digital Assistant (PDA), a pager, a laptop computer, a desktop computer, a wireless hand-held device, or any computing device including a wireless communication interface.

[0187] In at least one embodiment, any of UEs 2002 and 2004 can comprise an Internet of Things (IoT) UE, which can comprise an access layer of a network designed for low-power IoT applications using short-lived connections. In at least one embodiment, an IoT UE can utilize machine-to-machine (M2M) or machine-type communications (MTC) technology over a public land mobile network (PLMN), Proximity-Based Service (ProSe) or device-to-device (D2D) communication, sensor networks, or IoT networks, to exchange data with an MTC server or device. In at least one embodiment, M2M or MTC data exchange can be a machine-initiated data exchange. In at least one embodiment, an IoT network describes interconnecting IoT UEs, which can include uniquely identifiable embedded computing devices (within the Internet infrastructure), with short-lived connections. In at least one embodiment, an IoT UE can execute background applications (e.g., keep-alive messages, status updates, etc.) to facilitate connections for an IoT network.

[0188] In at least one embodiment, UEs 2002 and 2004 can be configured to connect with a radio access network (RAN) 2016 (e.g., communicatively coupled with the RAN 2016). In at least one embodiment, the RAN 2016 can be an evolved universal mobile telecommunication system (UMTS) terrestrial radio access network (E-UTRAN), a NextGen RAN (NG RAN), or some other type of RAN. In at least one embodiment, UEs 2002 and 2004 utilize connections 2012 and 2014, respectively, each of which includes a physical

[0189] In at least one embodiment, UEs 2002 and 2004 can further directly exchange communication data via a ProSe interface 2006. In at least one embodiment, the ProSe interface 2006 can alternatively be referred to as a sidelink interface comprising one or more logical channels, including but not limited to a physical sidelink control channel (PSCCH), a physical sidelink shared channel (PSSCH), a physical sidelink discovery channel (PSDCH), and a physical sidelink broadcast channel (PSBCH).

[0190] In at least one embodiment, UE 2004 is illustrated as being configured to access an access point (AP) 2010 via connection 2008. In at least one embodiment, connection 2008 can comprise a local wireless connection, such as a connection consistent with any IEEE 802.11 protocol, wherein the AP 2010 would comprise a wireless fidelity router. In at least one embodiment, AP 2010 is illustrated as connected to the Internet without connecting to the core network, although this is not required in every embodiment. In at least one embodiment, AP 2010 can represent a Wi-Fi access point. In at least one embodiment, AP 2010 can provide communication connection and / or service to one or more UEs 2002, 2004, and / or 2008.

[0191] In at least one embodiment, RAN 2016 can include one or more access nodes 2012 and 2014 that enable the connection 2012 and 2014. In at least one embodiment, these access nodes (ANs) can be referred to as base stations, Node-Bs, evolved Node-Bs (eNBs), next Generation Node-Bs (gNBs), RAN nodes, and / or the like, and can comprise ground stations (e.g., terrestrial access points) or satellite stations providing coverage over a geographic area, such as a cell. In at least one embodiment, RAN 2016 can include one or more RAN nodes for providing macrocells (e.g., macro RAN node 2018) and one or more RAN nodes for providing femtocells or picocells (e.g., low power (LP) RAN node 2020).

[0192] In at least one embodiment, any of the RAN nodes 2018 and 2020 can terminate the air interface protocol and can be the first point of contact for the UEs 2002 and 2004. In at least one embodiment, any of the RAN nodes 2018 and 2020 can fulfill various logical functions for the RAN 2016 including, but not limited to, RNC functionssuch as radio bearer management, uplink and downlink dynamic radio resource management and data packet scheduling, and mobility management.

[0193] In at least one embodiment, UEs 2002 and 2004 can be configured to communicate using orthogonal frequency division multiplexing (OFDM) communication signals with each other or with any of the RAN nodes 2018 and 2020 over a multicarrier communication channel in accordance with a variety of communication techniques, such as, but not limited to, an orthogonal frequency division multiple access (OFDMA) communication technique (e.g., for downlink communications) or a single carrier frequency division multiple access (SC-FDMA) communication technique (e.g., for uplink and ProSe or sidelink communications), and / or variants thereof. In at least one embodiment, OFDM signals can comprise orthogonal waveshapes used for transmission or reception of data over a communication signal.

[0194] In at least one embodiment, a downlink resource grid can be used for downlink transmissions from any of the RAN node 2018 and 2020 to the UEs 2002 and 2004, while uplink transmissions can utilize a similar approach. In at least one embodiment, the grid can be a time-frequency grid, called a resource grid or time-frequency resource grid, which is the physical resource in the downlink in each slot. In at least one embodiment, such a time-frequency plane representation is a common practice for OFDM systems, which makes it intuitive for radio resource allocation. In at least one embodiment, each column and each row of the resource grid corresponds to one OFDM symbol and one OFDM subcarrier, respectively. In at least one embodiment, the duration of the resource grid in the time domain corresponds to one slot, which depends on the downlink slot duration. In at least one embodiment, the minimum time-frequency unit in the resource grid is denoted as a resource element. In at least one embodiment, the resource grid comprises a number of resource blocks, which describe the mapping of certain physical channels to resource elements. In at least one embodiment, each resource block comprises a collection of resource elements in the time domain and frequency domain. In at least one embodiment, in the frequency domain, this can represent the smallest quantity of resources that can be allocated, in at least one embodiment, there are several different physical downlink channels that are conveyed using such resource blocks.

[0195] In at least one embodiment, a physical downlink shared channel (PDSCH) can carry user data and higher layer signaling to the UEs 2002 and 2004. In at least one embodiment, a physical downlink control channel (PDCCH) can carry information about the transport format and resource allocations for the PDSCH channels, etc. In at least one embodiment, it can also inform the UEs 2002 and 2004 about the transport format, resource allocation, and HARQ information for uplink shared channel. In at least one embodiment, generally, downlink scheduling (allocating control and shared channel resource blocks to the UEs 2002 within a cell) can be performed at any of the RAN nodes 2018 and 2020 based on channel quality information feedback from any of the UEs 2002 and 2004. In at least one embodiment, downlink resource allocation information can be sent on the PDCCH used for each of the UEs 2002 and 2004.

[0196] In at least one embodiment, a PDCCH can use control channel elements (CCEs) to convey control information. In at least one embodiment, PDCCH complex-valued symbols can first be organized into quadruplets, then permuted using a sub-block interleaver for rate matching, in at least one embodiment, one or more of these CCEs can be used to transmit each PDCCH, where each CCE can correspond to nine sets of four resource element groups (REGs), referred to as resource element groups (REGs). In at least one embodiment, four Quadrature Phase Shift Keying (QPSK) symbols can be mapped to each REG. In at least one embodiment, depending on the Downlink Control Information (DCI) size and the channel condition, one or more CCEs can be used to send a PDCCH. In at least one embodiment, there can be four or more different PDCCH formats (e.g., aggregation level, L=l, 2, 4, or 8) defined in LTE with different number of CCEs.

[0197] In at least one embodiment, an enhanced physical downlink control channel (EPDCCH) using PDSCH resources can be used for control information transmission. In at least one embodiment, one or more enhanced control channel elements (ECCEs) can be used to transmit EPDCCH. In at least one embodiment, each ECCE can correspond to nine sets of four physical resource elements called enhanced resource element groups (EREGs). In at least one embodiment, an ECCE can have other numbers of EREGs in some situations.

[0198] In at least one embodiment, the RAN 2016 is shown to be communicatively coupled to a core network (CN) 2038 via an S1 interface 2022. In at least one embodiment, the CN 2038 can be an evolved packet core (EPC) network, a NextGen packet core (NPC) network, or some other type of CN. In at least one embodiment, the S1 interface 2022 is split into two parts: the S1 -U interface 2026, which carries traffic data between the RAN nodes 2018 and 2020 and a serving gateway (S-GW) 2030, and the S1 -Mobility Management Entity (MME) interface 2024, which is a signaling interface between the RAN nodes 2018 and 2020 and a MME 2028.

[0199] In at least one embodiment, the CN 2038 includes a MME 2028, a S-GW 2030, a packet data network (PDN) gateway (P-GW) 2034, and a home subscriber server (HSS) 2032. In at least one embodiment, the MME 2028 can be similar in function to a control plane of legacy Serving General Packet Radio Service (GPRS) Support Nodes (SGSN). In at least one embodiment, the MME 2028 can manage mobility aspects in access such as gateway selection and tracking area list management. In at least one embodiment, the HSS 2032 can contain a database for network users, including subscription-related information to support the network entities’ handling of

[0200] In at least one embodiment, the S-GW 2030 can terminate the S1 interface 2022 towards RAN 2016, and route data packets between the RAN 2016 and the CN 2038. In at least one embodiment, the S-GW 2030 can be a local mobility anchor for inter-RAN node handovers and also for intra-RAN mobility including seamless handovers. In at least one embodiment, other responsibilities can include lawful intercept, charging, and some policy enforcement and steering functions.

[0201] In at least one embodiment, the P-GW 2034 can terminate an SGi interface toward a PDN. In at least one embodiment, the P-GW 2034 can route data packets between a LTE / PDSN packet core network 2038 and external networks such as the Internet, employing Internet Protocol (IP) addressing. In at least one embodiment, application servers 2040 (or application functions (AFs)) can be included in external networks, and can also be referred to as Internet of Things (IoT) platforms. In at least one embodiment, an application server 2040 can be an element offering applications that use IP bearer resources with the core network (e.g., UMTS Packet Services (PS) domain, LTE PS data services, etc.). In at least one embodiment, the P-GW 2034 is shown to be communicatively coupled to an application server 2040 via an IP communications interface 2042. In at least one embodiment, the application server 2040 can also be configured to support one or more communication services (e.g., Voice-over-Internet Protocol (VoIP) sessions, PTT sessions, group communication sessions, social networking services, etc.) for UEs 2002 and 2004 via the CN 2038.

[0202] In at least one embodiment, the P-GW 2034 can also be a node for policy enforcement and charging data collection. In at least one embodiment, a Policy and Charging Enforcement Function (PCRF) 2036 is a policy and charging control element of the CN 2038. In at least one embodiment, in a non-roaming scenario, there can be a single PCRF in a Home Public Land Mobile Network (HPLMN) associated with a UE’s Internet Protocol Connectivity Access Network (IP-CAN) session. In at least one embodiment, in a roaming scenario with local breakout of traffic, there can be two PCRFs associated with a UE’s IP-CAN session: a Home PCRF (H-PCRF) within a HPLMN and a Visited PCRF (V-PCRF) within a Visited Public Land Mobile Network (VPLMN). In at least one embodiment, the PCRF 2036 can be communicatively coupled to an application server 2040 via the P-GW 2034. In at least one embodiment, the application server 2040 can signal the PCRF 2036 to direct a new service flow and select appropriate Quality of Service (QoS) and charging parameters. In at least one embodiment, the PCRF 2036 can provision this rule into a Policy and Charging Enforcement Function (PCEF) (not shown) with a suitable traffic flow template (TFT) and a Quality of Class of Service (QCI) that commences the QoS and charging as specified by the application server 2040.

[0203] Figure 21 An architecture of a system 2100 of a network is shown in accordance with some embodiments. In at least one embodiment, the system 2100 is shown to include a UE 2102, a 5G access node or RAN node (shown as (R)AN node 2108), a User Plane Function (UPF 2104), a Data Network (DN 2106), which in at least one embodiment can be an operator’s services, Internet access, or 3rd party services, and a 5G Core Network (5GC) (shown as CN 2110).

[0204] In at least one embodiment, the CN 2110 includes an Authentication Server Function (AUSF 2114); a Core Access and Mobility Management Function (AMF 2112); a Session Management Function (SMF 2118); a Network Exposure Function (NEF 2116); a Policy Control Function (PCF 2122); a Network Function (NF) Repository Function (NRF 2120); a Unified Data Management (UDM 2124); and an Application Function (AF 2126). In at least one embodiment, the CN 2110 can also include other elements not shown, such as a Structured Data Storage Network Function (SDSF), an Unstructured Data Storage Network Function (UDSF), and variations thereof.

[0205] In at least one embodiment, UPF2104 can act as an anchor point for mobility within and between RATs, an external PDU session point interconnecting to DN2106, and a branch point supporting multihomed PDU sessions. In at least one embodiment, UPF2104 can also perform packet routing and forwarding, packet inspection, user plane portion of policy rule enforcement, lawful packet interception (UP collection), traffic usage reporting, QoS processing for the user plane (e.g., packet filtering, gating, UL / DL rate enforcement), uplink traffic verification (e.g., SDF-to-QoS flow mapping), transport-level packet marking in uplink and downlink, and downlink packet buffering and downlink data notification triggering. In at least one embodiment, UPF2104 may include an uplink classifier to support routing traffic flows to the data network. In at least one embodiment, DN2106 may represent different network operator services, Internet access, or third-party services.

[0206] In at least one embodiment, AUSF2114 can store data for authentication of UE2102 and handle authentication-related functions. In at least one embodiment, AUSF2114 can facilitate common authentication frames for different access types.

[0207] In at least one embodiment, AMF2112 can be responsible for registration management (e.g., for registering UE2102, etc.), connection management, reachability management, mobility management, and lawful interception of AMF-related events, as well as access authentication and authorization. In at least one embodiment, AMF2112 can provide SM message transmission for SMF2118 and act as a transparent proxy for routing SM messages. In at least one embodiment, AMF2112 can also provide UE2102 with SMS Functionality (SMSF) (…). Figure 21 Transmission of Short Message Service (SMS) messages between (not shown). In at least one embodiment, AMF2112 may act as a Security Anchoring Function (SEA), which may include interaction with AUSF2114 and UE2102 and receiving an intermediate key established as a result of the UE2102 authentication process. In at least one embodiment, in the case of using USIM-based authentication, AMF2112 may retrieve security material from AUSF2114. In at least one embodiment, AMF2112 may also include a Security Context Management (SCM) function, which receives from the SEA a key it uses to derive the access network-specific key. Furthermore, in at least one embodiment, AMF2112 may be the termination point (N2 reference point) of the RANCP interface, the termination point of NAS (NI) signaling, and perform NAS encryption and integrity protection.

[0208] In at least one embodiment, the AMF 2112 can also support NAS signaling with the UE 2102 over an N3 interworking function (IWF) interface. In at least one embodiment, N3IWF can be used to provide access to untrusted entities. In at least one embodiment, N3IWF can be a termination point for N2 and N3 interfaces of the control plane and user plane, and thus, can handle N2 signaling from SMF and AMF for PDU session and QoS respectively, encapsulate / decapsulate IPSec and N3 tunnel packets, mark N3 user-plane packets with appropriate QoS markers received over N2, and enforce QoS corresponding to N3 packet marking considering QoS requirements associated with such marking received over N2. In at least one embodiment, N3IWF can also relay uplink and downlink control-plane NAS (Nl) signaling between the UE 2102 and AMF 2112, and relay uplink and downlink user-plane packets between the UE 2102 and UPF 2104. In at least one embodiment, N3IWF also provides mechanisms for IPsec tunnel establishment with the UE 2102.

[0209] In at least one embodiment, the SMF 2118 can be responsible for session management (e.g., session establishment, modify, and release, including UPF and AN node

[0210] In at least one embodiment, the NEF 2116 can provide means for securely exposing services and capabilities offered by 3 GPP network functions for third party, internal exposure / reexposure, application functions (e.g., AF 2126), edge computing or fog computing systems, etc. In at least one embodiment, the NEF 2116 can authenticate, authorize, and / or throttle AFs. In at least one embodiment, the NEF 2116 can also translate information exchanged with AFs 2126 and information exchanged with internal network functions. In at least one embodiment, the NEF 2116 can translate between AF service identifiers and internal 5GC information. In at least one embodiment, the NEF 2116 can also receive information from other network functions (NFs) based on exposure capabilities of other network functions. In at least one embodiment, this information can be stored at the NEF 2116 as structured data, or at a data storage NF using standardized interfaces. In at least one embodiment, the stored information can then be re-exposed by the NEF 2116 to other NFs and AFs, and / or used for other purposes such as analytics.

[0211] In at least one embodiment, the NRF 2120 can support service discovery functions, receive NF discovery requests from NF instances, and provide NF instances with information of discovered NF instances. In at least one embodiment, the NRF 2120 also maintains information of available NF instances and their supported services.

[0212] In at least one embodiment, the PCF 2122 can provide policy rules to control plane functions to enforce them, and can also support a unified policy framework to govern network behavior. In at least one embodiment, the PCF 2122 can also implement a front end (FE) to access subscription information related to policy decisions in the UDR of UDM 2124.

[0213] In at least one embodiment, the UDM 2124 can handle subscription-related information to support network entities handling communication sessions, and can store subscription data of UEs 2102. In at least one embodiment, the UDM 2124 can include two parts, an application FE and a user data repository (UDR). In at least one embodiment, the UDM can include a UDM FE that is responsible for handling credentials, location management, subscription management, etc. In at least one embodiment, several different front ends can service the same user in different transactions. In at least one embodiment, the UDM-FE accesses subscription information stored in the UDR and performs authentication credential processing; user identification enhancement; access authorization; registration / mobility management; and subscription management. In at least one embodiment, the UDR can interact with the PCF 2122. In at least one embodiment, the UDM 2124 can also support SMS management, where an SMS-FE implements similar application logic as previously discussed.

[0214] In at least one embodiment, AF 2126 can provide application influence on traffic routing, access to network capability exposure (NCE), and interact with policy framework for policy control. In at least one embodiment, NCE can be a mechanism that allows 5GC and AFs 2126 to provide information to each other via NEF 2116, which can be used for edge computing implementation. In at least one embodiment, network operators and third party services can be hosted close to the point of attachment of a UE 2102 for efficient service delivery with reduced end-to-end latency and load on transport network. In at least one embodiment, for edge computing implementation, 5GC can choose a UPF 2104 close to the UE 2102 and perform traffic steering via a N6 interface from the UPF 2104 to DN 2106. In at least one embodiment, this can be based on UE subscription data, UE location, and information provided by AF 2126. In at least one embodiment, AF 2126 can influence UPF (re)selection and traffic routing. In at least one embodiment, based on operator deployment, when AF 2126 is considered a trusted entity, network operator can allow AF 2126 to interact directly with relevant NFs.

[0215] In at least one embodiment, CN 2110 can include an SMSF, which can be responsible for SMS subscription checking and verification, and relaying SM messages to / from UEs 2102 to / from other entities, such as SMS-GMSC / IWMSC / SMS-router. In at least one embodiment, SMS can also interact with AMF 2112 and UDM 2124 for a notification procedure that the UE 2102 is available for SMS transfer (e.g., setting a UE not reachable flag, and notifying UDM 2124 when UE 2102 is available for SMS).

[0216] In at least one embodiment, system 2100 can include the following service-based interfaces: Namf: service-based interface exposed by AMF; Nsmf: service-based interface exposed by SMF; Nnef: service-based interface exposed by NEF; Npcf: service-based interface exposed by PCF; Nudm: service-based interface exposed by UDM; Naf: service-based interface exposed by AF; Nnrf: service-based interface exposed by NRF; Nausf: service-based interface exposed by AUSF.

[0217] In at least one embodiment, system 2100 can include the following reference points: N1: Reference point between UE and AMF; N2: Reference point between (R)AN and AMF; N3: Reference point between (R)AN and UPF; N4: Reference point between SMF and UPF; N6: Reference point between UPF and Data Network. In at least one embodiment, there can be more reference points and / or service-based interfaces between NF services in NF, which have been omitted for clarity. In at least one embodiment, a NS reference point can be between PCF and AF; a N7 reference point can be between PCF and SMF; a N11 reference point between AMF and SMF; and the like. In at least one embodiment, CN 2110 can include an Nx interface, which is an inter-CN interface between MME and AMF 2112 in order to enable interworking between CN 2110 and CN 7221.

[0218] In at least one embodiment, system 2100 can include multiple RAN nodes, such as (R)AN nodes 2108, with an Xn interface defined between two or more (R)AN nodes 2108 (e.g., gNBs) connected to 5GC 410, between a (R)AN node 2108 (e.g., gNB) and an eNB (e.g., macro RAN node) connected to CN 2110, and / or between two eNBs connected to CN 2110.

[0219] In at least one embodiment, Xn interface can include an Xn user plane (Xn-U) interface and an Xn control plane (Xn-C) interface. In at least one embodiment, Xn-U can provide non- guaranteed delivery of user plane PDUs, and supports / provides data forwarding and flow control functionality. In at least one embodiment, Xn-C can provide management and error handling functionality, functionality to manage the Xn-C interface; mobility support for UEs 2102 in a connected mode (e.g., CM-CONNECTED) including functionality to manage the connected mode mobility of UEs between one or more (R)AN nodes 2108. In at least one embodiment, mobility support can include context transfer from an old (source) serving (R)AN node 2108 to new (target) serving (R)AN node 2108; and control of user plane tunnels between old (source) serving (R)AN node 2108 to new (target) serving (R)AN node 2108.

[0220] In at least one embodiment, the Xn-U protocol stack can include a transport network layer built on top of an Internet Protocol (IP) transport layer and a GTP-U layer on top of a UDP and / or IP layer to carry user plane PDUs. In at least one embodiment, the Xn-C protocol stack can include an application layer signaling protocol (referred to as Xn Application Protocol (Xn-AP)) and a transport network layer built on top of an SCTP layer. In at least one embodiment, the SCTP layer can be on top of an IP layer. In at least one embodiment, the SCTP layer provides a guaranteed delivery of application layer messages. In at least one embodiment, in the transport IP layer, point-to-point transmission is used to deliver signaling PDUs. In at least one embodiment, the Xn-U protocol stack and / or the Xn-C protocol stack can be the same as or similar to user plane and / or control plane protocol stacks shown and described herein.

[0221] Figure 22 is an illustration of a control plane protocol stack in accordance with some embodiments. In at least one embodiment, control plane 2200 is illustrated as a communication protocol stack between UE 2002 (or alternatively, UE 2004), RAN 2016, and MME 2028.

[0222] In at least one embodiment, PHY layer 2202 can transmit or receive information used by MAC layer 2204 over one or more air interfaces. In at least one embodiment, PHY layer 2202 can also perform link adaptation or adaptive modulation and coding (AMC), power control, cell search (e.g., for initial synchronization and handover purposes), and other measurements used by higher layers, such as RRC layer 2210. In at least one embodiment, PHY layer 2202 can further perform error detection on the transport channels, forward error correction (FEC) coding / decoding of the transport channels, modulation / demodulation of physical channels, interleaving, rate matching, mapping to physical channels, and Multiple Input Multiple Output (MIMO) antenna processing.

[0223] In at least one embodiment, MAC layer 2204 can perform mapping between logical channels and transport channels, multiplexing of MAC service data units (SDUs) from one or more logical channels into transport blocks (TB) to be delivered to PHY via transport channels, demultiplexing of MAC SDUs to one or more logical channels from TBs delivered from PHY via transport channels, multiplexing of MAC SDUs onto TBs, scheduling information reporting, error correction through hybrid automatic repeat request (HARQ), and logical channel prioritization.

[0224] In at least one embodiment, RLC layer 2206 can operate in multiple modes of operation, including: transparent mode (TM), unacknowledged mode (UM), and acknowledged mode (AM). In at least one embodiment, RLC layer 2206 can perform transfer of upper layer protocol data units (PDUs), retransmission of RLC data PDUs for AM data transfers by automatic repeat request (ARQ), and concatenation, segmentation, and reassembly of RLC SDUs for UM and AM data transfers. In at least one embodiment, RLC layer 2206 can also perform re-segmentation of RLC data PDUs for AM data transfers, reordering of RLC data PDUs for UM and AM data transfers, detect duplicate data for UM and AM data transfers, discard RLC SDUs for UM and AM data transfers, detect protocol errors for AM data transfers, and perform RLC re-establishment.

[0225] In at least one embodiment, PDCP layer 2208 can perform header compression and decompression of IP data, maintain PDCP sequence numbers (SNs), perform in-sequence delivery of upper layer PDUs at re-establishment of lower layers, eliminate duplication of lower layer SDUs at re-establishment of lower layers for RLC AM mapped radio bearers, cipher and decipher control plane data, integrity protect and integrity verify control plane data, perform data discard based on control timers, and perform security operations (e.g., ciphering, deciphering, integrity protection, integrity verification, etc.).

[0226] In at least one embodiment, main services and functions of RRC layer 2210 can include broadcast of system information (e.g., included in master information block (MIB) or system information blocks (SIBs) related to non-access stratum (NAS)), broadcast of system information related to access stratum (AS), paging of UEs involving E-UTRAN, establishment, maintenance and release of an RRC connection between the UE and E-UTRAN (e.g., RRC connection paging, RRC connection establishment, RRC connection modification, and RRC connection release), establishment, configuration, maintenance and release of point-to-point Radio Bearers, security functions including key management, inter-radio access technology (RAT) mobility, and measurement configuration for UE measurement reporting. In at least one embodiment, MIB and SIBs can include one or more information elements (IEs), each of which can include individual data fields or data structures.

[0227] In at least one embodiment, UE 2002 and RAN 2016 can utilize a Uu interface (e.g., LTE-Uu interface) to exchange control plane data via a protocol stack including PHY layer 2202, MAC layer 2204, RLC layer 2206, PDCP layer 2208, and RRC layer 2210.

[0228] In at least one embodiment, a non-access stratum (NAS) protocol (NAS protocol 2212) forms a highest stratum of the control plane between UE 2002 and MME 2028. In at least one embodiment, NAS protocol 2212 supports mobility of UE 2002 and session management procedures to establish and maintain IP connectivity between UE 2002 and P-GW 2034.

[0229] In at least one embodiment, an Si application protocol (S1-AP) layer (S1-AP layer 2222) can support functions of the Si interface and include elementary procedures (EPs). In at least one embodiment, an EP is a unit of interaction between RAN 2016 and CN 2028. In at least one embodiment, S1-AP layer services can include two groups: UE-associated services and non-UE-associated services. In at least one embodiment, these servers perform functions including, but not limited to: E-UTRAN Radio Access Bearer (E-RAB) management, UE capability indication, mobility, NAS signaling transfer, RAN Information Management (RIM), and configuration transfer.

[0230] In at least one embodiment, a stream control transmission protocol (SCTP) layer (alternatively referred to as a stream control transmission protocol / internet protocol (SCTP / IP) layer) (SCTP layer 2220) can ensure reliable delivery of signaling messages between RAN 2016 and MME 2028 based, in part, on IP protocols supported by IP layer 2218. In at least one embodiment, L2 layer 2216 and L1 layer 2214 can refer to communication links (e.g., wired or wireless) used by RAN nodes and MMEs to exchange information.

[0231] In at least one embodiment, RAN 2016 and one or more MMEs 2028 can utilize an S1-MME interface to exchange control plane data via a protocol stack including L1 layer 2214, L2 layer 2216, IP layer 2218, SCTP layer 2220, and S1-AP layer 2222.

[0232] Figure 23 is a diagram of a user plane protocol stack, in accordance with at least one embodiment. In at least one embodiment, user plane 2300 is shown as a communication protocol stack between UE 2002, RAN 2016, S-GW 2030, and P-GW 2034. In at least one embodiment, user plane 2300 can utilize the same protocol layers as control plane 2200. In at least one embodiment, UE 2002 and RAN 2016 can utilize a Uu interface (e.g., a LTE-Uu interface) to exchange user plane data via a protocol stack including PHY layer 2202, MAC layer 2204, RLC layer 2206, PDCP layer 2208.

[0233] In at least one embodiment, a general packet radio service (GPRS) tunnelling protocol (GTP-U) layer (GTP-U layer 2304) for user plane can be used to carry user data within the GPRS core network and between the radio access network and the core network. In at least one embodiment, user data transported can be packets in any of IPv4, IPv6, or PPP formats. In at least one embodiment, a UDP / IP layer (UDP / IP layer 2302) can provide checksums for data integrity, port numbers for addressing different functions at the source and destination, and encryption and authentication on selected data flows. In at least one embodiment, RAN 2016 and S-GW 2030 can utilize an S1-U interface to exchange user plane data via a protocol stack comprising L1 layer 2214, L2 layer 2216, UDP / IP layer 2302, and GTP-U layer 2304. In at least one embodiment, S-GW 2030 and P-GW 2034 can utilize a S5 / S8a interface to exchange user plane data via a protocol stack comprising L1 layer 2214, L2 layer 2216, UDP / IP layer 2302, and GTP-U layer 2304. In at least one embodiment, as discussed above with respect to FIG. 22, NAS protocols support mobility and session management procedures for UE 2002 to establish and maintain IP connectivity between UE 2002 and P-GW 2034. Figure 22

[0234] Figure 24 Components of a core network are illustrated according to at least one embodiment 2400. In at least one embodiment, components of CN 2038 can be implemented in one physical node or in separate physical nodes including components to read and execute instructions stored in a machine- or computer-readable storage medium (e.g., non-transitory machine-readable storage medium). In at least one embodiment, network function virtualization (NFV) is used to virtualize any or all of the above-described network node functions via executable instructions stored in one or more computer-readable storage media (described in further detail below). In at least one embodiment, a logical instance of CN 2038 can be referred to as a network slice 2402 (e.g., network slice 2402 is illustrated as including HSS 2032, MME 2028, and S-GW 2030). In at least one embodiment, a logical instance of a portion of CN 2038 can be referred to as a network sub-slice 2404 (e.g., network sub-slice 2404 is illustrated as including P-GW 2034 and PCRF 2036).

[0235] ​In at least one embodiment, NFV architecture and infrastructure can be used to virtualize one or more network functions onto physical resources comprising a combination of industry-standard server hardware, storage hardware, or switches, which can alternatively be performed by specialized hardware. In at least one embodiment, NFV can be used to perform a virtual or reconfigurable implementation of one or more EPC components / functions.

[0236] Figure 25 is a block diagram illustrating components of a system 2500 to support network function virtualization (NFV), according to at least one embodiment. In at least one embodiment, system 2500 is shown to include a virtualization infrastructure manager (shown as VIM 2502), a network function virtualization infrastructure (shown as NFVI 2504), a VNF manager (shown as VNFM 2506), a virtualized network function (shown as VNF 2508), an element manager (shown as EM 2510), an NFV orchestrator (shown as NFVO 2512), and a network manager (shown as NM 2514).

[0237] In at least one embodiment, VIM 2502 manages resources of NFVI 2504. In at least one embodiment, NFVI 2504 can include physical or virtual resources and applications, including hypervisors, utilized to execute system 2500. In at least one embodiment, VIM 2502 can utilize NFVI 2504 to manage life cycle of virtual resources (e.g., creation, maintenance, and tearing down of virtual machines (VMs) associated with one or more physical resources), track VM instances, track performance, fault and security of VM instances and associated physical resources, and expose VM instances and associated physical resources to other management systems.

[0238] In at least one embodiment, VNFM 2506 can manage VNF 2508. In at least one embodiment, VNF 2508 can be utilized to execute EPC components / functions. In at least one embodiment, VNFM 2506 can manage life cycle of VNF 2508 and track performance, fault and security of virtual aspects of VNF 2508. In at least one embodiment, EM 2510 can track performance, fault and security of functional aspects of VNF 2508. In at least one embodiment, tracking data from VNFM 2506 and EM 2510 can include, in at least one embodiment, performance measurement (PM) data used by VIM 2502 or NFVI 2504. In at least one embodiment, both VNFM 2506 and EM 2510 can scale up / down the number of VNFs of system 2500.

[0239] In at least one embodiment, NFVO 2512 can coordinate, authorize, release, and occupy resources of NFVI 2504 in order to provide requested services (e.g., to execute EPC functions, components, or slices). In at least one embodiment, NM 2514 can provide a package of end-user functions that are responsible for managing a network that can include network elements that are VNFs, non-virtualized network functions, or both (management of VNFs can occur via EM 2510).

[0240] Computer-based system

[0241] The following figures illustrate, without limitation, exemplary computer-based systems that can be used to implement at least one embodiment.

[0242] Figure 26 A processing system 2600, in accordance with at least one embodiment, is shown. In at least one embodiment, processing system 2600 includes one or more processor(s) 2602 and one or more graphics processor(s) 2608, and can be a single processor desktop system, a multiprocessor workstation system, or a server system having thousands of processors 2602 or processor cores 2607. In at least one embodiment, processing system 2600 is a processing platform incorporated within a system- on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0243] In at least one embodiment, processing system 2600 can include or be incorporated within a server-based gaming platform, including a game console, media console, mobile gaming console, handheld game console, or online game console. In at least one embodiment, processing system 2600 is a mobile phone, smart phone, tablet computing device, or mobile internet device. In at least one embodiment, processing system 2600 can also include or be coupled with a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In at least one embodiment, processing system 2600 is a television or set-top box device having one or more processor(s) 2602 and graphics processor(s) 2608, as well as a graphical interface generated by graphics processor(s) 2608.

[0244] In at least one embodiment, one or more processors 2602 each include one or more processor cores 2607 to process instructions which, when executed, perform operations such as operations for systems and user software. In at least one embodiment, each of the one or more processor cores 2607 is configured to process a specific instruction set 2609. In at least one embodiment, instruction set 2609 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via a very long instruction word (VLIW). In at least one embodiment, multiple processor cores 2607 can each process a different instruction set 2609, which can include instructions to facilitate emulation of other instruction sets. In at least one embodiment, processor core 2607 can also include other processing devices, such as a digital signal processor (DSP).

[0245] In at least one embodiment, processor 2602 includes cache memory 2604. In at least one embodiment, processor 2602 can have single-level or multi-level internal caches. In at least one embodiment, cache memory is shared among multiple components of processor 2602. In at least one embodiment, processor 2602 also uses an external cache (e.g., a level three (L3) cache or last level cache (LLC)) (not shown), which can be shared among processor cores 2607 using known cache coherency techniques. In at least one embodiment, register file 2606 is additionally included in processor 2602, which can include different types of registers to store different kinds of data (e.g., integer registers, floating point registers, status registers, and instruction pointer registers). In at least one embodiment, register file 2606 can include a general register file or other registers.

[0246] In at least one embodiment, one or more processors 2602 are coupled with one or more interface buses 2610 for passing communication signals between processor 2602 and other components of processing system 2600. In at least one embodiment, one or more interface buses 2610 can be versions of a processor bus, such as a direct media interface (DMI) bus. In at least one embodiment, interface bus 2610 is not limited to DMI bus, and can include one or more peripheral component interconnect buses (e.g., a PCI, a PCI Express (“PCIe”)), a memory bus, or other types of interface buses. In at least one embodiment, processor 2602 includes integrated memory controller 2616 and platform controller hub 2630. In at least one embodiment, memory controller 2616 facilitates communication over a memory bus between memory 2620 and other components of processing system 2600, while platform controller hub 2630 provides connections between a local I / O bus and input / output (I / O) devices.

[0247] In at least one embodiment, memory 2620 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, or some other memory device having suitable performance to serve as a processor memory. In at least one embodiment, memory 2620 can be used as system memory for processing system 2600, to store data 2622 and instructions 2621 for use when one or more processors 2602 executes an application or process. In at least one embodiment, memory controller 2616 also couples with an optional external graphics processor 2612, which can communicate with one or more graphics processors 2608 within processors 2602 to perform graphics and media operations. In at least one embodiment, a display device 2611 can be connected to processor 2602. In at least one embodiment, display device 2611 can include one or more internal display devices, such as a display device within a mobile electronic device or a laptop computer device, or an external display device connected to processor 2602 through a display interface, such as DisplayPort or the like. In at least one embodiment, display device 2611 can include a head mounted display (HMD) such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0248] In at least one embodiment, platform controller hub 2630 enables peripherals to connect to storage devices 2620 and processor 2602 via a high-speed I / O bus. In at least one embodiment, I / O peripherals include, but are not limited to, audio controller 2646, network controller 2634, firmware interface 2628, wireless transceiver 2626, touch sensors 2625, data storage devices 2624 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage devices 2624 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCIe). In at least one embodiment, touch sensors 2625 can include touch screen sensors, pressure sensors, or fingerprint sensors. In at least one embodiment, wireless transceiver 2626 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 2628 enables communication with system firmware, in at least one embodiment, and can be a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2634 can enable network connectivity to one or more wired networks. In at least one embodiment, a high-performance network controller (not shown) is coupled

[0249] In at least one embodiment, memory controller 2616 and instances of platform controller hub 2630 can be integrated into a discrete external graphics processor, such as external graphics processor 2612. In at least one embodiment, platform controller hub 2630 and / or memory controller 2616 can be external to one or more processor(s) 2602. For example, in at least one embodiment, processing system 2600 can include an external memory controller 2616 and platform controller hub 2630, which can be configured as a memory controller hub and a peripheral controller hub in a system chipset that is in communication with processor(s) 2602.

[0250] Figure 27A computer system 2700 according to at least one embodiment is shown. In at least one embodiment, computer system 2700 can be a system with interconnected devices and components, a SOC, or some combination thereof. In at least one embodiment, computer system 2700 is formed from a processor 2702 that can include execution units to execute an instruction. In at least one embodiment, computer system 2700 can include, without limitation, components such as processor 2702 that employ execution units including logic to perform algorithms for process data. In at least one embodiment, computer system 2700 can include processors such as Pentium®, CoreTM, XScaleTM, and / or StrongARM™, Core TM or Nervana TM microprocessors, although other systems (including PCs, workstations, set-top boxes, etc. with other microprocessors) can also be used. In at least one embodiment, computer system 2700 can execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux in at least one embodiment), embedded software, and / or graphical user interfaces can also be used.

[0251] In at least one embodiment, computer system 2700 can be used in other devices such as handheld devices and embedded applications. Some embodiments of at least one embodiment of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, embedded applications can include a microcontroller, a digital signal processor (“DSP”), a SOC, a network computer (“NetPC”), a set-top box, a network hub, a wide area

[0252] In at least one embodiment, computer system 2700 can include, without limitation, a processor 2702, which can include, without limitation, one or more execution units 2708 that can be configured to execute a computational unified device architecture (“CUDA”) (registered trademark) algorithm. In at least one embodiment, execution units 2708 can be configured to execute other algorithms efficiently to perform at a CUDA program. In at least one embodiment, a CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 2700 is a single processor desktop or server system. In at least one embodiment, computer system 2700 can be a multiprocessor system. In at least one embodiment, processor 2702 can include, without limitation, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, in at least one embodiment. In at least one embodiment, processor 2702 can be coupled to a processor bus 2710 that can transmit data signals between processor 2702 and other components in computer system 2700.

[0253] In at least one embodiment, processor 2702 can include, without limitation, a level 1 (“Ll”) internal cache memory (“cache”) 2704. In at least one embodiment, processor 2702 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, cache memory can reside in the processor 2702’s external. In at least one embodiment, processor 2702 can include a combination of internal and external caches. In at least one embodiment, register file 2706 can store different types of data within various registers including, without limitation, integer registers, floating point registers, status registers, and instruction pointer registers.

[0254] In at least one embodiment, execution unit 2708, including, without limitation, logic to perform integer and floating point operations, also resides in processor 2702. Processor 2702 can also include microcode (“ucode”) read-only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, execution unit 2708 can include logic to handle a packed instruction set 2709. In at least one embodiment, by including the packed instruction set 2709 in the instruction set of a general-purpose processor 2702, along with associated circuitry to execute the instructions, the general-purpose processor 2702 can be used to perform the operations on packed data that many multimedia applications use. In at least one embodiment, by using the full width of the processor’s data bus when performing operations on packed data, many multimedia applications can be accelerated as compared to using load / store type architectures, which can require multiple Tens of load and store operations per application.

[0255] In at least one embodiment, execution unit 2708 can also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 2700 can include, but not limited to, memory 2720. In at least one embodiment, memory 2720 can be implemented as a DRAM device, SRAM device, flash memory device, or other memory device. Memory 2720 can store instructions 2719 and / or data 2721 represented by data signals that can be executed by processor 2702.

[0256] In at least one embodiment, system logic chip can be coupled to processor bus 2710 and memory 2720. In at least one embodiment, system logic chip can include, without limitation, a memory controller hub (“MCH”) 2716, and processor 2702 can communicate with MCH 2716 via processor bus 2710. In at least one embodiment, MCH 2716 can provide a high bandwidth memory path 2718 to memory 2720 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, MCH 2716 can initiate data signals to and receive data signals from memory 2720 and other components in computer system 2700, and can bridge data signals between processor bus 2710, memory 2720, and system I / O 2722.

[0257] In at least one embodiment, system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 2716 can be coupled to memory 2720 through high bandwidth memory path 2718, and a graphics / video card 2712 can be coupled to MCH 2716 through an Accelerated Graphics Port (“AGP”) interconnect 2714.

[0258] In at least one embodiment, computer system 2700 can use system I / O 2722 as a proprietary hub interface bus to couple MCH 2716 to I / O controller hub (“ICH”) 2730. In at least one embodiment, ICH 2730 can provide direct connections to some I / O devices and a high-speed I / O bus to connect to other I / O devices. In at least one embodiment, the high-speed I / O bus can include, without limitation, a PCI Express bus or a revved version thereof. Examples can include, without limitation, audio controller 2729, firmware hub (“Flash BIOS”) 2728, wireless transceiver 2726, data storage 2724, legacy I / O controller 2723 containing user input interface 2725 and keyboard interface, serial expansion port 2777 (e.g., USB), and network controller 2734. Data storage 2724 can include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0259] In at least one embodiment, Figure 27 A system including interconnected hardware devices or “chips” is shown. In at least one embodiment, system 2700 is a server system. Figure 27 An exemplary SoC can be shown. In at least one embodiment, Figure 27 Devices shown in FIG. 27 can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 2700 are interconnected using Compute Express Link (CXL) interconnects.

[0260] Figure 28 System 2800 according to at least one embodiment is shown. In at least one embodiment, system 2800 is an electronic device that utilizes processor 2810. In at least one embodiment, system 2800 can be, for example and without limitation, a laptop personal computer, a tower server, a rack server, a blade server, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0261] In at least one embodiment, system 2800 can include, without limitation, processor 2810 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 2810 is coupled using a bus or interface, such as I 2a C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a USB (versions 1, 2, 3), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 28 A system can be shown that includes interconnected hardware devices or “chips.” In at least one embodiment, Figure 28 An exemplary SoC can be shown. In at least one embodiment, Figure 28 Devices shown in FIG. 6 can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 28 One or more components of FIG. 6 are interconnected using Compute Express Link (CXL) interconnects.

[0262] In at least one embodiment, Figure 28 may include a display 2824, a touchscreen 2825, a touchpad 2830, a near field communication unit (“NFC”) 2845, a sensor hub 2840, a thermal sensor 2846, an Express Chipset (“EC”) 2835, a Trusted Platform Module (“TPM”) 2838, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 2822, a DSP 2860, a solid state disk (“SSD”) or hard disk drive (“HDD”) 2820, a wireless local area network unit (“WLAN”) 2850, a Bluetooth unit 2852, a wireless wide area network unit (“WWAN”) 2856, a Global Positioning System (GPS) 2855, a camera (“USB 3.0 camera”) 2854 (e.g., a USB 3.0 camera), or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 2815 implemented in at least one embodiment in LPDDR3 standard. These components can each be implemented in any suitable manner.

[0263] In at least one embodiment, other components can be communicatively coupled to processor 2810 by components discussed above. In at least one embodiment, an accelerometer 2841, an ambient light sensor (“ALS”) 2842, a compass 2843, and a gyroscope 2844 can be communicatively coupled to a sensor hub 2840. In at least one embodiment, a thermal sensor 2839, a fan 2837, a keyboard 2846, and a touchpad 2830 can be communicatively coupled to EC 2835. In at least one embodiment, a speaker 2863, a headphone 2864, and a microphone (“mic”) 2865 can be communicatively coupled to an audio unit (“audio codec and class D amplifier”) 2864, which in turn can be communicatively coupled to a DSP 2860. In at least one embodiment, audio unit 2864 can include, without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 2857 can be communicatively coupled to a WWAN unit 2856. In at least one embodiment, components such as WLAN unit 2850 and Bluetooth unit 2852, as well as WWAN unit 2856, can be implemented in a next-generation form factor (NGFF).

[0264] Figure 29 An exemplary integrated circuit 2900 is shown, in accordance with at least one embodiment. In at least one embodiment, exemplary integrated circuit 2900 is a SoC, which can be fabricated using one or more IP cores. In at least one embodiment, integrated circuit 2900 includes one or more application processors 2905 (e.g., CPUs), at least one graphics processor 2910, and can additionally include an image processor 2915 and / or a video processor 2920, any of which can be a modular IP core. In at least one embodiment, integrated circuit 2900 includes peripheral or bus logic including a USB controller 2925, a UART controller 2930, an SPI / SDIO controller 2935, and an I 2 S / I 2 C controller 2940. In at least one embodiment, integrated circuit 2900 can include a display device 2945 coupled to one or more of a high-definition multimedia interface (HDMI) controller 2950 and a mobile industry processor interface (MIPI) display interface 2955. In at least one embodiment, storage can be provided by flash memory subsystem 2960, including flash memory and a flash memory controller. In at least one embodiment, a memory interface can be provided via a memory controller 2965 for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 2970.

[0265] Figure 30A computing system 3000 is shown in accordance with at least one embodiment. In at least one embodiment, the computing system 3000 includes a processing subsystem 3001 having one or more processor(s) 3002 and system memory 3004, which communicate via an interconnection path 3005 that can include a memory hub 3005. In at least one embodiment, the memory hub 3005 can be a separate component coupled with one or more processors 3002 via individual communication links 3007A-3007N. In at least one embodiment, memory hub 3005 can be integrated into one or more processors 3002.

[0266] In at least one embodiment, processing subsystem 3001 includes one or more parallel processor(s) 3012 coupled to memory hub 3005 via a bus or other communication link 3013. In at least one embodiment, communication link 3013 can be one of many such links which can be implemented as standard system buses, PCI Express busses, or proprietary

[0267] In at least one embodiment, system storage 3014 can connect to I / O hub 3007 to provide storage mechanisms for computing system 3000. In at least one embodiment, I / O switches 3016 can be used to provide interface mechanisms to enable connections between I / O hub 3007 and other components such as network adapter 3018 and / or wireless network adapter 3019 that can be integrated into a platform, as well as various other devices that can be added via one or more add-in devices 3020. In at least one embodiment, network adapter 3018 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 3019 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices that include one or more radios.

[0268] In at least one embodiment, computing system 3000 can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and / or the like, which can also be connected to I / O hub 3007. In at least one embodiment, communication paths interconnecting various components in Figure 30 Communication paths interconnecting various components in at least one embodiment can use any suitable protocols including, for example, PCI (Peripheral Component Interconnect) based protocols (e.g., PCI Express), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect, or inter-integrated circuit (I2C) protocols).

[0269] In at least one embodiment, parallel processor(s) 3012 include circuitry optimized for graphics and video processing, in at least one embodiment including video output circuitry, and can be used in a graphics processing unit (GPU). In at least one embodiment, parallel processor(s) 3012 include circuitry optimized for general use com puting. In at least one embodiment, components of computing system 3000 can be integrated with one or more other system elements on a single integrated circuit. In at least one embodiment, parallel processor(s) 3012, memory hub 3005, processor(s) 3002, and I / O hub 3007 can be integrated into a system on a chip (SoC) integrated circuit. In at least one embodiment, components of computing system 3000 can be integrated into a single package to form a system in a package (SIP) configuration. In at least one embodiment, at least a portion of components of computing system 3000 can be integrated into a multichip module (MCM), which can be interconnected with other multichip modules to form a modular computing platform. In at least one embodiment, I / O subsystem 3011 and display device 3010B are omitted from computing system 3000.

[0270] Processing system

[0271] The following figures set forth, without limitation, example processing systems that can be used to implement at least one embodiment.

[0272] Figure 31 An accelerated processing unit (“APU”) 3100, in accordance with at least one embodiment, is shown. In at least one embodiment, APU 3100 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, APU 3100 can be configured to execute application programs such as CUDA programs. In at least one embodiment, APU 3100 includes, without limitation, core complex 3110, graphics complex 3140, fabric 3160, I / O interface 3170, memory controllers 3180, display controllers 3192, and multimedia engines 3194. In at least one embodiment, APU 3100 can include, without limitation, any combination of any number of core complexes 3110, any number of graphics complexes 3140, any number of display controllers 3192, and any number of multimedia engines 3194. For purposes of illustration, multiple instances of similar objects are represented in this document by reference characters identifying the object, and a number in parentheses identifying the desired instance.

[0273] In at least one embodiment, core complex 3110 is a CPU, graphics complex 3140 is a GPU, and APU 3100 is a processing unit that integrates, without limitation, 3110 and 3140 onto a single chip. In at least one embodiment, some tasks can be assigned to core complex 3110, while other tasks can be assigned to graphics complex 3140. In at least one embodiment, core complex 3110 is configured to execute host control software associated with APU 3100, such as an operating system. In at least one embodiment, core complex 3110 is a master processor of APU 3100 that controls and coordinates the operations of the other processors. In at least one embodiment, core complex 3110 issues commands that control the operations of graphics complex 3140. In at least one embodiment, core complex 3110 can be configured to execute host executable code derived from CUDA source code, and graphics complex 3140 can be configured to execute device executable code derived from CUDA source code.

[0274] In at least one embodiment, core complex 3110 includes, without limitation, cores 3120(1)-3120(4) and L3 cache 3130. In at least one embodiment, core complex 3110 can include, without limitation, any combination of any number of cores 3120 and any number and type of caches. In at least one embodiment, cores 3120 are configured to execute instructions of a particular instruction set architecture (“ISA”). In at least one embodiment, each core 3120 is a CPU core.

[0275] In at least one embodiment, each core 3120 includes, without limitation, a fetch / decode unit 3122, an integer execution engine 3124, a floating point execution engine 3126, and an L2 cache 3128. In at least one embodiment, fetch / decode unit 3122 fetches instructions, decodes such instructions, generates micro-operations, and dispatches individual micro-instructions to integer execution engine 3124 and floating point execution engine 3126. In at least one embodiment, fetch / decode unit 3122 can concurrently dispatch one micro-instruction to integer execution engine 3124 and another micro-instruction to floating point execution engine 3126. In at least one embodiment, integer execution engine 3124 executes, without limitation, integer and memory operations. In at least one embodiment, floating point engine 3126 executes, without limitation, floating point and vector operations. In at least one embodiment, fetch-decode unit 3122 dispatches micro-instructions to a single execution engine in place of both integer execution engine 3124 and floating point execution engine 3126.

[0276] In at least one embodiment, each core 3120(i) has access to an L2 cache 3128(i) included in core 3120(i), where i is an integer representing a particular instance of core 3120. In at least one embodiment, each core 3120 included in core complex 3110(j) is connected to other cores 3120 included in core complex 3110(j) via an L3 cache 3130(j) included in core complex 3110(j), where j is an integer representing a particular instance of core complex 3110. In at least one embodiment, cores 3120 included in core complex 3110(j) have access to all L3 caches 3130(j) included in core complex 3110(j), where j is an integer representing a particular instance of core complex 3110. In at least one embodiment, L3 cache 3130 can include, without limitation, any number of slices.

[0277] In at least one embodiment, graphics complex 3140 can be configured to perform compute operations in a highly parallel manner. In at least one embodiment, graphics complex 3140 is configured to perform graphics pipeline operations such as draw commands, pixel operations, geometric calculations, and other operations associated with rendering images to a display. In at least one embodiment, graphics complex 3140 is configured to perform operations that are not graphics related. In at least one embodiment, graphics complex 3140 is configured to perform graphics related operations and operations that are not graphics related.

[0278] In at least one embodiment, graphics processing engine 3120 includes, without limitation, any number of graphics processing clusters 3130 and shared L2 cache 3132. In at least one embodiment, graphics processing clusters 3130 share shared L2 cache 3132. In at least one embodiment, shared L2 cache 3132 is partitioned among graphics processing clusters 3130. In at least one embodiment, graphics processing engine 3120 includes, without limitation, any number of graphics processing clusters 3130 and any number (including zero) and type of cache. In at least one embodiment, graphics processing engine 3120 includes, without limitation, any number of specialized graphics hardware.

[0279] In at least one embodiment, each graphics processing cluster 3130 includes, without limitation, any number of SIMD units 3132 and shared memory 3134. In at least one embodiment, each SIMD unit 3132 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each graphics processing cluster 3130 can execute any number of thread blocks, but each thread block executes on a single graphics processing cluster 3130. In at least one embodiment, a thread block includes, without limitation, any number of threads. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 3132 executes a different thread warp. In at least one embodiment, a thread warp is a group of threads (e.g., 16 threads), where each thread in a thread warp belongs to a single thread block and is configured to process a different set of data based on a single instruction set. In at least one embodiment, one or more threads in a thread warp can be disabled using predication. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a thread warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 3134.

[0280] In at least one embodiment, fabric 3160 is a system interconnect that facilitates data and control transmissions across core complex 3110, graphics complex 3140, I / O interface 3170, memory controllers 3180, display controller 3192, and multimedia engine 3194. In at least one embodiment, APU 3100 can include, without limitation, any number and type of system interconnects in addition to or instead of fabric 3160 that facilitate data and control transmissions across any number and type of directly or indirectly linked components that can be internal or external to APU 3100. In at least one embodiment, I / O interface 3170 represents any number and type of I / O interface (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 3170. In at least one embodiment, peripheral devices coupled to I / O interface 3170 can include, without limitation, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0281] In at least one embodiment, display controller 3192 displays images on one or more display devices, such as liquid crystal display (“LCD”) devices. In at least one embodiment, multimedia engine 3194 includes, without limitation, any number and type of multimedia-related circuitry, such as a video decoder, a video encoder, an image signal processor, etc. In at least one embodiment, memory controllers 3180 facilitate data transfers between APU 3100 and unified system memory 3190. In at least one embodiment, core complex 3110 and graphics complex 3140 share unified system memory 3190.

[0282] In at least one embodiment, APU 3100 implements a memory subsystem that includes, without limitation, any number and type of memory controllers 3180 and memory devices (e.g., shared memory 3154) that can be dedicated to one component or shared among multiple components. In at least one embodiment, APU 3100 implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 cache 2728, L3 cache 3130, and L2 cache 3142), each of which can be private to a component or shared among any number of components (e.g., core 3120, core complex 3110, SIMD unit 3152, compute unit 3150, and graphics complex 3140).

[0283] Figure 32A CPU 3200 is shown, in accordance with at least one embodiment. In at least one embodiment, CPU 3200 is developed by AMD Corporation, of Santa Clara, California. In at least one embodiment, CPU 3200 can be configured to execute application programs. In at least one embodiment, CPU 3200 is configured to execute host executable code derived from CUDA source code, and an external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, CPU 3200 includes, without limitation, any number of core complexes 3210, fabric 3260, I / O interfaces 3270, and memory controllers 3280.

[0284] In at least one embodiment, core complex 3210 includes, without limitation, cores 3220(1)-3220(4) and L3 cache 3230. In at least one embodiment, core complex 3210 can include, without limitation, any number of cores 3220 and any combination and type of caches. In at least one embodiment, cores 3220 are configured to execute instructions of a particular ISA. In at least one embodiment, each core 3220 is a CPU core.

[0285] In at least one embodiment, each core 3220 includes, without limitation, a fetch / decode unit 3222, an integer execution engine 3224, a floating point execution engine 3226, and an L2 cache 3228. In at least one embodiment, fetch / decode unit 3222 fetches instructions, decodes them, generates micro-operations, and dispatches individual micro-instructions to integer execution engine 3224 and floating point execution engine 3226. In at least one embodiment, fetch / decode unit 3222 can dispatch one micro-instruction to integer execution engine 3224 and another micro-instruction to floating point execution engine 3226 simultaneously. In at least one embodiment, integer execution engine 3224 executes, without limitation, integer and memory operations. In at least one embodiment, floating point engine 3226 executes, without limitation, floating point and vector operations. In at least one embodiment, fetch-decode unit 3222 dispatches micro-instructions to a single execution engine in place of both integer execution engine 3224 and floating point execution engine 3226.

[0286] In at least one embodiment, each core 3220(i) has access to an L2 cache 3228(i) included in the core 3220(i), where i is an integer representing a particular instance of a core 3220. In at least one embodiment, each core 3220 included in a core complex 3210(j) is connected to other cores 3220 in the core complex 3210(j) via an L3 cache 3230(j) included in the core complex 3210(j), where j is an integer representing a particular instance of a core complex 3210. In at least one embodiment, a core 3220 included in a core complex 3210(j) has access to all L3 caches 3230(j) included in the core complex 3210(j), where j is an integer representing a particular instance of a core complex 3210. In at least one embodiment, an L3 cache 3230 can include, without limitation, any number of slices.

[0287] In at least one embodiment, fabric 3260 is a system interconnect that facilitates data and control transfers across core complexes 3210(1)-3210(N) (where N is an integer greater than zero), I / O interface 3270, and memory controllers 3280. In at least one embodiment, CPU 3200 can include, without limitation, any number and type of system interconnects in addition to or instead of fabric 3260 that facilitate data and control transfers across any number and type of directly or indirectly linked components that can be internal or external to CPU 3200. In at least one embodiment, I / O interface 3270 represents any number and type of I / O interface (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 3270. In at least one embodiment, peripheral devices coupled to I / O interface 3270 can include, without limitation, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other types of game controller, a media recording device, an external storage device, a network interface card, etc.

[0288] In at least one embodiment, memory controllers 3280 facilitate data transfers between CPU 3200 and system memory 3290. In at least one embodiment, core complex 3210 and graphics complex 3240 share system memory 3290. In at least one embodiment, CPU 3200 implements a memory subsystem that includes, without limitation, any number and type of memory controllers 3280 and memory devices that can be dedicated to one component or shared among multiple components. In at least one embodiment, CPU 3200 implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 cache 3228 and L3 cache 3230), each of which can be private to a component or shared among any number of components (e.g., core 3220 and core complex 3210).

[0289] Figure 33 An exemplary accelerator integration slice 3390 is shown in accordance with at least one embodiment. As used herein, a “slice” includes a specified portion of processing resources of an accelerator integration circuit. In at least one embodiment, an accelerator integration circuit provides cache management, memory access, environment management, and interrupt management services on behalf of multiple graphics processing engines that are part of graphics acceleration modules. Graphics processing engines can each comprise a separate GPU. Alternatively, graphics processing engines can include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, a graphics acceleration module can be a GPU with a plurality of graphics processing engines. In at least one embodiment, a graphics processing engine can be a separate GPU integrated on a common package, line card, or chip as the CPU.

[0290] An application effective address space 3382 within system memory 3314 stores process elements 3383. In one embodiment, process elements 3383 are stored in response to GPU invocations 3381 from applications 3380 executing on processor 3307. Process elements 3383 contain processing state for corresponding applications 3380. A work descriptor (WD) 3384 contained in process element 3383 can be a single job requested by an application or can contain pointers to a queue of jobs. In at least one embodiment, WD 3384 is a pointer to a job request queue in application effective address space 3382.

[0291] Graphics acceleration module 3346 and / or individual graphics processing engines can be shared by all or a subset of processes in a system. In at least one embodiment, infrastructure for establishing process state and sending WDs 3384 to graphics acceleration module 3346 to start jobs in a virtualized environment can be included.

[0292] In at least one embodiment, a dedicated process programming model is implemented. In this model, a single process owns a graphics acceleration module 3346 or individual graphics processing engines. As graphics acceleration module 3346 is owned by a single process, a hypervisor initializes the accelerator integration circuit for the owning partition and an operating system initializes the accelerator integration circuit for the owning partition when assigning graphics acceleration module 3346.

[0293] In operation, a WD fetch unit 3391 in accelerator integration slice 3390 fetches a next WD 3384 including an indication of work to be completed by one or more graphics processing engines of graphics acceleration module 3346. Data from WD 3384 can be stored in registers 3345 used by memory management unit (MMU) 3339, interrupt management circuit 3347, and / or environment management circuit 3348, as shown. At least one embodiment of MMU 3339 includes segment / page walk circuitry to access segment / page tables 3386 within an OS virtual address space 3385. Interrupt management circuit 3347 can handle interrupt events (INTs) 3392 received from graphics acceleration module 3346. Effective addresses 3393 produced by graphics processing engines, when executing graphics operations, are translated to real addresses by MMU 3339.

[0294] In one embodiment, a same set of registers 3345 is replicated for each graphics processing engine and / or graphics acceleration module 3346 and can be initialized by a system hypervisor or operating system. Each of these replicated registers can be included in accelerator integration slice 3390. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0295] Table 1 - Hypervisor Initialized Registers

[0296] 1 Slice Control Register 2 Real Address (RA) Planed Processing Region Pointer 3 Authorization Mask Override Register 4 Interrupt Vector Table Input Offset 5 Interrupt Vector Table Entry Limit 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Log Pointer 9 Storage Description Register

[0297] Exemplary registers that can be initialized by an operating system are shown in Table 2.

[0298] Table 2 - Operating System Initialized Registers

[0299]

[0300]

[0301] In one embodiment, each WD 3384 is specific to a particular graphics processing module 3346 and / or a particular graphics processing engine. It contains all information the graphics processing engine needs to work or work on, or it can be a pointer to a memory location where an application has set up a command queue of work to be done.

[0302] Figures 34A-34B An exemplary graphics processor according to at least one embodiment is shown. In at least one embodiment, any of the exemplary graphics processors can be fabricated as one or more IP cores. In addition to the graphics processors illustrated, in at least one embodiment, other logic and circuits can be included, including additional graphics processors cores or general processor cores. In at least one embodiment, it is a graphics processor utilized within an SoC.

[0303] Figure 34A An exemplary graphics processor 3410 of an SoC integrated circuit, according to at least one embodiment, is shown, which can be fabricated using one or more IP cores. Figure 34B An additional exemplary graphics processor 3440 of an SoC integrated circuit, according to at least one embodiment, is shown, which can be fabricated using one or more IP cores. In at least one embodiment, Figure 34A The graphics processor 3410 of FIG. 34 is a low power graphics processor core. In at least one embodiment, the graphics processor 3410 of FIG. 34 is a variant of the graphics processor 510 of FIG. 5. Figure 34B The graphics processor 3440 of FIG. 34 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 3410, 3440 can be a variant of the graphics processor 510 of FIG. 5.

[0304] In at least one embodiment, graphics processor 3410 includes a vertex processor 3405 and one or more fragment processor(s) 3415A-3415N (e.g., 3415A, 3415B, 3415C, 3415D, through 3415N-1, and 3415N). In at least one embodiment, graphics processor 3410 can execute different shader programs via separate logic for vertex processing and / or for fragment / lumen processing, where some of the vertex / fragment processing logic can be shared or generic, and where some of the vertex / fragment processing logic can be customized for a particular shader program or vertex / fragment processing task. In at least one embodiment, graphics processor 3410 includes single program vertex processor 3405 and multi -program fragment processor 3415A-3415N, which is a logical organization of a plurality of homogeneous fragment processing units functioning as a single unit. In at least one embodiment, graphics processor 3410 can execute a plurality of shader programs simultaneously. In at least one embodiment, graphics processor 3410 includes a ring interconnect 3430A-3430B. In at least one embodiment, graphics processor 3410 connects to one or more other processors through ring interconnect 3430A-3430B. In at least one embodiment, graphics processor 3410 connects to memory through ring interconnect 3430A-3430B and / or through direct memory access (DMA).

[0305] In at least one embodiment, graphics processor 3410 additionally includes one or more MMU(s) 3420A-3420B, cache memory 3425A-3425B, and circuit interconnect 3430A-3430B. In at least one embodiment, one or more MMU(s) 3420A-3420B provide for virtual to physical address mapping for graphics processor 3410, including for vertex processor 3405 and / or fragment processor 3415A-3415N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more cache memories 3425A-3425B. In at least one embodiment, one or more MMU(s) 3420A-3420B can be synchronized with other MMUs within a system, including one or more MMUs associated with one or more application processor(s) 505, image processors 515, and / or video processors 520 of FIG. 5, such that each processor 505-520 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 3430A-3430B enable graphics processor 3410 to interface with other IP cores within a SoC, either via an internal bus, as shown, or via a direct connection.

[0306] In at least one embodiment, graphics processor 3440 includes Figure 34Aone or more MMUs 3420A-3420B, caches 3425A-3425B, and circuit interconnect 3430A-3430B of graphics processor 3410. In at least one embodiment, graphics processor 3440 includes one or more shader cores 3455A-3455N (e.g., 3455A, 3455B, 3455C, 3455D, 3455E, 3455F, through 3455N-1, and 3455N), which provide for a unified shader core architecture in which a single core or type or core can be tasked with all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, a plurality of shader cores can vary. In at least one embodiment, graphics processor 3440 includes an inter-core task manager 3445, which functions as a thread dispatcher to dispatch execution threads to one or more shader cores 3455A-3455N and tiling unit 3458 to speed up tiling operations based on tile-based rendering in which a scene is subdivided for rendering operations in image space, in at least one embodiment, to take advantage of local spatial coherence within a scene or to optimize use of an internal cache.

[0307] Figure 35A Graphics core 3500 is shown in accordance with at least one embodiment. In at least one embodiment, graphics core 3500 can be included within graphics processor 2410, as described above. Figure 24 Graphics core 3500 is shown in accordance with at least one embodiment. In at least one embodiment, graphics core 3500 can be included within graphics processor 2410, as described above. Figure 34BThe unified shader cores 3455A-3455N. In at least one embodiment, graphics core 3500 includes a shared instruction cache 3502, texture units 3518, and cache / shared memory 3520, which are common to the execution resources in graphics core 3500. In at least one embodiment, graphics core 3500 can include a number of slices 3501A-3501N or partitions of each core, graphics processing units can include multiple instances of graphics core 3500. Slices 3501A-3501N can include support logic including a local instruction cache 3504A-3504N, a thread scheduler 3506A-3506N, a thread dispatcher 3508A-3508N, and a set of registers 3510A-3510N. In at least one embodiment, slices 3501A-3501N can include a set of additional functional units (AFUs) 3512A-3512N, floating point units (FPUs) 3514A-3514N, integer arithmetic logic units (ALUs) 3516A-3516N, address computation units (ACUs) 3513A-3513N, double precision floating point units (DPFPUs) 3515A-3515N, and matrix processing units (MPUs) 3517A-3517N.

[0308] In one embodiment, FPUs 3514A-3514N can perform single precision (32-bit) and half precision (16-bit) floating point operations, while DPFPUs 3515A-3515N can perform double precision (64-bit) floating point operations. In at least one embodiment, ALUs 3516A-3516N can perform variable precision integer operations in 8-bit, 16-bit, and 32-bit precision, and can be configured to perform mixed precision operations. In at least one embodiment, MPUs 3517A-3517N can also be configured to perform mixed precision matrix operations including half-precision floating point operations and 8-bit integer operations. In at least one embodiment, MPUs 3517A-3517N can perform a variety of matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix to matrix multiplication (GEMM). In at least one embodiment, AFUs 3512A-3512N can perform additional logical operations not supported by floating point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0309] Figure 35BA general-purpose graphics processing unit (GPGPU) 3530 is illustrated in at least one embodiment. In at least one embodiment, the GPGPU 3530 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, the GPGPU 3530 can be configured to enable highly parallel computational operations to be performed by a GPU array. In at least one embodiment, the GPGPU 3530 can be directly linked to other instances of the GPGPU 3530 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, the GPGPU 3530 includes a host interface 3532 for connection to a host processor. In at least one embodiment, the host interface 3532 is a PCIe interface. In at least one embodiment, the host interface 3532 can be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 3530 receives commands from the host processor and uses a global scheduler 3534 to assign execution threads associated with those commands to a set of compute clusters 3536A-3536H. In at least one embodiment, computing clusters 3536A-3536H share cache memory 3538. In at least one embodiment, cache memory 3538 can be used as an advanced cache of cache memory within computing clusters 3536A-3536H.

[0310] In at least one embodiment, the GPGPU 3530 includes memory 3544A-3544B coupled to computing clusters 3536A-3536H via a set of memory controllers 3542A-3542B. In at least one embodiment, memory 3544A-3544B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0311] In at least one embodiment, computing clusters 3536A-3536H each include a set of graphics cores, such as Figure 35A The graphics core 3500 may include various types of integer and floating-point logic units, capable of performing computational operations at various precisions, including computations suitable for CUDA programs. In at least one embodiment, at least a subset of the floating-point units in each computing cluster 3536A-3536H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0312] In at least one embodiment, multiple instances of GPGPU 3530 can be configured to operate as a compute cluster. In at least one embodiment, compute clusters 3536A-3536H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 3530 communicate through host interface 3532. In at least one embodiment, GPGPU 3530 includes I / O hub 3539 that couples GPGPU 3530 with GPU links 3540 enabling a direct connection to other instances of GPGPU 3530. In at least one embodiment, GPU links 3540 are coupled to a specialized GPU-to-GPU bridge that enables communication and synchronization among multiple instances of GPGPU 3530. In at least one embodiment, GPU links 3540 are coupled with a high-speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 3530 are located in separate data processing systems and communicate via a network device accessible via host interface 3532. In at least one embodiment, GPU links 3540 can be configured to connect to a host processor, in addition to, or in place of, host interface 3532. In at least one embodiment, GPGPU 3530 can be configured to execute a CUDA program.

[0313] Figure 36A Parallel processor 3600 is shown in accordance with at least one embodiment. In at least one embodiment, various components of parallel processor 3600 can be implemented using one or more integrated circuit devices, such as programmable processor(s), application specific integrated circuit(s) (ASIC(s)), or FPGA(s).

[0314] In at least one embodiment, parallel processor 3600 includes a parallel processing unit 3602. In at least one embodiment, parallel processing unit 3602 includes an I / O unit 3604 that enables communication with other devices, including other instances of parallel processing unit 3602. In at least one embodiment, I / O unit 3604 can be directly connected to other devices. In at least one embodiment, I / O unit 3604 connects with other devices via use of a hub or switch interface, such as memory hub 605. In at least one embodiment, connections between memory hub 605 and I / O unit 3604 form a communication link. In at least one embodiment, I / O unit 3604 connects with host interface 3606 and memory crossbar 3616, where host interface 3606 receives commands directed to performing processing operations and memory crossbar 3616 receives commands directed to performing memory operations.

[0315] In at least one embodiment, when host interface 3606 receives a command buffer via I / O unit 3604, host interface 3606 can direct a work operation to execute those commands to front end 3608. In at least one embodiment, front end 3608 is coupled with scheduler 3610, which is configured to assign commands or other work items to processing array 3612. In at least one embodiment, scheduler 3610 ensures that processing array 3612 is properly configured and in an active state before assigning tasks to processing array 3612 of processing array 3612. In at least one embodiment, scheduler 3610 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, microcontroller- implemented scheduler 3610 is configurable to perform complex scheduling and work distribution operations with both coarse and fine grain, enabling fast preemption and context switching of threads executing on processing array 3612. In at least one embodiment, host software can prove a workload for scheduling on processing array 3612 through one of a number of graphics processing doorbells. In at least one embodiment, workload can then be automatically distributed on processing array 3612 by scheduler 3610 logic within microcontroller that includes scheduler 3610.

[0316] In at least one embodiment, processing array 3612 can include up to “N” processing clusters (e.g., cluster 3614A, cluster 3614B, through cluster 3614N). In at least one embodiment, each cluster 3614A-3614N of processing array 3612 can execute a large number of concurrent threads. In at least one embodiment, scheduler 3610 can use various scheduling and / or work distribution algorithms to assign work to clusters 3614A-3614N of processing array 3612, which can vary depending on workload produced by each program or type of computation. In at least one embodiment, scheduling can be handled dynamically by scheduler 3610, or can be assisted in part by compiler logic during compilation of program logic configured for execution by processing array 3612. In at least one embodiment, different clusters 3614A-3614N of processing array 3612 can be allocated for processing different types of programs or for performing different types of computations.

[0317] In at least one embodiment, processing array 3612 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing array 3612 is configured to perform general purpose parallel compute operations. In at least one embodiment, processing array 3612 can include logic to perform processing tasks including filtering of video and / or audio data, performing modeling operations including physical operations, and performing data transformations.

[0318] In at least one embodiment, processing array 3612 is configured to perform parallel graphics processing operations. In at least one embodiment, processing array 3612 can include additional logic to support performance of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, and tessellation logic and other vertex processing logic. In at least one embodiment, processing array 3612 can be configured to execute shader programs associated with graphics processing, for example, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 3602 can transfer data to be processed from a system memory over I / O unit 3604. In at least one embodiment, data can be stored to on-chip memory (e.g., parallel processor memory 3622) during processing, and then written back to system memory.

[0319] In at least one embodiment, when parallel processing unit 3602 is used to perform graphics processing, scheduler 3610 can be configured to divide the processing workload into approximately equal sized tasks, to better enable distribution of the graphics processing operations across multiple clusters 3614A-3614N of processing array 3612. In at least one embodiment, portions of processing array 3612 can be configured to perform different types of processing. In at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. In at least one embodiment, intermediate data produced by one or more of clusters 3614A-3614N can be stored in buffers to allow transmission of the intermediate data between clusters 3614A-3614N for further processing.

[0320] In at least one embodiment, processing array 3612 can receive processing tasks to be executed via scheduler 3610, which receives commands defining the processing tasks from front end 3608. In at least one embodiment, a processing task can include an index into data to be processed, for example, which can include surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is to be processed (e.g., what program is to be executed). In at least one embodiment, scheduler 3610 can be configured to fetch the index corresponding to a task, or can receive the index from front end 3608. In at least one embodiment, front end 3608 can be configured to ensure that processing array 3612 is configured in an effective state before launching a workload specified by an incoming command buffer (e.g., a batch-buffer, a push buffer, etc.).

[0321] In at least one embodiment, each of one or more instances of parallel processing unit 3602 can be coupled to a parallel processor memory 3622. In at least one embodiment, parallel processor memory 3622 can be accessed by the processing array 3612, as well as the I / O unit 3604, via a memory crossbar 3616. In at least one embodiment, memory crossbar 3616 can be used to transfer data between memory elements and the processing array 3612. In at least one embodiment, memory crossbar 3616 can be configured to handle memory requests from a number of coherent agents. In at least one embodiment, memory crossbar 3616 can be implemented as a fully connected crossbar. In at least one embodiment, memory crossbar 3616 can be configured to handle memory requests from a number of coherent agents. In at least one embodiment, memory crossbar 3616 can be implemented as a fully connected crossbar. In at least one embodiment, memory crossbar 3616 can be configured to handle memory requests from a number of coherent agents. In at least one embodiment, memory crossbar 3616 can be implemented as a fully connected crossbar.

[0322] In at least one embodiment, memory units 3624A-3624N can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 3624A-3624N can also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps can be stored across memory units 3624A-3624N, allowing partition units 3620A-3620N to write portions of each rendering target in parallel to effectively use available bandwidth of parallel processor memory 3622. In at least one embodiment, local instances of parallel processor memory 3622 can be excluded in favor of a unified memory design that utilizes system memory in combination with local cache memory.

[0323] In at least one embodiment, any of clusters 3614A-3614N of processing array 3612 can process data that is to be written into any of memory units 3624A-3624N within parallel processor memory 3622. In at least one embodiment, memory crossbar 3616 can be configured to transmit outputs of each cluster 3614A-3614N to any partition unit 3620A-3620N or another cluster 3614A-3614N, which can perform other processing operations on the outputs. In at least one embodiment, each cluster 3614A-3614N can communicate with memory interface 3618 through memory crossbar 3616 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 3616 has a connection to memory interface 3618 to communicate with I / O unit 3604, as well as a local instance of parallel processor memory 3622, to enable processing units within different processing clusters 3614A-3614N to communicate with system memory or other memory that is not local to the parallel processing units 3602. In at least one embodiment, memory crossbar 3616 can use virtual channels to separate traffic streams between clusters 3614A-3614N and partition units 3620A-3620N.

[0324] In at least one embodiment, multiple instances of parallel processing unit 3602 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 3602 can be configured to operate together as a single parallel processing unit 3602, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. In at least one embodiment, some instances of parallel processing unit 3602 can include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 3602 or parallel processor 3600 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0325] Figure 36BA processing cluster 3694 is shown in accordance with at least one embodiment. In at least one embodiment, processing cluster 3694 is included in a parallel processing unit. In at least one embodiment, processing cluster 3694 is an instance of one of processing clusters 3614A-3614N of FIG. 36. In at least one embodiment, processing cluster 3694 can be configured to execute many threads in parallel, where the term“thread” refers to a particular instance of a particular program executing on a particular set of input data. In at least one embodiment, Single Instruction, Multiple Data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads with no or negligible program overhead due to context switching. In at least one embodiment, Single Instruction, Multiple Thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronous threads with little or no program overhead due to context switching.

[0326] In at least one embodiment, operation of processing cluster 3694 can be controlled via a pipeline manager 3632 that is assigned to SIMT parallel processor. In at least one embodiment, pipeline manager 3632 receives instructions from scheduler 3610 of FIG. 36, and manages execution of those instructions via graphics multiprocessor 3634 and / or texture unit 3636. In at least one embodiment, graphics multiprocessor 3634 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of differing architectures can be included within processing cluster 3694. In at least one embodiment, one or more instances of graphics multiprocessor 3634 can be included within processing cluster 3694. In at least one embodiment, graphics multiprocessor 3634 can process data, and a data crossbar 3640 can be used to distribute processed data to one of a number of possible destinations, including other shader units. In at least one embodiment, pipeline manager 3632 can facilitate distribution by specifying destinations for processed data to be distributed via data crossbar 3640.

[0327] In at least one embodiment, each graphics multiprocessor 3634 within processing cluster 3694 can include an identical set of functional execution logic (e.g., arithmetic logic units, load store units (LSUs), etc.). In at least one embodiment, functional execution logic can be configured in a pipelined manner, where new instructions can be issued before previous instructions are complete. In at least one embodiment, functional execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, shift operations, and the like. In at least one embodiment, same functional-unit hardware can be leveraged to perform a number of these operations in different embodiments.

[0328] In at least one embodiment, instructions delivered to processing cluster 3694 constitute a thread. In at least one embodiment, a set of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 3634. In at least one embodiment, a thread group can include fewer threads than are present in a plurality of processing engines within graphics multiprocessor 3634. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines present in graphics multiprocessor 3634, one or more of the processing engines can be idle during a cycle when a thread assignment is not available.

[0329] In at least one embodiment, graphics multiprocessor 3634 includes internal cache memory, to perform load and store operations. In at least one embodiment, graphics multiprocessor 3634 can bypass internal cache and use cache memory within processing cluster 3694 (e.g., Ll cache 3648). In at least one embodiment, each graphics multiprocessor 3634 can also have access to L2 Cache within a partition unit (e.g., partition units 3620A-3620N) that is shared among all processing clusters 3694 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 3634 can also have access to off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processor 3602 can be used as global memory. In at least one embodiment, processing cluster 3694 includes multiple instances of graphics multiprocessor 3634 that share common instructions and data, which can be stored in Ll cache 3648. Figure 36A

[0330] ​In at least one embodiment, each processing cluster 3694 can include a MMU 3645 configured to translate virtual addresses into physical addresses. In at least one embodiment, one or more instances of MMU 3645 can reside within memory interface 3618 of FIG. 36. In at least one embodiment, MMU 3645 includes a set of page table entries (PTEs) used to translate virtual addresses into physical addresses and optionally into cache line indices of a cache memory. In at least one embodiment, MMU 3645 can include an address translation lookaside buffer (TLB) or can reside in graphics multiprocessor 3634 or L1 cache 3648 or processing cluster 3694 within a cache. In at least one embodiment, processing physical addresses enables data accesses to be aligned to accelerator data access granularity.

[0331] In at least one embodiment, processing cluster 3694 can be configured such that each graphics multiprocessor 3634 is coupled to a texture unit 3636 for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 3634 as needed. In at least one embodiment, texture data is fetched from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 3634 outputs processed tasks to data crossbar 3640 in order to provide processed task to another processing cluster 3694 for further processing or to store processed task in an L2 cache, local parallel processor memory, or system memory via memory crossbar 3616. In at least one embodiment, a pre-ROP unit 3642 is configured to receive data from graphics multiprocessor 3634, direct data to a ROP unit which can be located within a partition unit (e.g., partition unit 3620A-3620N of FIG. 36) as described herein. In at least one embodiment, Pre-ROP 3642 can perform optimizations to minimize or eliminate bandwidth usage (use of data crossbar 3640, use of memory crossbar 3616, etc.) by stalling in at least one embodiment, Pre-ROP 3642 can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0332] Figure 36C A graphics multiprocessor 3696 according to at least one embodiment is shown. In at least one embodiment, graphics multiprocessor 3696 is a GPC as described herein. In at least one embodiment, GPC 3696 is a next generation graphics processing unit (GPGPU) that intensively threads the shader ALUs 3692 to maximize geometry and rendering throughput. In at least one embodiment, GPC 3696 is a next generation graphics processing unit (GPGPU) that intensively threads the shader ALUs 3692 to maximize geometry and rendering throughput. In at least one embodiment, GPC 3696 is a next generation graphics processing unit (GPGPU) that intensively threads the shader ALUs 3692 to maximize geometry and rendering throughput. Figure 36Bgraphics processor 3634. In at least one embodiment, graphics processor 3696 couples with the pipeline manager 3632 of processing cluster 3694. In at least one embodiment, graphics processor 3696 has an execution pipeline that includes, without limitation, an instruction cache 3652, an instruction unit 3654, an address mapping unit 3656, a register file 3658, one or more GPGPU cores 3662, and one or more LSU(s) 3666. GPGPU cores 3662 and LSUs 3666 couple with cache memory 3672 and shared memory 3670 through memory and cache interconnect 3668.

[0333] In at least one embodiment, instruction cache 3652 receives a stream of instructions 3650 to execute from pipeline manager 3632. In at least one embodiment, instructions are cached in instruction cache 3652 and dispatched for execution by instruction unit 3654. In one embodiment, instruction unit 3654 can dispatch instructions to the various functional units available on GPGPU cores 3662 including, but not limited to, integer algebraic units, floating point units, and others. In at least one embodiment, instructions are dispatched as groups, e.g., thread groups, which are executed via a thread group instruction. In at least one embodiment, thread groups are distributed to the cores 3662 for execution via inter-thread communication channel 3653.

[0334] In at least one embodiment, register file 3658 provides a set of registers for functional units of graphics processor 3696. In at least one embodiment, register file 3658 provides temporary storage for operands of the data paths connected to the functional units (e.g., GPGPU cores 3662, LSUs 3666) of graphics processor 3696. In at least one embodiment, register file 3658 is split between each functional unit such that there is a dedicated portion of the register file 3658 for each functional unit. In at least one embodiment, register file 3658 is partitioned between different thread groups executing on graphics processor 3696.

[0335] In at least one embodiment, GPGPU cores 3662 can each include FPUs and / or ALUs for executing instructions for graphics processing. GPGPU cores 3662 can be similar to each other in architecture or can include a mixture of different GPGPU core architectures. In at least one embodiment, a first portion of GPGPU cores 3662 include single precision FPUs and integer ALUs, while a second portion of GPGPU cores include double precision FPUs. In at least one embodiment, FPUs can implement IEEE 754-2008 standard for floating point arithmetic or enable variable precision floating point arithmetic. In at least one embodiment, graphics processor 3696 can additionally include one or more fixed function or special-purpose processing units to perform specific computational tasks such as rectangle

[0336] In at least one embodiment, GPGPU cores 3662 include SIMD logic capable of performing a single -instruction multiple-data (SIMD) operation on multiple groups of data. In at least one embodiment, GPGPU cores 3662 can physically execute SIMD8, SIMD4, and SIMD2 instructions and logically execute a SIMD1, SIMD2, and SIMD8 instructions. In at least one embodiment, a SIMD instruction issued to the GPGPU cores is interpreted as a SIMD1 instruction with a lattice width (SL) of 1, a SIMD2 instruction with SL of 2, or a SIMD8 instruction with SL of 8. In at least one embodiment, individual threads of a program configured for an 8-wide SIMD instruction set are assigned data to process using any subset of the 8 lanes used in a single iteration.

[0337] In at least one embodiment, memory and cache interconnect 3668 is an interconnect network that connects each functional unit of graphics multiprocessor 3696 to register file 3658 and shared memory 3670. In at least one embodiment, memory and cache interconnect 3668 is a crossbar interconnect that allows LSUs 3666 to implement load and store operations between shared memory 3670 and register file 3658. In at least one embodiment, register file 3658 can operate at same frequency as GPGPU cores 3662, resulting in very low latency for data transfers between GPGPU cores 3662 and register file 3658. In at least one embodiment, shared memory 3670 can be used to enable communication between threads executing on functional units within graphics multiprocessor 3696. In at least one embodiment, cache memory 3672 can be used to store data for threads executing on functional units and texture data for textures accessed by these threads. In at least one embodiment, shared memory 3670 can also be used as a program managed cache.

[0338] In at least one embodiment, parallel processor or GPGPU as described herein is communicatively coupled to host / processor cores to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, GPU can be communicatively coupled to host processor / cores over a bus or other interconnect (e.g., a high-speed

[0339] General Purpose Computing

[0340] The following figures illustrate, without limitation, exemplary software configurations used in general purpose computing to implement at least one embodiment.

[0341] Figure 37A software stack of a programming platform is shown, in accordance with at least one embodiment. In at least one embodiment, a programming platform is a platform for utilizing hardware on a computing system to accelerate compute tasks. In at least one embodiment, a software developer can access a programming platform through libraries, compiler directives, and / or extensions to a programming language. In at least one embodiment, a programming platform can be, but is not limited to, CUDA, Radeon Open Compute Platform (“ROCm”), OpenCL (OpenCL TM ), SYCL, or Intel One API.

[0342] In at least one embodiment, software stack 3700 of a programming platform provides an execution environment for application 3701. In at least one embodiment, application 3701 can include any computer software capable of launching on software stack 3700. In at least one embodiment, application 3701 can include, but is not limited to, artificial intelligence (“AI”) / machine learning (“ML”) applications, high performance computing (“HPC”) applications, virtual desktop infrastructure (“VDI”), or data center workloads.

[0343] In at least one embodiment, application 3701 and software stack 3700 run on hardware 3707. In at least one embodiment, hardware 3707 can include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices that support a programming platform. In at least one embodiment, software stack 3700 can be vendor-specific and compatible only with devices from a particular vendor, e.g., with CUDA. In at least one embodiment, software stack 3700 can be used with devices from different vendors, e.g., with OpenCL. In at least one embodiment, hardware 3707 includes a host connected to one or more devices that can be accessed via application programming interface (API) calls to perform compute tasks. In at least one embodiment, in contrast to a host within hardware 3707, which can include, but is not limited to, a CPU (but can also include a computing device) and its memory, a device within hardware 3707 can include, but is not limited to, a GPU, FPGA, AI engine, or other computing device (but can also include a CPU) and its memory.

[0344] In at least one embodiment, software stack 3700 of a programming platform includes, without limitation, a plurality of libraries 3703, a runtime 3705, and a device kernel driver 3706. In at least one embodiment, each of libraries 3703 can include data and programming code that can be used by computer programs and leveraged during software development. In at least one embodiment, libraries 3703 can include, without limitation, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, libraries 3703 include functions that are optimized for execution on one or more types of devices. In at least one embodiment, libraries 3703 can include, without limitation, functions for performing mathematical, deep learning, and / or other types of operations on a device. In at least one embodiment, libraries 3803 are associated with corresponding APIs 3802, which can include one or more APIs that expose functions implemented in libraries 3803.

[0345] In at least one embodiment, application 3701 is written as source code that is compiled into executable code, as discussed in more detail below with respect to FIG. 37B. Figure 42 In at least one embodiment, executable code of application 3701 can run, at least partially, on an execution environment provided by software stack 3700. In at least one embodiment, during execution of application 3701, code can be derived that needs to run on a device (as opposed to a host). In such a case, in at least one embodiment, runtime 3705 can be invoked to load and launch the necessary code on a device. In at least one embodiment, runtime 3705 can include any technically feasible runtime system capable of supporting execution of application 3701.

[0346] In at least one embodiment, runtime 3705 is implemented as one or more runtime libraries associated with corresponding APIs (which are shown as APIs 3704). In at least one embodiment, one or more such runtime libraries can include, without limitation, functions for memory management, execution control, device management, error handling, and / or synchronization, among others. In at least one embodiment, memory management functions can include, without limitation, functions for allocating, deallocating, and copying device memory, as well as transferring data between host memory and device memory. In at least one embodiment, execution control functions can include, without limitation, functions for launching functions on a device (sometimes referred to as “kernels” when functions are global functions that are callable from a host), and functions for setting attribute values in buffers maintained by a runtime library for a given function to be executed on a device.

[0347] In at least one embodiment, runtime libraries and corresponding APIs 3704 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number) of APIs can expose a low-level set of functions for fine-grained control of a device, while another (or any number) of APIs can expose a higher-level set of functions. In at least one embodiment, high-level runtime APIs can be built on top of low-level APIs. In at least one embodiment, one or more runtime APIs can be language-specific APIs layered on top of language-independent runtime APIs.

[0348] In at least one embodiment, device kernel driver 3706 is configured to facilitate communication with underlying devices. In at least one embodiment, device kernel driver 3706 can provide low-level functions relied upon by APIs such as APIs 3704 and / or other software. In at least one embodiment, device kernel driver 3706 can be configured to compile intermediate representation (“IR”) code into binary code at runtime. In at least one embodiment, for CUDA, device kernel driver 3706 can compile non-hardware-specific parallel thread execution (“PTX”) IR code into binary code for a particular target device at runtime (caching compiled binary code), which is sometimes also referred to as “final” code. In at least one embodiment, doing so can allow final code to run on a target device that can not have existed when source code was initially compiled into PTX code. Alternatively, in at least one embodiment, device source code can be compiled into binary code offline without requiring device kernel driver 3706 to compile IR code at runtime.

[0349] Figure 38 A CUDA implementation of software stack 3700 is shown in accordance with at least one embodiment. Figure 37 In at least one embodiment, CUDA software stack 3800 on which application 3801 can be launched includes CUDA libraries 3803, CUDA runtime 3805, CUDA driver 3807, and device kernel driver 3808. In at least one embodiment, CUDA software stack 3800 executes on hardware 3809, which can include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0350] In at least one embodiment, application 3801, CUDA runtime 3805, and device kernel driver 3808 can perform similar functions as application 3701, runtime 3705, and device kernel driver 3706, respectively, described above in connection with Figure 37CUDA Driver 3807, which includes a library (libcuda.so) that implements the CUDA Driver API 3806. In at least one embodiment, similar to the CUDA Runtime API 3804 implemented by the CUDA Runtime Library (cudart), the CUDA Driver API 3806 can expose, without limitation, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability, among others. In at least one embodiment, the CUDA Driver API 3806 differs from the CUDA Runtime API 3804 in that the CUDA Runtime API 3804 simplifies device code management by providing implicit initialization, context (similar to a process) management, and module (similar to a dynamically loaded library) management. In contrast to the high-level CUDA Runtime API 3804, in at least one embodiment, the CUDA Driver API 3806 is a low-level API that provides more granular control over a device, particularly with respect to contexts and module loading. In at least one embodiment, the CUDA Driver API 3806 can expose functions for context management that are not exposed by the CUDA Runtime API 3804. In at least one embodiment, the CUDA Driver API 3806 is also language agnostic and supports, for example, OpenCL in addition to the CUDA Runtime API 3804. Further, in at least one embodiment, development libraries including the CUDA Runtime 3805 can be considered separate from driver components, including the user-mode CUDA Driver 3807 and the kernel-mode device driver 3808 (sometimes also referred to as a “display” driver).

[0351] In at least one embodiment, CUDA Libraries 3803 can include, without limitation, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries that can be utilized by parallel computing applications, such as application 3801. In at least one embodiment, CUDA Libraries 3803 can include mathematical libraries such as a cuBLAS library, which is an implementation of basic linear algebra subprograms (“BLAS”) for performing linear algebra operations; a cuFFT library for computing fast Fourier transforms (“FFTs”), and a cuRAND library for generating random numbers, among others. In at least one embodiment, CUDA Libraries 3803 can include deep learning libraries such as a cuDNN library for primitives of deep neural networks and a TensorRT platform for high-performance deep learning inference, among others.

[0352] Figure 39 FIG. 39 shows a block diagram of a system including a GPU 3900, in accordance with at least one embodiment Figure 37ROCm implementation of the software stack 3700. In at least one embodiment, the ROCm software stack 3900 on which the application 3901 can launch includes a language runtime 3903, a system runtime 3905, a thunk 3907, a ROCm kernel driver 3908, and a device kernel driver. In at least one embodiment, the ROCm software stack 3900 executes on hardware 3909, which can include a GPU that supports ROCm, which was developed by AMD Corporation of Santa Clara, California.

[0353] In at least one embodiment, the application 3901 can perform similar functions as the application 3701 discussed above in conjunction with Figure 37 In addition, in at least one embodiment, the language runtime 3903 and the system runtime 3905 can perform similar functions as the runtime 3705 discussed above in conjunction with Figure 37 In at least one embodiment, the language runtime 3903 and the system runtime 3905 differ in that the system runtime 3905 is a language-agnostic runtime that implements the ROCr system runtime API 3904 and utilizes a Heterogeneous System Architecture (“HAS”) runtime API. In at least one embodiment, the HAS runtime API is a thin user-mode API that exposes interfaces for accessing and interacting with AMD GPUs, including functions for memory management, execution control dispatching of kernels through the architecture, error handling, system and agent information, and runtime initialization and shutdown, among others. In at least one embodiment, the language runtime 3903 is an implementation of a language-specific runtime API 3902 layered on top of the ROCr system runtime API 3904 as compared to the system runtime 3905. In at least one embodiment, a language runtime API can include, without limitation, a Portable Compute Interface (“HIP”) language runtime API, a Heterogeneous Compute Compiler (“HCC”) language runtime API, or an OpenCL API, among others. In particular, the HIP language is an extension of the C++ programming language with functionally similar versions of CUDA mechanisms, and in at least one embodiment, the HIP language runtime API includes functions similar to the CUDA runtime API 3804 discussed above in conjunction with Figure 38

[0354] ​In at least one embodiment, thunk (ROCt) 3907 is an interface that can be used to interact with underlying ROCm drivers 3908. In at least one embodiment, ROCm drivers 3908 are ROCk drivers, which are a combination of AMDGPU drivers and HAS kernel drivers (amdkfd). In at least one embodiment, AMDGPU drivers are device kernel drivers for GPUs developed by AMD that perform similar functions to those discussed above in connection with Figure 37 In at least one embodiment, HAS kernel drivers are drivers that allow different types of processors to more efficiently share system resources via hardware features.

[0355] In at least one embodiment, various libraries (not shown) can be included in ROCm software stack 3900 above language runtime 3903 and provide similar functionality to CUDA libraries 3803 discussed above in connection with Figure 38 In at least one embodiment, various libraries can include, but are not limited to, math, deep learning, and / or other libraries such as a hipBLAS library that implements similar functions to CUDA cuBLAS, a rocFFT library similar to CUDA cuFFT for computing FFTs, etc.

[0356] Figure 40 FIG. 39 illustrates an OpenCL implementation of software stack 3700 in accordance with at least one embodiment. Figure 37 In at least one embodiment, OpenCL software stack 4000 on which application 4001 can be launched includes an OpenCL framework 4005, an OpenCL runtime 4006, and drivers 4007. In at least one embodiment, OpenCL software stack 4000 executes on hardware 4008 that is not vendor-specific. In at least one embodiment, because device is supported by different vendors, specific OpenCL drivers can be required to interoperate with hardware from such vendors.

[0357] In at least one embodiment, application 4001, OpenCL runtime 4006, device kernel drivers 4007, and hardware 4008 can perform similar functions to those discussed above in connection with Figure 37 application 3701, runtime 3705, device kernel driver 3706, and hardware 3707. In at least one embodiment, application 4001 also includes OpenCL kernels 4002 having code that is to be executed on a device.

[0358] In at least one embodiment, OpenCL defines a “platform” that allows a host to control devices connected to that host. In at least one embodiment, OpenCL framework provides a platform layer API and a runtime API, shown as platform API 4003 and runtime API 4005. In at least one embodiment, runtime API 4005 uses a context to manage execution of kernels on a device. In at least one embodiment, each identified device can be associated with a respective context, which runtime API 4005 can use to manage that device’s command queues, program and kernel objects, shared memory objects, etc. In at least one embodiment, platform API 4003 exposes functions that allow device contexts to be used to select and initialize devices, submit work to devices via command queues, enable data transfers to and from devices, etc. Additionally, in at least one embodiment, OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, and image processing functions, etc.

[0359] In at least one embodiment, compiler 4004 is also included in OpenCL framework 4005. In at least one embodiment, source code can be compiled offline before an application is executed or online during execution of an application. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment can be compiled online by compiler 4004, which is included to represent any number of compilers that can be used to compile source and / or IR code (e.g., Standard Portable Intermediate Representation (“SPIR-V”) code) into binary code. Alternatively, in at least one embodiment, OpenCL applications can be compiled offline before such applications are executed.

[0360] Figure 41 Software supported by a programming platform is shown, according to at least one embodiment. In at least one embodiment, programming platform 4104 is configured to support various programming models 4103, middleware and / or libraries 4102, and frameworks 4101 that an application 4100 can rely on. In at least one embodiment, application 4100 can be an AI / ML application implemented using, for example, a deep learning framework (in at least one embodiment, MXNet, PyTorch, or TensorFlow), which can rely on libraries such as cuDNN, NVIDIACollective Communications Library (“NCCL”), and / or NVIDIA Developer Data Loading Library (“DALI”) CUDA libraries to provide accelerated computation on underlying hardware.

[0361] In at least one embodiment, programming platform 4104 can be any of the programming platforms described above in connection with FIGS. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, and 100, respectively.Figure 33 FIG. 34 and Figure 40 one of the CUDA, ROCm, or OpenCL platforms described. In at least one embodiment, programming platform 4104 supports multiple programming models 4103, which are abstractions of underlying computing systems that allow expression of algorithms and data structures. In at least one embodiment, programming models 4103 can expose features of underlying hardware in order to improve performance. In at least one embodiment, programming models 4103 can include, but are not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism (“C++ AMP”), Open Multi-Processing (“OpenMP”), Open Accelerators (“OpenACC”), and / or Vulcan Compute.

[0362] In at least one embodiment, libraries and / or middleware 4102 provide implementations of abstractions of programming models 4104. In at least one embodiment, such libraries include data and programming code that can be used by computer programs and utilized during software development. In at least one embodiment, such middleware includes software that provides services to applications in addition to those that can be obtained from programming platform 4104. In at least one embodiment, libraries and / or middleware 4102 can include, but are not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. Additionally, in at least one embodiment, libraries and / or middleware 4102 can include NCCL and ROCm Communication Collectives Library (“RCCL”) libraries, which provide communication routines for GPUs, MIOpen libraries for deep learning acceleration, and / or Eigen libraries for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0363] In at least one embodiment, application frameworks 4101 rely on libraries and / or middleware 4102. In at least one embodiment, each application framework 4101 is a software framework for implementing a standard structure of application software. In at least one embodiment, AI / ML applications can be implemented using frameworks such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning frameworks.

[0364] Figure 42 shows compiled code to run on Figures 37-40on one of the programming platforms. In at least one embodiment, compiler 4201 receives source code 4200, which includes both host code as well as device code. In at least one embodiment, compiler 4201 is configured to convert source code 4200 into host executable code 4202 for execution on a host and device executable code 4203 for execution on a device. In at least one embodiment, source code 4200 can be compiled offline prior to execution of an application, or online during execution of an application.

[0365] In at least one embodiment, source code 4200 can include code in any programming language supported by compiler 4201, such as C++, C, Fortran, etc. In at least one embodiment, source code 4200 can be included in a single-source file that has a mix of host code and device code, with locations of device code indicated therein. In at least one embodiment, the single-source file can be a.cu file that includes CUDA code or a.hip.cpp file that includes HIP code. Alternatively, in at least one embodiment, source code 4200 can include multiple source code files, rather than a single-source file, with host code and device code separated.

[0366] In at least one embodiment, compiler 4201 is configured to compile source code 4200 into host executable code 4202 for execution on a host and device executable code 4203 for execution on a device. In at least one embodiment, compiler 4201 performs operations including parsing source code 4200 into an abstract syntax tree (AST), performing optimizations, and generating executable code. In at least one embodiment where source code 4200 includes a single-source file, compiler 4201 can separate device code from host code in such single-source file, compile device code and host code into device executable code 4203 and host executable code 4202, respectively, and link device executable code 4203 and host executable code 4202 together in a single file, as discussed in more detail below with respect to FIG. 5. Figure 26

[0367] In at least one embodiment, host executable code 4202 and device executable code 4203 can be in any suitable format, such as binary code and / or IR code. In the case of CUDA, in at least one embodiment, host executable code 4202 can include native object code, while device executable code 4203 can include PTX intermediate representation code. In the case of ROCm, in at least one embodiment, both host executable code 4202 and device executable code 4203 can include object binary code.

[0368] ​Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative configurations, certain preferred embodiments thereof have been shown by way of example in the drawings and have been described above in detail. It should be understood, however, that there is no intent to limit the disclosure to the particular forms disclosed but on the contrary, the intention is to cover all modifications, alternative configurations, and equivalents falling within the spirit and scope of the disclosure as defined by the appended claims.

[0369] Unless otherwise stated, or as is clear from the context, the use of terms such as "a," "an," and "the" in the context of describing the disclosed embodiments (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated by the context. The terms "including," "has," "having," and "comprises" and variations thereof, are to be construed as open-ended terms (meaning "including, but not limited to") unless otherwise noted or as is clear from the context. The term "connected" (when used, without modification, to refer to a physical connection) is to be construed as partly or fully encompassing, attached to, or joined together, even if there are some intervening materials. Unless otherwise indicated herein, the reference in this document to numerical ranges includes all the individual values subsumed in that range separately. Unless otherwise stated, or as is clear from the context, the use of the term "set" (e.g., "set of items") or "subset" is to be construed as a non-empty set of one or more members. Also, unless otherwise stated, or as is clear from the context, the term "subset" of a corresponding set does not necessarily mean a proper subset of the corresponding set, but the subset and the corresponding set can be equal.

[0370] Unless explicitly indicated otherwise, or otherwise clearly contradicted by context, a phrase such as "at least one of A, B, and C" or "at least one of A, B, or C" is understood to generally mean that an item, term, etc. can be A, or B, or C, or any non-empty subset of the set of A, B, and C. In at least one embodiment with a set of three members, the conjunctive phrases "at least one of A, B, and C" and "at least one of A, B, or C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctive language is generally not intended to imply that certain embodiments require the existence of at least one of A, at least one of B, and at least one of C. Additionally, unless otherwise noted or as is clear from context, the term "plurality" indicates a state of multiplicity (e.g., "a plurality of items" indicates multiple items). In at least one embodiment, a plurality of items has a quantity of at least two, but can be more if explicitly indicated or indicated by context. Furthermore, unless otherwise noted or as is clear from context, the phrase "based on" means "based, at least in part, on" rather than "based solely on."

[0371] The operations of a process described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. In at least one embodiment, a process, such as those described herein (or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with executable instructions to perform the operations of the process, and the processes can be implemented as code (e.g., executable instructions, one or more computer programs or one or more applications) executing collectively on one or more processing units, by hardware or combinations thereof. In at least one embodiment, the code is stored on a computer-readable storage medium, which in at least one embodiment is a non-transitory computer-readable storage medium, which excludes transitory signals (e.g., a propagating transient electric or electromagnetic transmission) but includes non-transitory data storage circuitry (e.g., buffers, cache, and queues). In at least one embodiment, the code (e.g., executable or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) having stored thereon executable instructions that, as a result of being executed by one or more processors of a computer system (i.e., as a result of being executed), cause the computer system to perform operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media includes multiple non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media of the multiple non-transitory computer-readable storage media lack all of the code, with the multiple non-transitory computer-readable storage media collectively storing the entire code. In at least one embodiment, executable instructions are executed by different processors to cause different instructions to be executed by different processors, in at least one embodiment, the non-transitory computer-readable storage media stores the instructions, and a main central processing unit (“CPU”) executes some instructions, while a graphics processing unit (“GPU”) executes other instructions. In at least one embodiment, different components of a computer system have separate processors, and different processors execute different subsets of the instructions.

[0372] Accordingly, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform operations of processes described herein, and such a computer system is configured with applicable hardware and / or software to enable implementation of the operations. Moreover, a computer system implementing at least one embodiment of the present disclosure is a single device, and in another embodiment is a distributed computer system including multiple devices operating in different manners such that the distributed computer system performs operations described herein and such that a single device does not perform all of the operations.

[0373] The use of any and all examples, or exemplary language (e.g., "such as") provided herein, only intends to better illuminate embodiments of the disclosure and does not pose a limitation to the scope of the disclosure unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

[0374] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0375] In the description and claims, the terms "coupled" and "connected," along with derivatives thereof, can be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in at least one embodiment in the specification, "connected" or "coupled" is used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" can also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

[0376] Unless specifically stated otherwise, it can be appreciated that throughout the specification terms such as "processing," "computing," "calculating," "determining," or the like, refer to the action and / or processes of a computer or computing system, or similar electronic

[0377] In a similar manner, the term "processor" can refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory. As used in at least one embodiment, a "processor" can be a CPU or GPU. A "computing platform" can include one or more processors. As used herein, in at least one embodiment, a "software" process can include software and / or hardware entities such as tasks, threads, and intelligent agents that perform work over time. Also, each process can refer to multiple processes to sequentially or concurrently execute instructions, either continuously or intermittently. The terms "system" and "method" can be used interchangeably herein, as long as the system can embody one or more methods, and the method can be considered a system.

[0378] In this document, obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, computer system, or computer-implemented machine can be referenced. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog and digital data can be accomplished in a variety of ways, such as by receiving data as a parameter of a function call or a call to an application programming interface. In some implementations, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data via a serial or parallel interface. In another implementation, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. Providing, outputting, transmitting, sending, or presenting analog or digital data can also be referenced. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by transmitting data as an input or output parameter of a function call, a parameter of an application programming interface, or an interprocess communication mechanism.

[0379] Although the above discussion discusses one implementation in at least one embodiment of the described technology, other architectures can be used to implement the described functionality and are intended to be within the scope of the present disclosure. Moreover, although specific

[0380] Further, although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims.

Claims

1. A processor, comprising: One or more circuits are used to predict future fluid flow rates and future temperature values ​​at one or more locations in the data center, based on inputs including temperature and flow data obtained from one or more sensors in the data center, using one or more neural networks associated with one or more different hardware components in the data center. The one or more circuits are also configured to determine one or more temperature control settings associated with one or more servers in the data center based on at least one of the future fluid flow rate value or future temperature value, wherein each neural network in each type of hardware component is specifically trained for that type of hardware component.

2. The processor of claim 1, wherein the one or more neural networks are stored on one or more computing boards of one or more temperature control devices associated with the one or more temperature control settings.

3. The processor of claim 1, wherein the one or more temperature control settings are determined for at least one of: each of the one or more servers, each rack of the one or more servers, or a data center including the one or more servers, and wherein the one or more neural networks are further configured to determine one or more environmental control settings associated with at least one of power, humidity, fluid flow rate, or electricity.

4. The processor of claim 1, wherein the one or more circuits are further configured to utilize the one or more neural networks over time to determine whether to update the one or more temperature control settings based on updated predictions generated by the one or more neural networks.

5. The processor of claim 1, wherein the one or more neural networks receive environmental data from at least one of a temperature sensor, pressure sensor, flow sensor, power sensor, humidity sensor, or load determination component associated with the one or more servers.

6. A system comprising: One or more processors are configured to use one or more neural networks associated with one or more different hardware components of a data center to predict future fluid flow rates and future temperature values ​​at one or more locations within the data center, based on inputs including temperature data and flow rate data obtained from one or more sensors in the data center. The one or more processors are also configured to determine one or more temperature control settings associated with one or more servers in the data center based on at least one of the future fluid flow rate values ​​or future temperature values, wherein each neural network in each type of hardware component is specifically trained for that type of hardware component.

7. The system of claim 6, wherein the one or more neural networks are stored on one or more computing boards of one or more temperature control devices associated with the one or more temperature control settings.

8. The system of claim 6, wherein the one or more temperature control settings are determined for at least one of: each of the one or more servers, each rack of the one or more servers, or a data center including the one or more servers, and wherein the one or more neural networks are further configured to determine one or more environmental control settings associated with at least one of power, humidity, fluid flow rate, or electricity.

9. The system of claim 6, wherein the one or more processors are further configured to utilize the one or more neural networks over time to determine whether to update the one or more temperature control settings based on updated predictions generated by the one or more neural networks.

10. The system of claim 6, wherein the one or more neural networks receive environmental data from at least one of a temperature sensor, pressure sensor, flow sensor, power sensor, humidity sensor, or load determination component associated with the one or more servers.

11. A method comprising: Using one or more neural networks associated with one or more different hardware components of the data center, based on inputs including temperature data and flow data obtained from one or more sensors in the data center, to predict future fluid flow and future temperature values ​​at one or more locations in the data center; as well as Based on at least one of the future fluid flow rate values ​​or future temperature values, determine one or more temperature control settings associated with one or more servers in the data center. Each neural network in each type of hardware component is trained specifically for that type of hardware component.

12. The method of claim 11, wherein the one or more neural networks are stored on one or more computing boards of one or more temperature control devices associated with the one or more temperature control settings.

13. The method of claim 11, wherein the one or more temperature control settings are determined for at least one of: each of the one or more servers, each rack of the one or more servers, or a data center including the one or more servers, and wherein the one or more neural networks are further configured to determine one or more environmental control settings associated with at least one of power, humidity, fluid flow rate, or electricity.

14. The method of claim 11, further comprising: Over time, the one or more neural networks are used to determine whether to update the one or more temperature control settings based on the updated predictions generated by the one or more neural networks.

15. The method of claim 11, wherein the one or more neural networks receive environmental data from at least one of a temperature sensor, pressure sensor, flow sensor, power sensor, humidity sensor, or load determination component associated with the one or more servers.

16. A machine-readable medium having a set of instructions stored thereon, the instructions, if executed by one or more processors, causing the one or more processors to at least: Using one or more neural networks associated with one or more different hardware components of the data center, and based on inputs including temperature and flow data obtained from one or more sensors in the data center, to predict future fluid flow rates and future temperature values ​​at one or more locations within the data center; and Based on at least one of the future fluid flow rate values ​​or future temperature values, determine one or more temperature control settings associated with one or more servers in the data center. in, Each neural network in each type of hardware component is trained specifically for that type of hardware component.

17. The machine-readable medium of claim 16, wherein the one or more neural networks are stored on one or more computing boards of one or more temperature control devices associated with the one or more temperature control settings.

18. The machine-readable medium of claim 16, wherein the one or more temperature control settings are determined for at least one of: each of the one or more servers, each rack of the one or more servers, or a data center including the one or more servers, and wherein the one or more neural networks are further configured to determine one or more environmental control settings associated with at least one of power, humidity, fluid flow rate, or electricity.

19. The machine-readable medium of claim 16, wherein the instructions, if executed, further cause the one or more processors to: Over time, the one or more neural networks are used to determine whether to update the one or more temperature control settings based on the updated predictions generated by the one or more neural networks.

20. The machine-readable medium of claim 16, wherein the one or more neural networks receive environmental data from at least one of a temperature sensor, pressure sensor, flow sensor, power sensor, humidity sensor, or load determination component associated with the one or more servers.

21. A data center cooling system, comprising: One or more cooling systems associated with one or more servers; One or more processors are configured to use one or more neural networks associated with one or more different hardware components of a data center to predict future fluid flow rates and future temperature values ​​at one or more locations within the data center, based on inputs including temperature data and flow rate data obtained from one or more sensors in the data center. The one or more processors are further configured to determine one or more temperature control settings for the one or more cooling systems based on at least one of the future fluid flow rate values ​​or future temperature values, wherein each neural network in each type of hardware component is specifically trained for that type of hardware component; and A memory for storing network parameters of the one or more neural networks.

22. The data center cooling system of claim 21, wherein the one or more neural networks are stored on one or more computing boards of one or more temperature control devices associated with the one or more temperature control settings.

23. The data center cooling system of claim 21, wherein the one or more temperature control settings are determined for at least one of: each of the one or more servers, each rack of the one or more servers, or a data center including the one or more servers, and wherein the one or more neural networks are further configured to determine one or more environmental control settings associated with at least one of power, humidity, fluid flow rate, or electricity.

24. The data center cooling system of claim 21, wherein the one or more circuits are further configured to utilize the one or more neural networks over time to determine whether to update the one or more temperature control settings based on updated predictions generated by the one or more neural networks.

25. The data center cooling system of claim 21, wherein the one or more neural networks receive environmental data from at least one of a temperature sensor, pressure sensor, flow sensor, power sensor, humidity sensor, or load determination component associated with the one or more servers.

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