Display panel driving circuit, display panel driving method, and display

Abstract

The application discloses a display panel driving circuit, a display panel driving method and a display. The display panel driving circuit comprises a driving signal access end, a conversion circuit, an integration circuit and a master control chip. The driving signal access end accesses a display panel driving signal. The conversion circuit converts the display panel driving signal into a PWM signal corresponding to a duty ratio. The integration circuit integrates the PWM signal into an analog level signal corresponding to a voltage value. The master control chip synchronously outputs the duty ratio of the PWM signal according to the voltage value of the analog level signal, and drives the display panel to work according to the duty ratio of the PWM signal and a preset frequency. The above scheme solves the technical problem of flickering of an LVDS display panel.

Description

Technical Field

[0001] This invention relates to the technical field of display panels, and particularly to display panel driving circuits, display panel driving methods, and display panels. Background Technology

[0002] Currently, display panels are divided into LVDS (Low-Voltage Differential Signaling) display panels and EDP (embedded DisplayPort) display panels. The driving process of LVDS display panels is as follows: the LVDS signal is converted into a PWM (Pulse Width Modulation) signal, and the PWM signal drives the display panel to light up. At this time, because the frequency of the PWM signal converted from the LVDS signal is low, the duty cycle of the PWM is small when the brightness of the display panel is low. When the frequency is low, the display panel will flicker, which will affect the user experience. Summary of the Invention

[0003] The main objective of this invention is to propose a driving method for a display panel, which aims to solve the technical problem of flickering in LVDS display panels.

[0004] To achieve the above objectives, the present invention proposes a display panel driving circuit, the display panel driving circuit comprising:

[0005] The drive signal input terminal is used to connect the display panel drive signal;

[0006] The conversion circuit is used to convert the display panel drive signal into a PWM signal with a corresponding duty cycle.

[0007] An integrating circuit is used to integrate the PWM signal into an analog level signal corresponding to the voltage value.

[0008] The main control chip is used to synchronize the duty cycle of the PWM signal according to the voltage value of the analog level signal, and drive the display panel to work according to the duty cycle of the PWM signal and the preset frequency.

[0009] Optionally, the display panel driving signal is an LVDS signal.

[0010] Optionally, the input terminal of the conversion circuit is connected to the drive signal access terminal, and the output terminal of the conversion circuit is connected to the input terminal of the integration circuit; the output terminal of the integration circuit is connected to the input terminal of the main control chip; and the output terminal of the main control chip is connected to the display panel.

[0011] Optionally, the integrating circuit includes a first resistor, a second resistor, a first capacitor, and a second capacitor. The first end of the first resistor is the input terminal of the integrating circuit. The second end of the first resistor, the first end of the second resistor, and the first end of the first capacitor are respectively connected to the first end of the second capacitor, and their connection node is the output terminal of the integrating circuit. The second end of the second resistor, the second end of the first capacitor, and the second end of the second capacitor are all grounded.

[0012] Optionally, the main control chip includes an analog-to-digital conversion module and a control module. The input terminal of the analog-to-digital conversion module is the input terminal of the main control chip, and the output terminal of the analog-to-digital conversion module is connected to the input terminal of the control module; the output terminal of the control module is the output terminal of the main control chip.

[0013] The analog-to-digital conversion module is used to synchronize the duty cycle of the PWM signal based on the voltage value of the analog level signal;

[0014] The control module is used to drive the display panel to work according to the duty cycle of the PWM signal and the preset frequency.

[0015] Optionally, the conversion circuit includes a conversion chip, the conversion chip being model CH7511B-BF.

[0016] To achieve the above objectives, the present invention also proposes a driving method for a display panel, the driving method comprising:

[0017] Receive the display panel drive signal and convert the received display panel drive signal into a PWM signal with the corresponding duty cycle;

[0018] The PWM signal is integrated to obtain an analog level signal corresponding to the voltage value;

[0019] The duty cycle of the PWM signal is synchronized based on the voltage value of the analog level signal, and the display panel is driven to work according to the duty cycle of the PWM signal and the preset frequency.

[0020] Optionally, the step of integrating the PWM signal to obtain an analog level signal corresponding to the voltage value includes:

[0021] The real-time voltage amplitude and real-time time of the PWM signal are collected.

[0022] The real-time voltage amplitude and real-time time of the PWM signal are integrated to obtain a voltage value;

[0023] Output an analog level signal based on the voltage value mentioned above.

[0024] Optionally, the voltage amplitude of the high-level PWM signal is denoted as UI, and the real-time is denoted as dt; the voltage value at the corresponding ground of the analog level signal...

[0025] Among them, U I The real-time voltage amplitude of the PWM signal is measured in real time, dt is the real-time time, and RC is the time constant.

[0026] To achieve the above objectives, the present invention also proposes a display panel, the display panel including the display panel driving circuit described above, or...

[0027] The display panel includes: a memory, a processor, and a control program for reducing display panel flicker stored in the memory and executable on the processor. When the control program for reducing display panel flicker is executed by the processor, it implements the steps of the display panel driving method as described above.

[0028] The technical solution of this invention provides a display panel driving circuit comprising a driving signal input terminal, a conversion circuit, an integrator circuit, and a main control chip. The driving signal input terminal receives the display panel driving signal. The conversion circuit converts the display panel driving signal into a PWM signal with a corresponding duty cycle. The integrator circuit integrates the PWM signal and processes it into an analog level signal with a corresponding voltage value. The main control chip synchronously calculates the duty cycle of the PWM signal based on the voltage value of the analog level signal and drives the display panel to operate according to the duty cycle of the PWM signal and a preset frequency. In the above scheme, the duty cycle of the input PWM signal can be transmitted to the main control chip through conversion and integration. The main control chip can then drive the display according to the duty cycle of the PWM signal and the preset frequency, ensuring that the duty cycle of the final output signal is consistent with the PWM signal. Furthermore, since the frequency of the final display panel drive signal is preset, it can be changed according to the actual driving conditions of the display panel, keeping the display panel drive signal at a high frequency within a certain range. This avoids flickering of the display panel. Simultaneously, separating and integrating the duty cycle during transmission prevents the main control chip from failing to recognize the PWM signal, fully guaranteeing the accuracy of the duty cycle driven by the main control chip to the display panel, thus enabling accurate adjustment of the display panel's brightness. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of a module of an embodiment of the display panel driving circuit of the present invention;

[0031] Figure 2 This is a circuit diagram of an embodiment of the display panel driving circuit of the present invention;

[0032] Figure 3 This is a flowchart illustrating the driving method for the display panel of the present invention.

[0033] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. If the embodiments of the present invention involve descriptions such as "first" or "second", such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of such features.

[0035] This invention proposes a display panel driving circuit, which aims to solve the technical problem of flickering in LVDS display panels.

[0036] In one embodiment, the display panel driving circuit includes a driving signal input terminal 10, a conversion circuit 20, an integrator circuit 30, and a main control chip EC. The driving signal input terminal 10 receives the display panel driving signal, and the conversion circuit 20 converts the display panel driving signal into a PWM signal with a corresponding duty cycle. The integrator circuit 30 integrates the PWM signal and processes it into an analog level signal with a corresponding voltage value. The main control chip EC synchronizes the duty cycle of the PWM signal according to the voltage value of the analog level signal, and drives the display panel 40 to work according to the duty cycle of the PWM signal and a preset frequency.

[0037] The display panel driving circuit transmits the duty cycle of the input PWM signal to the main control chip EC through conversion and integration. The main control chip EC can then drive the display according to the PWM signal's duty cycle and a preset frequency, ensuring that the duty cycle of the final output signal matches the PWM signal. Furthermore, since the frequency of the final display panel 40 driving signal is preset, it can be adjusted based on the actual driving conditions of the display panel 40, maintaining the driving signal at a high frequency within a certain range to prevent flickering. Simultaneously, during transmission, the duty cycle is separated and integrated, limiting the voltage value of the integrated analog level signal to a certain range, ensuring it remains within the voltage range recognizable by the main control chip EC. This also prevents the main control chip EC from failing to recognize the PWM signal's voltage magnitude during transmission, fully guaranteeing the accuracy of the duty cycle driven by the main control chip EC to the display panel 40, thus enabling precise brightness adjustment.

[0038] Optionally, the drive signal for the display panel 40 is an LVDS signal.

[0039] When an LVDS signal is converted into a PWM signal, the frequency of the converted PWM signal is always low. Therefore, when the display panel driving circuit scheme is combined with the above characteristics, the problem of the low frequency of the LVDS signal to PWM signal conversion can be fully solved.

[0040] It should be noted that any connection relationship for signal transmission between the above-mentioned functional circuits is acceptable and not limited. In this embodiment, the following connection relationship is used to achieve signal transmission between the above-mentioned functional circuits: the input terminal LVDS IN / IN of the conversion circuit 20 is connected to the drive signal access terminal 10; the output terminal PWM OUT of the conversion circuit 20 is connected to the input terminal of the integrator circuit 30; the output terminal of the integrator circuit 30 is connected to the input terminal PWM RC of the main control chip EC; and the output terminal PWM OUT / OUT of the main control chip EC is connected to the display panel 40.

[0041] Optionally, the integrating circuit 30 includes a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2. The first end of the first resistor R1 is the input terminal of the integrating circuit 30. The second ends of the first resistor R1, the first ends of the second resistor R2, and the first ends of the first capacitor C1 are respectively connected to the first end of the second capacitor C2, and the connection node is the output terminal of the integrating circuit 30. The second ends of the second resistor R2, the second ends of the first capacitor C1, and the second ends of the second capacitor C2 are all grounded.

[0042] Based on the circuit described above, the voltage value of the analog level signal...

[0043] The specific value of 1 / RC is determined based on the form of the integrator circuit 30, and is not limited here. I The voltage value of the PWM signal is measured in real time, where dt is the real-time time and RC is the time constant. The meaning of the RC time constant is: when a constant current I flows through the circuit, the time required for the voltage across the capacitor to reach its maximum value (equal to IR) by 1 - 1 / e, approximately 0.63 times, is the time constant. When the circuit is open, the time constant is the time required for the voltage across the capacitor to reach its maximum value by 1 / e, approximately 0.37 times. Determining the RC time constant can further reduce the signal transmission delay. Furthermore, the voltage value of the analog level signal can be quickly determined using the above integral formula. At this point, the integrated voltage value of the analog level signal is equivalent to averaging the area of ​​the high-level voltage and the corresponding time of the PWM signal over one cycle. Basically, with a duty cycle of 50%, the converted analog level signal voltage value is 50% of the highest voltage; with a duty cycle of 30%, the analog level signal voltage value is 30% of the highest voltage. For example, if the high level of the PWM is 5V, the converted analog level signal voltage value at a duty cycle of 50% is 2.5V. The voltage value of the converted analog level signal is 1.5V at a duty cycle of 30%.

[0044] Referring to Table 1, the actual process from LVDS signal input to EC output of the main control chip is as follows:

[0045]

[0046] Table 1

[0047] In this context, LVDS IC PWM duty 16Levels@200Hz represents the duty cycle of the PWM signal when the conversion chip outputs at a frequency of 200kHz; Duty step is the loss constant; RC integral V step is the integration constant; EC_ADC4(V) is the voltage value of the analog level signal acquired by the main control chip EC; and EC output PWM0duty@20kHz represents the duty cycle of the signal output by the main control chip EC when it reaches 20kHz. Here, EC refers to the main control chip EC.

[0048] Optionally, the main control chip EC includes an analog-to-digital converter module and a control module. The input terminal of the analog-to-digital converter module is the input terminal PWM RC of the main control chip EC, and the output terminal of the analog-to-digital converter module is connected to the input terminal of the control module. The output terminal of the control module is the output terminal PWM OUT of the main control chip EC.

[0049] The analog-to-digital conversion module synchronizes the duty cycle of the PWM signal based on the voltage value of the analog level signal. The control module drives the display panel 40 to operate based on the duty cycle of the PWM signal and a preset frequency. Specifically, the analog-to-digital conversion module acquires the high-level value of the PWM signal. This high-level value can be either actually measured or preset according to the type of conversion chip. h The duty cycle DR can be determined by the voltage value U of the analog level signal. The analog-to-digital converter module can use the formula DR = U / U h The duty cycle is calculated directly, thus achieving effective transmission of the duty cycle.

[0050] Optionally, the main control chip EC is model IT8528E.

[0051] Optionally, the conversion circuit 20 includes a conversion chip, the conversion chip being model CH7511B-BF.

[0052] When the conversion chip is of this type, the frequency of its output PWM signal is directly limited. If this conversion chip is directly replaced, the cost will increase significantly. Therefore, this chip, combined with the integration circuit 30, can achieve a significant performance increase at a relatively low cost, fully increasing the frequency of the PWM signal output by the conversion chip and simultaneously achieving brightness modulation.

[0053] The following combination Figure 1 and Figure 2 The working principle of this invention will be explained as follows:

[0054] After the signal from the display panel 40 is converted into a PWM signal by the conversion chip, the PWM signal is integrated by the integration circuit 30 composed of the first resistor R1, the second resistor R2, the first capacitor C1, and the second capacitor C2. Then, the analog-to-digital conversion module synchronizes the duty cycle of the PWM signal according to the voltage value of the analog level signal. The control module drives the display panel 40 to work according to the duty cycle of the PWM signal and the preset frequency. Through the above process, the frequency and duty cycle of the PWM signal are separated. Since the frequency of the PWM signal directly affects whether the display panel 40 flickers, and its driving frequency is stable, it can be directly set by the control module of the main control chip EC. However, the brightness of the display screen changes in real time, which is achieved by changing the duty cycle. If a fixed frequency is output directly without adjusting the duty cycle, the display panel 40 cannot be effectively driven. Therefore, a separate integrating circuit 30 is set up to transmit the duty cycle of the PWM signal. The PWM signal carrying duty cycle information is integrated and limited to a certain voltage range to obtain the corresponding analog level signal voltage value, which is then transmitted to the main control chip EC. This ensures that the analog-to-digital conversion module of the main control chip EC can recognize this voltage, thereby achieving effective transmission of the duty cycle. Since the duty cycle changes in real time, it is best to integrate based on one cycle to ensure the accuracy of the duty cycle transmission.

[0055] To achieve the above objectives, the present invention also proposes a driving method for a display panel 40, the driving method for the display panel 40 comprising:

[0056] S1. Receive the drive signal from the display panel 40 and convert the received drive signal from the display panel 40 into a PWM signal with the corresponding duty cycle;

[0057] The above process can be implemented by a conversion chip or conversion circuit 20, which can convert the display panel 40 driving signal into a PWM signal that can drive the display panel 40. For example, when the display panel 40 is an LVDS (Low-Voltage Differential Signaling) display panel 40, its driving signal is an LVDS signal; when the display panel 40 is an EDP (embedded DisplayPort) display panel 40, its driving signal is an EDP signal. The following explanation of the working principle of the present invention uses an LVDS driving signal as an example. The PWM signal converted by the conversion chip or conversion circuit 20 is generally limited by the performance of the conversion chip or conversion circuit 20, and the frequency of its output PWM signal will be relatively small.

[0058] S2. Integrate the PWM signal to obtain the analog level signal corresponding to the voltage value;

[0059] The integration process at this point can be implemented by the integrating circuit 30 or by a preset calculation program. Its basic purpose is to integrate the PWM signal to obtain the corresponding analog level signal with the voltage value. By integrating the PWM signal containing duty cycle information and limiting it to a certain voltage range, the voltage value of the corresponding analog level signal is obtained and transmitted to the main control chip EC. This ensures that the analog-to-digital converter module of the main control chip EC can recognize this voltage, thereby achieving effective transmission of the duty cycle. When implementing this step for the integrating circuit 30, the following can be used: Figure 2 The integrator circuit 30 shown is implemented here. When implementing this step for a calculation program, the integration formula can be preset according to actual needs, so that integration can be achieved directly by substituting numerical values ​​into the formula. The formula can be obtained by numerical simulation in the laboratory.

[0060] S3. Synchronize the duty cycle of the PWM signal according to the voltage value of the analog level signal, and drive the display panel 40 to work according to the duty cycle of the PWM signal and the preset frequency.

[0061] At this point, the above steps can be achieved through the main control chip EC. Specifically, the main control chip EC operates by acquiring the high-level value of the PWM signal. This high-level value can be either actually measured or preset based on the type of conversion chip. The high-level value U of the PWM signal... h The duty cycle DR can be determined by the voltage value U of the analog level signal. The main control chip EC can use the formula DR = U / U h The duty cycle is calculated directly, thus achieving effective duty cycle transmission. Alternatively, a signal of a certain frequency can be preset directly in the main control chip EC. During duty cycle transmission, the duty cycle of this signal is changed accordingly, enabling the display panel 40 to operate based on the PWM signal's duty cycle and the preset frequency. This avoids display panel flicker while also allowing for brightness adjustment.

[0062] Optionally, the step of integrating the PWM signal to obtain the analog level signal corresponding to the voltage value includes:

[0063] Acquire the real-time voltage amplitude and real-time time of the PWM signal;

[0064] The voltage amplitude and real-time time of the PWM signal are integrated to obtain a voltage value.

[0065] Output an analog level signal based on the voltage value mentioned above.

[0066] At this point, all the above steps can be implemented in the integrator circuit 30, thus enabling integration. It is worth noting that since the duty cycle changes in real time, it is best to perform integration based on one cycle to ensure the accuracy of the duty cycle transmission.

[0067] Optionally, the voltage amplitude of the high level of the PWM signal is denoted as U. I The real-time period is denoted as dt;

[0068] Voltage value at ground corresponding to analog level signal

[0069] The specific value of 1 / RC is determined based on the form of the integrator circuit 30, and is not limited here. I The real-time voltage amplitude of the PWM signal is measured in real time, dt is the real-time time, and RC is the time constant.

[0070] To achieve the above objectives, the present invention also provides a display panel 40, including the display panel driving circuit described above, or...

[0071] The display panel 40 includes: a memory, a processor, and a control program for reducing the flickering of the display panel 40 stored in the memory and executable on the processor. When the control program for reducing the flickering of the display panel 40 is executed by the processor, it implements the steps of the above-described driving method for the display panel 40.

[0072] It is worth noting that, since the display panel 40 of the present invention includes all embodiments of the above-described display panel driving circuit / driving method of the display panel 40, the portable computer of the present invention has all the beneficial effects of the above-described display panel 40 driving method, which will not be repeated here.

[0073] The above are merely optional embodiments of the present invention and do not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present invention specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A display panel driving circuit, characterized in that, The display panel driving circuit includes: The drive signal input terminal is used to connect the display panel drive signal; The conversion circuit is used to convert the display panel drive signal into a PWM signal with a corresponding duty cycle. An integrating circuit is used to integrate the PWM signal into an analog level signal corresponding to the voltage value. The main control chip is used to synchronize the duty cycle of the PWM signal according to the voltage value of the analog level signal, and drive the display panel to work according to the duty cycle of the PWM signal and the preset frequency. The display panel drive signal is an LVDS signal; The main control chip includes an analog-to-digital converter module and a control module. The input terminal of the analog-to-digital converter module is the input terminal of the main control chip, and the output terminal of the analog-to-digital converter module is connected to the input terminal of the control module; the output terminal of the control module is the output terminal of the main control chip. The analog-to-digital conversion module is used to synchronize the duty cycle of the PWM signal based on the voltage value of the analog level signal; The control module is used to drive the display panel to work according to the duty cycle of the PWM signal and the preset frequency.

2. The display panel driving circuit as described in claim 1, characterized in that, The input terminal of the conversion circuit is connected to the drive signal input terminal, and the output terminal of the conversion circuit is connected to the input terminal of the integration circuit; the output terminal of the integration circuit is connected to the input terminal of the main control chip; the output terminal of the main control chip is connected to the display panel.

3. The display panel driving circuit as described in claim 2, characterized in that, The integrating circuit includes a first resistor, a second resistor, a first capacitor, and a second capacitor. The first end of the first resistor is the input terminal of the integrating circuit. The second end of the first resistor, the first end of the second resistor, and the first end of the first capacitor are respectively connected to the first end of the second capacitor, and their connection node is the output terminal of the integrating circuit. The second end of the second resistor, the second end of the first capacitor, and the second end of the second capacitor are all grounded.

4. The display panel driving circuit as described in any one of claims 1-3, characterized in that, The conversion circuit includes a conversion chip, the model of which is CH7511B-BF.

5. A driving method for a display panel, applied to the display panel driving circuit as described in any one of claims 1-4, characterized in that, The driving method for the display panel includes: Receive the display panel drive signal and convert the received display panel drive signal into a PWM signal with the corresponding duty cycle; The PWM signal is integrated to obtain an analog level signal corresponding to the voltage value; The duty cycle of the PWM signal is synchronized based on the voltage value of the analog level signal, and the display panel is driven to work according to the duty cycle of the PWM signal and the preset frequency.

6. The driving method for a display panel as described in claim 5, characterized in that, The step of integrating the PWM signal to obtain the analog level signal corresponding to the voltage value includes: The real-time voltage amplitude and real-time time of the PWM signal are collected. The real-time voltage amplitude and real-time time of the PWM signal are integrated to obtain a voltage value; Output an analog level signal based on the voltage value mentioned above.

7. The driving method for a display panel as described in claim 5, characterized in that, The voltage amplitude of the high level of the PWM signal is denoted as UI, and the real-time is denoted as dt; The voltage value U corresponding to the analog level signal is... Among them, U I The real-time voltage amplitude of the PWM signal is measured in real time, dt is the real-time time, and RC is the time constant.

8. A display, characterized in that, The display includes the display panel driving circuit as described in any one of claims 1-4, or, The display includes: a memory, a processor, and a control program for reducing display panel flicker stored in the memory and executable on the processor, wherein the control program for reducing display panel flicker, when executed by the processor, implements the steps of the display panel driving method as described in any one of claims 5 to 7.

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