Memory system

Abstract

An embodiment of a memory system is provided to suppress deterioration of data reliability. According to an embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a plurality of banks each including a plurality of memory cells. The memory controller determines whether to perform a refresh process on a first bank based on whether a first temperature in a write process of the first bank and a second temperature after the write process of the first bank satisfy a first condition.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2020-157798, filed on September 18, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] In summary, the implementation methods described herein relate to memory systems. Background Technology

[0004] Memory systems including NAND flash memory and a memory controller configured to control non-volatile memory are known, wherein NAND flash memory is used as non-volatile memory. Summary of the Invention

[0005] An implementation of a memory system is provided to suppress the degradation of data reliability.

[0006] Generally, according to one embodiment, a memory system includes non-volatile memory and a memory controller. The non-volatile memory includes multiple groups, each group including multiple memory cells. The memory controller determines whether to perform a refresh process on the first group based on whether a first temperature during a write process of the first group and a second temperature after the write process of the first group satisfy a first condition. Attached Figure Description

[0007] Figure 1 This is a block diagram used to illustrate the structure of the memory system according to the first embodiment.

[0008] Figure 2 This is a block diagram illustrating the structure of a non-volatile memory according to the first embodiment.

[0009] Figure 3 This is a circuit diagram used to illustrate the structure of the memory cell array according to the first embodiment.

[0010] Figure 4 This is a schematic diagram illustrating the threshold voltage distribution of the memory cell according to the first embodiment.

[0011] Figure 5 This is a schematic diagram illustrating the change in threshold voltage distribution accompanying the temperature difference between write and read processes in a memory system according to the first embodiment.

[0012] Figure 6 This is a conceptual diagram used to illustrate temperature management information of a memory system according to the first embodiment.

[0013] Figure 7is a conceptual diagram for explaining refresh reservation information of a memory system according to the first embodiment.

[0014] Figure 8 is a flowchart for explaining an update process of temperature management information in a memory system according to the first embodiment.

[0015] Figure 9 is a flowchart for explaining a refresh reservation determination process in a memory system according to the first embodiment.

[0016] Figure 10 is a graph for explaining a relationship between a temperature transition and a state of a memory system according to the first embodiment.

[0017] Figure 11 is a conceptual diagram for explaining temperature management information of a memory system according to the second embodiment.

[0018] Figure 12 is a flowchart for explaining an update process of temperature management information in a memory system according to the second embodiment.

[0019] Figure 13 is a flowchart for explaining a refresh reservation determination process in a memory system according to the second embodiment.

[0020] Figure 14 is a conceptual diagram for explaining temperature management information of a memory system according to the third embodiment.

[0021] Figure 15 is a flowchart for explaining a first example of an update process of temperature management information in a memory system according to the third embodiment.

[0022] Figure 16 is a flowchart for explaining a second example of an update process of temperature management information in a memory system according to the third embodiment.

[0023] Figure 17 is a flowchart for explaining a refresh reservation determination process in a memory system according to the third embodiment.

[0024] Figure 18 is a flowchart for explaining a refresh reservation determination process in a memory system according to the fourth embodiment. DETAILED DESCRIPTION

[0025] Hereinafter, an embodiment will be described with reference to the drawings. In the following description, constituent elements having the same function and configuration will be denoted by the same reference numerals. In order to distinguish a plurality of constituent elements having the same reference numerals from each other, an additional reference numeral is added after the same reference numeral. If it is not necessary to particularly distinguish the constituent elements, only the same reference numeral is used without using the additional reference numeral.

[0026] 1. First Embodiment

[0027] A memory system according to the first embodiment will be described.

[0028] 1.1 Configuration

[0029] The first embodiment will be described. Hereinafter, a memory system including a NAND flash as a non-volatile memory will be described.

[0030] 1.1.1 Memory System

[0031] First, a configuration including the memory system will be described with reference to Figure 1

[0032] As shown in Figure 1 , the memory system 1 is connected to an external host device 2 and is configured to perform various operations according to an instruction from the host device 2. The memory system 1 includes a non-volatile memory 10, a volatile memory 20, and a memory controller 30. For example, the non-volatile memory 10, the volatile memory 20, and the memory controller 30 can be combined to constitute a single semiconductor device; examples of such a configuration include a memory card such as an SD card, a Universal Flash Storage (UFS) device, and a Solid State Drive (SSD). TM

[0033] The non-volatile memory 10 (hereinafter referred to as a NAND flash 10) includes, for example, a plurality of chips 10-0 to 10-N each including a plurality of memory cells (N is 1 or a larger integer). The NAND flash 10 non-volatile stores data indicated by the host device 2 to be written. In addition, the NAND flash 10 outputs data indicated by the host device 2 to be read to the host device 2 via the memory controller 30.

[0034] The volatile memory 20 is, for example, a Dynamic Random Access Memory (DRAM) and stores firmware for managing the NAND flash 10 and various management information. The volatile memory 20 is hereinafter referred to as a DRAM 20. The DRAM 20 also stores, for example, temperature management information 21 and refresh reservation information 22 as information used when deterioration in reliability of data stored in the NAND flash 10 is suppressed.

[0035] ​​As the temperature management information 21, the storage area in which data is stored in the NAND flash memory 10 and information related to the temperature at the time of writing the data are stored in association with each other.

[0036] The refresh reservation information 22 holds a list of storage areas in which refresh processing is to be performed in the storage area in which data is written in the NAND flash memory 10.

[0037] For example, the refresh processing includes writing data that has been written in a storage area in the NAND flash memory 10 to another storage area after performing an error correction process (described later), thereby reducing the number of errors (e.g., the number of error bits) detected in the data at the time of reading out the data.

[0038] The memory controller 30 includes a processor (CPU) 31, a buffer memory 32, a host interface circuit 33, an error check and correction (ECC) circuit 34, a NAND interface circuit 35, and a DRAM interface circuit 36. The function of each of the respective components 31 to 36 of the memory controller 30 to be described below can be implemented by dedicated hardware, a program (firmware), or a combination of hardware resources and firmware.

[0039] The processor 31 controls the overall operation of the memory controller 30 by loading firmware stored in a read only memory (ROM) into a random access memory (RAM) and executing the firmware. For example, when a write request is received from the host device 2, the processor 31 performs write processing in response thereto. Similar processes are performed at the time of read processing and erase processing.

[0040] The buffer memory 32 is, for example, a static random access memory (SRAM), and temporarily stores data read from the NAND flash memory 10 by the memory controller 30 and data received from the host device 2.

[0041] The host interface circuit 33 is connected to the host device 2 via a host bus, and performs communication between the memory controller 30 and the host device 2. The host bus is a bus compatible with, for example, SD TM Interface, Serial Attached SCSI (Small Computer System Interface) (SAS), Serial ATA (Advanced Technology Attachment) (SATA), or PCI (Peripheral Component Interconnect) express TM (PCIe).

[0042] The ECC circuit 34 performs error detection processing and error correction processing on data read from the NAND flash memory 10. In other words, the ECC circuit 34 generates an error correction code in write processing, and supplies data with the error correction code, and decodes the error correction code in read processing to detect whether or not there is an error bit. If an error bit is detected, the ECC circuit 34 determines the position of the error bit and corrects the error bit. The method of error correction includes, for example, hard bit decoding (hard decision decoding) and soft bit decoding (soft decision decoding). As encoding used in hard decision decoding, Bose-Chaudhuri-Hocquenghem (BCH) code, Reed-Solomon (RS) code, and the like can be used. As encoding used in soft decision decoding, Low Density Parity Check (LDPC) and the like can be used.

[0043] The NAND interface circuit 35 is connected to the NAND flash memory 10 through a NAND bus to communicate with the NAND flash memory 10. The NAND interface circuit 35 controls transmission of data, commands, and addresses between the memory controller 30 and the NAND flash memory 10, and can independently control the chips 10-0 to 10-N in the NAND flash memory 10. The NAND interface circuit 35 conforms to a NAND interface standard.

[0044] The DRAM interface circuit 36 is connected to the DRAM 20, and controls communication between the memory controller 30 and the DRAM 20. The DRAM interface circuit 36 conforms to a DRAM interface standard.

[0045] 1.1.2 Chip

[0046] Next, the structure of a chip in a nonvolatile memory will be described with reference to Figure 2 Figure 2 The structure of the chip 10-0 as an example is shown. Since the chips 10-1 to 10-N as chips other than the chip 10-0 have the same structure as the chip 10-0, the description of the chips 10-1 to 10-N will be omitted.

[0047] As shown in Figure 2 The chip 10-0 includes, for example, an input / output circuit 11, a register group 12, a logic controller 13, a sequencer 14, a temperature sensor 15, a voltage generation circuit 16, a memory cell array 17, a row decoder module 18, and a sense amplifier module 19.

[0048] ​The input / output circuit 11 transmits / receives an input / output signal I / O1-I / O8 of, for example, 8 bits width to / from the memory controller 30. The input / output signal I / O can include data DAT, status STS, address ADD, and command CMD. The input / output circuit 11 also transmits data DAT to the sense amplifier module 19, and receives data DAT from the sense amplifier module 19.

[0049] The register group 12 includes a status register 12A, an address register 12B, and a command register 12C. The status register 12A, the address register 12B, and the command register 12C store the status STS, the address ADD, and the command CMD, respectively.

[0050] The status STS is updated, for example, in accordance with an operation state of the sequencer 14. The status STS is transferred from the status register 12A to the input / output circuit 11, and output to the memory controller 30, based on an instruction from the memory controller 30. The address ADD is transferred from the input / output circuit 11 to the address register 12B, and the address ADD can include, for example, a chip address, a block address, a page address, and a column address. The command CMD is transferred from the input / output circuit 11 to the command register 12C, and the command CMD includes a command for various operations of the chip 10-0.

[0051] The logic controller 13 controls the input / output circuit 11 and the sequencer 14 based on a control signal received from the memory controller 30. Such a control signal includes, for example, a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, and a write protect signal WPn. The logic controller 13 notifies the memory controller 30 of a control signal (for example, a ready / busy signal RBn) received from the sequencer 14.

[0052] The chip enable signal CEn is a signal that activates the chip 10-0. The command latch enable signal CLE is a signal that notifies the input / output circuit 11 that the received input / output signal I / O is the command CMD. The address latch enable signal ALE is a signal that notifies the input / output circuit 11 that the received input / output signal I / O is the address ADD. The write enable signal WEn is a signal that instructs the input / output circuit 11 to input the input / output signal I / O. The read enable signal REn is a signal that instructs the input / output circuit 11 to output the input / output signal I / O. The write protect signal WPn is a signal that places the chip 10-0 in a protected state when a power is turned on or off.

[0053] The ready / busy signal RBn is a signal that notifies the memory controller 30 of whether the chip 10-0 is in a ready state or a busy state. In the present application, the "ready state" indicates that the chip 10-0 is ready to accept a command from the memory controller 30, and the "busy state" indicates that the chip 10-0 is not ready to accept a command from the memory controller 30.

[0054] The sequencer 14 controls the entire operation of the chip 10-0. For example, the sequencer 14 performs a read process, a write process, and an erase process based on a command CMD stored in the command register 12C and an address ADD stored in the address register 12B. The sequencer 14 causes the status register 12A to store temperature information acquired from the temperature sensor 15, for example, as a status STS, and outputs the temperature information to the memory controller 30 via the input / output circuit 11. The temperature information can be output to the memory controller 30 not as the status STS but as information other than the status STS.

[0055] The temperature sensor 15 is provided in the chip 10-0 and measures the temperature of, for example, the memory cell array 17. The temperature sensor 15 sends information about the measured temperature to the sequencer 14. The temperature sensor 15 can not directly measure the temperature of the memory cell array 17. The temperature sensor 15 can measure the temperature of, for example, a portion other than the memory cell array 17. In this case, the temperature of the memory cell array 17 can be estimated by the sequencer 14 based on the temperature measured by the temperature sensor 15.

[0056] The voltage generation circuit 16 generates, for example, voltages used in the read process, the write process, and the erase process. The voltage generation circuit 16 supplies the generated voltages to the memory cell array 17, the row decoder module 18, and the sense amplifier module 19.

[0057] The memory cell array 17 includes a plurality of planes PB. Figure 2 The plurality of planes PB in the illustrated example includes two planes PB0 and PB1. Each of the planes PB includes a plurality of blocks BLK0 to BLKn (where n is 1 or a larger integer). The planes PB can operate in parallel with each other. A block BLK is a collection of a plurality of memory cell transistors configured to store data in a nonvolatile manner, and serves as a unit of, for example, an erase process. Each memory cell transistor is associated with a single bit line BL and a single word line WL.

[0058] The row decoder module 18 selects a block BLK in which various processes are performed based on a block address. The row decoder module 18 transfers a voltage supplied from the voltage generation circuit 16 to a word line WL and the like in the selected block BLK.

[0059] The read amplifier module 19 reads data from the memory cell array 17 in a read process, and transfers the read data to the input / output circuit 11. The read amplifier module 19 applies a predetermined voltage to the bit line BL in a write process, in accordance with data received from the input / output circuit 11.

[0060] 1.1.3 Memory Cell Array

[0061] Next, the configuration of a memory cell array included in a chip of a nonvolatile memory according to the first embodiment will be described.

[0062] Figure 3 is an example of a circuit diagram showing the structure of the memory cell array 17 according to the first embodiment. In Figure 3 , one block BLK in the memory cell array 17 is shown. As Figure 3 indicated in

[0063] Each string unit SU includes a plurality of NAND strings NS associated with bit lines BL0 to BLm (m is 1 or a larger integer), respectively. The NAND string NS includes, for example, memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2.

[0064] Each memory cell transistor MT includes a control gate and a charge storage layer, and stores data in a nonvolatile manner. Each of the selection transistors ST1 and ST2 is used to select the string unit SU when various processes are performed.

[0065] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. The selection transistor ST1 is connected between one end of the series-connected memory cell transistors MT0 to MT7 and the associated bit line BL. The drain of the selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source of the selection transistor ST2 is connected to the source line CELSRC.

[0066] In the same block BLK, the gates of the plurality of selection transistors ST1 included in the string units SU0 to SU3 are commonly connected to selection gate lines SGD0 to SGD3, respectively. The control gates of the plurality of memory cell transistors MT0 to MT7 are commonly connected to word lines WL0 to WL7, respectively. The gates of the plurality of selection transistors ST2 are commonly connected to a selection gate line SGS, respectively.

[0067] The bit lines BL0 to BLm are shared among the plurality of blocks BLK. The NAND strings NS corresponding to the same column address are commonly connected to the same bit line BL. Each of the word lines WL0 to WL7 is provided per block BLK. The source line CELSRC is shared among the plurality of blocks BLK, for example.

[0068] A set of a plurality of memory cell transistors MT connected to a common word line WL in a single string unit SU is called, for example, a cell unit CU and serves as a unit of a write process. For example, a storage capacity of a cell unit CU including memory cell transistors MT storing 1-bit data is defined as "1 page data". 1 page data serves as a unit of, for example, a read operation. A cell unit CU can have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistors MT.

[0069] The above-described circuit structure of the memory cell array 17 is merely an example and is not limited thereto. For example, the number of string units SU included in each block BLK can be appropriately determined to be any number. The number of memory cell transistors MT and the number of selection transistors ST1 and ST2 included in each NAND string NS can be appropriately determined to be any number individually.

[0070] 1.1.4 Data Storage Mode

[0071] The memory system 1 can use a plurality of types of write modes. For example, the memory system 1 can use a single-level cell (SLC) mode, a multi-level cell (MLC) mode, a triple-level cell (TLC) mode, or a quad-level cell (QLC) mode. The SLC mode, the MLC mode, the TLC mode, and the QLC mode are write modes for storing 1-bit data, 2-bit data, 3-bit data, and 4-bit data, respectively, in a single memory cell transistor MT.

[0072] Figure 4 is an example of a threshold voltage distribution of the memory cell transistors MT in the memory system 1 according to the first embodiment. Figure 4 Four types of threshold voltage distributions and read voltage groups when the SLC mode, the MLC mode, the TLC mode, and the QLC mode are used are shown, respectively. Figure 4 In the threshold voltage distributions shown, the vertical axis represents the number of memory cell transistors MT, and the horizontal axis represents the threshold voltage Vth of the memory cell transistors MT. As shown in Figure 4 As shown in, the plurality of memory cell transistors MT form a plurality of threshold voltage distributions depending on the applied write mode (in other words, the number of bits of data stored).

[0073] When the SLC mode (1 bit / cell) is used, the threshold voltages of the plurality of memory cell transistors MT form two threshold voltage distributions. These two distributions are called "Er" state and "A" state (from low to high threshold voltage), respectively. In the SLC mode, 1-bit data having different values are respectively assigned to the "Er" state and the "A" state.

[0074] When the MLC mode (2 bits / cell) is used, the threshold voltages of the plurality of memory cell transistors MT form four threshold voltage distributions. The four distributions are respectively called an "Er" state, an "A" state, a "B" state, and a "C" state (from low to high threshold voltage). In the MLC mode, 2-bit data having different values are respectively assigned to the "Er" state to the "C" state.

[0075] When the TLC mode (3 bits / cell) is used, the threshold voltages of the plurality of memory cell transistors MT form eight threshold voltage distributions. The eight distributions are respectively called an "Er" state, an "A" state, a "B" state, a "C" state, a "D" state, an "E" state, an "F" state, and a "G" state (from low to high threshold voltage). In the TLC mode, 3-bit data having different values are respectively assigned to the "Er" state to the "G" state.

[0076] When the QLC mode (4 bits / cell) is used, the threshold voltages of the plurality of memory cell transistors MT form sixteen threshold voltage distributions. The sixteen distributions are respectively called an "Er" state, an "A" state, a "B" state, a "C" state, a "D" state, an "E" state, an "F" state, a "G" state, an "H" state, an "I" state, a "J" state, a "K" state, an "L" state, an "M" state, an "N" state, and an "O" state (from low to high threshold voltage). In the QLC mode, 4-bit data having different values are respectively assigned to the "Er" state to the "O" state.

[0077] In each of the write modes, a read voltage is set between two adjacent threshold distributions. Specifically, a read voltage VA is set between the maximum threshold voltage in the "Er" state and the minimum threshold voltage in the "A" state. Similarly, a read voltage VB is set between the "A" state and the "B" state. A read voltage VC is set between the "B" state and the "C" state. A read voltage VD is set between the "C" state and the "D" state. A read voltage VE is set between the "D" state and the "E" state. A read voltage VF is set between the "E" state and the "F" state. A read voltage VG is set between the "F" state and the "G" state. A read voltage VH is set between the "G" state and the "H" state. A read voltage VI is set between the "H" state and the "I" state. A read voltage VJ is set between the "I" state and the "J" state. A read voltage VK is set between the "J" state and the "K" state. A read voltage VL is set between the "K" state and the "L" state. A read voltage VM is set between the "L" state and the "M" state. A read voltage VN is set between the "M" state and the "N" state. A read voltage VO is set between the "N" state and the "O" state.

[0078] In each of the write modes, a read pass voltage VREAD is set to a voltage higher than the maximum threshold voltage of the highest threshold voltage distribution. The memory cell transistor MT to which the read pass voltage VREAD is applied is turned on regardless of the data stored therein.

[0079] The above-described number of bits of data stored in the memory cell transistor MT is merely an example, and is not limited thereto. For example, 5 bits or more of data can be stored in the memory cell transistor MT. In each of the write modes, each of the read voltage and the read pass voltage can be set to the same voltage value, or can be set to different voltage values.

[0080] Figure 4 A case where the threshold voltage distributions do not overlap is shown. However, in reality, the threshold voltage distributions can vary and overlap due to various factors. In this case, it can be that erroneous data is read from the memory cell transistor MT corresponding to the overlapping portion between two adjacent threshold distributions, which is undesirable.

[0081] Figure 5 is a diagram showing the number of erroneous bits due to the overlap of the threshold voltage distributions of the memory cell transistors MT according to the first embodiment. In Figure 5 In, it is assumed that the MLC mode is used as an example. Figure 5 The variation of the threshold voltage distributions is shown based on the temperature difference between the write processing and the read processing (as an example of a factor that changes the threshold voltage distributions) by using two threshold voltage distributions corresponding to the "B" state and the "C" state as an example. Specifically, Figure 5 (A) shows a state of the overlap of the threshold voltage distributions in a case where the temperature in the write processing and the temperature in the read processing are equal (hereinafter referred to as case (A)). Figure 5 (B) and Figure 5 (C) show a state of the overlap of the threshold voltage distributions in a case where the temperature in the write processing and the temperature in the read processing are significantly different (hereinafter referred to as case (B) and case (C)), respectively.

[0082] As shown in Figure 5 (A) to Figure 5 (C), the state of the overlap of the threshold voltage distributions under case (B) and case (C) is significantly different from that in case (A). Figure 5 (A) to Figure 5The area of the hatched portion of each of (C) corresponds to the sum of the number of storage cell transistors MT determined to have stored data corresponding to the "B" state as the "C" state, and the number of storage cell transistors MT determined to have stored data corresponding to the "C" state as the "B" state (hereinafter referred to as the number of error bits NE_BC). If the read voltage VC is set to a voltage corresponding to the intersection of the two threshold voltage distributions, the area can be the smallest. In case (B), the voltage corresponding to the intersection of the two threshold voltage distributions is different from that in case (A). Therefore, if data is read by using the read voltage VC, the number of error bits NE_BC will be larger than in case (A). Figure 5 The number of error bits NE_BC corresponding to the area of the hatched portion in (B) will be larger than in case (A).

[0083] Further, as Figure 5 (A) to Figure 5 As shown in (C), the two threshold voltage distributions in case (C) are wider than in case (A). Therefore, even if the read voltage is reset to a voltage VC' corresponding to the intersection of the two threshold voltage distributions in case (C), the number of error bits NE_BC will be larger than in case (A). Figure 6 The number of error bits NE_BC corresponding to the area of the hatched portion in (C) will be larger than in case (A).

[0084] Therefore, in cases (B) and (C), since the number of error bits NE_BC is larger than in case (A), the possibility that the ECC circuit 34 fails in the error correction processing can be high, which is undesirable. To avoid such a situation, the memory controller 30 stores the temperature management information 21 to judge whether or not the refresh processing is required, and stores the result of the judgment in the refresh reservation information 22.

[0085] 1.1.5 Temperature Management Information

[0086] Next, the structure of the temperature management information according to the first embodiment will be described. Figure 6 is a conceptual diagram showing a configuration example of the storage system 1 according to the first embodiment.

[0087] As Figure 6As shown, in temperature management information 21, for all storage areas in the NAND flash memory 10, each predetermined storage area (i.e., temperature management unit) stores a low-temperature flag. The low-temperature flag indicates whether the temperature of the cell array 17 is low when data is written to the storage area of ​​the corresponding temperature management unit. If the temperature of the cell array 17 is low when data is written, "true" is stored in the low-temperature flag; otherwise, "false" is stored. The memory controller 30 determines whether the temperature is low, for example, based on temperature information from the temperature sensor 15 sent from the NAND flash memory 10. For example, "false" is stored in the low-temperature flag of the temperature management unit where no data is written.

[0088] Figure 6 An example is shown where the temperature control unit is represented by the letter WL. Specifically, Figure 6 This illustrates the case where a low-temperature flag is assigned to a single cell unit (CU) (i.e., all memory cell transistors MT connected to the same word line WL in the same block BLK).

[0089] exist Figure 7 In the example, six low-temperature flags associated with word lines WL0 to WL5 in block BLK0 of chip Chip0 (chip 0) are set to "true," while two low-temperature flags associated with word lines WL6 and WL7 are set to "false." Referring to this information, when data is written to the memory cells connected to word lines WL0 to WL5 in block BLK0 of chip Chip0, the memory controller 30 recognizes that the memory cell array 17 is in a low-temperature state. When data is written to the memory cells connected to word lines WL6 and WL7 in block BLK0 of chip Chip0, the memory controller 30 also recognizes that the memory cell array 17 is not in a low-temperature state.

[0090] The structure described above allows the memory controller 30 to determine the temperature state of all storage areas in the NAND flash memory 10 when writing data.

[0091] 1.1.6 Refresh reservation information

[0092] Next, the structure for refreshing reservation information according to the first embodiment will be described. Figure 7 This is a conceptual diagram illustrating a structural example of refresh reservation information 22 in a memory system 1 according to a first embodiment.

[0093] like Figure 7 As shown, refresh reservation information 22, for example, is a refresh processing reservation area stored in the NAND flash memory 10, which is the unit of refresh processing execution. The unit of refresh processing execution is, for example, a block BLK. Figure 8It is shown that when the execution unit of the refresh processing is the block BLK, the refresh reservation information 22 stores information that the storage area including the block BLK0 and the block BLK1 of the chip Chip0 is reserved for the refresh processing.

[0094] The memory controller 30 refers to the refresh reservation information 22, and thereby performs the refresh processing on the reserved block BLK that can include a plurality of temperature management units in the order of reservation, for example, in units of the block BLK. It should be noted that the execution unit of the refresh processing is not limited to the block BLK, but can be the temperature management unit (for example, the word line WL).

[0095] 1.2 Operation

[0096] Next, the operation in the memory system according to the first embodiment will be described.

[0097] 1.2.1 Update processing of temperature management information

[0098] First, the update processing of the temperature management information accompanying the write processing in the memory system according to the first embodiment will be described.

[0099] Figure 8 is a flowchart showing the update processing of the temperature management information 21 in the memory system according to the first embodiment.

[0100] As shown in Figure 8 In step ST11, the memory system 1 performs the write processing. Specifically, for example, the memory controller 30 issues a write command set in response to a write request from the host device 2, and transmits it to the NAND flash 10. For example, the write command set includes a command instructing the NAND flash 10 to perform the write processing, an address specifying a storage area to which data is to be written, and data to be written in the storage area. After the NAND flash 10 receives the write command set, the data included in the write command set is written in the storage area of the specified address.

[0101] In step ST12, the memory controller 30 acquires information on the temperature at the time of the write processing (hereinafter referred to as "write processing time temperature") from the NAND flash 10. Specifically, for example, the memory controller 30 issues a temperature reading command, and transmits it to the NAND flash 10. For example, the temperature reading command is a status reading command. After receiving the temperature reading command, the NAND flash 10 transmits information on the temperature measured by the temperature sensor 15 to the memory controller 30.

[0102] In Figure 9In the example, the processing of step S12 is executed after the processing of step S11, but the embodiment is not limited to this example. For example, the processing of step S12 can be executed in parallel with the execution of the processing of step S11; the timing at which the temperature at the time of the write processing is acquired can be any timing during the execution of the write processing. Further, for example, the processing of step S12 can be executed before the processing of step S11.

[0103] For example, the memory controller 30 can acquire the temperature at the time of the write processing each time the write processing to one word line WL is executed. In this case, since the write processing to one word line WL is completed within several milliseconds, there is no significant difference in the temperature obtained at which time during the write processing. Therefore, the memory controller 30 can acquire the temperature measured once at a certain timing during the write processing to one word line WL as the temperature at the time of the write processing.

[0104] Further, for example, the memory controller 30 can acquire the temperature at the time of the write processing each time the write processing to one block BLK is executed. In this case, the temperature during the write processing can greatly change. Therefore, the memory controller 30 can acquire a plurality of temperatures measured at a plurality of specific timings during the write processing to one block BLK (for example, at the start and end of the write processing). In that case, the memory controller 30 can use the average of the plurality of acquired temperatures as the temperature at the time of the write processing. Alternatively, the memory controller 30 can use the lowest value of a plurality of temperatures measured at a plurality of predetermined timings during the write processing to one block BLK as the temperature at the time of the write processing.

[0105] In step ST13, the memory controller 30 determines whether the temperature at the time of the write processing acquired in step ST12 is lower than the threshold value Tth1. The memory controller 30 uses the threshold value Tth1 as a threshold value for determining whether the temperature at the time of the write processing is low.

[0106] If the temperature at the time of the write processing is lower than the threshold value Tth1 (step ST13; Yes), the memory controller 30 determines that the temperature at the time of the write processing is low, and the processing proceeds to step ST14. In step ST14, the memory controller 30 sets the low temperature flag of the temperature management unit corresponding to the write target region whose temperature at the time of the write processing is lower than the threshold value Tth1 to "True".

[0107] On the other hand, if the temperature during the write process is equal to or higher than the threshold Tth1 (step ST13; no), the memory controller 30 determines that the temperature during the write process is not low, and the process proceeds to step ST15. In step ST15, the memory controller 30 sets the low temperature flag of the temperature management unit corresponding to the write target area where the temperature during the write process is equal to or higher than the threshold Tth1 to "false".

[0108] At this point, the writing and updating of the temperature management information 21 involved in the writing process has been completed.

[0109] 1.2.2 Refresh Reservation Judgment Processing

[0110] Next, the refresh reservation determination process in the memory system according to the first embodiment will be described. Figure 9 This is a flowchart illustrating the refresh reservation determination process in the memory system 1 according to the first embodiment. Figure 9 The refresh reservation determination process steps ST21 to ST24 shown are executed periodically by the memory controller 30, for example.

[0111] like Figure 10 As shown, in step ST21, the memory controller 30 obtains information from the NAND flash memory 10 regarding the temperature used when determining whether to schedule a refresh process (hereinafter referred to as the "refresh process determination temperature"). It should be noted that when obtaining the refresh process determination temperature, the memory controller 30 obtains a temperature at a single point in time as the refresh process determination temperature. Therefore, the method used to obtain the refresh process determination temperature differs from the method used to obtain the temperature during the write process, which obtains representative values ​​of multiple temperatures over a specific time period.

[0112] In step ST22, the memory controller 30 determines whether the temperature at the time of the refresh process determination obtained in step ST21 is equal to or higher than the threshold Tth2. For temperature management units with the low-temperature flag "true", the memory controller 30 uses the threshold Tth2 as the threshold for determining whether the temperature at the time of the refresh process determination is significantly higher than the temperature at the time of the write process. The threshold Tth2 is higher than the threshold Tth1 (i.e., Tth2 > Tth1).

[0113] If the temperature is equal to or higher than the threshold Tth2 during the refresh process (step ST22; yes), the process proceeds to step ST23. If the temperature is lower than the threshold Tth2 during the refresh process (step ST22; no), steps ST23 and ST24 are omitted.

[0114] In step ST23, the memory controller 30 reserves refresh processing for all of the temperature management units having the low temperature flag "true". Specifically, the memory controller 30 refers to the temperature management information 21 to select all of the temperature management units having the low temperature flag "true". Then, the memory controller 30 stores information that the refresh processing for the block BLK including all of the selected temperature management units has been reserved in the refresh reservation information 22.

[0115] In step ST24, the memory controller 30 sets the low temperature flag of all of the temperature management units for which the refresh processing has been reserved to "false".

[0116] Thus, the refresh reservation judgment processing is completed.

[0117] The memory controller 30 can execute the reserved refresh processing at any time.

[0118] Specifically, for example, the memory controller 30 issues a read command set including the address of the block BLK that is the target of the refresh processing, and transmits the read command set to the NAND flash memory 10. Upon receiving the read command set, the NAND flash memory 10 reads data from the block BLK that is the target of the refresh processing, and outputs the read data to the memory controller 30. Upon receiving the read data from the NAND flash memory 10, the ECC circuit 34 in the memory controller 30 performs error correction processing on the read data, and acquires error-corrected data.

[0119] The memory controller 30 issues a write command set including the error-corrected data, and transmits the write command set to the NAND flash memory 10. Upon receiving the write command set, the NAND flash memory 10 writes the error-corrected data in another block BLK different from the block BLK that is the target of the refresh processing. Alternatively, the NAND flash memory 10 erases the written data from the block BLK that is the target of the refresh processing, and then writes the error-corrected data in the block BLK that is the target of the refresh processing. Then, the memory controller 30 invalidates the information indicating the block BLK that is the target of the refresh processing in the refresh reservation information 22.

[0120] Thus far, the refresh processing is completed.

[0121] 1.2.3 Relationship between state of memory system and temperature

[0122] Figure 10 is a graph showing the relationship between the state of the memory system 1 and the temperature transition according to the first embodiment. Figure 10 An example of a sequence from the start of the memory system 1 in the power-off state to the return to the power-off state again, and the temperature change in the memory system 1 involved in this state transition, is shown in a time series.

[0123] As Figure 10As shown in FIG. 1, the memory system 1 is in a power-off state until time tO. In the power-off state, the memory system 1 is maintained at a temperature TpO. The temperature TpO is the temperature of an indoor environment in which the memory system 1 is placed (e.g., 5°C). The temperature TpO can be 20°C or 25°C, and is not limited to these examples, as it can be set by a user.

[0124] At time tO, power is started to be supplied to the memory system 1. Accordingly, the memory system 1 performs a startup process (e.g., a power-on read process). In addition, the memory system 1 performs host processes, such as read and write processes, in accordance with a request from the host device 2. The memory system 1 also performs background processes, which are processes not based on a request from the host device 2, as necessary. Accordingly, the temperature of the memory system 1 increases from the temperature TpO and reaches a temperature TpI (> TpO) at time tl. The temperature TpI is, for example, 45°C. In Figure 10 In the period in which the temperature of the memory system 1 is equal to or higher than the temperature TpO and equal to or lower than the temperature TpI, the state of the memory system 1 is referred to as a "startup state".

[0125] Subsequently, when the host processes and the background processes are performed, the temperature of the memory system 1 still increases after time tl and reaches a temperature Tp2 (> TpI) at time t2. The temperature Tp2 is, for example, 70°C. Then, during time t2 to time t3, the heat generated by the performance of the host processes and the background processes is balanced with the heat released by a temperature control mechanism (not shown), and the temperature of the memory system 1 becomes stable at the temperature Tp2. In Figure 10 In the period in which the temperature of the memory system 1 is equal to or higher than the temperature TpO and equal to or lower than the temperature TpI, the state of the memory system 1 is referred to as a "startup state".

[0126] At time t3, the temperature of the memory system 1 starts to decrease, for example, due to the absence of a request from the host device 2. Since the background processes are still being performed after time t3, the temperature of the memory system 1 again becomes stable at the temperature TpI at time t4. In Figure 10 In the period in which the temperature of the memory system 1 starts to decrease from the temperature Tp2 to the time t5 at which the temperature remains stable at the temperature TpI, the state of the memory system 1 is referred to as an "idling state". The temperature TpI can be the lowest temperature among all states in which the temperature is stable in the power-on state of the memory system 1. The memory system 1 can set a threshold value Tthl to a temperature lower than the temperature TpI.

[0127] At time t5, the host processes are again performed. Accordingly, the temperature of the memory system 1 increases and reaches the temperature Tp2 at time t6. In the period from time t6 to time t7, the memory system 1 is again in a stable state.

[0128] At time t7, power supply to memory system 1 is stopped, and memory system 1 is in a power-off state. Therefore, host processing and background processing in memory system 1 cease, and the temperature of memory system 1 drops to temperature Tp0.

[0129] This completes the sequence of memory system 1.

[0130] based on Figure 10 For the temperatures Tp0 to Tp2 in each state of the sequence shown, the memory controller 30 sets thresholds Tth1 and Tth2 between temperatures Tp0 and Tp1. Threshold Tth2 is lower than temperature Tp1, for example, set to a range between 30°C and 40°C (30°C < Tth2 < 40°C). Threshold Tth1 is lower than threshold Tth2, for example, set to a range between 10°C and 30°C (10°C < Tth1 < 30°C). As a result, the memory controller 30 can avoid endlessly repeating refresh processing in both stable and idle states.

[0131] 1.3 Effects of this implementation method

[0132] According to the first embodiment, when the temperature of a certain storage area is below the threshold Tth1 during write processing, and the temperature of a certain storage area after write processing is equal to or higher than the threshold Tth2, the memory controller 30 schedules a refresh process for that storage area. Therefore, data written in the startup state can be rewritten at a higher temperature during read processing in a stable state (or idle state) before the number of erroneous bits included in the read data exceeds the correction capability of the soft-decision decoding of the ECC circuit 34. Therefore, changes in the threshold voltage distribution caused by the temperature difference between write and read processing can be suppressed, thereby suppressing the increase in the number of erroneous bits included in the read data. Therefore, the deterioration of data reliability can be suppressed.

[0133] As a supplementary explanation, according to Figure 11 As shown, the temperature difference between the startup state and the stable state is greater than the temperature difference between the idle state and the stable state, and also greater than the temperature difference between the startup state and the idle state. Therefore, when reading data written in the startup state from the stable state, the reliability of the data read is more likely to be compromised compared to reading data written in the idle state (e.g., via background processing) from the stable state, and reading data written in the startup state (e.g., via background processing) from the idle state, and reading data written in the startup state (e.g., via background processing) from the idle state.

[0134] According to the first embodiment, in the update processing of the temperature management information 21, when the temperature of the NAND flash memory 10 is lower than the threshold value Tthl, the memory controller 30 sets the low temperature flag "True" for each temperature management unit with respect to the storage region of the written data. As a result, the memory controller 30 can determine the storage region of the written data in the low temperature state (particularly, in the vicinity of the temperature TpO) in the start state. Further, in the refresh reservation determination processing, when the temperature of the NAND flash memory 10 is equal to or higher than the threshold value Tth2, the memory controller 30 reserves the refresh processing for all the temperature management units in which the low temperature flag "True" is set. For this reason, until the memory system 1 becomes the stable state (for example, in the idle state), the memory controller 30 can reserve the execution of the refresh processing for all the temperature management units in which the low temperature flag "True" is set. Therefore, it is possible to avoid a case where the number of error bits detected at the time of reading the data written at the low temperature exceeds the correction capability of the soft decision decoding of the ECC circuit 34 at the high temperature.

[0135] 2. Second Embodiment

[0136] Next, the memory system according to the second embodiment will be described. The second embodiment differs from the first embodiment in that the threshold value is not separately set for the temperature at the time of the refresh processing determination and the temperature at the time of the write processing. In fact, in the second embodiment, the threshold value is set with respect to the difference between the temperature at the time of the refresh processing determination and the temperature at the time of the write processing. Hereinafter, the description of the configuration and operation that is the same as that of the first embodiment will be omitted, and the configuration and operation that differs from that of the first embodiment will be mainly described.

[0137] 2.1 Temperature Management Information

[0138] Figure 6 is a conceptual diagram showing a configuration example of the memory system according to the second embodiment, and corresponds to Figure 11 .

[0139] As Figure 11 indicated in , the temperature management information 21A stores the temperature at the time of the write processing for each temperature management unit in all the storage regions of the NAND flash memory 10, instead of the low temperature flag.

[0140] Figure 12 The example of

[0141] 2.2 Update Processing of Temperature Management Information

[0142] Figure 8is a flowchart showing update processing of the temperature management information 21A in the memory system according to the second embodiment, and corresponds to the step ST31 in the first embodiment. Figure 12 .

[0143] As shown in Figure 8 , in the step ST31, the memory system 1 performs write processing. Since details of the write processing are similar to the step ST11 in the Figure 8 , the description thereof is omitted.

[0144] In the step ST32, the memory controller 30 acquires the temperature at the time of the write processing from the NAND flash memory 10. Since the processing of acquiring the temperature at the time of the write processing is similar to the processing of the step ST12 in the Figure 13 , the description thereof is omitted.

[0145] In the step ST33, the memory controller 30 stores the temperature at the time of the write processing of the temperature management unit corresponding to the write target area.

[0146] Up to this point, the update processing of the temperature management information 21A is completed.

[0147] 2.3 Refresh reservation determination processing

[0148] Figure 9 is a flowchart showing refresh reservation determination processing in the memory system according to the second embodiment, and corresponds to the refresh reservation determination processing shown in the steps ST41 to ST45 in the first embodiment. Figure 13 . Figure 13 The steps ST41 to ST45 of the refresh reservation determination processing shown in the , are periodically performed by the memory controller 30, for example.

[0149] Figure 9 As shown in the step ST41, the memory controller 30 acquires the temperature at the time of the refresh processing determination. Since the processing of acquiring the temperature at the time of the refresh processing determination is similar to the processing of the step ST21 in the Figure 14 , the description thereof is omitted.

[0150] In the step ST42, the memory controller 30 refers to the temperature management information 21A, and selects the temperature management unit in which the temperature at the time of the write processing is stored.

[0151] In step ST43, the memory controller 30 determines whether the difference between the refresh processing judgment time temperature acquired in step S41 and the write processing time temperature of the temperature management unit selected in step ST42 is equal to or higher than a threshold value Tth3. The threshold value Tth3 can be set within a range in which a change in threshold voltage distribution caused by a difference between the write processing time temperature and the read processing time temperature is allowed, for example. If the number of error bits occurring due to the change in threshold voltage distribution is equal to or smaller than the number of error bits that the ECC circuit 34 can correct by error correction processing, the change in threshold voltage distribution is allowed.

[0152] If the difference is equal to or greater than the threshold value Tth3 (step ST43; YES), the process proceeds to step ST44. If the difference is smaller than the threshold value Tth3 (step ST43; NO), step ST44 is omitted, and the process proceeds to step ST45.

[0153] In step ST44, the memory controller 30 stores information about the refresh processing being reserved for the block BLK including the temperature management unit selected in step ST42 in the refresh reservation information 22, thereby reserving the refresh processing.

[0154] In step ST45, the memory controller 30 determines whether all of the temperature management units managed in the temperature management information 21A have been selected. If there is a temperature management unit that has not been selected (step ST45; NO), the process returns to step ST42. In this way, steps ST42 to ST45 are repeated until all of the temperature management units are selected. If all of the temperature management units have been selected (step ST45; YES), the refresh reservation judgment processing is completed.

[0155] 2.4 Effects of the Present Embodiment

[0156] According to the second embodiment, when a temperature management unit has a difference between the refresh processing judgment time temperature and the write processing time temperature equal to or greater than the threshold value Tth3, the memory controller 30 reserves the refresh processing for the temperature management unit. Therefore, it is possible to detect, for each temperature management unit, a storage area that has entered a state in which a change in threshold voltage is not allowed. Therefore, since the memory controller 30 can determine whether to reserve the refresh processing for each temperature management unit, more adaptive control can be performed.

[0157] 3. Third Embodiment

[0158] Next, a memory system according to the third embodiment will be described. The third embodiment differs from the first and second embodiments in that refresh processing is not reserved for some temperature management units even if the temperature at the time of write processing and the temperature at the time of refresh processing determination satisfy the condition. Hereinafter, the description of the configuration and operation common to the second embodiment will be omitted, and the configuration and operation different from those of the second embodiment will be mainly described.

[0159] 3.1 Temperature management information

[0160] Figure 11 is a conceptual diagram showing a configuration example of the memory system according to the third embodiment, and corresponds to Figure 14 .

[0161] As shown in Figure 14 , the temperature management information 21B stores an exclusion flag and the temperature at the time of write processing for each temperature management unit in all the memory areas of the NAND flash memory 10. The exclusion flag is a flag that determines whether refresh processing is reserved for the memory area in the corresponding temperature management unit even if the temperature at the time of write processing and the temperature at the time of refresh processing determination satisfy the condition.

[0162] If whether the temperature at the time of write processing and the temperature at the time of refresh processing determination satisfy the condition is not considered at the time of reservation of refresh processing, "true" is stored in the exclusion flag. If whether the temperature at the time of write processing and the temperature at the time of refresh processing determination satisfy the condition is considered at the time of reservation of refresh processing, "false" is stored in the exclusion flag.

[0163] In the example of Figure 15 , six exclusion flags associated with the word lines WL0 to WL2 and WL5 to WL7 in the block BLK0 of the chip Chip0 are set to "false", and two exclusion flags associated with the word lines WL3 and WL4 are set to "true". With reference to this information, the memory controller 30 recognizes that the temperature at the time of write processing is not considered at the time of determination of whether to reserve refresh processing for the memory cells connected to the word lines WL3 and WL4 in the block BLK0 of the chip Chip0.

[0164] 3.2 Temperature management information update processing

[0165] Next, an example of update processing of the temperature management information in the memory system according to the third embodiment will be described.

[0166] 3.2.1 First example

[0167] First, a first example of update processing for the temperature management information will be described. In the first example, the exclusion flag is set based on a state in which access to the write target area is likely to occur.

[0168] Figure 12 is a flowchart showing a first example of update processing of the temperature management information 21B in the memory system according to the third embodiment, and corresponds to the processing of the steps ST31 to ST33 in the second embodiment. Figure 12 .

[0169] In the steps ST51 to ST53, the memory controller 30 performs the write processing and stores the write processing time temperature of the temperature management unit corresponding to the write target area in the temperature management information 21B. Since the processing of the steps ST51 to ST53 is similar to the processing of the steps ST31 to ST33 shown in the second embodiment, the description thereof is omitted. Figure 16

[0170] In the step ST54, the memory controller 30 determines whether the write target area is a storage area in which the access (for example, the write processing, the read processing) to the NAND flash memory 10 occurs only in the boot state.

[0171] If the access occurs only in the boot state in the write target area (step ST54; Yes), the processing proceeds to the step ST55. In the step ST55, the memory controller 30 sets the exclusion flag of the temperature management unit corresponding to the write target area to "True".

[0172] On the other hand, if the access is possible in the idle state and the steady state in the write target area (step ST54; No), the processing proceeds to the step ST56. In the step ST56, the memory controller 30 sets the exclusion flag of the temperature management unit corresponding to the write target area to "False".

[0173] The memory controller 30 can preliminarily distinguish the following data: data in which the access does not occur in the steady state and the idle state (for example, the access occurs only in the boot state), and data in which the access is possible in the steady state and the idle state. Then, the memory controller 30 can store the distinguished data in different storage areas of the NAND flash memory 10. In other words, the memory controller 30 can set the exclusion flag of the temperature management unit corresponding to the write target area based on the address of the write target area. For example, it is assumed that the data in which the access does not occur in the steady state and the idle state is system data which is read in the power-on read processing. For example, it is assumed that the storage area in which the access does not occur in the steady state and the idle state is a system data area for storing the system data. Therefore, the memory controller 30 can determine, for each temperature management unit managed in the temperature management information 21B, whether the temperature management unit is a storage area which is accessed only in the boot state based on the address of the write target area.

[0174] Up to this point, the update processing of the temperature management information 21B is completed. ​

[0175] In step ST54, the memory controller 30 can also determine whether the frequency of access to the write target area in the steady state and the idle state is less than a threshold. Specifically, if the frequency of access to the write target area in the steady state and the idle state is lower than the threshold (ST54; Yes), the process proceeds to step ST55. If the frequency is equal to or higher than the threshold (ST54; No), the process proceeds to step ST56. By the above operation, for example, if the background processing is performed at a lower frequency without the host processing, the refresh processing is not scheduled. An example in which the background processing is performed at a lower frequency without the host processing is, for example, a read processing (i.e., a patrol processing) for confirming whether data is correctly read, which is performed periodically or aperiodically, and the like.

[0176] In step ST54, the memory controller 30 can also determine whether the exclusion flag is set in the write target area according to the intended use of the write target area. Specifically, if the write target area is a storage area for storing data assumed to be accessed at a low frequency in the steady state and the idle state (ST54; Yes), the process proceeds to step ST55. If the write target area is a storage area for storing data assumed to be accessed at a high frequency (ST54; No), the process proceeds to step ST56. By the above operation, the memory controller 30 can determine whether the exclusion flag is set according to the intended use of the storage area in the NAND flash memory 10 in advance (e.g., at the time of designing the memory controller 30) rather than based on the frequency of access based on actual access.

[0177] 3.2.2 Second Example

[0178] Next, a second example of the update processing of the temperature management information will be described. In the second example, the exclusion flag is set based on the write mode. Specifically, for a write mode in which the margin between the threshold voltage distributions is relatively small, the exclusion flag is set to "False", and for a write mode in which the margin between the threshold voltage distributions is relatively large, the exclusion flag is set to "True".

[0179] Figure 16 Fig. 16 is a flowchart showing a second example of the update processing of the temperature management information 21B in the memory system according to the third embodiment.

[0180] In steps ST51 to ST53, the memory controller 30 performs the write processing and stores the write processing time temperature of the temperature management unit corresponding to the write target area in the temperature management information 21B. Since the processes of steps ST51 to ST53 are similar to those of the first example, the description thereof is omitted.

[0181] In step ST54A, the memory controller 30 determines whether the SLC mode is used for the write processing.

[0182] If the SLC mode is used, that is, if 1-bit data is written in the memory cell transistor MT (step ST54A; Yes), the processing proceeds to step ST55. In step ST55, the memory controller 30 sets the exclusion flag of the temperature management unit corresponding to the write target area to "True".

[0183] On the other hand, if the SLC mode is not used, that is, if 2 bits or more of data is written in the memory cell transistor MT (step ST54A; No), the processing proceeds to step ST56. In step ST56, the memory controller 30 sets the exclusion flag of the temperature management unit corresponding to the write target area to "False".

[0184] Up to this point, the update processing of the temperature management information 21B is completed.

[0185] In the case described above Figure 17 , the memory controller 30 sets the exclusion flag to "True" if the write mode is the SLC mode; however, the present embodiment is not limited to this case. For example, the memory controller 30 can set the exclusion flag to "True" if the write mode is the SLC mode or the MLC mode. In this case, the memory controller 30 sets the exclusion flag to "False" if the write mode is the TLC mode or the QLC mode.

[0186] 3.3 Refresh Reservation Determination Processing

[0187] Figure 13 is a flowchart showing the refresh reservation determination processing in the memory system according to the third embodiment, and corresponds to the refresh reservation determination processing shown in steps ST41 to ST46 in the second embodiment. Figure 17 .The steps ST61 to ST66 of the refresh reservation determination processing shown in Figure 17 are periodically executed by the memory controller 30, for example.

[0188] As shown in Figure 13 , in step ST61, the memory controller 30 acquires the refresh processing determination temperature. Since the details of the processing of acquiring the refresh processing determination temperature are similar to those of step ST41 in the second embodiment, the description thereof is omitted. Figure 13

[0189] In step ST62, the memory controller 30 refers to the temperature management information 21B, and selects the temperature management unit in which the write processing temperature is stored.

[0190] In step ST63, the memory controller 30 determines whether the exclusion flag of the temperature management unit selected in step ST62 is "false". If the exclusion flag is "false" (step ST63; Yes), the process proceeds to step ST64. If the exclusion flag is "true" (step ST63; No), the process proceeds to step ST66.

[0191] In step ST64, the memory controller 30 determines whether the difference between the refresh processing decision time temperature acquired in step ST61 and the write processing time temperature of the temperature management unit selected in step ST62 is equal to or higher than the threshold value Tth3. Since the details of the judgment processing based on the threshold value Tth3 are similar to those of step ST43 in Figure 18

[0192] If the difference is equal to or greater than the threshold value Tth3 (step ST64; Yes), the process proceeds to step ST65. If the difference is less than the threshold value Tth3 (step ST64; No), step ST65 is omitted, and the process proceeds to step ST66.

[0193] In step ST65, the memory controller 30 stores information about the refresh processing being reserved for the block BLK including the temperature management unit selected in step ST62 in the refresh reservation information 22, thereby reserving the refresh processing.

[0194] In step ST66, the memory controller 30 determines whether all of the temperature management units managed in the temperature management information 21B have been selected. If there is a temperature management unit that has not been selected (step ST66; No), the process returns to step ST62. In this way, steps ST62 to ST66 are repeated until all of the temperature management units are selected. If all of the temperature management units have been selected (step ST66; Yes), the refresh reservation judgment processing is completed.

[0195] 3.4 Effects of the Present Embodiment

[0196] ​According to the third embodiment, in the update processing of the temperature management information 21B, the memory controller 30 sets the exclusion flag in accordance with the address of the temperature management unit. In the refresh reservation determination processing, even if the temperature at the time of the refresh processing determination and the temperature at the time of the write processing satisfy the condition, the memory controller 30 does not reserve the refresh processing for the temperature management unit having the exclusion flag "true". Therefore, even for the data written in the low-temperature state, for which there is no possibility of reading in the high-temperature state in which the threshold voltage distribution change is more significant than in the low-temperature state, the execution of the refresh processing can be omitted. Therefore, it is possible to suppress the increase in the frequency of the background processing due to the execution of the refresh processing. Therefore, it is possible to suppress the decrease in the response performance of the memory system 1 in response to the request from the host device 2. It is also possible to avoid the risk of impairing the reliability of the read data that can occur when the system data rewritten in the high-temperature state by the refresh processing is read in the start state by the start processing.

[0197] 4. Fourth Embodiment

[0198] Next, the memory system according to the fourth embodiment will be described. The fourth embodiment differs from the first to third embodiments in that the determination criterion in the refresh reservation determination processing is changed in accordance with the degree of wear of the NAND flash memory 10. Hereinafter, the description of the configuration and operation that are the same as those of the second embodiment will be omitted, and the configuration and operation that differ from those of the second embodiment will be mainly described.

[0199] 4.1 Refresh Reservation Determination Processing

[0200] Figure 13 is a flowchart showing the refresh reservation determination processing in the memory system according to the fourth embodiment, and corresponds to Figure 18 . Figure 18 The steps ST71 to ST77 of the refresh reservation determination processing shown in

[0201] As shown in Figure 13 , in the step ST71, the memory controller 30 acquires the temperature at the time of the refresh processing determination. Since the details of the processing of acquiring the temperature at the time of the refresh processing determination are similar to those of the step ST41 in Figure 18 , the description thereof will be omitted.

[0202] In the step ST72, the memory controller 30 selects the temperature management unit in which the temperature at the time of the write processing is stored.

[0203] In step ST73, the memory controller 30 determines whether the degree of wear of the temperature management unit selected in step ST72 is equal to or higher than a threshold WEth. The degree of wear can include an index related to easiness of shift and spread of the threshold voltage distribution, and can be the number of write and erase (W / E) cycles, which can also be referred to as the number of program and erase (P / E) cycles of the temperature management unit. The number of W / E cycles is managed by the memory controller 30 (e.g., in units of blocks BLK).

[0204] If the degree of wear is lower than the threshold WEth (step ST73; No), the process proceeds to step ST74. In step ST74, the memory controller 30 determines whether the difference between the refresh processing judgment time temperature acquired in step ST71 and the write processing time temperature of the temperature management unit selected in step ST72 is equal to or higher than a threshold Tth3.

[0205] If the difference is equal to or greater than the threshold Tth3 (step ST74; Yes), the process proceeds to step ST76. If the difference is less than the threshold Tth3 (step ST74; No), step ST76 is omitted, and the process proceeds to step ST77.

[0206] On the other hand, if the degree of wear is equal to or higher than the threshold WEth (step ST73; Yes), the process proceeds to step ST75. In step ST75, the memory controller 30 determines whether the difference is equal to or higher than a threshold Tth4, which is smaller than the threshold Tth3 (i.e., Tth4 < Tth3).

[0207] If the difference is equal to or greater than the threshold Tth4 (step ST75; Yes), the process proceeds to step ST76. If the difference is less than the threshold Tth4 (step ST75; No), step ST76 is omitted, and the process proceeds to step ST77.

[0208] In step ST76, the memory controller 30 stores information about reservation of refresh processing for the blocks BLK including the temperature management unit selected in step ST72 in the refresh reservation information 22, thereby reserving the refresh processing.

[0209] In step ST77, the memory controller 30 determines whether all of the temperature management units have been selected. If there is a temperature management unit that has not been selected (step ST77; No), the process returns to step ST72. In this way, steps ST72 to ST77 are repeated until all of the temperature management units are selected. If all of the temperature management units have been selected (step ST77; Yes), the refresh reservation judgment processing is completed.

[0210] In the above-described Figure 17In the case where the value of the degree of wear is relatively low, the processing for determining whether to execute the refresh reservation is executed (step ST74 or ST75); however, the embodiment is not limited to this case. For example, if the degree of wear is lower than the threshold WEth (step ST73; No), step ST74 can be omitted, and the processing can proceed to step ST77.

[0211] 4.2 Effects of the Embodiment

[0212] According to the fourth embodiment, the memory controller 30 sets the threshold Tth to a smaller value as the degree of wear increases. Therefore, for the temperature management unit in which the degree of wear is high, the memory controller 30 can determine that the refresh processing needs to be reserved when the difference between the temperature at the time of the refresh processing reservation determination and the temperature at the time of the write processing is small. Thus, even for the temperature management unit in which the threshold voltage distribution is likely to shift or spread due to repeated use, the refresh processing can be reserved at an appropriate time before the number of error bits exceeds the error correction capability of the soft decision decoding of the ECC circuit 34. Therefore, it is possible to suppress the deterioration of data reliability.

[0213] 5. Modification

[0214] The first to fourth embodiments are not limited to the examples described above, and can be modified in various ways.

[0215] For example, in the first to fourth embodiments described above, in the update processing of the temperature management information 21, the memory controller 30 acquires the temperature measured by the temperature sensor 15 in the NAND flash memory 10; however, the embodiments are not limited to this example. The memory controller 30 can acquire the temperature from outside of the NAND flash memory 10, for example. For example, the temperature can be acquired by an analog-digital converter (ADC) or the like within the memory controller 30. In this case, the memory controller 30 can estimate the temperature in the NAND flash memory 10 (particularly, in the memory cell array 17) by appropriately correcting the acquired temperature, and execute the update processing of the temperature management information 21 based on the estimated temperature.

[0216] Furthermore, in the first to fourth embodiments described above, the temperature management unit is four unit units (CUs) commonly connected to word lines WL; however, these embodiments are not limited to this example. For example, the temperature management unit may be three or fewer unit units (CUs), or it may be five or more unit units (CUs) associated with multiple word lines WL. Five or more unit units (CUs) associated with word lines WL are also referred to as a word line group. Alternatively, for example, the temperature management unit may be a block BLK or multiple block BLKs. If the temperature management unit is multiple block BLKs, the block BLKs contained in the same temperature management unit may belong to different chips. Furthermore, if the temperature management unit is multiple block BLKs, the block BLKs contained in the same temperature management unit may belong to different planes PB within the same chip.

[0217] Multiple block BLKs serving as temperature management units can be logic block BLKs. A logic block can include multiple block BLKs on multiple chips and includes error correction frames constituting inter-block parity checking. A set of corresponding word lines (WLs) within the chip constituting the logic block are also called logic word lines. A temperature management unit can be multiple unit units (CUs) associated with logic word lines. Alternatively, a temperature management unit can be multiple unit units (CUs) associated with multiple logic word lines. A set of multiple unit units (CUs) associated with multiple logic word lines (WLs) is also called a logic word line group.

[0218] The memory controller 30 can change the temperature management unit to various sizes as described above. Therefore, the required storage capacity and refresh processing reservation unit of the temperature management information 21 can be appropriately adjusted according to the state of the NAND flash memory 10.

[0219] The third and fourth embodiments are described as being applied to the second embodiment, but they can also be applied to the first embodiment. If the fourth embodiment is applied to the first embodiment, then in Figure 17 In steps ST74 and ST75 shown, the memory controller 30 can change the threshold used for comparing with the temperature during refresh processing determination based on the degree of wear. Specifically, if the degree of wear is below the threshold WEth, the memory controller 30 determines whether the temperature during refresh processing determination is equal to or higher than the threshold Tth2. If the degree of wear is equal to or higher than the threshold WEth, the memory controller 30 determines whether the temperature during refresh processing determination is equal to or higher than the threshold Tth5, where the threshold Tth5 is lower than the threshold Tth2 (i.e., Tth5...). <Tth2)。

[0220] Alternatively, for example, in ​In steps ST74 and ST75, the memory controller 30 can change the threshold value used for comparison with the temperature at the time of the write processing according to the degree of wear. Specifically, if the degree of wear is lower than the threshold WEth, the memory controller 30 determines whether the temperature at the time of the write processing is equal to or lower than the threshold Tthl. If the degree of wear is equal to or higher than the threshold WEth, the memory controller 30 determines whether the temperature at the time of the write processing is equal to or lower than the threshold Tth6, which is higher than the threshold Tthl (i.e., Tth6 > Tthl).

[0221] Further, in the first to fourth embodiments described above, the temperature management information 21 and the refresh reservation information 22 are stored in the DRAM 20; however, the embodiments are not limited thereto. For example, the temperature management information 21 and the refresh reservation information 22 can be stored in the NAND flash 10 in a nonvolatile manner as appropriate, to avoid a situation where information is lost from the memory system 1 due to unexpected power-off.

[0222] In the first to fourth embodiments, 2-bit data can be stored in a single memory cell transistor MT; however, the embodiments are not limited thereto, and can be configured to store 3-bit data, 4-bit data, or 5-bit data or more.

[0223] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the protection sought. Indeed, the embodiments described herein can be embodied in a multitude of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein can be made without departing from the spirit of the application. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the application.

[0224] REFERENCE NUMERALS

[0225] 1: Memory system

[0226] 2: External host device

[0227] 10: Nonvolatile memory

[0228] 11: Input / output circuit

[0229] 12: Register set

[0230] 12A: Status register

[0231] 12B: Address register

[0232] 12C: Command register

[0233] 13: Logic controller

[0234] 14: sequencer

[0235] 15: temperature sensor

[0236] 16: voltage generation circuit

[0237] 17: memory cell array

[0238] 18: row decode module

[0239] 19: sense amplifier module

[0240] 20: volatile memory

[0241] 21: temperature management information

[0242] 22: refresh reservation information

[0243] 30: memory controller

[0244] 31: processor (CPU)

[0245] 32: buffer memory

[0246] 33: host interface circuit

[0247] 34: error checking and correction (ECC) circuit

[0248] 35: NAND interface circuit

[0249] 36: DRAM interface circuit

Claims

1. A memory system, comprising: The non-volatile memory includes multiple groups, each of the multiple groups including multiple memory cells, and the multiple groups include at least a first group; as well as The memory controller determines to perform a refresh process on the first group when a first temperature during the write process of the first group is equal to or lower than a first threshold, and a second temperature after the write process of the first group is equal to or higher than a second threshold, wherein the second threshold is higher than the first threshold.

2. The memory system according to claim 1, wherein: When the wear level of the first group is equal to or higher than the third threshold, the memory controller reduces the second threshold.

3. The memory system according to claim 2, wherein: The wear level of the first group is relative to the number of write and erase cycles of the first group.

4. The memory system according to claim 1, wherein, When the wear level of the first group is equal to or higher than the third threshold, the memory controller increases the first threshold.

5. The memory system according to claim 4, wherein: The wear level of the first group is relative to the number of write and erase cycles of the first group.

6. The memory system according to claim 1, wherein: The non-volatile memory comprises multiple blocks, each of the multiple blocks comprising the multiple groups; and Each of the plurality of blocks is a unit used for the erasure process.

7. The memory system according to claim 1, wherein: Each of the multiple groups is a unit used for the erasure process.

8. A memory system, comprising: The non-volatile memory includes multiple groups, each of the multiple groups including multiple memory cells, and the multiple groups include at least a first group; as well as The memory controller determines to perform refresh processing on the first group when the difference between the second temperature after the write processing of the first group and the first temperature during the write processing of the first group is equal to or greater than a first threshold.

9. The memory system according to claim 8, wherein: When the wear level of the first group is equal to or higher than the second threshold, the memory controller reduces the first threshold.

10. The memory system according to claim 9, wherein: The wear level of the first group is relative to the number of write and erase cycles of the first group.

11. A memory system, comprising: The non-volatile memory includes multiple groups, each of the multiple groups including multiple memory cells, and the multiple groups include at least a first group; as well as The memory controller determines whether to perform a refresh process on the first group if the number of bits written in each of the plurality of memory cells in the first group is greater than or equal to a first threshold, based on a first temperature during the write process of the first group and a second temperature after the write process of the first group. If the number of bits written in each of the plurality of storage cells in the first group is less than the first threshold, then regardless of the first temperature or the second temperature, the memory controller determines that the refresh process will not be performed on the first group.

12. The memory system according to claim 11, wherein: If the address of the first group is within a certain range, the memory controller determines whether to perform the refresh process on the first group based on the first temperature and the second temperature. If the address of the first group exceeds the certain range, the memory controller determines that it will not perform the refresh process on the first group, regardless of the first temperature or the second temperature.

13. The memory system according to claim 11, wherein: If the frequency of reading data written to the first group is higher than or equal to the third threshold when the second temperature is equal to or higher than the second threshold, the memory controller determines whether to perform the refresh process on the first group based on the first temperature and the second temperature. If the frequency is lower than the third threshold, the memory controller determines that it will not perform the refresh process on the first group, regardless of the first temperature or the second temperature.

14. The memory system of claim 11, wherein: If the purpose of the first group is to store system data, then regardless of the first temperature or the second temperature, the memory controller determines that the refresh process will not be performed on the first group.

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