Semiconductor memory device and method of controlling the same

Abstract

Embodiments provide a highly reliable semiconductor memory device and a control method thereof. The semiconductor memory device of the embodiments includes a plurality of memory cells. A first node holds first data read out from a first memory cell among the plurality of memory cells. A second node holds second data read out from a second memory cell near the first memory cell among the plurality of memory cells. A difference circuit has a first current path through which a first current corresponding to a voltage of the first node flows, a second current path through which a second current corresponding to a voltage of the second node flows, and outputs an output signal corresponding to a voltage difference between the first node and the second node from an output section. A first register latches the output signal and outputs the same as a hold signal. A first offset section is connected to the first current path and offsets the first current when the hold signal is a first logic. A second offset section is connected to the second current path and offsets the second current when the hold signal is a second logic opposite to the first logic.

Description

[0001] Related Applications

[0002] This application claims priority to Japanese Patent Application No. 2020-157775 (Filing date: September 18, 2020). This application incorporates the entire contents of the base application by reference thereto. TECHNICAL FIELD

[0003] The present embodiment relates to a semiconductor storage device and a control method thereof. BACKGROUND

[0004] There is a case where MRAM (Magnetoresistive Random Access Memory) has a stacked type memory cell array in which memory cells are provided corresponding to intersections of bit lines and word lines. In the case of the stacked type, the wiring resistance or the characteristics of the memory cells differ depending on the positions of the memory cells, and if data is read out by the same reference voltage, there is a concern that the logic of the data detected is erroneous. In response to this, there is proposed a method of adjusting the reference voltage depending on the position of the memory cell, or a self-reference method. SUMMARY

[0005] The present application is to provide a semiconductor storage device and a control method thereof with high reliability.

[0006] The semiconductor storage device of the present embodiment has a plurality of memory cells. A first node holds first data read out from a first memory cell among the plurality of memory cells. A second node holds second data read out from a second memory cell near the first memory cell among the plurality of memory cells. A difference circuit has a first current path through which a first current corresponding to the voltage of the first node flows and a second current path through which a second current corresponding to the voltage of the second node flows, and outputs an output signal corresponding to the voltage difference between the first node and the second node from an output section. A first register latches the output signal and outputs it as a hold signal. A first offset section is connected to the first current path and offsets the first current when the hold signal is a first logic. A second offset section is connected to the second current path and offsets the second current when the hold signal is a second logic opposite to the first logic. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a block diagram showing a configuration example of the semiconductor storage device of the first embodiment.

[0008] Figure 2 is a circuit diagram showing a configuration example of a memory cell array.

[0009] Figure 3 is an explanatory diagram of a memory cell.

[0010] Figure 4 is a block diagram showing a configuration example of a sensing circuit in the sense amplifier / write driver of the first embodiment.

[0011] Figure 5 is a circuit diagram showing a configuration example of the preamplifier.

[0012] Figure 6 is a circuit diagram showing a configuration example of the sense amplifier.

[0013] Figure 7 is a timing chart showing one example of the readout operation of the preamplifier and the sense amplifier of the first embodiment.

[0014] Figure 8 (A) to (C) are conceptual diagrams showing one example of the readout operation.

[0015] Figure 9 (A) to (C) are conceptual diagrams showing one example of the readout operation.

[0016] Figure 10 (A) to (D) are conceptual diagrams showing the readout sequence of the memory cell.

[0017] Figure 11 (A) to (C) are conceptual diagrams showing another example of the readout operation.

[0018] Figure 12 (A) to (C) are conceptual diagrams showing another example of the readout operation.

[0019] Figure 13 is a timing chart showing one example of the readout operation of the preamplifier and the sense amplifier of the second embodiment.

[0020] Figure 14 is a circuit diagram showing a configuration example of the preamplifier of the third embodiment.

[0021] Figure 15 is a circuit diagram showing a configuration example of the sense amplifier of the third embodiment.

[0022] Figure 16 is a timing chart showing one example of the readout operation of the preamplifier and the sense amplifier of the third embodiment. DETAILED DESCRIPTION

[0023] Embodiments of the present application will be described below with reference to the accompanying drawings. The present embodiments are not intended to limit the present application. The accompanying drawings are schematic or conceptual drawings, and the proportions of the parts and the like are not necessarily the same as in reality. In the specification and the drawings, the same reference signs are assigned to the same elements described in the drawings, and detailed description will be appropriately omitted.

[0024] (First Embodiment)

[0025] Figure 1 is a block diagram showing a configuration example of a semiconductor storage device of the first embodiment. Figure 2 is a circuit diagram showing a configuration example of a memory cell array. The semiconductor storage device is not particularly limited, but can be a memory such as an MRAM (Magnetoresistive Random Access Memory), a ReRAM (Resistive Random Access Memory), or the like. In the following embodiments, a memory system 1 as the semiconductor storage device is described as an MRAM.

[0026] The memory system 1 as the semiconductor storage device includes a memory device 10 and a memory controller 20.

[0027] The memory controller 20 receives a command from a host (external machine) 2 such as a personal computer, reads out data from the memory device 10, or writes data to the memory device 10. The memory controller 20 includes a host interface 21, a data buffer 22, a register 23, a CPU (Central Processing Unit) 24, a device interface 25, and an ECC (Error Correcting Code) circuit 26.

[0028] The host interface 21 is connected to the host 2. Through the host interface 21, data transmission and reception and the like are performed between the host 2 and the memory system 1.

[0029] The data buffer 22 is connected to the host interface 21. The data buffer 22 receives data transmitted from the host 2 to the memory system 1 through the host interface 21, and temporarily stores the data. In addition, the data buffer 22 temporarily stores data transmitted from the memory system 1 to the host 2 through the host interface 21. The data buffer 22 can be a volatile memory, or can be a non-volatile memory.

[0030] The register 23 is, for example, a volatile memory, and stores setting information, instructions, and states, and the like executed by the CPU 24. The register 23 can be a volatile memory, or can be a non-volatile memory.

[0031] The CPU 24 is responsible for the overall operation of the memory system 1. The CPU 24 performs a specific process on the memory device 10, for example, in accordance with an instruction received from the host 2.

[0032] The device interface 25 performs transmission and reception of various signals and the like between the memory controller 20 and the memory device 10.

[0033] ECC circuit 26 receives write data from host 2 via data buffer 22. ECC circuit 26 appends error correction codes to the write data. ECC circuit 26 supplies the write data with the appended error correction codes to, for example, data buffer 22 or device interface 25.

[0034] Furthermore, the ECC circuit 26 receives data supplied from the memory device 10 via the device interface 25. This data is stored in the memory cells of the memory cell array 11. The ECC circuit 26 determines whether there are errors in the data received from the memory device 10. If the ECC circuit 26 determines that the received data contains errors, it performs error correction processing on the received data using an error correction code. Then, the ECC circuit 26 supplies the error-corrected data to, for example, a data buffer 22, the device interface 25, etc.

[0035] The memory device 10 includes a memory cell array 11, a sense amplifier / write driver 12, a column decoder 13, a word line driver 14, a row decoder 15, an I / O circuit 16, a controller 17, and an instruction address input circuit 18.

[0036] The memory controller 20 inputs various external control signals to the instruction address input circuit 18, such as the chip select signal CS, clock signal CK, clock start signal CKE, and instruction address signal CA. The instruction address input circuit 18 then transmits the instruction address signal CA to the controller 17.

[0037] Controller 17 identifies instructions and addresses. Controller 17 controls memory device 10.

[0038] Storage cell array 11, such as Figure 2 As shown, for example, an MRAM may have multiple memory cells MC arranged in two or three dimensions. Each memory cell MC may be, for example, a magnetoresistive variable memory cell or a resistive variable memory cell. In an embodiment, each magnetoresistive variable memory cell MC includes an MTJ (Magnetic Tunnel Junction) element 30 and a selection transistor 31 as a storage element. The MTJ element 30 is a magnetic tunnel junction element that stores data based on changes in resistance and can rewrite data using current. The selection transistor 31 is configured to correspond to the MTJ element 30, such that it becomes conductive when current flows in the corresponding MTJ element 30. Alternatively, the MTJ element may also be referred to as a resistive variable element or a magnetoresistive variable element.

[0039] like Figure 2As shown, a plurality of word lines WL extend in the row direction, and a plurality of bit lines BL extend in the column direction. The word lines WL and the bit lines BL are routed in a manner of crossing each other. Adjacent bit lines BL are paired with the source lines SL, and the memory cells MC are provided corresponding to the intersections of the word lines WL and the bit lines BL or the source lines SL. The MTJ element 30 and the selection transistor 31 of each memory cell MC are connected in series between the bit line BL and the source line SL. The gate of the selection transistor 31 is connected to the word line WL.

[0040] The word line driver 14 is arranged at least along one side of the memory cell array 11. Further, the word line driver 14 is configured to apply a voltage to the word line WL at the time of data readout or data write.

[0041] The row decoder 15 decodes the address of the command address signal CA supplied from the command address input circuit 18. More specifically, the row decoder 15 supplies the decoded row address to the word line driver 14. Thereby, the word line driver 14 can apply a voltage to the selected word line WL.

[0042] The column decoder 13 decodes the address of the command address signal CA supplied from the command address input circuit 18. The column decoder 13 supplies the decoded column address to the sense amplifier / write driver 12.

[0043] The sense amplifier / write driver 12 is provided with a sense amplifier and a write driver. The sense amplifier / write driver 12 is arranged at least along one side of the memory cell array 11. The sense amplifier is connected to the bit line BL via the global bit line GBL, and reads out the data stored in the memory cell MC by detecting the current flowing in the memory cell MC connected to the selected word line WL. The write driver is connected to the bit line BL via the global bit line GBL, or connected to the source line SL via the global source line GSL. Also, the write driver causes the current to flow in the selected memory cell MC connected to the selected word line WL at the time of writing data to the selected memory cell MC.

[0044] Further, the sense amplifier / write driver 12 is provided with a page buffer not shown. The page buffer is, for example, a volatile memory, and stores the data read out by the sense amplifier, or the write data transferred via the IO circuit 16.

[0045] The data reception and transmission between the sense amplifier / write driver 12 and the data line DQ is performed via the IO circuit 16.

[0046] As Figure 2As shown, the memory cell array 11 includes a plurality of memory cells MC arranged in two dimensions or three dimensions. The memory cell array 11 has a plurality of word lines WL0 to WLi-1 (i is an integer of one or more), a plurality of bit lines BL0 to BLj-1, and a plurality of source lines SL0 to SLj-1 (j is an integer of one or more). The memory cells MC are arranged corresponding to the intersections of the word lines WL and the bit lines BL or the source lines SL. That is, the memory cell array 11 is a laminated memory cell array.

[0047] The memory cell MC is composed of an MTJ element 30 and a selection transistor 31. The selection transistor 31 is composed of, for example, an N-type MOSFET (Metal Oxide Silicon Field Effect Transistor).

[0048] One end of the MTJ element 30 is connected to the bit line BL, and the other end is connected to the drain of the selection transistor 31. The gate of the selection transistor 31 is connected to the word line WL, and the source is connected to the source line SL.

[0049] Figure 3 is an explanatory view of the memory cell MC.

[0050] The MTJ element 30 utilizing the TMR (Tunneling Magnetoresistance) effect has a laminated structure including two ferromagnetic layers F, P and a non-magnetic layer (tunnel insulating film) B interposed between these layers, and stores digital data by utilizing the change in magnetic resistance by the spin polarized tunneling effect. The MTJ element 30 can take a low resistance state and a high resistance state by the magnetization arrangement of the two ferromagnetic layers F, P. For example, if the low resistance state is defined as "0" data and the high resistance state is defined as "1" data, one bit of data can be recorded in the MTJ element 30. Of course, the low resistance state can be defined as "1" data and the high resistance state can be defined as "0" data.

[0051] For example, the MTJ element 30 is composed of a fixed layer (pinned layer) P, a tunnel barrier layer B, and a recording layer (free layer) F, which are laminated in this order. The pinned layer P is a layer in which the direction of the magnetization arrangement is fixed, and the free layer F is a layer in which the direction of the magnetization arrangement is variable, and data is stored according to the direction of the magnetization. The pinned layer P and the free layer F are composed of a ferromagnetic substance, and the tunnel barrier layer B is composed of an insulating film.

[0052] The free layer F can also use, for example, cobalt iron boron (CoFeB) or iron boride (FeB). The pinned layer P can also use, for example, cobalt platinum (CoPt), cobalt nickel (CoNi), or cobalt palladium (CoPd). The tunnel barrier layer B includes a non-magnetic material, and a non-magnetic metal, a non-magnetic semiconductor, an insulator, or the like can be used. The tunnel barrier layer B can also use, for example, magnesium oxide (MgO) or aluminum oxide (Al2O3) or the like.

[0053] If the current flows in the direction of arrow Al at the time of writing, the magnetization direction of the free layer F becomes an anti-parallel state (AP state) with respect to the magnetization direction of the pinned layer P, and becomes a high resistance state ("1" data). This writing operation can also be set as a "1" writing operation. If the current flows in the direction of arrow A2 at the time of writing, the magnetization direction of each of the pinned layer P and the free layer F becomes a parallel state (P state), and becomes a low resistance state ("0" data). This writing operation can also be set as a "0" writing operation. In this way, the MTJ element can write different data by the direction of the current flow.

[0054] Figure 4 is a block diagram showing a configuration example of a sensing circuit 100 in the sense amplifier / writing driver 12 of the first embodiment.

[0055] The sensing circuit 100 is provided for each bit line (global bit line). Each sensing circuit 100 is provided with a preamplifier 110 and a sense amplifier (SA) 120. The preamplifier 110 supplies a current (cell current) to the memory cell MC via the bit line, and stores voltages V1st and V2nd based on the cell current. The sense amplifier 120 determines data (D0, DOB) based on the voltages V1st and V2nd stored in the preamplifier 110.

[0056] Figure 5 is a circuit diagram showing a configuration example of the preamplifier 110.

[0057] The preamplifier 110 is provided with PMOS (Positive Channel Metal Oxide Semiconductor) transistors M29, M30, M31, M34, NMOS (N-Metal-Oxide-Semiconductor) transistors M6, M7, M32, M33, M35, and capacitors C3, C4.

[0058] One end of the transistor M29 is applied with a power supply voltage VDD, and the other end and the gate electrode are connected to a node N15. One end of the transistor M30 is applied with the power supply voltage VDD, and the other end is connected to a node N16, and the gate electrode is connected to the node N15. The transistors M29, M30 constitute a current mirror circuit.

[0059] One end of the transistor M6 is connected to the node N15, the other end is connected to the node N4, and the gate electrode receives a signal Vclamp.

[0060] One end of the transistor M7 is connected to the node N4, the other end is connected to the bit line (global bit line), and the gate electrode receives a read enable signal REN.

[0061] One end of the transistors M31, M32 is connected to the node N16, the other end is connected to the node N17. The gate electrodes of the transistors M31, M32 receive signals SW1B, SW1P, respectively. The transistors M31, M32 function as a CMOS (Complementary MOS) switch. The transistors M31, M32 are also referred to as switches M31, M32.

[0062] One end of the transistor M33 is connected to the node N16, the other end is applied with a ground voltage VSS, and the gate electrode is connected to the node N17.

[0063] One end of the capacitor C3 is connected to the node N17, the other end is connected to the ground voltage source VSS.

[0064] One end of the transistors M34, M35 is connected to the node N16, the other end is connected to the node N18. The gate electrodes of the transistors M34, M35 receive signals SW2B, SW2P, respectively. The transistors M34, M35 function as a CMOS switch. The transistors M34, M35 are also referred to as switches M34, M35.

[0065] One end of the capacitor C4 is connected to the node N18, the other end is connected to the ground voltage source VSS.

[0066] The voltage of the node N17 is supplied to the sense amplifier 120 as V1st. The voltage V1st is transferred to the capacitor C3 via the switches M31, M32. The capacitor C3 can hold the voltage of the node N17 as the voltage V1st. The voltage of the node N18 is supplied to the sense amplifier 120 as V2nd. The voltage V2nd is transferred to the capacitor C4 via the switches M34, M35. The capacitor C4 can hold the voltage of the node N18 as the voltage V2nd.

[0067] Figure 6 is a circuit diagram showing a configuration example of the sense amplifier 120.

[0068] The sensing amplifier 120 includes PMOS transistors M8, M9, M10, M11, M12, M13, NMOS transistors M14, M15, M16, M17, M18, M19, M20, M21, M22, M23, M24, and M25. The sensing amplifier 120 further includes a register REG1 and inverters INV1 and INV2.

[0069] One end of the transistor M8 is supplied with a power supply voltage VDD, the other end is connected to a node N5, and the gate electrode receives a signal LATPB.

[0070] One end of the transistor M9 is connected to the node N5, the other end is connected to a node N6, and the gate electrode is connected to a node N7. The transistor M9 as the first transistor is provided in the current path CP1, and the gate is connected to the node N7 of the current path CP2.

[0071] One end of the transistor M10 is connected to the node N5, the other end is connected to the node N7, and the gate electrode is connected to the node N6. The transistor M10 as the second transistor is provided in the current path CP2, and the gate is connected to the node N6 of the current path CP1.

[0072] One end of the transistor M11 is connected to the node N6, the other end is connected to the node N7, and the gate electrode receives a signal SEN.

[0073] One end of the transistor M12 is supplied with a power supply voltage VDD, the other end is connected to the node N6, and the gate electrode receives the signal SEN.

[0074] One end of the transistor M13 is supplied with a power supply voltage VDD, the other end is connected to the node N7, and the gate electrode receives the signal SEN.

[0075] One end of the transistor M14 is connected to the node N6, the other end is connected to a node N8, and the gate electrode is connected to the node N7. The transistor M14 as the first transistor is provided in the current path CP1, and the gate is connected to the node N7 of the current path CP2.

[0076] One end of the transistor M15 is connected to the node N8, the other end is connected to a node N11, and the gate electrode receives a signal SEN2 via a node N10.

[0077] One end of the transistor M16 is connected to the node N8, the other end is supplied with a ground voltage VSS, and the gate electrode receives a signal LATN.

[0078] One end of the transistor M17 is connected to the node N7, the other end is connected to a node N9, and the gate electrode is connected to the node N6. The transistor M17 as the second transistor is provided in the current path CP2, and the gate is connected to the node N6 of the current path CP1.

[0079] One end of the transistor M18 is connected to the node N9, the other end is connected to the node N13, and the gate electrode receives the signal SEN2 via the node N10.

[0080] One end of the transistor M19 is connected to the node N9, the other end is applied with the ground voltage VSS, and the gate electrode receives the signal LATN.

[0081] One end of the transistor M20 is connected to the node N11, the other end is applied with the ground voltage VSS, and the gate electrode receives the signal V1st.

[0082] One end of the transistor M21 is connected to the node N11, the other end is connected to the node N12, and the gate electrode receives the signal SHFTDO.

[0083] One end of the transistor M22 is connected to the node N12, the other end is applied with the ground voltage VSS, and the gate electrode receives the shift voltage VSHFT1.

[0084] One end of the transistor M23 is connected to the node N13, the other end is applied with the ground voltage VSS, and the gate electrode receives the signal V2nd.

[0085] One end of the transistor M24 is connected to the node N13, the other end is connected to the node N14, and the gate electrode receives the signal SHFTDOB.

[0086] One end of the transistor M25 is connected to the node N14, the other end is applied with the ground voltage VSS, and the gate electrode receives the shift voltage VSHFT2.

[0087] In this sense amplifier 120, the transistors M9, M14, M15, M20 constitute a current path CP1. The transistors M10, M17, M18, M23 constitute a current path CP2. The gates of the transistors M9, M14 of the current path CP1 are commonly connected to the node N7 of the current path CP2, and the gates of the transistors M10, M17 of the current path CP2 are commonly connected to the node 6 of the current path CP1. The node N6 is a node between the transistors M9 and M14, and the node N7 is a node between the transistors M10 and M17. That is, the gates of the transistors M9, M14 and the gates of the transistors M10, M17 are cross-coupled. Thus, the sense amplifier 120 can function as a differential amplification circuit. The current path CP1 flows a current I1st corresponding to the voltage V1st of the node N17. The current path CP2 flows a current I2nd corresponding to the voltage V2nd of the node N18. The sense amplifier 120 outputs an output signal DO corresponding to the voltage difference between the node N17 and the node N18 from the output section. In addition, when the sense amplifier 120 functions as a differential amplification circuit, the signal SEN is at a high level, and the transistors M11 to M13 need to be turned off.

[0088] The transistors M21 and M22 constitute an offset section OFS1 connected to the current path CP1. The offset section OFS1 branches from the node N11 between the transistors M15 and M20, and can flow an offset current Iofs1 in accordance with a shift voltage (first shift voltage) VSHFT1. The transistor M22 as a first offset transistor flows the offset current Iofs1 when the shift voltage VSHFT1 is applied to the gate. Further, in the offset section OFS1, the transistor M22 can flow the offset current Iofs1 when the transistor M21 is on.

[0089] The transistors M24 and M25 constitute an offset section OFS2 connected to the current path CP2. The offset section OFS2 branches from the node N13 between the transistors M18 and M23, and can flow an offset current Iofs2 in accordance with a shift voltage (second shift voltage) VSHFT2. The transistor M25 as a second offset transistor flows the offset current Iofs2 when the shift voltage VSHFT2 is applied to the gate. Further, in the offset section OFS2, the transistor M25 can flow the offset current Iofs2 when the transistor M24 is on.

[0090] The shift voltages VSHFT1 and VSHFT2 control the on states of the transistors M22 and M25 in such a manner that a specific offset current Iofs1 or Iofs2 flows in the transistor M22 or M25. If the transistor M22 flows the offset current Iofs1, the current I1st flowing in the current path CP1 increases by the offset current Iofs1. That is, the current flowing in the current path CP1 is I1st + Iofs1. This means that it appears as if the voltage V1st is shifted to the high voltage side. On the other hand, if the transistor M25 flows the offset current Iofs2, the current I2nd flowing in the current path CP2 increases by the offset current Iofs2. That is, the current flowing in the current path CP2 is I2nd + Iofs2. This means that it appears as if the voltage V2nd is shifted to the high voltage side. That is, by flowing the offset current Iofs1, it can be regarded that the voltage V1st is raised by an offset voltage Vofs1 corresponding to the offset current Iofs1. By flowing the offset current Iofs2, it can be regarded that the voltage V2nd is raised by an offset voltage Vofs2 corresponding to the offset current Iofs2.

[0091] The shift amounts of the voltages V1st and V2nd corresponding to the offset currents Iofs1 and Iofs2 are called the offset voltages Vofs1 and Vofs2. The offset current Iofs1 is any current (e.g., approximately intermediate current) between the current flowing in current path CP1 when data is "0" and the current flowing in current path CP1 when data is "1". The offset current Iofs2 is any current (e.g., approximately intermediate current) between the current flowing in current path CP2 when data is "0" and the current flowing in current path CP2 when data is "1". The offset voltage Vofs1 can be node N17 when data is "0" (see reference). Figure 5 The shift voltage VSHFT1 and VSHFT2 are any voltage (approximately intermediate) between the voltage V1st of node N18 when data is "0" and the voltage V1st of node N17 when data is "1". The offset voltage Vofs2 can be any voltage (approximately intermediate) between the voltage V2nd of node N18 when data is "0" and the voltage V2nd of node N18 when data is "1". The shift voltages VSHFT1 and VSHFT2 are set as follows: the shift currents Iofs1 and Iofs2 flowing through transistors M22 and M25 shift the voltages V1st and V2nd to the offset voltages Vofs1 and Vofs2. The offset voltages Vofs1 and Vofs2 are both approximately intermediate voltages between data "0" and data "1", or they can be approximately equal to each other. In addition, the shift voltage VSHFT1 can also be the gate voltage, which makes the current flowing in the current path CP1 when data is "0" in transistor M22 less than (for example, approximately half the current) the difference between the current flowing in the current path CP1 when data is "0" and the current flowing in the current path CP1 when data is "1". The offset voltage Vofs2 can also be a voltage such that the difference between the current flowing in the current path CP2 when data "0" flows in transistor M25 and the current flowing in the current path CP2 when data "1" flows is less than (for example, approximately half the current).

[0092] In the sense amplifier 120, at nodes N6 and N7, a voltage difference is generated by the currents I1st (or I1st + Iofs1) and I2nd (or I2nd + Iofs2) flowing through current paths CP1 and CP2. This voltage difference between nodes N6 and N7 is significantly amplified by the cross-coupled transistors M9 and M14, and transistors M10 and M17. Therefore, the voltage difference between nodes N6 and N7 becomes a voltage difference between mutually complementary logic levels. The voltage at node N6 is used as the output signal DO and supplied to... Figure 1 The IO circuit 16. The voltage at node N7 is used as the inverted output signal DOB of the output signal DO, and supplied to... Figure 1 The I / O circuit 16. In addition, the output signal DO is input to register REG1, and it is latched in register REG1 during the timing of the latch signal DLAT.

[0093] The register REG1 as the 1st register has an input portion connected to the node N6, an output portion connected to the inverter INV1, and a clock input portion inputting the latch signal DLAT. The register REG1 latches the output signal DO at the timing when the latch signal DLAT rises to the high level, for example, and outputs it as the hold signal DO_PREV.

[0094] The inverter INV1 is connected between the register REG1 and the gate of the transistor M21. The inverter INV1 gives the gate of the transistor M21 the shift signal SHFTDO which inverts the hold signal DO_PREV from the register REG1.

[0095] The inverter INV2 is connected between the output of the inverter INV1 and the gate of the transistor M24. The inverter INV2 gives the gate of the transistor M24 the shift signal SHFTDOB which inverts the shift signal SHFTDO from the inverter INV1.

[0096] Thus, either the transistor M21 or M24 is on and the other is off by the hold signal DO_PREV latched by the register REG1. When the transistor M21 is on, the shift current flows in the current path CP1. In this case, as described above, it is equivalent to raising the voltage V1st by the shift voltage Vofs. When the transistor M24 is on, the shift current flows in the current path CP2. In this case, it is equivalent to raising the voltage V2nd by the shift voltage Vofs. Since the shift voltage Vofs is the voltage approximately intermediate between the data "0" and the data "1", by shifting the voltage V1st or V2nd by the shift voltage Vofs, it is possible to set the voltage V1st or V2nd to the voltage approximately intermediate between the data "0" and the data "1". Alternatively, it is possible to shift either of the voltages V1st or V2nd at approximately the same level to the high voltage side. Thus, after shifting by the shift voltage Vofs, it is possible to use one of the voltages V1st, V2nd as a reference voltage and detect the other voltage.

[0097] For example, the data detected by a certain readout operation is held as the voltage V1st at the node N17, and the data detected by the next readout operation is held as the voltage V2nd at the node N18. At this point in time, the voltage V1st is output as the hold signal DO_PREV, and according to the voltage level of the voltage V1st, either of the shift currents Iofsl or Iofs2 flows in one of the shift portions OFSl, OFS2.

[0098] When the voltage V1st is at the low level and the hold signal DO_PREV is at the low level, the transistor M21 is turned on, and the offset section OFS1 flows the offset current Iofs1 in the current path CP1. On the other hand, when the voltage V1st is at the high level and the hold signal DO_PREV is at the high level, the transistor M24 is turned on, and the offset section OFS2 flows the offset current Iofs2 in the current path CP2.

[0099] Thus, the sense amplifier 120 raises either of the voltage V1st or the voltage V2nd by the offset voltage Vofs based on the logic (voltage level of the voltage V1st) of the previous read data. Thereby, the sense amplifier 120 can detect the present read data (voltage V2nd) using the previous read data (voltage V1st) as a reference signal.

[0100] Hereinafter, the read operation of the preamplifier 110 and the sense amplifier 120 according to the present embodiment will be described in more detail.

[0101] Figure 7 is a timing chart showing one example of the read operation of the preamplifier 110 and the sense amplifier 120. Figure 8 (A) ~ Figure 9 (C) is a conceptual diagram showing one example of the read operation.

[0102] In the read operation, the signal Vclamp is maintained at the high level, the signal LATPB is maintained at the low level, the signal SW2P is maintained at the high level, and the signal SW2B is maintained at the low level. Therefore, in the read operation, the transistor M6, the switches M34, M35 of the preamplifier 110, and the transistor M8 of the sense amplifier 120 are maintained in the on state (turned on). The shift voltages VSHFT1, VSHFT2 are maintained at specific voltages in such a manner that the transistors M22, M25 can flow the specific offset currents Iofs1, Iofs2. Therefore, the transistors M21, M24 are turned off, and the offset sections OFS1, OFS2 do not flow the offset currents Iofs1, Iofs2. Figure 7 In the read operation, the timing charts of these signals are omitted.

[0103] In the initial state before t1, the signal SW1P is at the low level, and the signal SW1B is at the high level. In addition, the signals REN, SEN, SEN2, and LATN are at the low level. The transistor M7, the switches M31, M32 of the preamplifier 110 are changed to the off state (turned off). The transistors M11 to M13 of the sense amplifier 120 are turned on, and the transistors M15, M16, M18, and M19 are turned off.

[0104] Since the transistors M11 to M13 are turned on in the initial state, the nodes N6, N7 are charged to the high level, and the output signal DO of the initial state is at the high level. In addition, the transistors M14, M17 are turned on, but the transistors M9, M10 are turned off.

[0105] The register REG1 latches a high level as the holding signal DO_PREV of the initial state. In this case, the transistor M21 is off, and the transistor M24 is on. In addition, since the transistors M15 and M18 are off in the initial state before tl, the offset currents Iofsl and Iofsl do not flow in the sense amplifier 120. Further, the output signal DO of the initial state is set by reading out a specific initial memory cell storing existing data. The initial memory cell is the first reading target. At this time, the position of the initial memory cell is determined, and the initial memory cell stores the existing initial data (for example, data "1"). Therefore, the data of the initial memory cell can be read out in a self-reference manner, or can be read out using a reference signal suitable for the initial memory cell. Of course, the output signal DO of the initial state and the holding signal DO_PREV can also be low levels.

[0106] Hereinafter, the reading operation is performed in the order of the memory cells MC1 to MC4.

[0107] (Reading operation of the memory cell MC1)

[0108] First, the data of the memory cell MC1 is read out. At tl, when the read enable signal REN rises to a high level, the transistor M7 is on, and a memory current corresponding to the data (resistance) of the memory cell MC1 flows in the current path of the transistors M29, M6, and M7. Further, the transistors M29 and M30 function as a current mirror, and a mirror current corresponding to the memory current flows in the current path of the transistors M30 and M33. At this time, the switches M31 and M32 are off, and the switches M34 and M35 are on. Therefore, the voltage of the node N16 is output as the voltage V2nd to the sense amplifier 120 of the memory cell MC2, and is accumulated in the capacitor C4. Thus, the voltage Vlst remains unchanged (for example, VO), and the voltage V2nd changes to the voltage VI corresponding to the data of the memory cell MC1. For example, in the case where the memory cell MC1 has a low resistance, since the memory current and the mirror current become large, the voltage V2nd becomes a high level higher than the voltage Vlst. In the case where the memory cell MC1 has a high resistance, since the memory current and the mirror current become small, the voltage V2nd becomes a low level lower than the voltage Vlst. Figure 6

[0109] Next, at t2, the signal SEN2 of the sense amplifier 120 is raised to a high level, and the transistors M15 and M18 are turned on.

[0110] ​Next, at t3, the signal SEN of the sensing amplifier 120 rises to a high level, turning off transistors M11 to M13. As a result, current from the power supply VDD flows through transistor M8 to current paths CP1 and CP2. The current I1st flowing in current path CP1 is determined by the resistance state of transistor M20, which is controlled by voltage V1st. Furthermore, when transistor M21 is turned on, an additional offset current Iofs1 flows in current path CP1. The current I2nd flowing in current path CP2 is determined by the resistance state of transistor M23, which is controlled by voltage V2nd. Furthermore, when transistor M24 is turned on, an additional offset current Iofs2 flows in current path CP2.

[0111] Here, for reference Figure 8 (A)~ Figure 8 (C) The data detection method for the storage cell MC1 when the holding signal DO_PREV is high is explained. Figure 8 (A)~ Figure 8 In the graph (C), the horizontal axis represents the voltage levels V1st and V2nd (i.e., the logic of the data in the memory cell), and the vertical axis represents the number of memory cells (clock). The parallel state (P state) represents the low resistance state of the memory cell, for example, representing the low level of voltage V1st and V2nd (data "0"). The anti-parallel state (AP state) represents the high resistance state of the memory cell, for example, representing the high level of voltage V1st and V2nd (data "1").

[0112] like Figure 8 As shown in (A), in the initial state, with the signal DO_PREV kept high, Figure 6 The offset section OFS2 carries an offset current Iofs2 in the current path CP2. At this time, the offset section OFS1 does not carry an offset current Iofs1. In this case, as... Figure 8 As shown in (B), the voltage V2nd+Vofs2 can be considered as the rising offset voltage Vofs2 corresponding to the storage cell MC1 of the detection target. The sensing amplifier 120 compares the voltage V2nd+Vofs2 with the high-level voltage V1st. That is, the sensing amplifier 120 compares the voltage of the gate (node ​​N7) of the transistors M9 and M14 that are shifted and have reduced offset current Iofs2 with the voltage of the gate (node ​​N6) of the unshifted transistors M10 and M17.

[0113] At this time, the logic value of the data in memory cell MC1 is "0", and the voltage V2nd is low. Figure 8As shown in (B), the voltage V2nd is shifted to approximately the midpoint between the high-level voltage V1st and the low-level voltage V2nd (V2nd + Vofs2). Therefore, the sensing amplifier 120 can detect that the voltage V2nd is low by comparing the midpoint voltage V2nd + Vofs2 with the high-level voltage V1st. In other words, the sensing amplifier 120 can detect that the data in the memory cell MC1 is "0".

[0114] On the other hand, when the logic of the data in memory cell MC1 is "1" and the voltage V2nd is high, such as Figure 8 As shown in (C), the voltage V2nd is shifted to a voltage V2nd+Vofs2 that is higher than the high-level voltages V1st and V2nd by an offset voltage Vofs2. In other words, if both voltages V1st and V2nd are high, there is a concern that the voltages V1st and V2nd cannot be distinguished. However, according to this embodiment, the high-level voltage V2nd is shifted to a voltage V2nd+Vofs2 that is further higher than the offset voltage Vofs2. Therefore, the sensing amplifier 120 can detect that the voltage V2nd is high by comparing the voltage V2nd+Vofs2 with the high-level voltage V1st. That is, the sensing amplifier 120 can detect that the data in the memory cell MC1 is "1".

[0115] Thus, the sensing amplifier 120 can use the voltage V1st of node N17 in the initial state as a reference signal to detect the data of the memory cell MC1.

[0116] Refer again Figure 7 Between t3 and t4, a voltage difference appears between nodes N6 and N7 in the output signal DO. This voltage difference depends on the current flowing in current path CP1 (I1st or I1st+Iofs1) and current path CP2 (I2nd or I2nd+Iofs2). Furthermore, these currents flowing in current paths CP1 and CP2 are determined by voltages V1st, V2nd, and the holding signal DO_PREV. Thus, a voltage difference appears between voltage V2nd+Vofs2 and voltage V1st in the output signal DO.

[0117] At t4, by raising the signal LATN to a high level, transistors M16 and M19 are activated, significantly increasing the voltage difference between nodes N6 and N7. At this time, the logic value of the data in memory cell MC1 is "0", and with voltage V2nd low, the output signal DO becomes low. Conversely, if the logic value of the data in memory cell MC1 is "1", and voltage V2nd is high, the output signal DO becomes high.

[0118] Next, at t5, Figure 5the signals SW1P, SW1B of the preamplifier 110 each become high and low, and the switches M31, M32 are turned on. As a result, the data of the memory cell MC1 is also transferred to the node N17, and the voltage V1st, like the voltage V2nd, becomes a voltage corresponding to the data of the memory cell MC1. The capacitor C3 is charged with the voltage corresponding to the data of the memory cell MC1. Further, the latch signal DLAT becomes high, Figure 6 the register REG1 latches the output signal DO as the hold signal DO_PREV. As a result, the output signal DO, which is the result of detection of the data of the memory cell MC1, is held as the hold signal DO_PREV.

[0119] Next, at t6, the signals SEN, SEN2, LATN, DLAT fall to low. As a result, the transistors M11 to M13 are turned on, and the transistors M15, M16, M18, M19 are turned off. As a result, the currents I1st, I2nd of the current paths CP1, CP2 stop, and the nodes N6, N7 are reset to the same voltage. However, by invalidating the latch signal DLAT to low, the register REG1 maintains the logic of the data of the memory cell MC1 as the hold signal DO_PREV, independently of the output signal DO.

[0120] Further, the signals SW1P, SW1B each become low and high, and the switches M31, M32 are turned off. However, the capacitor C3 holds the voltage V1st of the node N17 as a voltage corresponding to the data of the memory cell MC1. That is, the hold signal DO_PREV and the voltage V1st of the node N17 maintain the logic of the data of the memory cell MC1. On the other hand, the voltage V2nd of the node N18, the output signals DO, DOB of the nodes N6, N7 are reset.

[0121] Next, at t7, the read enable signal REN falls to low. As a result, the readout operation of the memory cell MC1 ends.

[0122] (Readout operation of the memory cell MC2)

[0123] Next, for the memory cell MC2, the same readout operation is performed. The operations at t11 to t17 can be basically the same as those at t1 to t7. However, at the data detection at t13 to t14, the hold signal DO_PREV and the voltage V1st of the node N17 maintain the logic of the data of the memory cell MC1, and the data of the memory cell MC2 is transferred to the voltage V2nd of the node N18.

[0124] For example, in the case where the data of the memory cell MC1 is "1" and the hold signal DO_PREV is at the high level, the offset section OFS2 flows the offset current Iofs2 in the current path CP2 in the data detection of the memory cell MC2. Thereby, the voltage of the node N18 corresponding to the data of the memory cell MC2 can be considered to be offset to the voltage V2nd+Vofs2. Therefore, the sense amplifier 120 can detect the data of the memory cell MC2 by comparing the voltage V2nd+Vofs2 with the voltage V1st. This is the same action as the reference Figure 8 illustrated. The sense amplifier 120 makes the voltage V2nd corresponding to the data of the memory cell MC2 appear to be offset to the voltage V2nd+Vofs2 based on the hold signal DO_PREV (the data of the memory cell MC1) latched to the register REG1. Thereby, the data of the memory cell MC2 can be detected using the voltage V1st corresponding to the data of the memory cell MC1 as the reference voltage.

[0125] On the other hand, in the case where the data of the memory cell MC1 is "0" and the hold signal DO_PREV is at the low level, the offset section OFS1 flows the offset current Iofs1 in the current path CP1. Therefore, the voltage of the node N17 corresponding to the data of the memory cell MC1 can be considered to be offset to the voltage V1st+Vofs1.

[0126] Here, the data detection method of the memory cell MC2 when the hold signal DO_PREV is at the low level is described with reference to Figure 9 (A) ~ Figure 9 (C). Figure 9 (A) ~ Figure 9 (C) are the same as those of Figure 8 (A) ~ Figure 8 (C).

[0127] As illustrated in Figure 9 (A), in the case where the hold signal DO_PREV is at the low level, Figure 6 the offset section OFS1 flows the offset current Iofs1 in the current path CP1. At this time, the offset section OFS2 does not flow the offset current Iofs2. In this case, the data of the memory cell MC1 (the voltage V1st) stored in the node N17 which has been read out can be considered to be raised by the offset voltage Vofs1. In this case, as illustrated in Figure 9As shown in (A), the voltage V1st can be considered as a voltage V1st+Vofs1 which is offset to substantially the middle of the high level and the low level. The sense amplifier 120 compares the middle voltage V1st+Vofs1 as a reference voltage with the voltage V2nd. That is, the sense amplifier 120 compares the voltage of the gate (node N6) of the transistors M10, M17, which are shifted and have a part of the offset current Iofs1, with the voltage of the gate (node N7) of the transistors M9, M14, which are not shifted. In addition, the hold signal DO_PREV maintains the state (low level) latched to the register REG1.

[0128] At this time, in the case where the logic of the data of the memory cell MC2 is "0" and the voltage V2nd is low, as shown in (B), the sense amplifier 120 shifts the voltage V1st of the low level to the middle voltage V1st+Vofs1 and compares the middle voltage V1st+Vofs1 with the voltage V2nd of the low level. Thus, the voltage V1st departs from the vicinity of the voltage V2nd to the middle voltage V1st+Vofs1, so the sense amplifier 120 can detect that the voltage V2nd is low (data "0"). Figure 9 (B), the sense amplifier 120 shifts the voltage V1st of the low level to the middle voltage V1st+Vofs1 and compares the middle voltage V1st+Vofs1 with the voltage V2nd of the low level. Thus, the voltage V1st departs from the vicinity of the voltage V2nd to the middle voltage V1st+Vofs1, so the sense amplifier 120 can detect that the voltage V2nd is low (data "0").

[0129] On the other hand, in the case where the logic of the data of the memory cell MC2 is "1" and the voltage V2nd is high, as shown in (C), the sense amplifier 120 compares the offset middle voltage V1st+Vofs1 with the voltage V2nd of the high level. Thus, the voltage V1st is close to the voltage V2nd but still sufficiently departs, so the sense amplifier 120 can detect that the voltage V2nd is high (data "1"). Figure 9 (C), the sense amplifier 120 compares the offset middle voltage V1st+Vofs1 with the voltage V2nd of the high level. Thus, the voltage V1st is close to the voltage V2nd but still sufficiently departs, so the sense amplifier 120 can detect that the voltage V2nd is high (data "1").

[0130] Thus, the sense amplifier 120 uses the middle voltage V1st+Vofs1 as a reference signal and can detect the data of the memory cell MC2.

[0131] After that, the operations of t14 to t17 can be substantially the same as those of t4 to t7.

[0132] (Readout operation of memory cell MC3)

[0133] Next, the readout operation is also performed for the memory cell MC3. The operations of t21 to t27 can be substantially the same as those of t1 to t7. However, at the time of data detection of t23 to t24, the voltage V1st of the hold signal DO_PREV and the node N17 maintains the logic of the data of the memory cell MC2, and the data of the memory cell MC3 is transferred to the voltage V2nd of the node N18.

[0134] For example, in the case where the data of the memory cell MC2 is "1" and the hold signal DO_PREV is at the high level, in the data detection of the memory cell MC3, the offset section OFS2 flows the offset current Iofs2 in the current path CP2. Thus, the voltage of the node N18 corresponding to the data of the memory cell MC3 can be considered to be offset to the voltage V2nd+Vofs2. Therefore, the sense amplifier 120 can detect the data of the memory cell MC3 by comparing the voltage V2nd+Vofs2 with the voltage V1st. This is the same action as that described with reference to Figure 8 the sense amplifier 120 causes the voltage V2nd corresponding to the data of the memory cell MC3 to be offset in appearance to the voltage V2nd+Vofs2 based on the hold signal DO_PREV (the data of the memory cell MC2) latched to the register REG1. Thus, the data of the memory cell MC3 can be detected using the voltage V1st corresponding to the data of the memory cell MC2 as the reference voltage.

[0135] Further, for example, in the case where the data of the memory cell MC2 is "0" and the hold signal DO_PREV is at the low level, in the data detection of the memory cell MC3, the offset section OFS1 flows the offset current Iofs1 in the current path CP1. Therefore, the voltage of the node N17 corresponding to the data of the memory cell MC2 can be considered to be offset to the voltage V1st+Vofs1. Thus, the sense amplifier 120 can detect the data of the memory cell MC3 by comparing the voltage V1st+Vofs1 with the voltage V2nd. This is the same action as that described with reference to Figure 9 the sense amplifier 120 causes the voltage V1st corresponding to the data of the memory cell MC2 to be offset in appearance to the voltage V1st+Vofs1 based on the hold signal DO_PREV (the data of the memory cell MC2) latched to the register REG1. Thus, the data of the memory cell MC3 can be detected using the voltage V1st corresponding to the data of the memory cell MC2 as the reference voltage.

[0136] (Readout action of the memory cell MC4)

[0137] Next, the readout action is performed also for the memory cell MC4. The actions at t31 to t37 can be basically the same as those at t1 to t7. However, at the time of the data detection at t33 to t34, the hold signal DO_PREV and the voltage V1st of the node N17 maintain the logic of the data of the memory cell MC3, and the data of the memory cell MC4 is transferred to the voltage V2nd of the node N18. The other readout action of the memory cell MC4 can be the same as that of the memory cell MC3.

[0138] Thus, the sense amplifier 120 uses the voltage V1st corresponding to the data of the memory cell MC3 as a reference voltage, and can detect the data of the memory cell MC4.

[0139] Figure 7 Only the readout operation of the memory cells MC1 to MC4 is shown, but the memory cells MC5 and subsequent memory cells can also be read out in the same manner. In this case, the sense amplifier 120 uses the voltage V1st corresponding to the data of the memory cell MCk-1 (k > 1) as a reference voltage, and detects the data of the memory cell MCk.

[0140] In addition, in the embodiment, the initial memory cell stores high-level data of "1". However, the initial memory cell can also store low-level data of "0". In this case, as described with reference to FIG. 6, the sense amplifier 120 shifts the voltage V1st in the initial state by the offset voltage V1st+Vofsl, and detects the voltage V2nd corresponding to the data of the memory cell MC1 using the offset voltage V1st+Vofsl as a reference voltage. Thus, the data of the initial memory cell can also be either "0" or "1". Figure 9 As described above, the sense amplifier 120 detects the data of the memory cell MC1 using the voltage V1st or the offset voltage V1st+Vofsl corresponding to the data of the initial memory cell as a reference voltage. Similarly, the sense amplifier 120 detects the data of the memory cell MCk using the data of the memory cell MCk-1 as a reference data.

[0141] In addition, in the embodiment, the initial memory cell stores high-level data of "1". However, the initial memory cell can also store low-level data of "0". In this case, as described with reference to FIG. 6, the sense amplifier 120 shifts the voltage V1st in the initial state by the offset voltage V1st+Vofsl, and detects the voltage V2nd corresponding to the data of the memory cell MC1 using the offset voltage V1st+Vofsl as a reference voltage. Thus, the data of the initial memory cell can also be either "0" or "1".

[0142] Figure 10 (A) to (D) Figure 10 (D) is a conceptual diagram showing the readout order of the memory cells MC.

[0143] As described above, the sense amplifier 120 detects the data of the memory cell MC1 using the voltage V1st or the offset voltage V1st+Vofsl corresponding to the data of the initial memory cell as a reference voltage. Similarly, the sense amplifier 120 detects the data of the memory cell MCk using the data of the memory cell MCk-1 as a reference data.

[0144] In the memory cell array 11, the memory cell MCk is disposed in the vicinity of the memory cell MCk-1, preferably, the adjacent cell of the memory cell MCk-1. By disposing the memory cell MCk in the vicinity of or adjacent to the memory cell MCk-1, the electrical characteristics of the memory cell MCk and the memory cell MCk-1 are close to each other and similar. Further, since the wiring distances from the driver 14 or the sensing circuit 100 and the like to the memory cell MCk and the memory cell MCk-1 are not greatly changed from each other, the wiring resistances are also substantially equal. Therefore, the sense amplifier 120 can correctly detect the data of the memory cell MCk using the data of the memory cell MCk-1 as the reference data.

[0145] For example, Figure 11 (A) ~ Figure 12 (C) is a conceptual diagram showing another example of the read operation.

[0146] As Figure 11 (A) shows, in the case where the voltage V1st corresponding to the data of the memory cell MCk-1 is located at the lower end of the distribution of the data "1", it is considered that the memory cell MCk in the vicinity of the memory cell MCk-1 also has the same characteristics as the memory cell MCk-1. That is, the voltage V2nd corresponding to the data of the memory cell MCk is also highly likely to be located at the lower end of the distribution of the data "1" or "0". Therefore, in the case where the data of the memory cell MCk is "0", as Figure 11 (B) shows, the voltage V2nd is located at the lower end of the distribution of the data "0". The sense amplifier 120 causes the voltage V2nd corresponding to the data of the memory cell MCk to be shifted in appearance to V2nd+Vofs2 based on the hold signal DO_PREV. Since the data of the memory cells MCk-1, MCk are each located at the lower end of the distribution of the data "1", "0", the data of the memory cell MCk (voltage V2nd+Vofs2) can be detected using the voltage V1st corresponding to the data of the memory cell MCk-1 as the reference voltage. Further, since the hold signal DO_PREV is the signal after detection by the sense amplifier 120, it is located at the substantially center of the distribution.

[0147] In the case where the data of the memory cell MCk is "1", as Figure 11 (C) shows, the voltage V2nd is located at the lower end of the distribution of the data "1". The sense amplifier 120 causes the voltage V2nd corresponding to the data of the memory cell MCk to be shifted in appearance to V2nd+Vofs2 based on the hold signal DO_PREV. Since the data of the memory cells MCk-1, MCk are each located at the lower end of the distribution of the data "1", the data of the memory cell MCk (voltage V2nd+Vofs2) can be detected using the voltage V1st corresponding to the data of the memory cell MCk-1 as the reference voltage.

[0148] In addition, Figure 11 (A) ~ Figure 11 In the specific example of (C), the data of the memory cells MCk-1 and MCk are located at the lower end of the distribution, but the same applies to the case where the data of the memory cells MCk-1 and MCk are located at the upper end of the distribution.

[0149] As Figure 12 (A) shows, in the case where the voltage V1st corresponding to the data of the memory cell MCk-1 is located at the upper end of the distribution of the data "0", it is considered that the memory cell MCk in the vicinity of the memory cell MCk-1 also has the same characteristics as the memory cell MCk-1. That is, there is a high possibility that the voltage V2nd corresponding to the data of the memory cell MCk is also located at the upper end of the distribution of the data "1" or "0". Therefore, in the case where the data of the memory cell MCk is "0", as Figure 12 (B) shows, the voltage V2nd is located at the upper end of the distribution of the data "0". The sense amplifier 120 causes the voltage V1st corresponding to the data of the memory cell MCk-1 to be apparently shifted to V1st+Vofs1 based on the hold signal DO_PREV. Since the data of the memory cells MCk-1 and MCk are both located at the upper end of the distribution of the data "0", the data of the memory cell MCk (voltage V2nd) can be detected using the voltage V1st+Vofs1 which is the voltage V1st corresponding to the data of the memory cell MCk-1 shifted as the reference voltage.

[0150] In the case where the data of the memory cell MCk is "1", as Figure 12 (C) shows, the voltage V2nd is located at the upper end of the distribution of the data "1". The sense amplifier 120 causes the voltage V1st corresponding to the data of the memory cell MCk-1 to be apparently shifted to V1st+Vofs1 based on the hold signal DO_PREV. Since the data of the memory cells MCk-1 and MCk are located at the upper end of the distribution of the data "0" and "1", respectively, the data of the memory cell MCk (voltage V2nd) can be detected using the voltage V1st+Vofs1 which is the voltage V1st corresponding to the data of the memory cell MCk-1 shifted as the reference voltage.

[0151] In addition, Figure 12 (A) ~ Figure 12 (C), the data of the memory cells MCk-1 and MCk are located at the upper end of the distribution, but the same applies to the case where the data of the memory cells MCk-1 and MCk are located at the lower end of the distribution.

[0152] Thus, the storage units MCk and MCk-1 which are successively read out are preferably arranged close to or adjacent to each other, and have similar electrical characteristics to each other. Further, it is preferable that the wiring resistances from the driver 14 or the sensing circuit 100 and the like to the storage units MCk and MCk-1 are also substantially equal. Thus, the sensing amplifier 120 can correctly detect the data of the storage unit MCk using the data of the storage unit MCk-1 as reference data.

[0153] The readout order of the storage units MC can also be Figure 10 (A) to Figure 10 (D) in any order. Figure 10 (A) or Figure 10 (B) sequentially accesses the storage units MC arranged along the word lines WL or the bit lines BL to read out data. At this time, the sensing circuit 100 reads out data from a plurality of storage units MC which are successively adjacent from one end to the other end of a certain word line WL or bit line BL. Thereafter, the sensing circuit 100 reads out data from a plurality of storage units MC which are successively adjacent from the other end to the one end of another word line WL or bit line BL which is adjacent. By repeating the operation, the sensing circuit 100 reads out data from the storage units MC which are successively in a zigzag shape. Thus, even if the electrical characteristics of the storage units MC which are distant from each other in the storage unit array 11 are different from each other, as long as the electrical characteristics of the storage units MC which are close to each other are similar to each other, the sensing circuit 100 can detect the data of the storage unit MCk using the data of the storage unit MCk-1 as reference data.

[0154] Figure 10 In (C), the sensing circuit 100 successively accesses the storage units MC which are adjacent in the diagonal direction (the direction inclined with respect to the word lines and the bit lines) of the storage unit array 11. In this case, the two adjacent storage units MC are connected to different word lines WL and bit lines BL.

[0155] Figure 10 In (D), the sensing circuit 100 accesses the storage units which are adjacent or close to each other in the order of the storage units MC0 to MC13. After accessing the storage unit MC13, the sensing circuit 100 accesses 13 groups of storage units which are adjacent in the direction of the word lines WL or the bit lines BL in the same order. Thus, it is preferable that the storage unit MCk is adjacent to the storage unit MCk-1, but it is not necessary to be adjacent, and can be arranged close to the storage unit MCk-1. By close, it is meant a range in which the storage units MCk and MCk-1 have similar electrical characteristics to each other and wiring resistances.

[0156] According to the above embodiment, the sensing circuit 100 does not need to perform a plurality of read and write operations to the memory cell MC as in the self-reference method in order to read out data of one memory cell MC. Therefore, the data read speed is faster than the self-reference method, and the dissipation power is smaller. Further, the data rewrite resistance is not worse than the self-reference method.

[0157] Further, since the sensing circuit 100 of the present embodiment uses data of the adjacent memory cell MC as the reference data, the reference signal is naturally adjusted. That is, the circuit for adjusting the reference signal according to the position of the memory cell MC is not needed, and the reference signal is naturally adjusted. Thus, the sensing circuit 100 can reduce the circuit size, and can correctly detect data of the memory cell MC.

[0158] Further, the sensing circuit 100 of the present embodiment is similar to the sensing circuit used in the self-reference method. Therefore, the sensing circuit 100 of the present embodiment can use the existing sensing circuit of the self-reference method, and is easily manufactured.

[0159] (Second Embodiment)

[0160] In a case where read data is detected to have an error by ECC (Error-Correcting Code) or the like, the next data is detected using the erroneous data as the reference. In this case, there is a concern that correct data detection cannot be performed.

[0161] In the present embodiment, in a case where an error is detected, data is detected using normal data detected earlier (data of two or more cells in advance) as the reference data. Alternatively, in this case, the next data can be detected using the self-reference method.

[0162] Figure 13 is a timing chart showing one example of the read operation of the preamplifier 110 and the sense amplifier 120 of the second embodiment. In the example, the read data of the memory cell MC2 is erroneous. In this case, the memory cell MC3 detects using the data of the memory cell MC1 as the reference data. The read operation of the memory cells MC1 and MC4 can be the same as the operation of the first embodiment shown in Figure 7 . Therefore, the operation explanation of t1 to t7 and t31 to t37 is omitted.

[0163] In a case where the read data of the memory cell MC2 is erroneous, the signals SW1P and SW1B do not operate, and the switches M31 and M32 maintain the open state at t15 to t16. Thus, the data of the memory cell MC2 is not transferred to the node N17, and the voltage V1st maintains the voltage corresponding to the data of the memory cell MC1. The capacitor C3 maintains the state charged with the voltage corresponding to the data of the memory cell MC1. Further, the signal DLAT does not rise, Figure 6The register REG1 does not update the holding signal DO_PREV, and maintains the detection result of the data of the memory cell MC1 as the holding signal DO_PREV.

[0164] Therefore, when the data of the next memory cell MC3 is read, in the case where the data of the memory cell MC3 is correct, the read data of the memory cell MC1 is used as the reference signal, and the data of the memory cell MC3 is detected. That is, in the case where the read data is incorrect, the preamplifier 110 does not hold the incorrect data at the node N17, and the sense amplifier 120 does not latch the output signal DO based on the incorrect data as the holding signal DO_PREV. The preamplifier 110 and the sense amplifier 120 hold the previous correct read data at the node N17, and maintain as the holding signal DO_PREV.

[0165] Therefore, the data of the memory cell MC3 is detected with reference to the read data (for example, the data of the memory cell MC1) of the memory cell which is two or more cells ahead of it. Thus, even if the data of the memory cell MC2 is incorrect, the sense amplifier 120 can correctly read the data of the memory cell MC3.

[0166] Further, even if two memory cells are incorrect in succession, the preamplifier 110 and the sense amplifier 120 continue to hold the previous correct data, so the data of the next memory cell can be correctly read. In the present embodiment, in the case where an error occurs, there is a case where the memory cell in which the reference data is stored is not adjacent to the memory cell which is the object of reading. However, since these memory cells are arranged in the vicinity of each other, this is not a problem.

[0167] (3rd Embodiment)

[0168] Figure 14 is a circuit diagram showing a configuration example of the preamplifier 110 of the 3rd embodiment.

[0169] In the 3rd embodiment, the preamplifier 110 includes a plurality of blocks 200_1, 200_2 each configured by the switches M31, M32, the switches M34, M35, the transistor M33, and the capacitor C3. The blocks 200_1, 200_2 are connected in parallel with respect to the nodes N16, N18. The other configurations of the preamplifier 110 can be the same as the corresponding configurations of the 1st embodiment, and can be shared by the blocks 200_1, 200_2. Therefore, the node N17 is provided in each of the blocks 200_1, 200_2, and a plurality of voltages V1st can be held. On the other hand, the nodes N18 are shared by the blocks 200_1, 200_2, and one voltage V2nd is used for the read operation.

[0170] Figure 15is a circuit diagram showing a configuration example of the sense amplifier 120 of the third embodiment. The sense amplifier 120 includes a plurality of blocks 301_1, 301_2 configured of the offset section OFS1 and the transistor M20, and a plurality of blocks 302_1, 302_2 configured of the offset section OFS2 and the transistor M25. The blocks 301_1, 301_2 are connected to the outputs of the inverters INV1_1, INV1_2, respectively, and receive each of the signals SHFTDO_1, SHFTDO_2. Further, the blocks 301_1, 301_2 are commonly connected to the source of the transistor M15. The blocks 302_1, 302_2 are connected to the outputs of the inverters INV2_1, INV2_2, respectively, and receive each of the signals SHFTDOB_1, SHFTDOB_2. Further, the blocks 302_1, 302_2 are commonly connected to the source of the transistor M18.

[0171] Further, the sense amplifier 120 includes a plurality of registers REG1, REG2, a plurality of inverters INV1_1, INV1_2, and a plurality of inverters INV2_1, INV2_2. The plurality of registers REG1, REG2 input and output the signal DO, latch the output signal DO at the timing when the latch signals DLAT_1, DLAT_2 rise, respectively, and output it as the hold signals DO_PREV_1, DO_PREV_2. The inverters INV1_1, INV1_2 invert and output the hold signals DO_PREV_1, DO_PREV_2 as the signals SHFTDO_1, SHFTDO_2, respectively. The inverters INV2_1, INV2_2 invert and output the signals SHFTDO_1, SHFTDO_2 as the signals SHFTDOB_1, SHFTDOB_2, respectively.

[0172] The other configurations of the sense amplifier 120 can be the same as the corresponding configurations of the first embodiment, and can be shared by the blocks 301_1, 302_2, the registers REG1, REG2, and the like.

[0173] Thus, in the third embodiment, the sense circuit 100 has two systems of the registers REG1, REG2, the nodes N17, N18, and the like, and can hold a plurality of normal data read out in the past. Note that the reference symbol ***_1 indicates the first system, and the reference symbol ***_2 indicates the second system. Further, the present embodiment has two systems, but can have three or more systems.

[0174] Figure 16 is a timing chart showing one example of the readout operation of the preamplifier 110 and the sense amplifier 120 of the third embodiment. In the example, the readout data of the memory cells MC2, MC3 is erroneous. Hereinafter, the points different from the first embodiment will be mainly described.

[0175] The voltage V0 corresponding to the read data of the initial memory cell is held at the node N17 of the block 200_1 and 200_2. Therefore, before tl, the voltages V1st_1 and V1st_2 are the voltage V0. In conjunction therewith, in the initial state, the registers REG1 and REG2 hold the data D0 of the initial memory cell as the hold signals DO_PREV_1 and DO_PREV_2. The sensing circuit 100 alternately uses the first system and the second system at the time of data read of the memory cell MC.

[0176] In the read operation of the memory cell MC1 from tl to t7, the voltage V2nd of the node N18 becomes the voltage V1 corresponding to the data of the memory cell MC1. First, if the second system is used, the sense amplifier 120 detects the data of the memory cell MC1 using the voltage V1st_2 of the initial state as the reference signal. The detection method of the memory cell MC1 can be the same as that of the first embodiment.

[0177] In the normal case of the data of the memory cell MC1, at t5 to t6, the voltage V1 corresponding to the data of the memory cell MC1 is held at the node N17 of the block 200_1 on the first system side. Therefore, in the read operation of the memory cell MC2, the voltage V1st_1 becomes the voltage V1. The voltage V1st_2 of the node N17 on the second system side is held at the voltage V0.

[0178] Further, at t5 to t6, the latch signal DTAL_1 of the first system rises. Thereby, the register REG1 latches the data D1 output as the output signal DO and outputs it as the hold signal DO_PREV_1. At this time, the register REG2 on the second system side still latches the data D0 as the hold signal DO_PREV_2.

[0179] In the read operation of the memory cell MC2 from tl l to tl 7, the voltage V2nd of the node N18 becomes the voltage V2 corresponding to the data of the memory cell MC2. Since the first system is used this time, the sense amplifier 120 detects the data of the memory cell MC2 using the voltage V1st_1 as the reference signal. The detection method of the memory cell MC2 can be substantially the same as that of the first embodiment.

[0180] Here, in the case where the data of the memory cell MC2 is erroneous, the signals SW1P_1, SW1P_2 do not rise, and the latch signals DLAT_1, DLAT_2 do not rise either. Therefore, the voltage V2 corresponding to the data of the memory cell MC2 appears as the voltage V2nd of the node N18, but is not held at the node N17 of the blocks 200_1, 200_2. Thus, the voltage V1st_1 of the node N17 of the block 200_1 maintains the state of the voltage V1, and the voltage V1st_2 of the node N17 of the block 200_2 maintains the state of the voltage V0. Further, the registers REG1, REG2 do not change the hold signals DO_PREV_1, DO_PREV_2, and each maintains the data D1, D0.

[0181] In the readout operation of the memory cell MC3 at t21 to t27, the voltage V2nd of the node N18 becomes the voltage V3 corresponding to the data of the memory cell MC3. Since the second system is used this time, the sense amplifier 120 detects the data of the memory cell MC3 using the voltage V1st_2 as the reference signal. The detection method of the memory cell MC3 can be substantially the same as the detection method of the first embodiment.

[0182] Here, in the case where the data of the memory cell MC3 is erroneous, the signals SW1P_1, SW1P_2 do not rise, and the latch signals DLAT_1, DLAT_2 do not rise either. Therefore, the voltage V3 corresponding to the data of the memory cell MC3 appears as the voltage V2nd of the node N18, but is not held at the node N17 of the blocks 200_1, 200_2. Thus, the voltage V1st_1 of the node N17 of the block 200_1 maintains the state of the voltage V1, and the voltage V1st_2 of the node N17 of the block 200_2 maintains the state of the voltage V0. Further, the registers REG1, REG2 do not change the hold signals DO_PREV_1, DO_PREV_2, and each maintains the data D1, D0.

[0183] In the readout operation of the memory cell MC4 at t31 to t37, the voltage V2nd of the node N18 becomes the voltage V4 corresponding to the data of the memory cell MC4. Since the second system is used this time, the sense amplifier 120 detects the data of the memory cell MC4 using the voltage V1st_2 as the reference signal. The detection method of the memory cell MC4 can be substantially the same as the detection method of the first embodiment.

[0184] Here, in the case where the data of the memory cell MC4 is normal, the signal SW1P_2 and the latch signal DLAT_2 rise at t35 to t36. Therefore, the voltage V4 corresponding to the data of the memory cell MC4 is held as the voltage V1st_2 at the node N17 of the block 200_2. The voltage V1st_1 of the node N17 of the block 200_1 maintains the state where the voltage V1 is held. Further, the register REG2 latches the data D4 output as the output signal DO from the sense amplifier 120, and outputs it as the held signal DO_PREV_2. At this time, the register REG1 of the first system side still latches the data D1 as the held signal DO_PREV_1.

[0185] Thus, the sensing circuit 100 of the present embodiment holds the plurality of normal data before as the voltage V1st at the plurality of nodes N17, and does not hold the error data in the case where the error data is detected. The voltage V1st corresponding to the plurality of normal data before is used as the reference voltage of the data detected later. The register REG1, REG2 does not latch (update) the output signal DO of the error data as the held signal DO_PREV_1, DO_PREV_2 in the case where the error data is detected, and maintains the held signal DO_PREV_1, DO_PREV_2 based on the normal data before. Thus, in the case where the data of the read target is erroneous, the sensing circuit 100 can detect the data later with reference to the normal data before.

[0186] In the present embodiment, the switching operation is explained as an example in which a 3-terminal transistor is used as the switching element. The switching element is not limited to this, and a 2-terminal switching element can also be applied. In this case, the switching element is in a "high resistance" state, for example, an electrically non-conductive state, in the case where the voltage applied between the two terminals does not reach the threshold value. The switching element becomes in a "low resistance" state, for example, an electrically conductive state, in the case where the voltage applied between the two terminals is equal to or higher than the threshold value.

[0187] Although a number of embodiments of the present application have been described above with a certain degree of particularity, one of ordinary skill in the art will readily appreciate that changes can be made to these embodiments without departing from the spirit and scope of the application as hereinafter claimed. The embodiments thus represent the principles of the application and, although changes in the specific details of the embodiments can be made, it is intended to fall within the scope of the application as hereinafter claimed.

[0188] [Explanation of Symbols]

[0189] 100 sensing circuit

[0190] 110 preamplifier

[0191] 120 sense amplifier

[0192] M6-M25, M29-M35 MOS transistors

[0193] C3, C4 capacitors

[0194] REG1 register

[0195] INV1, INV2 inverters

Claims

1. A semiconductor memory device comprising: a plurality of memory cells; The first node stores the first data read from the first storage unit within the plurality of storage units; The second node stores the second data read from the second storage unit near the first storage unit within the plurality of storage units; The differential circuit has a first current path through which a first current flows corresponding to the voltage of the first node, and a second current path through which a second current flows corresponding to the voltage of the second node, and outputs an output signal from the output unit corresponding to the voltage difference between the first node and the second node; The first register latches the output signal and outputs it as a hold signal; The first offset section is connected to the first current path and offsets the first current when the holding signal is the first logic. and The second offset section is connected to the second current path, and when the holding signal is a second logic that is the opposite of the first logic, it causes the second current to offset.

2. The semiconductor memory device according to claim 1, wherein the differential circuit comprises: A first transistor is disposed in the first current path, and its gate is connected to the second current path; and The second transistor is disposed in the second current path, and its gate is connected to the first current path and the output section.

3. The semiconductor memory device according to claim 1, wherein the first data is data read before the second data is read.

4. The semiconductor memory device according to claim 2, wherein the holding signal is the first logic, A first offset current flows through the first offset portion, causing a shift in the gate voltage of the second transistor. When the holding signal is the second logic, the second offset portion flows a second offset current, causing the gate voltage of the first transistor to shift.

5. The semiconductor memory device of claim 4, wherein the first offset portion includes a first offset transistor, wherein a first offset current flows when a first shift voltage is applied to the gate. The second offset portion includes a second offset transistor, which allows the second offset current to flow when a second shift voltage is applied to the gate.

6. The semiconductor memory device of claim 4, wherein the first offset current is the current flowing in the first current path when the first data is the first logic, and the current flowing in the first current path when the first data is the second logic. The second offset current is the current flowing in the second current path when the second data is the first logic, and the current flowing in the second current path when the second data is the second logic.

7. The semiconductor memory device according to claim 1, wherein the memory cell from which the object is initially read in the plurality of memory cells stores known initial data.

8. The semiconductor memory device according to claim 1, wherein the first register latches the output signal, and the first node stores the second data. The second node stores the third data read from the third storage unit near the second storage unit among the plurality of storage units.

9. The semiconductor memory device according to claim 1, further comprising: a first capacitor connected to the first node for storing the first data; and The second capacitor is connected to the second node to store the second data.

10. The semiconductor memory device of claim 1, wherein the first memory cell and the second memory cell are adjacent to each other.

11. The semiconductor memory device of claim 1, wherein the plurality of memory cells are arranged corresponding to the intersection of the intersecting first wiring and the second wiring.

12. The semiconductor memory device according to claim 1, wherein the plurality of memory cells are magnetoresistive variable memory cells or resistive variable memory cells.

13. A control method for a semiconductor memory device, comprising: a plurality of memory cells; a differential circuit that outputs a voltage difference between a first node and a second node as an output signal; a first register that latches the output signal and outputs it as a holding signal; a first offset portion that carries a first offset current in a first current path of the differential circuit; and a second offset portion that carries a second offset current in a second current path of the differential circuit; and the control method for the semiconductor memory device further comprising: The first data read from the first storage unit within the plurality of storage units is stored in the first node; The first register outputs the hold signal based on the first data; The second data read from the second storage unit near the first storage unit within the plurality of storage units is stored in the second node; When the holding signal is the first logic, the first offset current flows in the first current path; when the holding signal is the second logic, which is the opposite of the first logic, the second offset current flows in the second current path. The voltage difference between the first node and the second node is output as the output signal.

14. The method according to claim 13, wherein the differential circuit comprises: a first transistor disposed in the first current path, the gate of which is connected to the second current path; and a second transistor disposed in the second current path, the gate of which is connected to the first current path and the output section; When the hold signal is the first logic, a first offset current flows through the first offset portion, shifting the gate voltage of the second transistor. When the holding signal is the second logic, the second offset portion flows a second offset current, causing the gate voltage of the first transistor to shift.

15. The method of claim 14, wherein the first offset portion comprises a first offset transistor in which the first offset current flows when a first shift voltage is applied to the gate. The second offset portion includes a second offset transistor in which the second offset current flows when the second shift voltage is applied to the gate. The first shift voltage is approximately the intermediate voltage between the voltage of the first node when the first data is the first logic and the voltage of the first node when the first data is the second logic. The second shift voltage is approximately the intermediate voltage between the voltage of the second node when the second data is the first logic and the voltage of the second node when the second data is the second logic.

16. The method of claim 13, wherein the storage unit of the first read object among the plurality of storage units stores known initial data.

17. The method according to claim 13, further comprising: when outputting the voltage difference between the first node and the second node as the output signal, the first register latches the output signal as the holding signal; The third data read from the third storage unit near the second storage unit within the plurality of storage units is stored in the second node; When the holding signal is the first logic, the first offset current flows in the first current path; when the holding signal is the second logic, which is the opposite of the first logic, the second offset current flows in the second current path. The voltage difference between the first node and the second node is output as the output signal.

18. The method of claim 13, wherein the first storage cell and the second storage cell are adjacent to each other.

19. The method of claim 17, wherein the second storage cell and the third storage cell are adjacent to each other.

20. The method of claim 17, wherein in the event of a second data error, the first register does not latch the output signal based on the voltage difference between the first node and the second node as the hold signal, but maintains the previous hold signal.

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