Variable resistance memory device

Abstract

Embodiments provide a variable resistance memory device that can efficiently read data. A first memory cell is coupled to a first interconnect and a third interconnect. A second memory cell is coupled to a second interconnect and a fourth interconnect. A first sense amplifier has a node coupled to a first potential and a first terminal of the first interconnect and a second terminal positioned proximate a node coupled to a second potential and the third interconnect, and has a potential difference between the first terminal and the second terminal. A second sense amplifier has a node coupled to a third potential and a third terminal of the fourth interconnect and a fourth terminal positioned proximate a node coupled to a fourth potential and the second interconnect, and has a potential difference between the third terminal and the fourth terminal.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2020-157866, filed September 18, 2020, and U.S. Patent Application No. 17 / 198495, filed March 11, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to variable resistive memory devices. Background Technology

[0004] A memory device is known that includes memory cells, which may have resistances of different magnitudes depending on the state. Summary of the Invention

[0005] The embodiments provide a variable resistive memory device that can efficiently read data.

[0006] Generally, according to one embodiment, a variable-resistive memory device includes: a first interconnect; a second interconnect; a third interconnect; a fourth interconnect; a first memory cell; a second memory cell; a first sense amplifier; and a second sense amplifier. The first memory cell is coupled to the first interconnect and the third interconnect and has a variable resistance. The second memory cell is coupled to the second interconnect and the fourth interconnect and has a variable resistance. The first sense amplifier has a first terminal and a second terminal, and a potential difference exists between the first terminal and the second terminal. The first terminal is coupled to the first interconnect and a node at a first potential. The second terminal is positioned near a node at a second potential and coupled to the third interconnect. The second sense amplifier has a third terminal and a fourth terminal, and a potential difference exists between the third terminal and the fourth terminal. The third terminal is coupled to the fourth interconnect and a node at a third potential. The fourth terminal is positioned near a node at a fourth potential and coupled to the second interconnect. Attached Figure Description

[0007] Figure 1 Functional blocks of a memory device according to a first embodiment are shown.

[0008] Figure 2 This is a circuit diagram of a memory cell array according to the first embodiment.

[0009] Figure 3 A cross-sectional structure of a portion of the memory primitive array according to the first embodiment is shown.

[0010] Figure 4A cross-section structure of a portion of a memory cell array according to the first embodiment is shown.

[0011] Figure 5 A cross-section of an example of a structure of a memory cell according to the first embodiment is shown.

[0012] Figure 6 Details of some functional blocks of a memory device according to the first embodiment are shown.

[0013] Figure 7 An example of components and connections of a row selector and a column selector according to the first embodiment is shown.

[0014] Figure 8 A first example of components and connections of a sense amplifier according to the first embodiment is shown.

[0015] Figure 9 A first example of components and connections of another sense amplifier according to the first embodiment is shown.

[0016] Figure 10 A second example of components and connections of a sense amplifier according to the first embodiment is shown.

[0017] Figure 11 A state during reading data from a memory device according to the first embodiment is shown.

[0018] Figure 12 A state of a memory device according to the first embodiment is shown.

[0019] Figure 13 A state during reading data from a memory device according to the first embodiment is shown.

[0020] Figure 14 A state of a memory device according to the first embodiment is shown.

[0021] Figure 15 A state during reading data from a memory device according to the first reference example is shown.

[0022] Figure 16 A state during reading data from a memory device according to the second reference example is shown.

[0023] Figure 17 A state during reading data from a memory device according to the third reference example is shown.

[0024] Figure 18 Components and a state during data reading of a memory device according to the fourth reference example are shown.

[0025] Figure 19Details of some functional blocks of the memory device according to the second embodiment are shown.

[0026] Figure 20 An example of components and connections of the row selector and the column selector according to the second embodiment is shown.

[0027] Figure 21 States during reading data from the memory device according to the second embodiment are shown. DETAILED DESCRIPTION

[0028] Embodiments will now be described with reference to the accompanying drawings. In the following description, like drawing reference numerals are used for like elements having substantially the same functions and configurations, and repetitive description can be omitted. In order to distinguish between elements having substantially the same function and configuration from each other, an additional number or letter can be added to the end of each drawing reference numeral.

[0029] Unless explicitly mentioned or apparently excluded, the entire description for a certain embodiment is also applicable to another embodiment.

[0030] In the specification and claims, the phrase that a certain first component is “coupled” to another second component includes that the first component is coupled to the second component directly or through one or more conductive components that are always or selectively conductive.

[0031] Embodiments will be described by using an xyz orthogonal coordinate system. In the following description, the term “under” and terms and related terms derived thereof refer to a position having a smaller coordinate on the z-axis, and the term “above” and terms and related terms derived thereof refer to a position having a larger coordinate on the z-axis.

[0032] 1. First Embodiment

[0033] 1.1. Structure (Configuration)

[0034] 1.1.1. Overall Structure

[0035] Figure 1 Functional blocks of the variable resistance memory device of the first embodiment are shown. As shown, the memory device 1 includes a memory cell array 11, an input / output circuit 12, a control circuit 13, a row selector 14, a column selector 15, a write circuit 16, and a read circuit 17. Figure 1

[0036] The memory cell array 11 includes memory cells MC, word lines WL, and bit lines BL. The memory cells MC can store data in a non-volatile manner. Each memory cell MC is coupled to a single word line WL and a single bit line BL. Each word line WL is associated with a row. Each bit line BL is associated with a column. Selection of a row and selection of one or more columns designate one or more memory cells MC.​

[0037] The input / output circuit 12 receives various types of control signals CNT, various types of commands CMD, address signals ADD, and data (write data) DAT from, for example, the memory controller 2, and transmits data (read data) DAT to, for example, the memory controller 2.

[0038] The row selector 14 receives the address signals ADD from the input / output circuit 12, and causes a single word line WL associated with a row designated by the received address signals ADD to enter a selected state.

[0039] The column selector 15 receives the address signals ADD from the input / output circuit 12, and causes a bit line BL associated with a column designated by the received address signals ADD to enter a selected state.

[0040] The control circuit 13 receives the control signals CNT and the commands CMD from the input / output circuit 12. The control circuit 13 controls the write circuit 16 and the read circuit 17 based on the control indicated by the control signals CNT and the commands CMD. Specifically, the control circuit 13 supplies a voltage for data writing to the write circuit 16 during writing of data to the memory cell array 11. Further, the control circuit 13 supplies a voltage for data reading to the read circuit 17 during reading of data from the memory cell array 11.

[0041] The write circuit 16 receives the write data DAT from the input / output circuit 12, and supplies a voltage for data writing to the column selector 15 based on the control of the control circuit 13 and the write data DAT.

[0042] The read circuit 17 includes a sense amplifier SA, and determines data stored in the memory cell MC using a voltage for data reading based on the control of the control circuit 13. The determined data is supplied as read data DAT to the input / output circuit 12.

[0043] 1.1.2. Circuit structure of memory cell array

[0044] Figure 2 is a circuit diagram of the memory cell array 11 according to the first embodiment. As shown in Figure 2 The memory cell array 11 includes (M+1) word lines WLa (WLa<0>, WLa<1>,..., and WLa <m>) and (M+1) word lines WLb (WLb<0>, WLb<1>,... and WLb <m>), where M is a natural number.

[0045] The memory cell array 11 also includes (N+1) bit lines BL (BL<0>, BL<1>,..., and BL <n>), where N is a natural number.

[0046] Each memory cell MC (MCa and MCb) includes two nodes: a first node N1 coupled to a single word line WL; and a second node N2 coupled to a single bit line BL. More specifically, the memory cell MCa includes memory cells MCa<α,β> for any combination of α and β, where α is an integer equal to or greater than 0 and equal to or less than M, β is an integer equal to or greater than 0 and equal to or less than N, and the memory cell MCa<α,β> is coupled between the word line WLa<α> and the bit line BL<β>. Similarly, the memory cell MCb includes memory cells MCb<α,β> for any combination of α and β, where α is an integer equal to or greater than 0 and equal to or less than M, β is an integer equal to or greater than 0 and equal to or less than N, and the memory cell MCb<α,β> is coupled between the word line WLb<α> and the bit line BL<β>.

[0047] Each memory cell MC includes a variable resistance element VR (VRa or VRb) and a switching element SE (SEa or SEb). More specifically, the memory cell MCa<α,β> includes a variable resistance element VRa<α,β> and a switching element SEa<α,β> for any combination of α and β, where α is an integer equal to or greater than 0 and equal to or less than M, β is an integer equal to or greater than 0 and equal to or less than N. Further, the memory cell MCb<α,β> includes a variable resistance element VRb<α,β> and a switching element SEb<α,β> for any combination of α and β, where α is an integer equal to or greater than 0 and equal to or less than M, β is an integer equal to or greater than 0 and equal to or less than N.

[0048] In each memory cell MC, the variable resistance element VR and the switching element SE are coupled in series. The variable resistance element VR is coupled to a single word line WL, and the switching element SE is coupled to a single bit line BL.

[0049] The variable resistance element VR can be switched between a low resistance state and a high resistance state. The variable resistance element VR can store 1 bit of data with the difference between the two resistance states.

[0050] For example, the switching element SE can be a switching element described below. The switching element includes two terminals, and when a voltage smaller than a first threshold is applied in a first direction between the two terminals, the switching element is in a high-resistance state, i.e., non-conductive (in an off state). On the other hand, when a voltage equal to or larger than the first threshold is applied in the first direction between the two terminals, the switching element is in a low-resistance state, i.e., conductive (in an on state). The switching element is also equipped with a function similar to switching between the high-resistance state and the low-resistance state based on the magnitude of the voltage applied in the first direction (with respect to a second direction opposite to the first direction). By turning on or off the switching element, control can be performed on whether to supply a current to the variable resistance element VR coupled to the switching element (i.e., whether to select the variable resistance element VR).

[0051] 1.1.3. Structure of memory cell array

[0052] Figure 3 and Figure 4 A cross-sectional structure of a portion of the memory cell array 11 of the first embodiment is shown. Figure 3 A cross-section along the xz plane is shown, Figure 4 A cross-section along the yz plane is shown. Figure 3 and Figure 4 An example in which the variable resistance element VR is a magnetoresistance effect element is shown. The following description is based on this example.

[0053] As Figure 3 and Figure 4 A plurality of conductors 21 are provided above a semiconductor substrate (not shown). The conductors 21 extend along the y axis and are aligned along the x axis. Each conductor 21 functions as a word line WL.

[0054] Each conductor 21 is coupled at its top surface to a bottom surface of a plurality of memory cells MCb. For example, each memory cell MCb has a circular shape in the xy plane. The memory cells MCb are aligned along the y axis on each conductor 21, and this arrangement provides a matrix of memory cells MCb on the xy plane. Each memory cell MCb includes a structure functioning as a switching element SEb and a structure functioning as a magnetoresistance effect element VRb. The structure functioning as a switching element SEb and the structure functioning as a magnetoresistance effect element VRb each have one or more layers, as described below.

[0055] A plurality of conductors 22 are provided above the memory cells MCb. The conductors 22 extend along the x axis and are aligned along the y axis. Each conductor 22 is coupled at its bottom surface to a top surface of a plurality of memory cells MCb aligned along the x axis. Each conductor 22 functions as a bit line BL.

[0056] Each conductor 22 is coupled at its top surface to the bottom surface of a plurality of memory cells MCa. Each memory cell MCa has, for example, a circular shape in the xy-plane. The memory cells MCa are arranged along the x-axis on each conductor 22, and this arrangement provides a matrix of memory cells MCa in the xy-plane. Each memory cell MCa includes a structure serving as a switching element SEa and a structure serving as a magnetoresistive effect element VRa. As described below, the structure serving as the switching element SEa and the structure serving as the magnetoresistive effect element VRa each have one or more layers.

[0057] An additional conductor 21 is placed on the top surface of the memory cells MCa arranged along the y-axis.

[0058] Repeat along the z-axis Figure 3 and Figure 4 The structure shown extends from the bottom conductor 21 layer to the memory cell MCa layer, thereby enabling the realization of... Figure 2 The memory primitive array 11 shown.

[0059] The memory cell array 11 also includes interlayer insulators located in regions in which conductors 21 and 22 and memory cells MC are not disposed.

[0060] Figure 5 A cross-section of an example structure of a memory primitive MC according to a first embodiment is shown. Figure 5 As shown, the switching element SE includes a lower electrode 24, a variable resistive material (layer) 25, and an upper electrode 26. The lower electrode 24 is located on the top surface of conductor 21 or 22 (not shown). The variable resistive material 25 is located on the top surface of the lower electrode 24. The upper electrode 26 is located on the top surface of the variable resistive material 25.

[0061] Each of the lower electrode 24 and the upper electrode 26 comprises, for example, titanium nitride (TiN) or is made of, for example, titanium nitride (TiN).

[0062] The variable resistive material 25 is, for example, a switching element between two terminals. The first terminal of the two terminals is one of the top surface and the bottom surface of the variable resistive material 25, and the second terminal of the two terminals is the other of the top surface and the bottom surface of the variable resistive material 25.

[0063] A single magnetoresistive element VR is located on the top surface of each upper electrode 26. The magnetoresistive element VR exhibits tunnel magnetoresistive properties and includes a magnetic tunnel junction (MTJ). In this embodiment, an MTJ element used as a memory element is used for description. Note that, for ease of description, the MTJ element will be referred to hereinafter as the magnetoresistive element VR. More specifically, the magnetoresistive element VR includes a ferromagnetic layer 31, an insulating layer 32, and a ferromagnetic layer 33. For example, as Figure 5 As shown, the insulating layer 32 is located on a top surface of the ferromagnetic layer 31, and the ferromagnetic layer 33 is located on a top surface of the insulating layer 32.

[0064] The ferromagnetic layer 31 has an easy axis in a direction across the interface between the ferromagnetic layer 31, the insulating layer 32, and the ferromagnetic layer 33, e.g., at an angle of 45° to 90° with respect to the interface, or in a direction orthogonal to the interface. The magnetization direction of the ferromagnetic layer 31 is intended to remain unchanged even when data is read or written in the memory device 1. The ferromagnetic layer 31 can be used as a so-called reference layer. The ferromagnetic layer 31 can include a stacked ferromagnetic layer and / or a conductive layer.

[0065] The insulating layer 32 contains or is made of, for example, magnesium oxide (MgO), and is used as a so-called "tunnel barrier".

[0066] For example, the ferromagnetic layer 33 contains or is made of cobalt iron boron (CoFeB) or iron boron (FeB). The ferromagnetic layer 33 has an easy axis in a direction across the interface between the ferromagnetic layer 31, the insulating layer 32, and the ferromagnetic layer 33, e.g., at an angle of 45° to 90° with respect to the interface, or in a direction orthogonal to the interface. The magnetization direction of the ferromagnetic layer 33 can be changed by data writing, and the ferromagnetic layer 33 can be used as a so-called "storage layer".

[0067] When the magnetization direction of the ferromagnetic layer 33 is parallel to the magnetization direction of the ferromagnetic layer 31, the magnetoresistive effect element VR is in a state having a lower resistance. When the magnetization direction of the ferromagnetic layer 33 is anti-parallel to the magnetization direction of the ferromagnetic layer 31, the magnetoresistive effect element VR is in a state having a higher resistance than in the case where the magnetization directions of the ferromagnetic layers 31 and 33 are anti-parallel to each other.

[0068] When a write current Iwp of a certain magnitude flows from the ferromagnetic layer 33 to the ferromagnetic layer 31, the magnetization direction of the ferromagnetic layer 33 becomes parallel to the magnetization direction of the ferromagnetic layer 31. Conversely, when a write current Iwap of another magnitude flows from the ferromagnetic layer 31 to the ferromagnetic layer 33, the magnetization direction of the ferromagnetic layer 33 becomes anti-parallel to the magnetization direction of the ferromagnetic layer 31. By supplying a read current Ir to the magnetoresistive effect element VR, the resistance state of the magnetoresistive effect element VR can be determined based on a voltage across the magnetoresistive effect element VR in the case where the read current is supplied.

[0069] The memory cell MC can further include a conductor, an insulator, and / or a ferromagnet.

[0070] Figure 6 Details of some functional blocks of the memory device 1 according to the first embodiment are shown. More specifically, Figure 6 The components, connections, and layout of a portion of each of the memory cell array 11, the row selector 14, the column selector 15, and the write circuit 16 are shown.

[0071] As Figure 6 illustrated, the memory cell array 11 is divided into four portions. The four portions each have a rectangular shape in the xy plane, do not overlap with each other, and will be hereinafter referred to as sub-arrays 11ul, 11ur, 11dl, and 11dr. The sub-arrays 11ul, 11ur, 11dl, and 11dr have the same or different areas, i.e., include the same or different number of memory cells MC. The sub-arrays 11ul, 11ur, 11dl, and 11dr are separated from each other. The sub-arrays 11ul, 11ur, 11dl, and 11dr each include word lines WL, bit lines BL, and memory cells MC. The sub-arrays 11ul, 11ur, 11dl, and 11dr respectively occupy the upper left, upper right, lower left, and lower right portions of the memory cell array 11 in the xy plane. The sub-arrays 11ul, 11ur, 11dl, and 11dr can hereinafter be respectively referred to as an upper left sub-array 11ul, an upper right sub-array 11ur, a lower left sub-array 11dl, and a lower right sub-array 11dr.

[0072] The word lines WL in the upper left sub-array 11ul and the word lines WL in the upper right sub-array 11ur are common. In other words, each word line WL in the upper left sub-array 11ul extends over the upper left sub-array 11ul and the upper right sub-array 11ur. Hereinafter, the word lines WL that extend over the upper left sub-array 11ul and the upper right sub-array 11ur can be referred to as upper word lines WLu.

[0073] The word lines WL in the lower left sub-array 11dl and the word lines WL in the lower right sub-array 11dr are common. In other words, each word line WL in the lower left sub-array 11dl extends over the lower left sub-array 11dl and the lower right sub-array 11dr. Hereinafter, the word lines WL that extend over the lower left sub-array 11dl and the lower right sub-array 11dr can be referred to as lower word lines WLd.

[0074] The bit lines BL in the upper left sub-array 11ul and the bit lines BL in the lower left sub-array 11dl are common. In other words, each bit line BL in the upper left sub-array 11ul extends over the upper left sub-array 11ul and the lower left sub-array 11dl. Hereinafter, the bit lines BL that extend over the upper left sub-array 11ul and the lower left sub-array 11dl can be referred to as left bit lines BLl.

[0075] The bit lines BL in the upper right sub-array 11ur and the bit lines BL in the lower right sub-array 11dr are common. In other words, each bit line BL in the upper right sub-array 11ur extends over the upper right sub-array 11ur and the lower right sub-array 11dr. Hereinafter, the bit lines BL that extend over the upper right sub-array 11ur and the lower right sub-array 11dr can be referred to as right bit lines BLr.

[0076] Each memory cell MC is located between a single word line WL and a single bit line BL, as referred to in the following Figure 3 and Figure 4 In the following, the memory cells MC located between the upper word line WLu and the left bit line BLl, i.e. the memory cells MC in the upper left subarray 11ul, can be referred to as upper left memory cells MCul.

[0077] In the following, the memory cells MC located between the upper word line WLu and the right bit line BLr, i.e. the memory cells MC in the upper right subarray 11ur, can be referred to as upper right memory cells MCur.

[0078] In the following, the memory cells MC located between the lower word line WLd and the left bit line BLl, i.e. the memory cells MC in the lower left subarray 11dl, can be referred to as lower left memory cells MCdl.

[0079] In the following, the memory cells MC located between the lower word line WLd and the right bit line BLr, i.e. the memory cells MC in the lower right subarray 11dr, can be referred to as lower right memory cells MCdr.

[0080] The row selector 14 extends along the y-axis and is located in the area between the upper left subarray 11ul and the upper right subarray 11ur and in the area between the lower left subarray 11dl and the lower right subarray 11dr. The row selector 14 extends from the upper end of each of the upper left subarray 11ul and the upper right subarray 11ur to the lower end of each of the lower left subarray 11dl and the lower right subarray 11dr.

[0081] The row selector 14 is formed by a first portion 14u and a second portion 14d. The first portion 14u is formed by a portion of the area between the upper left subarray 11ul and the upper right subarray 11ur in the row selector 14. The second portion 14d is formed by a portion of the area between the lower left subarray 11dl and the lower right subarray 11dr in the row selector 14. The first portion 14u can be referred to as upper row selector 14u in the following, the second portion 14d can be referred to as lower row selector 14d in the following.

[0082] The upper row selector 14u is coupled to all upper word lines WLu. The upper row selector 14u receives an address signal ADD and couples one of the upper word lines WLu specified by the address signal ADD to a first node Nl of a sense amplifier SAul (described later). Furthermore, the upper row selector 14u couples one of the upper word lines WLu specified by the address signal ADD to a first node Nl of a sense amplifier SAur (described later).

[0083] The down selector 14d is coupled to all of the down word lines WLd. The down selector 14d receives the address signal ADD and couples one of the down word lines WLd specified by the address signal ADD to a first node N1 of the sense amplifier SAdl (described later). In addition, the down selector 14d couples one of the down word lines WLd specified by the address signal ADD to a first node N1 of the sense amplifier SAdr (described later).

[0084] The column selector 15 extends along the x-axis and is located in a region between the upper left subarray 11ul and the lower left subarray 11dl and in a region between the upper right subarray 11ur and the lower right subarray 11dr. The column selector 15 extends from a left end of each of the upper left subarray 11ul and the lower left subarray 11dl to a right end of each of the upper right subarray 11ur and the lower right subarray 11dr.

[0085] The column selector 15 is formed of a first portion 15l and a second portion 15r. The first portion 15l is formed of a part of the region of the column selector 15 between the upper left subarray 11ul and the lower left subarray 11dl. The second portion 15r is formed of a part of the region of the column selector 15 between the upper right subarray 11ur and the lower right subarray 11dr. The first portion 15l can be referred to hereinafter as a left column selector 15l and the second portion 15r can be referred to hereinafter as a right column selector 15r.

[0086] The left column selector 15l is coupled to all of the left bit lines BLl. The left column selector 15l receives the address signal ADD and couples one of the left bit lines BLl specified by the address signal ADD to a second node N2 of the sense amplifier Sau1. In addition, the left column selector 15l couples one of the left bit lines BLl specified by the address signal ADD to a second node N2 of the sense amplifier SAdl.

[0087] The right column selector 15r is coupled to all of the right bit lines BLr. The right column selector 15r receives the address signal ADD and couples one of the right bit lines BLr specified by the address signal ADD to a second node N2 of the sense amplifier SAur. In addition, the right column selector 15r couples one of the right bit lines BLr specified by the address signal ADD to a second node N2 of the sense amplifier SAdr.

[0088] The sense amplifiers SA (the sense amplifiers SAul, SAur, SAdl, and SAdr) are included in the read circuit 17 and implement at least some of the operations of the read circuit 17. The sense amplifiers SAul, SAur, SAdl, and SAdr can be referred to hereinafter as the upper left sense amplifier SAul, the upper right sense amplifier SAur, the lower left sense amplifier SAdl, and the lower right sense amplifier SAdr, respectively.

[0089] Hereinafter, the first node N1 and the second node N2 of the left upper sense amplifier SAul can be referred to as a first node N1ul and a second node N2ul, respectively. Hereinafter, the first node N1 and the second node N2 of the right upper sense amplifier SAur can be referred to as a first node N1ur and a second node N2ur, respectively. Hereinafter, the first node N1 and the second node N2 of the left lower sense amplifier SAdl can be referred to as a first node N1dl and a second node N2dl, respectively. Hereinafter, the first node N1 and the second node N2 of the right lower sense amplifier SAdr can be referred to as a first node N1dr and a second node N2dr, respectively.

[0090] The first node N1ul of the left upper sense amplifier SAul is coupled to the upper selector 14u. The first node N1ul of the left upper sense amplifier SAul can be coupled to one of the upper bit lines WLu through the upper selector 14u as described above.

[0091] The second node N2ul of the left upper sense amplifier SAul is coupled to the left column selector 15l. The second node N2ul of the left upper sense amplifier SAul can be coupled to one of the left bit lines BLl through the left column selector 15l as described above.

[0092] The left upper sense amplifier SAul is coupled at the second node N2ul to a node in the left upper sense amplifier SAul at which a high potential (e.g., a power supply potential) occurs, and is coupled at the first node N1ul to a node in the left upper sense amplifier SAul at which a low potential (e.g., a ground potential) occurs. The potential of the second node N2ul is lower than the potential of the first node N1ul. The left upper sense amplifier SAul is configured to supply a current from the second node N2ul and also draw a current at the first node N1ul. In addition, the left upper sense amplifier SAul can obtain data stored in a read target memory cell MC (hereinafter referred to as a selected memory cell MCS) coupled to the left upper sense amplifier SAul. That is, the left upper sense amplifier SAul receives a reference voltage Vref and can compare the reference voltage Vref with a voltage of a node (hereinafter sometimes referred to as a sense node SEN) in the left upper sense amplifier SAul at which a voltage based on a resistance state of the selected memory cell MCS occurs. The left upper sense amplifier SAul can output a voltage based on the state of the selected memory cell MCS by operating when the selected memory cell MCS is coupled between the first node N1ul and the second node N2ul, based on which of the two compared voltages is higher.

[0093] The first node Nlur of the upper-right sense amplifier SAur is coupled to the upper-row selector 14u. The first node Nlur of the upper-right sense amplifier SAur can be coupled to one of the upper word lines WLu through the upper-row selector 14u as described above.

[0094] The second node N2ur of the upper-right sense amplifier SAur is coupled to the right-column selector 15r. The second node N2ur of the upper-right sense amplifier SAur can be coupled to one of the right bit lines BLr through the right-column selector 15r as described above.

[0095] The upper-right sense amplifier SAur is coupled at the second node N2ur to a node in the upper-right sense amplifier SAur that is at a high potential (e.g., a power supply potential) and at the first node Nlur to a node in the upper-right sense amplifier SAur that is at a low potential (e.g., a ground potential). The potential of the second node N2ur is lower than the potential of the first node Nlur. The upper-right sense amplifier SAur is configured to source current from the second node N2ur and sink current at the first node Nlur. In addition, the upper-right sense amplifier SAur can obtain data stored in the selected memory cell MCS coupled to the upper-right sense amplifier SAur. That is, the upper-right sense amplifier SAur receives the reference voltage Vref and can compare the reference voltage Vref to a voltage of a sense node SEN of the upper-right sense amplifier SAur. The upper-right sense amplifier SAur can output a voltage based on a state of the selected memory cell MCS by operating when the selected memory cell MCS is coupled between the first node Nlur and the second node N2ur based on which of the two compared voltages is higher.

[0096] The first node Nldl of the lower-left sense amplifier SAdl is coupled to the lower-row selector 14d. The first node Nldl of the lower-left sense amplifier SAdl can be coupled to one of the lower word lines WLd through the lower-row selector 14d as described above.

[0097] The second node N2dl of the lower-left sense amplifier SAdl is coupled to the left-column selector 15l. The second node N2dl of the lower-left sense amplifier SAdl can be coupled to one of the left bit lines BLl through the left-column selector 15l as described above.

[0098] The left-down sense amplifier SAdl is coupled to a node in the left-down sense amplifier SAdl that is at a high potential (e.g., a power supply potential) at a first node Nldl and to a node in the left-down sense amplifier SAdl that is at a low potential (e.g., a ground potential) at a second node N2dl. The potential of the first node Nldl is lower than the potential of the second node N2dl. The left-down sense amplifier SAdl is configured to source current from the first node Nldl and sink current at the second node N2dl. In addition, the left-down sense amplifier SAdl can obtain data stored in a selected memory cell MCS coupled to the left-down sense amplifier SAdl. That is, the left-down sense amplifier SAdl receives a reference voltage Vref and can compare the reference voltage Vref to a voltage of a sense node SEN of the left-down sense amplifier SAdl. The left-down sense amplifier SAdl can output a voltage based on a state of the selected memory cell MCS by operating when the selected memory cell MCS is coupled between the first node Nldl and the second node N2dl based on which of the two compared voltages is higher.

[0099] The first node Nldr of the right-down sense amplifier SAdr is coupled to the down selector 14d. The first node Nldr of the right-down sense amplifier SAdr can be coupled to one of the down word lines WLd through the down selector 14d as described above.

[0100] The second node N2dr of the right-down sense amplifier SAdr is coupled to the right column selector 15r. The second node N2dr of the right-down sense amplifier SAdr can be coupled to one of the right bit lines BLr through the right column selector 15r as described above.

[0101] The left-down sense amplifier SAdl is coupled to a node in the left-down sense amplifier SAdl that is at a high potential (e.g., a power supply potential) at a first node Nldl and to a node in the left-down sense amplifier SAdl that is at a low potential (e.g., a ground potential) at a second node N2dl. The potential of the first node Nldl is lower than the potential of the second node N2dl. The left-down sense amplifier SAdl is configured to source current from the first node Nldl and sink current at the second node N2dl. In addition, the left-down sense amplifier SAdl can obtain data stored in a selected memory cell MCS coupled to the left-down sense amplifier SAdl. That is, the left-down sense amplifier SAdl receives a reference voltage Vref and can compare the reference voltage Vref to a voltage of a sense node SEN of the left-down sense amplifier SAdl. The left-down sense amplifier SAdl can output a voltage based on a state of the selected memory cell MCS by operating when the selected memory cell MCS is coupled between the first node Nldl and the second node N2dl based on which of the two compared voltages is higher.

[0102] 1.1.3.1. Details of row selector and column selector

[0103] Figure 7 An example of components and connections of the row selector 14 and the column selector 15 according to the first embodiment is shown.

[0104] As Figure 7 shown, the upper row selector 14u includes a plurality of local row switches TLYu, local word lines LWLu, a global row switch TGYu, and a global word line GWLu. Each local row switch TLYu is coupled between a single upper word line WLu and a local word line LWLu. Each local row switch TLYu receives, at its control terminal, a control signal LYu (LYul, LYu2,..., or LYut (t is a natural number)) unique to the local row switch TLYu from another component (not shown) in the row selector 14, and is turned on or off based on the control signal LYu. Each local row switch TLYu can be an n-type metal oxide semiconductor field effect transistor (MOSFET), and receives the control signal LYu at its gate terminal. The upper row selector 14u sets the control signal LYu provided to only one of the plurality of local row switches TLYu specified by the address signal ADD to a level for specifying selection (e.g., a high level). As a result, among the plurality of local row switches TLYu, only the local row switch TLYu that receives the control signal LYu for specifying selection remains turned on.

[0105] When one of the plurality of local row switches TLYu is turned on, the upper word line WLu coupled to the local row switch TLYu is coupled to the local word line LWLu via the local row switch TLYu.

[0106] The local word line LWLu is coupled to the global word line GWLu via the global row switch TGYu. The global row switch TGYu receives, at its control terminal, a control signal GY from another component (not shown) in the row selector 14, and is turned on or off based on the control signal GY. The global row switch TGYu can be an n-type MOSFET, and receives the control signal GY at its gate terminal.

[0107] The down selector 14d includes a plurality of local row switches TLYd, a local word line LWLd, a global row switch TGYd, and a global word line GWLd. Each local row switch TLYd is coupled between a single down word line WLd and the local word line LWLd. Each local row switch TLYd receives at its control terminal a control signal LYd (LYdl, LYd2,..., or LYds (s is a natural number)) unique to the local row switch TLYd from another component (not shown) in the row selector 14 and is turned on or off based on the control signal LYd. Each local row switch TLYd can be an n-type MOSFET and receives the control signal LYd at its gate terminal. The down selector 14d sets the control signal LYd supplied to only one of the plurality of local row switches TLYd specified by the address signal ADD to a level for specifying selection (e.g., a high level). As a result, among the plurality of local row switches TLYd, only the local row switch TLYd that receives the control signal LYd for specifying selection remains on.

[0108] When one of the plurality of local row switches TLYd is on, the down word line WLd coupled to the local row switch TLYd is coupled to the local word line LWLd via the local row switch TLYd.

[0109] The local word line LWLd is coupled to the global word line GWLd via the global row switch TGYd. The global row switch TGYd receives at its control terminal a control signal GY from another component (not shown) in the row selector 14 and is turned on or off based on the control signal GY. The global row switch TGYd can be an n-type MOSFET and receives the control signal GY at its gate terminal.

[0110] The left column selector 15l includes a plurality of local column switches TLXl, a local bit line LBLl, a global column switch TGXl, and a global bit line GBLl. Each local column switch TLXl is coupled between a single left bit line BLl and the local bit line LBLl. Each local column switch TLXl receives at its control terminal a control signal LXl (LXll, LXl2,..., or LXlp (p is a natural number)) unique to the local column switch TLXl from another component (not shown) in the column selector 15 and is turned on or off based on the control signal LXl. Each local column switch TLXl can be an n-type MOSFET and receives the control signal LYl at its gate terminal. The left column selector 15l sets the control signal LYl supplied to only one of the plurality of local column switches TLXl specified by the address signal ADD to a level for specifying selection (e.g., a high level). As a result, among the plurality of local column switches TLXl, only the local column switch TLXl that receives the control signal LYl for specifying selection remains on.

[0111] When one of the plurality of local column switches TLXl is on, the left bit line BLl coupled to the local column switch TLXl is coupled to the local bit line LBLl via the local column switch TLXl.

[0112] The local bit line LBLl is coupled to the global bit line GBLl through the global column switch TGXl. The global column switch TGXl receives a control signal GX at its control terminal from another component (not shown) in the column selector 15, and is turned on or off based on the control signal GX. The global column switch TGXl can be an n-type MOSFET, and receives the control signal GX at its gate terminal.

[0113] The right column selector 15r includes a plurality of local column switches TLXr, a local bit line LBLr, a global column switch TGXr, and a global bit line GBLr. Each local column switch TLXr is coupled between a single right bit line BLr and the local bit line LBLr. Each local column switch TLXr receives a control signal LXr (LXrl, LXr2,..., or LXrq (q is a natural number)) unique to the local column switch TLXr at its control terminal from another component (not shown) in the column selector 15, and is turned on or off based on the control signal LXr. Each local column switch TLXr can be an n-type MOSFET, and receives the control signal LYr at its gate terminal. The right column selector 15r sets the control signal LYr provided to only one of the plurality of local column switches TLXr specified by the address signal ADD to a level for specifying selection (e.g., a high level). As a result, among the plurality of local column switches TLXr, only the local column switch TLXr that receives the control signal LYr for specifying selection remains on.

[0114] When one of the plurality of local column switches TLXr is on, the right bit line BLr coupled to the local column switch TLXr is coupled to the local bit line LBLr via the local column switch TLXr.

[0115] The local bit line LBLr is coupled to the global bit line GBLr through the global column switch TGXr. The global column switch TGXr receives a control signal GX at its control terminal from another component (not shown) in the column selector 15, and is turned on or off based on the control signal GX. The global column switch TGXr can be an n-type MOSFET, and receives the control signal GX at its gate terminal.

[0116] 1.1.3.2. Details of sense amplifier

[0117] Each of the left upper sense amplifier SAul and the right upper sense amplifier SAur can comprise any components and connections as long as it is able to provide a current from its second node N2, draw a current at its first node Nl, and obtain read data based on the voltage of the sense node SEN and the reference voltage Vref as described above. Similarly, each of the left lower sense amplifier SAdl and the right lower sense amplifier SAdr can comprise any components and connections as long as it is able to provide a current from its first node Nl, draw a current at its second node N2, and obtain read data based on the voltage of the sense node SEN and the reference voltage Vref.

[0118] Some detailed examples will be described below. However, the details of the left upper sense amplifier SAul, the right upper sense amplifier SAur, the left lower sense amplifier SAdl, and the right lower sense amplifier SAdr do not limit the first embodiment.

[0119] 1.1.3.2.1. First example

[0120] Figure 8 A first example of components and connections of the left upper sense amplifier SAul or the right upper sense amplifier SAur according to the first embodiment is shown. As shown, each of the left upper sense amplifier SAul and the right upper sense amplifier SAur comprises a p-type MOSFET TP11, n-type MOSFETs TN11 and TN12, and an operational amplifier OP1. Figure 8

[0121] The transistor TP11 is coupled at its first terminal (one of the source and the drain) to a node of a supply potential (e.g., Vdd) and at its second terminal (the other of the source and the drain) to its gate and the first terminal of the transistor TN11. The gate of the transistor TP11 serves as the sense node SEN and is coupled to the non-inverting input terminal of the operational amplifier OP1.

[0122] The operational amplifier OP1 receives the reference voltage Vref at its inverting input terminal. The data latches in the read circuit 17 receive the output from the operational amplifier OP1.

[0123] The second terminal of the transistor TN11 is coupled to the second node N2ul in the left upper sense amplifier SAul and to the second node N2ur in the right upper sense amplifier SAur. The gate of the transistor TN11 receives the enable signal EN. The enable signal EN is provided, for example, by the control circuit 13.

[0124] ​The first terminal of the transistor TN12 is coupled to a first node N1ul in the upper left sense amplifier SAul and to a first node N1ur in the upper right sense amplifier SAur. The second terminal of the transistor TN12 is coupled to a node of a common potential (e.g., ground potential Vss). The gate of the transistor TN12 receives an enable signal EN.

[0125] Figure 9 A first example of components and connections of the lower left sense amplifier SAdl or the lower right sense amplifier SAdr according to the first embodiment is shown. As shown in Figure 9 Each of the lower left sense amplifier SAdl and the lower right sense amplifier SAdr includes a p-type MOSFET TP21, n-type MOSFETs TN21 and TN22, and an operational amplifier OP2.

[0126] The transistor TP21 is coupled at its first terminal to a node of a supply potential and at its second terminal to its gate and the first terminal of the transistor TN21. The gate of the transistor TP21 serves as a sense node SEN and is coupled to a non-inverting input terminal of the operational amplifier OP2.

[0127] The operational amplifier OP2 receives at its inverting input terminal a reference voltage Vref. The data latches in the read circuit 17 receive an output from the operational amplifier OP2.

[0128] The second terminal of the transistor TN21 is coupled to a first node N1dl in the lower left sense amplifier SAdl and to a first node N1dr in the lower right sense amplifier SAdr. The gate of the transistor TN21 receives an enable signal EN.

[0129] The first terminal of the transistor TN22 is coupled to a second node N2dl in the lower left sense amplifier SAdl and to a second node N2dr in the lower right sense amplifier SAdr. The second terminal of the transistor TN22 is coupled to a node of a ground potential. The gate of the transistor TN22 receives an enable signal EN.

[0130] 1.1.3.2.2. Second example

[0131] Figure 10 A second example of components and connections of the lower left sense amplifier SAdl or the lower right sense amplifier SAdr according to the first embodiment is shown. As shown in Figure 10 Each of the lower left sense amplifier SAdl and the lower right sense amplifier SAdr includes a n-type MOSFET TN31, p-type MOSFETs TP31 and TP32, and an operational amplifier OP3.

[0132] The transistor TP31 is coupled at its first terminal to a node of the power supply potential. The second terminal of the transistor TP31 is coupled to a first node N1dl in the lower left sense amplifier SAdl and to a first node N1dr in the lower right sense amplifier SAdr. The gate of the transistor TP31 receives an enable signal EN. The symbol "-" indicates that the signal to which the symbol "-" is added has the logic obtained by inverting the logic of the signal whose name does not contain the symbol "-".

[0133] The transistor TN31 is coupled at its first terminal to a second node N2dl in the lower left sense amplifier SAdl and to a second node N2dr in the lower right sense amplifier SAdr. The transistor TN31 is coupled at its first terminal to its gate. The gate of the transistor TN31 serves as a sense node SEN and is coupled to a non-inverting input terminal of the operational amplifier OP3. The operational amplifier OP3 receives a reference voltage Vref at its inverting input terminal. The data latch in the read circuit 17 receives an output from the operational amplifier OP3.

[0134] The second terminal of the transistor TN31 is coupled to a first terminal of the transistor TP32. The transistor TP32 is coupled at its second terminal to a node of the ground potential and receives at its gate the enable signal EN.

[0135] EN.

[0136] 1.2. Operation

[0137] Figure 11 The state during reading of data from the memory device 1 according to the first embodiment is shown. Figure 11 The same components and ranges as in Figure 6 are shown, and are similar to Figure 6 , which indicates the layout.

[0138] The memory device 1 reads data in parallel from the selected upper left memory cell MCulS of the upper left memory cell MCul and the selected lower right memory cell MCdrS of the lower right memory cell MCdr, or from the selected upper right memory cell MCurS of the upper right memory cell MCur and the selected lower left memory cell MCdlS of the lower left memory cell MCdl. Figure 11 An example involving reading of data from the selected upper left memory cell MCulS and the selected lower right memory cell MCdrS is shown. Figure 11 Only components associated with reading of data from the selected upper left memory cell MCulS and the selected lower right memory cell MCdrS are shown.

[0139] When the local row switch TLYu (not shown) coupled to the upper word line WLu to which the selected left upper memory cell MCulS is coupled is turned on, the upper word line WLu is coupled to the local word line LWLu. Further, when the global row switch TGYu (not shown) is turned on, the local word line LWLu is coupled to the first node Nlul of the left upper sense amplifier SAul. Hereinafter, the upper word line WLu coupled to the selected left upper memory cell MCulS can be referred to as the selected upper word line WLuS.

[0140] When the local column switch TLXl (not shown) coupled to the left bit line BLl to which the selected left upper memory cell MCulS is coupled is turned on, the left bit line BLl is coupled to the local bit line LBLl. Further, when the global column switch TGXl (not shown) is turned on, the local bit line LBLl is coupled to the second node N2ul of the left upper sense amplifier SAul. Hereinafter, the left bit line BLl coupled to the selected left upper memory cell MCulS can be referred to as the selected left bit line BLlS.

[0141] The state in which the selected left upper memory cell MCulS is coupled to the first node Nlul and the second node N2ul of the left upper sense amplifier SAul via the local row switch TLYu and the local column switch TLXl coupled to the selected left upper memory cell MCulS and turned on, as described above, can be referred to as a left upper memory cell selected state hereinafter.

[0142] When the local row switch TLYd (not shown) coupled to the lower word line WLd to which the selected right lower memory cell MCdrS is coupled is turned on, the lower word line WLd is coupled to the local word line LWLd. Further, when the global row switch TGYd (not shown) is turned on, the local word line LWLd is coupled to the first node Nldr of the right lower sense amplifier SAdr. Hereinafter, the lower word line WLd coupled to the selected right lower memory cell MCdrS can be referred to as the selected lower word line WLdS.

[0143] When the local column switch TLXr (not shown) coupled to the right bit line BLr to which the selected right lower memory cell MCdrS is coupled is turned on, the right bit line BLr is coupled to the local bit line LBLr. Further, when the global column switch TGXr (not shown) is turned on, the local bit line LBLr is coupled to the second node N2dr of the right lower sense amplifier SAdr. Hereinafter, the right bit line BLr coupled to the selected right lower memory cell MCdrS can be referred to as the selected right bit line BLrS.

[0144] The state as follows can be referred to as the right lower memory cell selected state in the following: in this state, as described above, the selected right lower memory cell MCdrS is coupled to the first node Nl dr and the second node N2 dr of the right lower sense amplifier SAdr via the local row switch TLYd and the local column switch TLXr coupled to and turned on with the selected right lower memory cell MCdrS.

[0145] In the local row switches TLYu and TLYd and the local column switches TLXl and TLXr, the switches that do not contribute to the formation of either of the left upper memory cell selected state and the right lower memory cell selected state remain turned off during the left upper memory cell selected state and the right lower memory cell selected state.

[0146] In the state in which both the left upper memory cell selected state and the right lower memory cell selected state are formed as described above, the enable signals EN of the left upper sense amplifier SAul and the right lower sense amplifier SAdr are set to high level. This enables the left upper sense amplifier SAul and the right lower sense amplifier SAdr to start reading data from the selected left upper memory cell MCulS and the selected right lower memory cell MCdrS.

[0147] With the start of the data reading, in the left upper subarray 11ul, the selected left bit line BLlS is coupled to a node of the power supply potential via the left upper sense amplifier SAul, and the selected upper word line WLuS is coupled to a node of the ground potential via the left upper sense amplifier SAul. Thus, in the selected left upper memory cell MCulS, a read current Irul flows from the selected left bit line BLlS to the selected upper word line WLuS. The read current Irul has a magnitude based on the resistive state of the selected left upper memory cell MCulS and affects the voltage of the sense node SEN in the left upper sense amplifier SAul, i.e. the voltage of the non-inverting input terminal of the operational amplifier OP1. The left upper sense amplifier SAul outputs a voltage based on the voltage of the non-inverting input terminal of the operational amplifier OP1. The voltage thus output reflects the resistive state of the selected left upper memory cell MCulS and is the data read from the selected left upper memory cell MCulS.

[0148] With the commencement of data reading, in the lower right subarray 11dr, the selected lower word line WLdS is coupled to a node at the power supply potential via the lower right sense amplifier SAdr, and the selected right bit line BLrS is coupled to a node at the ground potential via the lower right sense amplifier Sadr. Therefore, in the selected lower right memory cell MCdrS, the read current Irdr flows from the selected lower word line WLdS to the selected right bit line BLrS. The read current Irdr has a magnitude based on the resistance state of the selected lower right memory cell MCdrS and affects the voltage of the sense node SEN in the lower right sense amplifier SAdr, i.e., the voltage at the non-inverting input terminal of operational amplifier OP2. The lower right sense amplifier SAdr outputs a voltage based on the voltage at the non-inverting input terminal of operational amplifier OP2. This output voltage reflects the resistance state of the selected lower right memory cell MCdrS and the data read from the selected lower right memory cell MCdrS.

[0149] Data reading from the selected top-left memory cell MCulS and data reading from the selected bottom-right memory cell MCdrS can occur in parallel.

[0150] Figure 12 The state of the memory device according to the first embodiment is shown. More specifically, Figure 12 Further demonstrated in relation to Figure 11 The same top-left memory cell and bottom-right memory cell are not in the selected state. Figure 11 Some components are shown in the diagram. In the following description, the word line WL and bit line BL of a node coupled to the power supply potential via the sense amplifier SA are referred to as being at a high (H) level. The word line WL and bit line BL of a node coupled to the ground potential via the sense amplifier SA are referred to as being at a low (L) level.

[0151] like Figure 12 As shown, a high-level voltage is applied to the selected left bit line BLlS to form a left upper memory cell selected state, and a high-level voltage is applied to the selected lower word line WLdS to form a right lower memory cell selected state. The selected left bit line BLlS at a high level applies a high-level voltage to the second node of the left lower memory cell MCdl coupled to the selected left bit line BLlS, which can be referred to hereinafter as an unselected left lower memory cell MCdlh. However, the first node of the unselected left lower memory cell MCdlh is applied a high-level voltage by the selected lower word line WLdS at a high level. That is, the same voltage is applied to both terminals of the unselected left lower memory cell MCdlh. Therefore, a read current does not flow or hardly flows in the unselected left lower memory cell MCdlh, and no data read from the unselected left lower memory cell MCdlh occurs. That is, the resistance state of the unselected left lower memory cell MCdlh is inhibited from interfering with the data read from the selected left upper memory cell MCulS and the selected right lower memory cell MCdrS.

[0152] Similarly, a low-level voltage is applied to the selected upper word line WLuS to form a left upper memory cell selected state, and a low-level voltage is applied to the selected right bit line BLrS to form a right lower memory cell selected state. The selected upper word line WLuS at a low level applies a low-level voltage to the first node of the right upper memory cell MCur coupled to the selected left bit line BLlS, which can be referred to hereinafter as an unselected right upper memory cell MCurh. However, the second node of the unselected right upper memory cell MCurh is applied a low-level voltage by the selected right bit line BLrS at a low level. That is, the same voltage is applied to both terminals of the unselected right upper memory cell MCurh. Therefore, a read current does not flow or hardly flows in the unselected right upper memory cell MCurh, and no data read from the unselected right upper memory cell MCurh occurs. That is, the resistance state of the unselected right upper memory cell MCurh is inhibited from interfering with the data read from the selected left upper memory cell MCulS and the selected right lower memory cell MCdrS.

[0153] The parallel data read from the selected right upper memory cell MCurS in the right upper memory cell MCur and the selected left lower memory cell MCdlS in the left lower memory cell MCdl is similarly performed by the same principle as that of the data read from the selected left upper memory cell MCulS and the selected right lower memory cell MCdrS. The outline is as follows.

[0154] Figure 13 States during the data read from the memory device 1 according to the first embodiment are shown. Figure 13 The same components and ranges are shown and similar to Figure 6 , indicating the layout. Figure 6 The example involves reading data from the selected upper-right memory cell MCurS and the selected lower-left memory cell MCdlS. Figure 13 Only components associated with reading data from the selected upper-right memory cell MCurS and the selected lower-left memory cell MCdlS are shown. Figure 13

[0155] The selected upper-right memory cell MCurS is coupled to the first node Nlur and the second node N2ur of the upper-right sense amplifier SAur via the local row switch TLYu (not shown) and the local column switch TLXr (not shown) that are coupled to and turned on by the selected upper-right memory cell MCurS. Thereby, an upper-right memory cell selected state is formed.

[0156] In addition, the selected lower-left memory cell MCdlS is coupled to the first node Nldl and the second node N2dl of the lower-left sense amplifier SAdl via the local row switch TLYd (not shown) and the local column switch TLXl (not shown) that are coupled to and turned on by the selected lower-left memory cell MCdlS. Thereby, a lower-left memory cell selected state is formed.

[0157] In a state where both the upper-right memory cell selected state and the lower-left memory cell selected state are formed, the enable signals EN of the upper-right sense amplifier SAur and the lower-left sense amplifier SAdl are set to high level. This will enable the upper-right sense amplifier SAur and the lower-left sense amplifier SAdl.

[0158] In the upper-right subarray 11ur, the selected right bit line BLrS is coupled to a node of the power supply potential via the upper-right sense amplifier SAur, and the selected upper word line WLuS is coupled to a node of the ground potential via the upper-right sense amplifier SAur. Therefore, in the selected upper-right memory cell MCurS, a read current Irur flows from the selected right bit line BLrS to the selected upper word line WLuS. Thereby, the upper-right sense amplifier SAur obtains data read from the selected upper-right memory cell MCurS.

[0159] In the lower-left subarray 11dl, the selected lower word line WLdS is coupled to a node of the power supply potential via the lower-left sense amplifier SAdl, and the selected left bit line BLlS is coupled to a node of the ground potential via the lower-left sense amplifier SAdl. Therefore, in the selected lower-left memory cell MCdlS, a read current Irdl flows from the selected lower word line WLdS to the selected left bit line BLlS. Thereby, the lower-left sense amplifier SAdl obtains data read from the selected lower-left memory cell MCdlS. ​

[0160] In Figure 13 As shown in the data read, likewise, the data read from the selected upper-right memory cell MCurS and the selected lower-left memory cell MCdlS is not disturbed by the resistance state of the upper-left memory cell MCul or the lower-right memory cell MCdr, as Figure 14 shown. Figure 14 The state of the memory device according to the first embodiment is shown.

[0161] To form the upper-right memory cell selected state, a high-level voltage is applied to the selected right bit line BLrS, and a low-level voltage is applied to the selected upper word line WLuS. To form the lower-left memory cell selected state, a high-level voltage is applied to the selected lower word line WLdS, and a low-level voltage is applied to the selected left bit line BLlS. The selected left bit line BLlS applies a low-level voltage to a second node of the upper-left memory cell MCul coupled with the selected upper word line WLuS at a low level, which can be referred to hereinafter as the unselected upper-left memory cell MCulh. Thus, the same voltage is applied to both terminals of the unselected upper-left memory cell MCulh, and a read current does not flow or hardly flows in the unselected upper-left memory cell MCulh at all.

[0162] Similarly, the selected lower word line WLdS applies a high-level voltage to a first node of the lower-right memory cell MCdr coupled with the selected right bit line BLrS at a high level, which can be referred to hereinafter as the unselected lower-right memory cell MCdrh. Thus, the same voltage is applied to both terminals of the unselected lower-right memory cell MCdrh, and a read current does not flow or hardly flows in the unselected lower-right memory cell MCdrh at all.

[0163] 1.3. Advantages (beneficial effects)

[0164] According to the first embodiment, as described below, it is possible to provide a memory device 1 capable of efficiently reading data while avoiding an increase in area of each of the row selector 14 and the column selector 15.

[0165] Data can be read from the memory cell array 11 including the upper-left subarray 11ul, the upper-right subarray 11ur, the lower-left subarray 11dl, and the lower-right subarray 11dr as follows.

[0166] Figure 15 Some components of the memory device 100 and states during data read according to the first reference example are shown. The memory device 100 includes only a single sense amplifier 41a for the memory cell array 11. The sense amplifier 41a includes the same components and connections as those of the left-up sense amplifier SAul or the right-up sense amplifier SAur, and provides a read current Ir from the second node N2 to the first node N1. Since the memory device 100 includes only a single sense amplifier 41, a single data read operation can read data from only a single memory cell MC. To be able to read data from two memory cells MC by a single data read operation, it is considered that Figure 16 the configuration shown.

[0167] Figure 16 Some components of the memory device 200 and states during data read according to the second reference example are shown. The memory device 200 includes two sense amplifiers 41a and 41b. Each of the sense amplifiers 41a and 41b includes the same components and connections as those of the left-up sense amplifier SAur, and provides a read current Ir from the second node N2 to the first node N1. The first node N1 of the sense amplifier 41a is coupled to the global word line GWLu, and the second node N2 of the sense amplifier 41a is coupled to the global bit line GBLl. The first node N1 of the sense amplifier 41b is coupled to the global word line GWLu, and the second node N2 of the sense amplifier 41b is coupled to the global bit line GBLr.

[0168] As described with reference to Figure 7 The plurality of upper word lines WLu share a single local word line LWLu. Therefore, two memory cells MC from which data can be read in parallel need to be coupled to a single upper word line WLu. Data is read from the selected left-up memory cell MCulS and the selected right-up memory cell MCurS that satisfy the above condition. To this end, the selected left bit line BLlS and the selected right bit line BLrS are applied with a high-level voltage via the sense amplifiers 41a and 41b, respectively. The selected upper word line WLuS is applied with a low-level voltage via the sense amplifiers 41a and 41b. When the sense amplifiers 41a and 41b are enabled in this state, data can be read from the selected left-up memory cell MCulS and the selected right-up memory cell MCurS.

[0169] During data reading, a read current Irul flows from the sense amplifier 41a to the selected upper word line WLuS, and a read current Irur flows from the sense amplifier 41b to the selected upper word line WLuS. Thus, a current of size Irul + Irur (i.e., a current of twice the size of the read current Ir) flows to the selected upper word line WLuS. In order to allow such a size of current to flow from the selected upper word line WLuS to the local word line LWLu, the local row switch TLY1, which plays the same role as the local row switch TLYu between each upper word line WLu and the local word line LWLu, needs to have a capability of conducting (or, driving) a current (current driving capability) that is twice the current driving capability of the local row switch TLYu having the driving capability of the current Ir only. The current driving capability of a transistor generally depends on the size of the transistor. All the local row switches TLY1 need to be twice the size of the local row switch TLYu having the driving capability of the current Ir only. Since the memory device includes hundreds or more than 1000 local row switches TLY1, the effect of the size increase is significant. Similarly, the global row switch TGY1 between the local word line LWLu and the global word line GWLu also needs to have twice the current driving capability of the global row switch TGYu.

[0170] Figure 17 Some components of the memory device 300 according to the third reference example and states during data reading are shown. The memory device 300 includes two sense amplifiers 41a and 41c. The sense amplifier 41c includes the same components and connections as those of the upper left sense amplifier SAul and provides a read current Ir from its second node N2 to its first node N1. The first node N1 of the sense amplifier 41c is coupled to the global word line GWLd, and the second node N2 of the sense amplifier 41c is coupled to the global bit line GBLl.

[0171] A plurality of left bit lines BLl share a single local bit line LBLl. Thus, two memory cells MC from which data can be read in parallel need to be coupled to a single left bit line BLl. Data is read from the selected upper left memory cell MCulS and the selected lower left memory cell MCdlS that satisfy the above condition. To this end, the selected upper word line WLuS and the selected lower word line WLdS are applied with a low level voltage via the sense amplifiers 41a and 41c, respectively. The selected left bit line BLlS is applied with a high level voltage via the sense amplifiers 41a and 41c. It is considered that data is read from the selected upper left memory cell MCulS and the selected lower left memory cell MCdlS when the sense amplifiers 41a and 41c are enabled in this state.

[0172] However, since two selected memory cells MCS are coupled to a single selected left bit line BLls, data read from one of the two selected memory cells MCS is interfered by data of the other selected memory cell MCS, so that data cannot be correctly read from one of the two selected memory cells MCS.

[0173] To handle the above problems in the memory devices 200 and 300, it can be considered Figure 18 the configuration shown. Figure 18 Some components of the memory device 400 according to the fourth reference example and states during data read are shown. The memory device 400 comprises two sense amplifiers 41a and 41d. The sense amplifier 41d comprises the same components and connections as the components and connections of the upper left sense amplifier SAul and provides a read current Ir from its second node N2 to its first node Nl. The first node Nl of the sense amplifier 41d is coupled to the global word line GWLd and the second node N2 of the sense amplifier 41d is coupled to the global bit line GBLr.

[0174] By selecting a single upper left memory cell MCul and a single lower right memory cell MCdr, data can be read in parallel from the selected upper left memory cell MCulS and the selected lower right memory cell MCdrS. To perform such a data read, a high level voltage needs to be applied to the selected left bit line BLls and the selected right bit line BLrS via the sense amplifiers 41a and 41d, respectively. Furthermore, a low level voltage needs to be applied to the selected upper word line WLuS and the selected lower word line WLdS via the sense amplifiers 41a and 41d, respectively. However, by applying such voltages, the unselected upper right memory cell MCurh coupled to the selected right bit line BLrS and the selected upper word line WLuS is also set in a selected state. Furthermore, the unselected lower left memory cell MCdlh coupled to the selected left bit line BLls and the selected lower word line WLdS is set in a selected state. Thus, data read from the selected upper left memory cell MCulS is interfered by voltages based on the state of the unselected lower left memory cell MCdlh and cannot be performed correctly. Similarly, data read from the selected lower right memory cell MCdrS is interfered by voltages based on the state of the unselected upper right memory cell MCurh and cannot be performed correctly.

[0175] The memory device 1 according to the first embodiment includes a first sense amplifier SA and a second sense amplifier SA. The first sense amplifier SA provides a read current Ir from a first selected bit line BL in a first bit line group to a first selected word line WL in a first word line group to a first selected memory cell MCS. The second sense amplifier SA provides another read current from a second selected word line WL in a second word line group to a second selected bit line BL in a second bit line group to a second selected memory cell MCS.

[0176] As a more detailed example, the upper left sense amplifier SAul is coupled at a second node N2ul to a selected left bit line BLls and at a first node N1ul to a selected upper word line WLuS, such that a read current Ir flows from the second node N2ul to the first node N1ul and reads data from a selected upper left memory cell MCulS coupled between the selected left bit line BLls and the selected upper word line WLuS. In addition, the lower right sense amplifier SAdr is coupled at a first node N1dr to a selected lower word line WLdS and at a second node N2dr to a selected right bit line BLrS, such that a read current Ir flows from the second node N2dr to the first node N1dr and reads data from a selected lower right memory cell MCdrS coupled between the selected lower word line WLdS and the selected right bit line BLrS. This configuration can form a state required for reading data from the selected upper left memory cell MCulS (i.e., the upper left memory cell selected state) and a state required for reading data from the selected lower right memory cell MCdrS (i.e., the lower right memory cell selected state) without interfering with each other. In addition, the state required for reading data from the selected upper left memory cell MCulS and the state required for reading data from the selected lower right memory cell MCdrS avoid unintentionally forming a state for reading data from a memory cell MC that is not selected. This suppresses an impediment to correctly reading data from the selected memory cell MCS. Thus, correct data can be read in parallel from two selected memory cells MCS.

[0177] 2. Second embodiment

[0178] The second embodiment differs from the first embodiment in the number of selected memory cells MCS from which data is read in parallel. The differences from the first embodiment will be mainly described below. Matters not mentioned can follow the description in the first embodiment.

[0179] The memory device 1 according to the second embodiment differs from the memory device 1 according to the first embodiment in the details of the row selector 14, the details of the column selector 15, and the control of the control circuit 13. The memory device 1, the row selector 14, and the column selector 15 according to the second embodiment can be referred to as memory device 1B, row selector 14B, and column selector 15B hereinafter, to distinguish from the memory device 1, the row selector 14, and the column selector 15 according to the first embodiment.

[0180] 2.1. Architecture (Configuration)

[0181] Figure 19 Details of some functional blocks of the memory device 1B according to the second embodiment are shown. More specifically, Figure 19 Components, connections, and layout of each of the memory cell array 11, the row selector 14B, the column selector 15B, and the write circuit 16 are shown.

[0182] As Figure 19 shown, the left upper sense amplifier SAul, the right upper sense amplifier SAur, the left lower sense amplifier SAdl, and the right lower sense amplifier SAdr are coupled to different components than in the first embodiment.

[0183] Similar to the row selector 14 of the first embodiment, the row selector 14B includes an upper row selector 14Bu and a lower row selector 14Bd.

[0184] The column selector 15B corresponds to a configuration in which each of the left column selector 15l and the right column selector 15r of the first embodiment is divided into two separate parts. Hereinafter, the left part (e.g., the left half part) of the left column selector 15l in the first embodiment will be referred to as the left end column selector 15Blm, and the remaining part will be referred to as the left column selector 15Bl. Similarly, hereinafter, the right part (e.g., the right half part) of the right column selector 15r in the first embodiment will be referred to as the right end column selector 15Brm, and the remaining part will be referred to as the right column selector 15Br.

[0185] The left end column selector 15Blm is coupled to some of the left bit lines BLl arranged in series, and the left column selector 15Bl is coupled to the remaining left bit lines BLl. For example, the left bit lines BLl located in the left half part of all the left bit lines BLl are coupled to the left end column selector 15Blm, and the left bit lines BLl located in the right half part of all the left bit lines BLl are coupled to the left column selector 15Bl. The left bit lines BLl coupled to the left end column selector 15Blm will be referred to as left end bit lines BLlm hereinafter, and the left bit lines BLl coupled to the left column selector 15Bl will be referred to as left bit lines BLl hereinafter.

[0186] The left end column selector 15BIm couples one of the left end bit lines BLIm designated by the address signal ADD in the left end bit lines BLIm to the second node N2ul of the left upper sense amplifier SAul. The left column selector 15Bl couples one of the left bit lines BLl designated by the address signal ADD in the left bit lines BLl to the second node N2dl of the left lower sense amplifier SAdl.

[0187] The right end column selector 15Brm is coupled to some of the right bit lines BLr arranged in succession, and the right column selector 15Br is coupled to the remaining right bit lines BLr. For example, the right bit lines BLr located in the right half of all the right bit lines BLr are coupled to the right end column selector 15Brm, and the right bit lines BLr located in the left half of all the right bit lines BLr are coupled to the right column selector 15Br. The right bit lines BLr coupled to the right end column selector 15Brm will be referred to hereinafter as right end bit lines BLrm, and the right bit lines BLr coupled to the right column selector 15Br will be referred to hereinafter as right bit lines BLr.

[0188] The right column selector 15Br receives the address signal ADD and couples one of the right bit lines BLr designated by the address signal ADD in the right bit lines BLr to the second node N2ur of the right upper sense amplifier SAur. The right end column selector 15Brm couples one of the right end bit lines BLrm designated by the address signal ADD in the right end bit lines BLrm to the second node N2dr of the right lower sense amplifier SAdr.

[0189] 2.1.1. Details of the column selectors

[0190] Figure 20 An example of the components and connections of the column selectors according to the second embodiment is shown.

[0191] The up selector 14Bu does not include the local row switch TLYu of the first embodiment, but includes a local row switch TLYul. The up selector 14Bu does not include the global row switch TGYu of the first embodiment, but includes a global row switch TGYul.

[0192] The down selector 14Bd does not include the local row switch TLYd of the first embodiment, but includes a local row switch TLYdl. The down selector 14Bd does not include the global row switch TGYd, but includes a global row switch TGYdl.

[0193] Each local row switch TLYul is provided in place of each local row switch TLYu in the row selector 14 of the first embodiment. A global row switch TGYul is provided in place of the global row switch TGYu in the row selector 14 of the first embodiment. Each local row switch TLYdl is provided in place of each local row switch TLYd in the row selector 14 of the first embodiment. A global row switch TGYdl is provided in place of the global row switch TGYd in the row selector 14 of the first embodiment.

[0194] The local row switches TLYul and TLYdl have higher current driving capability than the local row switches TLYu and TLYd, respectively. To this end, the sizes (particularly, gate widths) of the local row switches TLYul and TLYdl can be larger than those (particularly, gate widths) of the local row switches TLYu and TLYd, respectively. The local row switches TLYul and TLYdl each have a driving capability that can cause a current twice as large as the read current Ir to flow.

[0195] The global row switches TGYul and TGYdl have higher current driving capability than the global row switches TGYu and TGYd, respectively. To this end, the sizes (particularly, gate widths) of the global row switches TGYul and TGYdl can be larger than those (particularly, gate widths) of the global row switches TGYu and TGYd, respectively. The global row switches TGYul and TGYdl each have at least a driving capability that can cause a current twice as large as the read current Ir to flow.

[0196] Each of the left-end column selector 15BIm, the left column selector 15Bl, the right column selector 15Br, and the right-end column selector 15Brm has the same configuration and functions as the left column selector 15l or the right column selector 15r of the first embodiment. That is, each of the left-end column selector 15BIm, the left column selector 15Bl, the right column selector 15Br, and the right-end column selector 15Brm includes sets of a plurality of local column switches, local bit lines, global column switches, and global bit lines. These sets are independent of each other. In each of the left-end column selector 15BIm, the left column selector 15Bl, the right column selector 15Br, and the right-end column selector 15Brm, the plurality of local column switches, the local bit lines, the global column switches, and the global bit lines are coupled in a manner similar to that in the left column selector 15l or the right column selector 15r of the first embodiment. Details are as follows.

[0197] The left end column selector 15Blm includes a plurality of local column switches TLXlm, local bit lines LBLlm, a global column switch TGXlm, and a global bit line GBLlm. Each local column switch TLXlm is coupled between a single left end bit line BLlm and a local bit line LBLlm. Like the local column switch TLXl of the first embodiment, each local column switch TLXlm receives a control signal LXl at its control terminal that is unique to that local column switch TLXlm. The local bit lines LBLlm are coupled to the global bit line GBLlm via the global column switch TGXlm. The global column switch TGXlm receives a control signal GXl at its control terminal. When the local column switch TLXlm and the global column switch TGXlm are turned on, the single left end bit line BLlm can be coupled to the second node N2ul of the left upper sense amplifier SAul.

[0198] The left column selector 15l includes a plurality of local column switches TLXl, local bit lines LBLl, a global column switch TGXl, and a global bit line GBLl. Each local column switch TLXl is coupled between a single left bit line BLl and a local bit line LBLl. Like the local column switch TLXl of the first embodiment, each local column switch TLXl receives a control signal LX1 at its control terminal that is unique to that local column switch TLXl. The local bit lines LBLl are coupled to the global bit line GBLl via the global column switch TGXl. The global column switch TGXl receives a control signal GXl at its control terminal. When the local column switch TLXl and the global column switch TGXl are turned on, the single left bit line BLl can be coupled to the second node N2dl of the left lower sense amplifier SAdl.

[0199] The right column selector 15r includes a plurality of local column switches TLXr, local bit lines LBLr, a global column switch TGXr, and a global bit line GBLr. Each local column switch TLXr is coupled between a single right bit line BLr and a local bit line LBLr. Like the local column switch TLXr of the first embodiment, each local column switch TLXr receives a control signal LXr at its control terminal that is unique to that local column switch TLXr. The local bit lines LBLr are coupled to the global bit line GBLr via the global column switch TGXr. The global column switch TGXr receives a control signal GXr at its control terminal. When the local column switch TLXr and the global column switch TGXr are turned on, the single right bit line BLr can be coupled to the second node N2ur of the right upper sense amplifier SAur.

[0200] The right-end column selector 15Brm comprises a plurality of local column switches TLXrm, local bit lines LBLrm, a global column switch TGXrm, and a global bit line GBLrm. Each local column switch TLXrm is coupled between a single right-end bit line BLrm and a local bit line LBLrm. Like the local column switch TLXr of the first embodiment, each local column switch TLXrm receives at its control terminal a control signal LXr that is unique to that local column switch TLXrm. The local bit lines LBLrm are coupled to the global bit line GBLrm via the global column switch TGXrm. The global column switch TGXrm receives at its control terminal a control signal GXr. When the local column switch TLXrm and the global column switch TGXrm are turned on, the single right-end bit line BLrm can be coupled to the second node N2dr of the right-down sense amplifier SAdr.

[0201] 2.2. Operation

[0202] Figure 21 States during reading of data from the memory device 1 according to the second embodiment are shown. Figure 21 The same ranges as in Figure 19 are shown, and similar to Figure 19 , the layout is indicated.

[0203] The memory device 1B reads data from a total of four memory cells MC of the upper-left subarray 11ul, the upper-right subarray 11ur, the lower-left subarray 11dl, and the lower-right subarray 11dr in parallel. That is, the memory device 1B reads data from the selected upper-left memory cell MCulS, the selected upper-right memory cell MCurS, the selected lower-left memory cell MCdlS, and the selected lower-right memory cell MCdrS in parallel. Figure 21 Only components associated with reading data from the selected upper-left memory cell MCulS, the selected upper-right memory cell MCurS, the selected lower-left memory cell MCdlS, and the selected lower-right memory cell MCdrS are shown. The overview of data reading in the second embodiment corresponds to or is similar to the case of reading data from the selected upper-left memory cell MCulS and the selected lower-right memory cell MCdrS in parallel Figure 11 ) and reading data from the selected upper-right memory cell MCurS and the selected lower-left memory cell MCdlS in parallel Figure 13 ).

[0204] The selected upper-left memory cell MCulS and the selected upper-right memory cell MCurS need to be coupled to the same upper word line WLu. The selected lower-left memory cell MCdlS and the selected lower-right memory cell MCdrS need to be coupled to the same lower word line WLd. Data can be read in parallel from the four memory cells MC that satisfy the above conditions.

[0205] In the following, the left end bit line BLlm coupled to the selected left upper memory cell MCulS will be referred to as the selected left end bit line BLlmS. In the following, the left bit line BLl coupled to the selected left lower memory cell MCdlS will be referred to as the selected left bit line BLlS. In the following, the right bit line BLr coupled to the selected right upper memory cell MCurS will be referred to as the selected right bit line BLrS. In the following, the right end bit line BLrm coupled to the selected right lower memory cell MCdrS will be referred to as the selected right end bit line BLrmS.

[0206] Similar to the method according to the first embodiment, a left upper memory cell selected state, a right upper memory cell selected state, a left lower memory cell selected state and a right lower memory cell selected state are formed. Details can be estimated from the description of the first embodiment and are outlined as follows.

[0207] The selected upper word line WLuS is coupled to the first node Nlul of the left upper sense amplifier SAul and the first node Nlur of the right upper sense amplifier SAur via a local row switch TLYul (not shown) and a global row switch TGYul (not shown) coupled to the selected upper word line WLuS and turned on.

[0208] The selected lower word line WLdS is coupled to the first node Nldl of the left lower sense amplifier SAdl and the first node Nldr of the right lower sense amplifier SAdr via a local row switch TLYdl (not shown) and a global row switch TGYd (not shown) coupled to the selected lower word line WLdS and turned on.

[0209] The selected left end bit line BLlmS is coupled to the second node N2ul of the left upper sense amplifier SAul via a local column switch TLXlm (not shown) and a global column switch TGXlm (not shown) coupled to the selected left end bit line BLlmS and turned on.

[0210] The selected left bit line BLlS is coupled to the second node N2dl of the left lower sense amplifier SAdl via a local column switch TLXl (not shown) and a global column switch TGXl (not shown) coupled to the selected left bit line BLlS and turned on.

[0211] The selected right bit line BLrS is coupled to the second node N2ur of the right upper sense amplifier SAur via a local column switch TLXr (not shown) and a global column switch TGXr (not shown) coupled to the selected right bit line BLrS and turned on.

[0212] The selected right end bit line BLrmS is coupled to a second node N2dr of the right lower sense amplifier SAdr via a local column switch TLXrm (not shown) and a global column switch TGXrm (not shown) that are turned on with the selected right end bit line BLrmS.

[0213] In the state where the upper left memory cell selected state, the upper right memory cell selected state, the lower left memory cell selected state, and the lower right memory cell selected state are formed as described above, the upper left sense amplifier SAul, the upper right sense amplifier SAur, the lower left sense amplifier SAdl, and the lower right sense amplifier SAdr are enabled similarly to the first embodiment. This starts reading data from the selected upper left memory cell MCulS, the selected upper right memory cell MCurS, the selected lower left memory cell MCdlS, and the selected lower right memory cell MCdrS.

[0214] With the start of the data read, each interconnection associated with the data read is applied with a voltage as follows. A low level voltage is applied to the selected upper word line WLuS. A high level voltage is applied to the selected lower word line WLdS. A high level voltage is applied to the selected left end bit line BLlmS. A low level voltage is applied to the selected left bit line BLlS. A low level voltage is applied to the selected right bit line BLrS. A low level voltage is applied to the selected right end bit line BLrmS.

[0215] The application of the voltages for the data read makes it possible to prevent the data read from the selected upper left memory cell MCulS, the data read from the selected upper right memory cell MCurS, the data read from the selected lower left memory cell MCdlS, and the data read from the selected lower right memory cell MCdrS from interfering with each other. Thus, the read data can be obtained as follows.

[0216] A read current Irul flows from the selected left end bit line BLlmS to the selected upper word line WLuS through the selected upper left memory cell MCulS. The upper left sense amplifier SAul outputs a voltage that reflects the resistance state of the selected upper left memory cell MCulS. The voltage corresponds to the data read from the selected upper left memory cell MCulS.

[0217] A read current Irur flows from the selected right bit line BLrS to the selected upper word line WLuS through the selected upper right memory cell MCurS. The upper right sense amplifier SAur outputs a voltage that reflects the resistance state of the selected upper right memory cell MCurS. The voltage corresponds to the data read from the selected upper right memory cell MCurS.

[0218] A read current Irdl flows from the selected lower word line WLdS to the selected left bit line BLlS through the selected lower left memory cell MCdlS. The left lower sense amplifier SAdl outputs a voltage reflecting the resistive state of the selected lower left memory cell MCdlS. This voltage corresponds to the data read from the selected lower left memory cell MCdlS.

[0219] A read current Irdr flows from the selected lower word line WLdS to the selected right end bit line BLrmS through the selected lower right memory cell MCdrS. The right lower sense amplifier SAdr outputs a voltage reflecting the resistive state of the selected lower right memory cell MCdrS. This voltage corresponds to the data read from the selected lower right memory cell MCdrS.

[0220] By performing the data read, a current of size 2xIr can flow through the local row switch TLYul (not shown) and the global row switch TGYul (not shown) coupled to the selected upper word line WLuS. In addition, a current of size 2xIr can flow through the local row switch TLYdl (not shown) and the global row switch TGYdl (not shown) coupled to the selected lower word line WLdS.

[0221] 2.3. Advantages (beneficial effects)

[0222] Local row switches with large current driving capability can be provided, such as the local row switches TLYul and TLYdl. In this case, according to the second embodiment, correct data can be read from four memory cells MC in parallel, as described below.

[0223] Similar to the first embodiment, the memory device IB comprises a first sense amplifier SA and a second sense amplifier SA. The first sense amplifier SA provides a read current Ir from a first selected bit line BLS in a first bit line group to a first selected word line WLS in a first word line group to a first selected memory cell MCS. The second sense amplifier SA provides another read current Ir from a second selected word line WLS in a second word line group to a second selected bit line BLS in a second bit line group to a second selected memory cell MCS.

[0224] In addition, the memory device IB comprises a third sense amplifier SA and a fourth sense amplifier SA. The third sense amplifier SA provides a read current Ir from a third selected bit line BLS in a third bit line group to the first selected word line WLS to a third selected memory cell MCS. The fourth sense amplifier SA provides another read current Ir from the second selected word line WLS to a fourth selected bit line BLS in a fourth bit line group to a fourth selected memory cell MCS.

[0225] The states required to read data from the first to fourth selected memory cells MCS, respectively, can be formed without interfering with each other. Thus, the correct data can be read from the four memory cells MC in parallel.

[0226] 2.4. Modification example

[0227] An example corresponding to a configuration in which each of the left column selector 15l and the right column selector 15r of the first embodiment is divided into two separate parts has been described. However, the second embodiment is not limited to this. That is, each of the left column selector 15l and the right column selector 15r of the first embodiment can be divided into three or more separate parts.

[0228] 3. Modification example

[0229] Each of the upper left sense amplifier SAul, the upper right sense amplifier SAur, the lower left sense amplifier SAdl, and the lower right sense amplifier SAdr can have a function of supplying the read current Ir from a first node N1 thereof and drawing the read current Ir from a second node N2 thereof, and a function of supplying the read current Ir from the second node N2 thereof and drawing the read current Ir from the first node N1 thereof. That is, each sense amplifier SA includes Figure 8 the configuration shown in Figure 9 or Figure 10 the configuration shown in, and can be configured to dynamically select Figure 8 the configuration shown in Figure 9 or Figure 10 one of the configurations shown in.

[0230] The variable resistance element VR can include a phase change element, a ferroelectric element, or another element. The phase change element is used to set a phase change random access memory (PCRAM) to a crystal state or an amorphous state by heat generated by a write current, thereby exhibiting different resistance values according to the states. The variable resistance element VR can include an element for resistive RAM (ReRAM). For such a variable resistance element VR, the resistance value of the variable resistance element VR varies according to the width (pulse application period) or amplitude (current value or voltage value) of a write pulse and the polarity (application direction) of the write pulse.

[0231] While specific embodiments have been described in detail, these particular embodiments are shown and described by way of illustration only, and are not intended to limit the scope of the present disclosure. Indeed, the novel embodiments described herein can be embodied in a multitude of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein can be made without departing from the spirit of the disclosure. The appended claims as well as the equivalents thereof are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.

[0232] Explanation of symbols

[0233] 1: magnetic memory device, 2: memory controller, 11: memory cell array, 12: input / output circuit, 13: control circuit, 14: row selection circuit, 15: column selection circuit, 16: write circuit, 17: read circuit, MC: memory cell, WL: word line, BL: bit line, VR: magnetoresistive element, SE: switching element, 21: conductor, 22: conductor, 24: lower electrode, 25: variable resistance material, 26: upper electrode, 31: ferromagnetic layer, 32: insulating layer, 33: ferromagnetic layer, 11ul: upper left subarray, 11ur: upper right subarray, 11dl: lower left subarray, 11dr: lower right subarray, WLu: upper word line, WLd: lower word line, BLl: left bit line, BLr: right bit line, MCul: upper left memory cell, MCur: upper right memory cell, MCdl: lower left memory cell, MCdr: lower right memory cell, 14u: upper row selector, 14d: lower row selector, 15l: left column selector, 15r: right column selector, SAul: upper left sense amplifier, SAur: upper right sense amplifier, SAdl: lower left sense amplifier, SAdr: lower right sense amplifier, N1ul: first node, N1ur: first node, N1dl: first node, N1dr: first node, N2ul: second node, N2ur: second node, N2dl: second node, N2dr: second node, LWLu: local word line, LWLd: local word line, GWLu: global word line, GWLd: global word line, LBLl: local bit line, LBLr: local bit line, GBLl: global bit line, GBLr: global bit line, MCulS: selected upper left memory cell, MCdrS: selected lower right memory cell, MCurS: selected upper right memory cell, MCdlS: selected lower left memory cell, WLuS: selected upper word line, BLlS: selected left bit line, WLdS: selected lower word line, BLrS: selected right bit line.< / n> < / m> < / m>

Claims

1. A variable resistance memory device, comprising: a first interconnect; a second interconnect; a third interconnect; a fourth interconnect; a first memory cell coupled to the first interconnect and the third interconnect and having a variable resistance; a second memory cell coupled to the second interconnect and the fourth interconnect and having a variable resistance; a first sense amplifier having a first terminal and a second terminal and having a potential difference between the first terminal and the second terminal, the first terminal coupled to a node of a first potential and the second terminal positioned proximate to a node of a second potential and coupled to the third interconnect; and a second sense amplifier having a third terminal and a fourth terminal and having a potential difference between the third terminal and the fourth terminal, the third terminal coupled to a node of a third potential and the fourth terminal positioned proximate to a node of a fourth potential and coupled to the second interconnect.

2. The device of claim 1, wherein the first sense amplifier is configured to output a voltage based on a voltage of the second terminal, and the second sense amplifier is configured to output a voltage based on a voltage of the fourth terminal.

3. The device of claim 1, wherein the first sense amplifier is configured to output a voltage based on a voltage of the second terminal, and the second sense amplifier is configured to output a voltage based on a voltage of the third terminal.

4. The device of claim 1, wherein the first sense amplifier is configured to output a first current from the second terminal and draw the first current at the first terminal, and the second sense amplifier is configured to output a second current from the fourth terminal and draw the second current at the third terminal.

5. The device of claim 1, wherein the first sense amplifier and the second sense amplifier are enabled in parallel.

6. The device of claim 1, further comprising: a first memory cell array including the first memory cell; a second memory cell array; a third memory cell array; a fourth memory cell array including the second memory cell; a first circuit between the first memory cell array and the second memory cell array and including a first switch between the first terminal and the first interconnect; a second circuit between the first memory cell array and the third memory cell array and including a second switch between the second terminal and the third interconnect; a third circuit between the third memory cell array and the fourth memory cell array and including a third switch between the fourth terminal and the second interconnect; and a fourth circuit between the second memory cell array and the fourth memory cell array and including a fourth switch between the third terminal and the fourth interconnect.

7. The device of claim 1, further comprising: a third memory cell coupled to the first interconnect and the fourth interconnect and having a variable resistance; and a fourth memory cell coupled to the second interconnect and the third interconnect and having a variable resistance. ​ ​ a fourth memory element coupled to the third interconnect and the second interconnect and having a variable resistance.

8. The apparatus of claim 7, further comprising: a first memory element array including the first memory element; a second memory element array including the third memory element; a third memory element array including the fourth memory element; a fourth memory element array including the second memory element; a first circuit between the first memory element array and the second memory element array and including a first switch between the first terminal and the first interconnect; a second circuit between the first memory element array and the third memory element array and including a second switch between the second terminal and the third interconnect; a third circuit between the third memory element array and the fourth memory element array and including a third switch between the fourth terminal and the second interconnect; and a fourth circuit between the second memory element array and the fourth memory element array and including a fourth switch between the third terminal and the fourth interconnect.

9. The apparatus of claim 7, further comprising: a third sense amplifier having a fifth terminal and a sixth terminal, the fifth terminal coupled to a node of a fifth potential and the first interconnect, the sixth terminal positioned closer to a node of a sixth potential higher than the fifth potential than the fifth terminal and coupled to the fourth interconnect; and a fourth sense amplifier having a seventh terminal and an eighth terminal, the seventh terminal coupled to a node of a seventh potential and the third interconnect, the eighth terminal positioned closer to a node of an eighth potential higher than the seventh potential than the seventh terminal and coupled to the second interconnect.

10. The apparatus of claim 1, further comprising: a fifth interconnect; a sixth interconnect; a third memory element coupled to the first interconnect and the fifth interconnect and having a variable resistance; a fourth memory element coupled to the sixth interconnect and the second interconnect and having a variable resistance; a third sense amplifier having a fifth terminal and a sixth terminal, the fifth terminal coupled to a node of a fifth potential and the first interconnect, the sixth terminal positioned closer to a node of a sixth potential higher than the fifth potential than the fifth terminal and coupled to the fifth interconnect; and a fourth sense amplifier having a seventh terminal and an eighth terminal, the seventh terminal coupled to a node of a seventh potential and the sixth interconnect, the eighth terminal positioned closer to a node of an eighth potential higher than the seventh potential than the seventh terminal and coupled to the second interconnect.

11. The apparatus of claim 10, wherein the first sense amplifier, the second sense amplifier, the third sense amplifier, and the fourth sense amplifier are enabled simultaneously.

12. The apparatus of claim 10, further comprising: a first memory element array including the first memory element; ​ ​ ​ a second array of memory cells including the third memory cell; a third array of memory cells including the fourth memory cell; a fourth array of memory cells including the second memory cell; a first circuit between the first array of memory cells and the second array of memory cells and including a first switch between the first terminal and the fifth terminal and the first interconnect; a second circuit between the first array of memory cells and the third array of memory cells and including a second switch between the second terminal and the third interconnect; a third circuit between the first array of memory cells and the third array of memory cells and including a third switch between the seventh terminal and the sixth interconnect; a fourth circuit between the third array of memory cells and the fourth array of memory cells and including a fourth switch between the fourth terminal and the eighth terminal and the second interconnect; a fifth circuit between the second array of memory cells and the fourth array of memory cells and including a fifth switch between the sixth terminal and the fifth interconnect; and a sixth circuit between the second array of memory cells and the fourth array of memory cells and including a sixth switch between the third terminal and the fourth interconnect. ​

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