Magnetic storage device and storage system

Abstract

Embodiments provide a magnetic storage device capable of stably storing information and a storage system. A magnetic storage device of one embodiment includes a first storage unit and a control circuit. The first storage unit includes a first magnetic resistance effect element and a first switching element connected in series. The control circuit is configured to repeatedly apply a first voltage to the first storage unit until a first condition is satisfied in a first operation.

Description

[0001] This application claims priority to Japanese Patent Application No. 2020-156432 (Filing date: September 17, 2020). The entire contents of the base application are incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments relate to a magnetic storage device and a storage system. BACKGROUND

[0003] A storage system including a magnetic storage device (MRAM: Magnetoresistive Random Access Memory) using a magnetoresistance effect element as a storage element and a storage controller that controls the magnetic storage device is known. SUMMARY

[0004] An object of the present application is to provide a magnetic storage device and a storage system capable of stably storing information.

[0005] The magnetic storage device of the embodiment has a first storage unit and a control circuit. The first storage unit includes a first magnetoresistance effect element and a first switching element connected in series. The control circuit is configured to repeatedly apply a first voltage to the first storage unit until a first condition is satisfied in a first operation. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a block diagram for explaining a configuration of a storage system including a magnetic storage device to which the embodiment relates.

[0007] Figure 2 is a circuit diagram for explaining a configuration of a storage unit array of a magnetic storage device to which the embodiment relates.

[0008] Figure 3 is a cross-sectional view for explaining a configuration of a storage unit array of a magnetic storage device to which the embodiment relates.

[0009] Figure 4 is a cross-sectional view for explaining a configuration of a storage unit array of a magnetic storage device to which the embodiment relates.

[0010] Figure 5 is a cross-sectional view for explaining a configuration of a magnetoresistance effect element of a magnetic storage device to which the embodiment relates.

[0011] Figure 6 is a conceptual view for explaining a bad storage unit table stored in a storage system including a magnetic storage device to which the embodiment relates.

[0012] Figure 7is a flowchart for describing a series of actions in the magnetic storage device to which the embodiment relates.

[0013] Figure 8 is a flowchart for describing a scanning action in the magnetic storage device to which the embodiment relates.

[0014] Figure 9 is a schematic diagram for describing a scanning action in the magnetic storage device to which the embodiment relates.

[0015] Figure 10 is a schematic diagram for describing a scanning action in the magnetic storage device to which the embodiment relates.

[0016] Figure 11 is a flowchart for describing a high-resistance action in the magnetic storage device to which the embodiment relates.

[0017] Figure 12 is a time chart for describing a high-resistance action in the magnetic storage device to which the embodiment relates.

[0018] Figure 13 is a schematic diagram for describing a high-resistance action in the magnetic storage device to which the embodiment relates.

[0019] Figure 14 is a flowchart for describing a series of actions in the magnetic storage device to which the first modification of the embodiment relates.

[0020] Figure 15 is a flowchart for describing a high-resistance action in the magnetic storage device to which the first modification of the embodiment relates.

[0021] Figure 16 is a flowchart for describing a high-resistance action in the magnetic storage device to which the second modification of the embodiment relates.

[0022] Reference Signs Description

[0023] 1 storage system; 2 magnetic storage device; 3 storage controller; 5 defective storage cell table; 10 storage cell array; 11 row selection circuit; 12 column selection circuit; 13 decoder circuit; 14 write circuit; 15 readout circuit; 16 voltage generation circuit; 17 input / output circuit; 18 control circuit; 20 semiconductor substrate; 21, 24, 27 electrically conductive body; 22, 23, 25, 26 element; 31, 32, 34, 36, 38 non-magnetic body; 33, 35, 37 ferromagnetic body. DETAILED DESCRIPTION

[0024] Embodiments will be described below with reference to the accompanying drawings. Note that the same portions or similar portions in different drawings are denoted with the same reference numerals, and the description thereof will not be repeated. In the following description, components having the same function and structure are denoted by the same reference numerals. In the case where a plurality of components denoted by the same reference numeral are distinguished from each other, a suffix is added to the reference numeral. In the case where it is not necessary to particularly distinguish a plurality of components denoted by the same reference numeral, only the reference numeral is assigned to the plurality of components, without the suffix. Here, the suffix is not limited to a subscript or a superscript, and includes, for example, a lowercase letter added at the end of a reference numeral and an index indicating arrangement, and the like.

[0025] 1. Embodiment

[0026] A magnetic storage device according to an embodiment will be described. The magnetic storage device according to the embodiment includes, for example, a magnetic storage device of a perpendicular magnetization method which uses an element (MTJ element) having a magnetoresistance effect by a magnetic tunnel junction (MTJ) as a resistance change element. The MTJ element is also referred to as a magnetoresistance effect element. In the embodiments described later, including the present embodiment, a case where the MTJ element is applied as the magnetoresistance effect element will be described. In addition, for convenience of description, the magnetoresistance effect element MTJ will be described.

[0027] 1.1 Configuration

[0028] First, a configuration of the magnetic storage device according to the embodiment will be described.

[0029] 1.1.1 Storage system

[0030] Figure 1 is a block diagram illustrating a configuration of a storage system including the magnetic storage device according to the embodiment.

[0031] As illustrated in Figure 1 , the storage system 1 includes a magnetic storage device 2 including a plurality of storage units MC capable of storing data in a nonvolatile manner and a storage controller 3 which controls the magnetic storage device 2. The storage system 1 is connected to a host device (not illustrated), such as a processor.

[0032] The storage controller 3 communicates a control signal CNT with the magnetic storage device 2, and instructs the magnetic storage device 2 to perform an access operation (e.g., a write operation of data and a read operation, etc.) to a storage unit MC in the magnetic storage device 2. In addition, the storage controller 3 issues a command CMD corresponding to each operation when performing the operation, and transmits the command CMD and an address ADD of an operation target to the magnetic storage device 2. The address ADD is information capable of specifying one of a plurality of storage units MC, and includes, for example, a layer address, a row address, and a column address.

[0033] For example, at the time of a write operation, the storage controller 3 transmits data to be written (write data) DAT to the magnetic storage device 2 together with a command CMD instructing the write operation and an address ADD of a write target. At the time of a read operation, the storage controller 3 transmits a command CMD instructing the read operation and an address ADD of a read target to the magnetic storage device 2, and receives data read (read data) DAT from the magnetic storage device 2.

[0034] In addition, the storage controller 3 stores, for example, in a not-illustrated RAM inside, a defective storage unit table 5. The defective storage unit table 5 includes information for specifying a storage unit MC in the magnetic storage device 2 that is determined to not normally function. Details of the defective storage unit table 5 will be described later.

[0035] The magnetic storage device 2 includes a storage unit array 10, a row selection circuit 11, a column selection circuit 12, a decoder circuit 13, a write circuit 14, a read circuit 15, a voltage generation circuit 16, an input / output circuit 17, and a control circuit 18.

[0036] The storage unit array 10 includes a plurality of storage units MC associated with groups of rows and columns. Specifically, storage units MC located in the same row are connected to the same word line WL, and storage units MC located in the same column are connected to the same bit line BL.

[0037] The row selection circuit 11 is connected to the storage unit array 10 via the word line WL. A decoder result (layer address and row address) of the address ADD from the decoder circuit 13 is supplied to the row selection circuit 11. The row selection circuit 11 sets the word line WL corresponding to the layer and the row based on the decoder result of the address ADD to a selected state. In the following, the word line WL set to the selected state is referred to as a selected word line WL. In addition, the word line WL other than the selected word line WL is referred to as a non-selected word line WL.

[0038] The column selection circuit 12 is connected with the memory cell array 10 via the bit lines BL. Decoder results (layer address and column address) of the address ADD from the decoder circuit 13 are supplied to the column selection circuit 12. The column selection circuit 12 sets the bit line BL corresponding to the layer and column based on the decoder results of the address ADD to a selected state. In the following, the bit line BL set to the selected state is referred to as a selected bit line BL. In addition, the bit line BL other than the selected bit line BL is referred to as a non-selected bit line BL.

[0039] The decoder circuit 13 decodes the address ADD from the input / output circuit 17. The decoder circuit 13 supplies decoder results of the address ADD to the row selection circuit 11 and the column selection circuit 12. The address ADD includes a selected column address and a row address.

[0040] The write circuit 14 performs writing of data to the memory cell MC. The write circuit 14 includes, for example, a write driver (not shown).

[0041] The read circuit 15 performs reading of data from the memory cell MC. The read circuit 15 includes, for example, a sense amplifier (not shown).

[0042] The voltage generation circuit 16 generates voltages used for various operations of the memory cell array 10 using a power supply voltage supplied from the outside (not shown) of the magnetic storage device 2. For example, the voltage generation circuit 16 generates various voltages required at the time of a write operation, and outputs to the write circuit 14. In addition, for example, the voltage generation circuit 16 generates various voltages required at the time of a read operation, and outputs to the read circuit 15.

[0043] The input / output circuit 17 transmits the address ADD from the storage controller 3 to the decoder circuit 13. The input / output circuit 17 transmits the command CMD from the storage controller 3 to the control circuit 18. The input / output circuit 17 transmits and receives various control signals CNT between the storage controller 3 and the control circuit 18. The input / output circuit 17 transmits the data DAT from the storage controller 3 to the write circuit 14, and outputs the data DAT transmitted from the read circuit 15 to the storage controller 3.

[0044] The control circuit 18 controls the operations of the row selection circuit 11, the column selection circuit 12, the decoder circuit 13, the write circuit 14, the read circuit 15, the voltage generation circuit 16, and the input / output circuit 17 in the magnetic storage device 2 based on the control signals CNT and the command CMD.

[0045] 1.1.2 Configuration of Memory Cell Array

[0046] Next, the configuration of the memory cell array of the magnetic storage device according to the embodiment will be described. Figure 2 The configuration of the memory cell array of the magnetic storage device according to the embodiment will be described. Figure 2is a circuit diagram showing the configuration of the memory cell array of the magnetic storage device to which the embodiment relates.

[0047] In the following description, the word line WL is provided to be uniquely identified by the row address m and the even-numbered layer address k, and is expressed as "WL<k,m>" using the index <>. The bit line BL is provided to be identified by the column address n and the odd-numbered layer address k, and is expressed as "BL<k,n>" using the index <>. The memory cell MC is provided to be uniquely identified by the layer address k, the row address m, and the column address n, and is expressed as "MC<k,m,n>". Here, k, m, n are integers satisfying 0≤k≤K, 0≤m≤M, 0≤n≤N (K, M, N are natural numbers).

[0048] As shown in Figure 2 , the memory cell MC is arranged in the memory cell array 10 in a matrix shape in association with a group of one of the plurality of bit lines BL (BL<1,0>, BL<1,1>,..., BL<3,0>, BL<3,1>,...) and one of the plurality of word lines WL (WL<0,0>, WL<0,1>,..., WL<2,0>, WL<2,1>,...), and is uniquely identified by the group of the layer address k, the row address m, and the column address n. More specifically, in the case where the layer address k is even, the memory cell MC<k,m,n> is connected between the word line WL<k,m> and the bit line BL<k+1,n>, and in the case where the layer address k is odd, the memory cell MC<k,m,n> is connected between the word line WL<k+1,m> and the bit line BL<k,n>.

[0049] The memory cell MC<k,m,n> includes a switching element SEL<k,m,n> and a magnetoresistive effect element MTJ<k,m,n> connected in series.

[0050] The switching element SEL has a function as a switch that controls the supply of current to the magnetoresistive effect element MTJ at the time of data writing and reading with respect to the magnetoresistive effect element MTJ. More specifically, for example, the switching element SEL within a certain memory cell MC cuts off the current as an insulator (becomes an off state) in the case where the voltage applied to the memory cell MC is lower than a threshold voltage Vth, and flows the current as a conductor with a small resistance value (becomes an on state) in the case where it is higher than the threshold voltage Vth. That is, the switching element SEL has a function of being able to switch whether to flow the current or to cut off the current, according to the magnitude of the voltage applied to the memory cell MC, independently of the direction of the current flowing.

[0051] The switching element SEL can also be a two-terminal switching element, for example. In a case where a voltage applied across the two terminals is less than a threshold value, the switching element is in a "high resistance" state, for example, an electrically non-conductive state. In a case where the voltage applied across the two terminals is equal to or greater than the threshold value, the switching element changes to a "low resistance" state, for example, an electrically conductive state. The switching element can also have this function regardless of the polarity of the voltage.

[0052] The magnetoresistive effect element MTJ can switch the resistance value to a low resistance state and a high resistance state using the current supplied controlled by the switching element SEL. The magnetoresistive effect element MTJ functions as a storage element that can write data by a change in the resistance state thereof, hold the written data in a non-volatile manner, and read out the data.

[0053] However, in a case where the switching element SEL has some malfunction and is short-circuited, the switching element SEL cannot control the current flowing in the magnetoresistive effect element MTJ according to the applied voltage. In this case, in the storage unit MC including the short-circuited switching element SEL, it is possible that an unintended current flows even in a case where another storage unit MC is selected, which is undesirable. Hereinafter, the storage unit MC including the short-circuited switching element SEL is referred to as a "defective storage unit MC" or a "failed bit" to distinguish from a normal storage unit MC.

[0054] Next, the cross-sectional configuration of the storage unit array 10 will be described using Figure 3 and Figure 4 The cross-sectional configuration of the storage unit array 10 will be described. Figure 3 and Figure 4 is one example of a cross-sectional view for describing the configuration of the storage unit array of the magnetic storage device according to the embodiments, and is represented with omission of the interlayer insulating film for convenience of description.

[0055] Further, in the following description, a plane parallel to the surface of the semiconductor substrate 20 is referred to as the XY plane, and an axis perpendicular to the XY plane is referred to as the Z axis. The direction along the Z axis approaching the semiconductor substrate 20 is referred to as "downward", and the direction away from the semiconductor substrate 20 is referred to as "upward". In the XY plane, one group of two axes orthogonal to each other is referred to as the X axis and the Y axis.

[0056] As shown in Figure 3 and Figure 4 The storage unit array 10 is provided above the semiconductor substrate 20.

[0057] A plurality of conductive bodies 21 is provided on the upper surface of the semiconductor substrate 20, for example. The plurality of conductive bodies 21 each has conductivity and functions as a word line WL. An insulating body 41 is provided in a portion between two adjacent conductive bodies 21. Thus, the plurality of conductive bodies 21 each is insulated from each other. Further, an insulating body 42 is provided on the upper surface of the semiconductor substrate 20 in a portion other than the portion between the two adjacent conductive bodies 21. Thus, the plurality of conductive bodies 21 is insulated from the semiconductor substrate 20.Figure 3 and Figure 4 The example described a case where multiple conductors 21 are provided on the semiconductor substrate 20, but this is not the only possibility. For example, the multiple conductors 21 may not be in contact with the semiconductor substrate 20, but may be positioned upwards.

[0058] Multiple elements 22, each functioning as a magnetoresistive element (MTJ), are disposed on the upper surface of a conductor 21. These multiple elements 22 are arranged, for example, along the X-axis. That is, the multiple elements 22 arranged along the X-axis are collectively connected to the upper surface of the conductor 21. Furthermore, the detailed configuration of the elements 22 will be described later.

[0059] Each of the multiple elements 22 has an element 23 on its upper surface that functions as a switching element SEL. The upper surface of each of the multiple elements 23 is connected to one of the multiple conductors 24.

[0060] Multiple conductors 24 are conductive and function as bit lines BL. Multiple elements 23 arranged along the Y-axis are collectively connected to a single conductor 24. Furthermore, in... Figure 3 and Figure 4 The description illustrates a case where multiple elements 23 are respectively disposed on element 22 and conductor 24, but is not limited thereto. For example, each of the multiple elements 23 may also be connected to element 22 and conductor 24 via a conductive contact plug (not shown).

[0061] As described above, the memory cell array 10 has a memory cell MC disposed between a word line WL and a bit line BL.

[0062] 1.1.3 Magnetoresistive Effect Components

[0063] Next, use Figure 5 The configuration of the magnetoresistive element in the magnetic storage device according to the embodiment will be described. Figure 5 This is a cross-sectional view showing the configuration of the magnetoresistive element in the magnetic storage device according to the embodiment. Figure 5 For example, it means along a plane perpendicular to the Z-axis (e.g., the XZ plane). Figure 3 and Figure 4 An example of the cross-section obtained by cutting the magnetoresistive element MTJ is shown.

[0064] like Figure 5As shown, the magnetoresistive effect element MTJ includes, for example, a non-magnetic body 31 functioning as a top layer TOP, a non-magnetic body 32 functioning as a capping layer CAP, a ferromagnetic body 33 functioning as a storage layer SL, a non-magnetic body 34 functioning as a tunnel barrier layer TB, a ferromagnetic body 35 functioning as a reference layer RL, a non-magnetic body 36 functioning as a spacer layer SP, a ferromagnetic body 37 functioning as a shift cancelling layer SCL, and a non-magnetic body 38 functioning as an under layer UL.

[0065] The magnetoresistive effect element MTJ has, for example, a plurality of films stacked in the order of the non-magnetic body 38, the ferromagnetic body 37, the non-magnetic body 36, the ferromagnetic body 35, the non-magnetic body 34, the ferromagnetic body 33, the non-magnetic body 32, and the non-magnetic body 31 from the side of the word line WL to the side of the bit line BL (in the Z-axis direction). The magnetoresistive effect element MTJ functions, for example, as a perpendicular magnetization type MTJ element in which the direction of magnetization of the magnetic body constituting the magnetoresistive effect element MTJ is oriented in a direction perpendicular to the film surface. In addition, the magnetoresistive effect element MTJ can include other layers not shown between the above-described layers 31 to 38.

[0066] The non-magnetic body 31 is a non-magnetic conductor having a function as a top electrode for improving the electrical connectivity of the upper end of the magnetoresistive effect element MTJ to the bit line BL or the word line WL. The non-magnetic body 31 contains, for example, at least one element or compound selected from tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and titanium nitride (TiN).

[0067] The non-magnetic body 32 is a non-magnetic body having a function of suppressing the increase in the attenuation constant of the ferromagnetic body 33 and reducing the write current. The non-magnetic body 32 contains, for example, at least one nitride or oxide selected from magnesium oxide (MgO), magnesium nitride (MgN), zirconium nitride (ZrN), niobium nitride (NbN), silicon nitride (SiN), aluminum nitride (AlN), hafnium nitride (HfN), tantalum nitride (TaN), tungsten nitride (WN), chromium nitride (CrN), molybdenum nitride (MoN), titanium nitride (TiN), and vanadium nitride (VN). In addition, the non-magnetic body 32 can be a mixture of these nitrides or oxides. That is, the non-magnetic body 32 is not limited to a binary compound formed of two elements, and can contain a ternary compound formed of three elements, such as aluminum titanium nitride (AlTiN), and the like.

[0068] The ferromagnetic body 33 has ferromagnetism and has an easy magnetization axis direction in a direction perpendicular to the film surface. The ferromagnetic body 33 has a magnetization direction toward one of the bit line BL side and the word line WL side along the Z axis. The ferromagnetic body 33 contains at least any one of iron (Fe), cobalt (Co), and nickel (Ni), and further contains boron (B). More specifically, for example, the ferromagnetic body 33 can contain iron cobalt boron (FeCoB) or iron boride (FeB), and can have a body-centered cubic crystal structure.

[0069] The non-magnetic body 34 is a non-magnetic insulator, for example, contains magnesium oxide (MgO), and as described above, can further contain boron (B). The non-magnetic body 34 has a NaCl crystal structure with a (001) film surface orientation, and functions as a seed material for growing a crystalline film from the interface with the ferromagnetic body 33 during the crystallization processing of the ferromagnetic body 33. The non-magnetic body 34 is provided between the ferromagnetic body 33 and the ferromagnetic body 35, and forms a magnetic tunnel junction together with the two ferromagnetic bodies.

[0070] The ferromagnetic body 35 has ferromagnetism and has an easy magnetization axis direction in a direction perpendicular to the film surface. The ferromagnetic body 35 has a magnetization direction toward one of the bit line BL side and the word line WL side along the Z axis. The ferromagnetic body 35 contains at least any one of iron (Fe), cobalt (Co), and nickel (Ni). In addition, the ferromagnetic body 35 can further contain boron (B). More specifically, for example, the ferromagnetic body 35 can contain iron cobalt boron (FeCoB) or iron boride (FeB), and can have a body-centered cubic crystal structure. The magnetization direction of the ferromagnetic body 35 is fixed, and in the example of the ferromagnetic body 37, toward the direction of the ferromagnetic body 37. Further, "the magnetization direction is fixed" means that the magnetization direction does not change due to a current (spin torque) of a size capable of inverting the magnetization direction of the ferromagnetic body 33. Figure 5

[0071] Further, in the example of the ferromagnetic body 37, the magnetization direction of the ferromagnetic body 37 is fixed, and in the example of the ferromagnetic body 37, toward the direction of the ferromagnetic body 37. Further, "the magnetization direction is fixed" means that the magnetization direction does not change due to a current (spin torque) of a size capable of inverting the magnetization direction of the ferromagnetic body 33. Figure 5 ​The ferromagnetic body 35 can also be a laminate including a plurality of layers, although not illustrated. Specifically, for example, the laminate constituting the ferromagnetic body 35 can also be configured to have a layer containing the aforementioned iron-cobalt-boron (FeCoB) or iron-boron (FeB) as an interface layer with the nonmagnetic body 34, and other ferromagnetic bodies are laminated with a nonmagnetic electrically conductive body interposed between the interface layer and the nonmagnetic body 36. The nonmagnetic electrically conductive body within the laminate constituting the ferromagnetic body 35 can contain, for example, at least one metal selected from tantalum (Ta), hafnium (Hf), tungsten (W), zirconium (Zr), molybdenum (Mo), niobium (Nb), and titanium (Ti). The other ferromagnetic bodies within the laminate constituting the ferromagnetic body 35 can contain, for example, at least one multilayer film selected from a multilayer film of cobalt (Co) and platinum (Pt) (Co / Pt multilayer film), a multilayer film of cobalt (Co) and nickel (Ni) (Co / Ni multilayer film), and a multilayer film of cobalt (Co) and palladium (Pd) (Co / Pd multilayer film).

[0072] The nonmagnetic body 36 is a nonmagnetic electrically conductive body, and contains, for example, at least one element selected from ruthenium (Ru), osmium (Os), iridium (Ir), vanadium (V), and chromium (Cr).

[0073] The ferromagnetic body 37 has ferromagnetism and has an easy magnetization axis direction in a direction perpendicular to the film surface. The ferromagnetic body 37 has a magnetization direction toward one of the bit line BL side and the word line WL side along the Z axis. The magnetization direction of the ferromagnetic body 37 is fixed in the same manner as the ferromagnetic body 35, in the direction toward the ferromagnetic body 35 in the example. Figure 5 The ferromagnetic body 37 contains, for example, at least one alloy selected from cobalt-platinum (CoPt), cobalt-nickel (CoNi), and cobalt-palladium (CoPd). The ferromagnetic body 37 can also be a laminate including a plurality of layers in the same manner as the ferromagnetic body 35. In this case, the ferromagnetic body 37 can include, for example, at least one multilayer film selected from a multilayer film of cobalt (Co) and platinum (Pt) (Co / Pt multilayer film), a multilayer film of cobalt (Co) and nickel (Ni) (Co / Ni multilayer film), and a multilayer film of cobalt (Co) and palladium (Pd) (Co / Pd multilayer film).

[0074] The ferromagnetic bodies 35 and 37 are coupled in an antiferromagnetic manner by the nonmagnetic body 36. That is, the ferromagnetic bodies 35 and 37 are coupled in such a manner that they have magnetization directions in opposite parallel directions to each other. Thus, in the example, the magnetization direction of the ferromagnetic body 35 is in the direction toward the ferromagnetic body 37, and the magnetization direction of the ferromagnetic body 37 is in the direction toward the ferromagnetic body 35. Figure 5In the example, the magnetization directions of ferromagnetic materials 35 and 37 are oriented in opposite directions. This combined structure of ferromagnetic material 35, non-magnetic material 36, and ferromagnetic material 37 is called a SAF (Synthetic Anti-Ferromagnetic) structure. Thus, ferromagnetic material 37 can counteract the influence of the leakage magnetic field of ferromagnetic material 35 on the magnetization direction of ferromagnetic material 33. Therefore, it can suppress the asymmetry in the reversibility of magnetization of ferromagnetic material 33 caused by the leakage magnetic field of ferromagnetic material 35 (i.e., the reversibility of magnetization direction of ferromagnetic material 33 when reversing differs depending on whether it is reversed from one direction to the other or in the opposite direction).

[0075] The non-magnetic body 38 is a non-magnetic conductor that functions as an electrode to improve the electrical connection with the bit line BL and the word line WL. Furthermore, the non-magnetic body 38 may contain, for example, a high-melting-point metal. A high-melting-point metal refers to a material with a melting point higher than iron (Fe) and cobalt (Co), and may contain at least one element selected from zirconium (Zr), hafnium (Hf), tungsten (W), chromium (Cr), molybdenum (Mo), niobium (Nb), titanium (Ti), tantalum (Ta), vanadium (V), ruthenium (Ru), and platinum (Pt).

[0076] In this implementation, a spin injection writing method is employed: a write current flows directly into the magnetoresistive element MTJ, injecting spin torque into the storage layer SL and the reference layer RL through this write current, thereby controlling the magnetization directions of the storage layer SL and the reference layer RL. The magnetoresistive element MTJ can operate in either a low-resistance state or a high-resistance state, depending on whether the magnetization directions of the storage layer SL and the reference layer RL are parallel or antiparallel.

[0077] When along the magnetoresistive element MTJ Figure 5 When a write current Ic0 of a certain magnitude flows in the direction of arrow A1, that is, from the storage layer SL towards the reference layer RL, the relative magnetization directions of the storage layer SL and the reference layer RL become parallel. In this parallel state, the resistance of the magnetoresistive element MTJ becomes the lowest, and the magnetoresistive element MTJ is set to a low-resistance state. This low-resistance state is called the "P (Parallel) state," and is, for example, defined as the state of data "0."

[0078] Additionally, when along the magnetoresistive effect element MTJ Figure 5When a write current Ic1, greater than the write current Ic0, flows in the direction of arrow A2—that is, from the reference layer RL towards the storage layer SL (opposite to arrow A1)—the relative magnetization directions of the storage layer SL and the reference layer RL become antiparallel. In this antiparallel state, the resistance of the magnetoresistive element MTJ reaches its maximum, and the magnetoresistive element MTJ is set to a high-resistance state. This high-resistance state is called the "AP (Anti-Parallel) state," and is, for example, defined as the state of data "1".

[0079] Furthermore, the following explanation follows the data specification method described above, but the way data "1" and data "0" are specified is not limited to the examples above. For example, the P state can also be specified as data "1" and the AP state as data "0".

[0080] 1.1.4 Table of Defective Storage Units

[0081] Next, use Figure 6 The conceptual diagram shown illustrates a table of faulty storage cells stored within a storage system that includes the magnetic storage device according to the embodiments.

[0082] like Figure 6 As shown in Table 5, the address information of the faulty memory cell MC and the address information of the word line WL and bit line BL connected to the faulty memory cell MC are stored in a mutually related manner.

[0083] Specifically, in Figure 6 In the example, the address information <3,5,7> of storage cell MC<3,5,7> and the address information <6,8,9> of storage cell MC<6,8,9> are stored as the address information of the faulty storage cell MC.

[0084] Additionally, address information <4,5> for word line WL <4,5> sandwiching memory cells MC <3,5,7> and address information <3,7> for bit line BL <3,7> are stored respectively. Address information <6,8> for word line WL <6,8> sandwiching memory cells MC <6,8,9> and address information <7,9> for bit line BL <7,9> are stored respectively as address information for word line WL and bit line BL connected to faulty memory cells MC.

[0085] Furthermore, the address information of the faulty memory cell MC and the address information of the word line WL and bit line BL connected to the faulty memory cell MC are in a one-to-one correspondence. Therefore, at least one of these needs to be stored in the faulty memory cell table 5.

[0086] Further, the defective memory cell table 5 is described as a table stored in the storage controller 3, but is not limited thereto. For example, the defective memory cell table 5 can also be stored in the memory cell array 10 in the magnetic storage device 2 in a nonvolatile manner.

[0087] 1.2 Action

[0088] Next, the action of the magnetic storage device according to the embodiment will be described.

[0089] 1.2.1 Series of actions until the defective memory cell is made high resistance

[0090] First, a series of actions until the defective memory cell MC in the magnetic storage device 2 is made high resistance will be described with reference to the flowchart shown in FIG. 10. Figure 7 As shown in FIG. 10, in step ST10, the storage controller 3 issues a command (access command) to perform a write action or a read action, and sends it to the magnetic storage device 2. The magnetic storage device 2 performs the write action or the read action when it receives the access command from the storage controller 3. As described above, the control circuit 18 performs the constant current mode control in the write action so that a predetermined write current IcO or Icl flows in the memory cell MC that is the write target. Likewise, the control circuit 18 performs the constant current mode control in the read action so that a predetermined read current flows in the memory cell MC that is the read target.

[0091] Figure 7 The storage controller 3, for example, counts the number of times of execution of the write action and the read action, and stores the count value. Further, the storage controller 3 can count only the count value of the write action or the read action.

[0092] In step ST30, the storage controller 3 determines whether the number of times of execution of the write action and the read action is equal to or greater than a threshold value Nth. For example, the storage controller 3 compares the count value of the number of times of execution of the write action and the read action with a predetermined threshold value Nth (for example, 10,000 times). In a case where the number of times of execution of the write action and the read action is equal to or greater than the threshold value Nth (step ST30; YES), the process proceeds to step ST50, and in a case where it is less than the threshold value Nth (step ST30; NO), the process returns to step ST10. That is, the storage system 1 can act without performing the process after step ST50 until the number of times of execution of the write action and the read action becomes equal to or greater than the threshold value Nth. Further, the threshold value Nth can be set to a plurality of values, and the process after step ST50 can be implemented once each time the number of times of execution of the write action and the read action exceeds one of the plurality of threshold values Nth that are different from each other.

[0093] In step ST30, the storage controller 3 determines whether the number of times of execution of the write action and the read action is equal to or greater than a threshold value Nth. For example, the storage controller 3 compares the count value of the number of times of execution of the write action and the read action with a predetermined threshold value Nth (for example, 10,000 times). In a case where the number of times of execution of the write action and the read action is equal to or greater than the threshold value Nth (step ST30; YES), the process proceeds to step ST50, and in a case where it is less than the threshold value Nth (step ST30; NO), the process returns to step ST10. That is, the storage system 1 can act without performing the process after step ST50 until the number of times of execution of the write action and the read action becomes equal to or greater than the threshold value Nth. Further, the threshold value Nth can be set to a plurality of values, and the process after step ST50 can be implemented once each time the number of times of execution of the write action and the read action exceeds one of the plurality of threshold values Nth that are different from each other.

[0094] ​In step ST50, the storage controller 3 issues a command (scan command) to perform a scan operation, and sends it to the magnetic storage device 2. When the scan command is accepted, the magnetic storage device 2 performs a scan operation on all the memory cells MC within the memory cell array 10.

[0095] The control circuit 18 performs, for example, a constant voltage mode control in the scan operation, so that a predetermined voltage is applied to the memory cell MC that is the scan target. As a result of the scan operation, the magnetic storage device 2 determines the address information of the defective memory cell MC, and notifies the storage controller 3. Thus, the storage controller 3 can store the address of the defective memory cell MC within the memory cell array 10 in the defective memory cell table 5. Details of the scan operation will be described later.

[0096] In step ST70, the storage controller 3 determines whether there is a defective memory cell MC within the magnetic storage device 2, based on the information stored in the defective memory cell table 5. In the case where the information of the defective memory cell MC is stored in the defective memory cell table 5 (step ST70; Yes), the process proceeds to step ST90, and in the case where the information of the defective memory cell MC is not stored (step ST70; No), the process omits step ST90.

[0097] In step ST90, the storage controller 3 issues a command (high-resistance command) to perform a high-resistance operation, and sends it to the magnetic storage device 2. The magnetic storage device 2 performs the high-resistance operation when the high-resistance command is accepted from the storage controller 3. The high-resistance command contains, for example, the address information of the defective memory cell MC that is the high-resistance target.

[0098] The control circuit 18 performs a constant voltage mode control in the high-resistance operation, so that a predetermined voltage is applied to the defective memory cell MC that is the high-resistance target. Thus, the magnetic storage device 2 can high-resistance the switching element SEL within the defective memory cell MC. Details of the high-resistance operation will be described later.

[0099] The series of operations up to the high-resistance of the defective memory cell MC within the magnetic storage device 2 ends above.

[0100] 1.2.2 Scan operation

[0101] Next, details of the scan operation will be described.

[0102] Figure 8 is a flowchart for describing the scan operation in the magnetic storage device according to the embodiment, and corresponds to step ST50 in Figure 7 Figure 8 ​The means indicates the action in the magnetic storage device 2 based on the scan command and the action of the storage controller 3 accompanying therewith.

[0103] As shown in FIG. 6, in step ST51, the row selection circuit 11 and the column selection circuit 12 apply the voltage VSS to all the word lines WL and all the bit lines BL. The voltage VSS is a ground voltage, for example, 0 V. Hereinafter, the case where the voltage VSS is 0 V is described. Figure 8

[0104] In step ST52, the row selection circuit 11 selects one of the word lines WL and applies the voltage Varb to the word line WL. The voltage Varb is a voltage higher than the voltage VSS and lower than the threshold voltage Vth of the switching element SEL.

[0105] In step ST53, the control circuit 18 determines whether a current of a predetermined size flows in the selected word line WL in the state set in steps ST51 and ST52. In the case where the current of the predetermined size is detected (step ST53; YES), the process proceeds to step ST54, and in the case where the current of the predetermined size is not detected (step ST53; NO), the process proceeds to step ST55.

[0106] In step ST54, the control circuit 18 outputs the address information of the word line WL selected in step ST52 to the storage controller 3. The storage controller 3 stores the address information in the defective memory cell table 5.

[0107] In step ST55, the control circuit 18 determines whether all the word lines WL are selected. In the case where all the word lines WL are not selected (step ST55; NO), the process returns to step ST51. Thus, the process of steps ST51 to ST54 is repeated until all the word lines WL are selected. In the case where all the word lines WL are selected (step ST55; YES), the process proceeds to step ST56.

[0108] In step ST56, the row selection circuit 11 and the column selection circuit 12 apply the voltage VSS to all the word lines WL and all the bit lines BL.

[0109] In step ST57, the column selection circuit 12 selects one of the bit lines BL and applies the voltage Varb to the bit line BL.

[0110] ​In step ST58, the control circuit 18 determines whether a current of a predetermined size is flowing in the selected bit line BL in the state set in steps ST56 and ST57. In the case where a current of a predetermined size is detected (step ST58; YES), the processing proceeds to step ST59, and in the case where a current of a predetermined size is not detected (step ST58; NO), the processing proceeds to step ST60.

[0111] In step ST59, the control circuit 18 outputs the address information of the bit line BL selected in step ST57 to the memory controller 3. The memory controller 3 stores the address information in the defective memory cell table 5. At this time, the memory controller 3 associates the address information of the bit line BL with one of the address information of the word lines WL already stored in the defective memory cell table 5. Thus, the address information of the defective memory cell can be determined.

[0112] In step ST60, the control circuit 18 determines whether all the bit lines BL are selected. In the case where all the bit lines BL are not selected (step ST60; NO), the processing returns to step ST56. Thus, the processing of steps ST56 to ST59 is repeated until all the bit lines BL are selected. In the case where all the bit lines BL are selected (step ST60; YES), the scanning operation ends.

[0113] Figure 9 and Figure 10 are schematic diagrams for explaining the scanning operation in the magnetic storage device according to the embodiment, and correspond to steps ST51 to ST54 and steps ST56 to ST59 in Figure 8

[0114] In Figure 9 and Figure 10 , 12 memory cells MC between one of the four word lines WL <k, m>, <k, m+1>, <k+2, m>, and <k+2, m+1> and one of the four bit lines BL <k+1, n>, <k+1, n+1>, <k+3, n>, and <k+3, n+1> are indicated. In addition, in Figure 9 and Figure 10 , a scanning operation in the case where a memory cell MC <k+1, m, n> of the 12 memory cells MC is a defective memory cell MC is indicated.

[0115] First, the operation in the case where the word line WL is selected will be described with reference to Figure 9

[0116] As shown in Figure 9 ​​As shown, when word line WL<k+2,m> is selected, a voltage Varb is applied to multiple memory cells MC (e.g., bad memory cell MC<k+1,m,n> and normal memory cells MC<k+1,m,n+1>, MC<k+2,m,n> and MC<k+2,m,n+1>) connected to word line WL<k+2,m>.

[0117] Even when a voltage Varb lower than the threshold voltage Vth is applied to the switching elements SEL in the normal storage cells MC<k+1,m,n+1>, MC<k+2,m,n>, and MC<k+2,m,n+1>, they remain in the off state. Therefore, no current flows in the normal storage cells MC<k+1,m,n+1>, MC<k+2,m,n>, and MC<k+2,m,n+1>.

[0118] On the other hand, the switching element SEL in the faulty memory cell MC<k+1,m,n> is short-circuited. Therefore, when a voltage Varb lower than the threshold voltage Vth is applied, it operates as if it were in the on state. As a result, current flows through the faulty memory cell MC<k+1,m,n>.

[0119] Thus, it can be determined that when a voltage Varb is applied to the word line WL<k+2,m> and current flows, at least one of the multiple memory cells MC connected to the word line WL<k+2,m> is a faulty memory cell MC. Therefore, the control circuit 18 outputs the address information <k+2,m> of the word line WL<k+2,m> to the memory controller 3, storing it in the faulty memory cell table 5.

[0120] Next, refer to Figure 10 The actions when the bit line BL is selected are explained.

[0121] like Figure 10 As shown, when the bit line BL<k+1,n> is selected, a voltage Varb is applied to multiple memory cells MC (e.g., bad memory cells MC<k+1,m,n> and normal memory cells MC<k+1,m+1,n>, MC<k,m,n> and MC<k,m+1,n>) connected to the bit line BL<k+1,n>.

[0122] Even when a voltage Varb lower than the threshold voltage Vth is applied to the individual switching elements SEL in the normal storage cells MC<k+1,m+1,n>, MC<k,m,n>, and MC<k,m+1,n>, they remain in the off state. Therefore, no current flows in the normal storage cells MC<k+1,m+1,n>, MC<k,m,n>, and MC<k,m+1,n>.

[0123] On the other hand, the switching element SEL<k+1,m,n> in the defective memory cell MC<k+1,m,n> is short-circuited, and thus, operates in the same manner as in the ON state when a voltage Varb lower than the threshold voltage Vth is applied. Therefore, a current flows through the defective memory cell MC<k+1,m,n>.

[0124] Thus, it is known that, in the case where a current flows when the voltage Varb is applied to the bit line BL<k+1,n>, at least one of the plurality of memory cells MC connected to the bit line BL<k+1,n> is the defective memory cell MC. Therefore, the control circuit 18 outputs the address information <k+1,n> of the bit line BL<k+1,n> to the memory controller 3 so as to be stored in the defective memory cell table 5.

[0125] Thus, the memory controller 3 can determine that the memory cell MC<k+1,m,n> between the address information <k+2,m> of the word line WL stored in the defective memory cell table 5 and the address information <k+1,n> of the bit line BL is the defective memory cell MC, and can store these address information in association with each other.

[0126] 1.2.3 High-resistance operation

[0127] Next, the high-resistance operation of the defective memory cell MC will be described.

[0128] Figure 11 is a flowchart for explaining the high-resistance operation of the defective memory cell in the magnetic storage device according to the embodiment, and corresponds to the step ST90 in Figure 7 . The operation in the magnetic storage device 2 based on the high-resistance command from the memory controller 3 is shown in Figure 11

[0129] First, the memory controller 3 issues a high-resistance command including the address information of the defective memory cell MC as a target of the high-resistance operation, and sends it to the magnetic storage device 2.

[0130] As shown in Figure 11 , in the step ST91, the control circuit 18 selects the defective memory cell MC as a target of the high-resistance operation based on the address information of the defective memory cell MC included in the high-resistance command when the high-resistance command is accepted. Hereinafter, for convenience of explanation, the selected defective memory cell MC will be referred to as a "selected memory cell MC".

[0131] In the step ST92, the control circuit 18 initializes the variable i to "0" (i = 0).

[0132] ​In step ST93, the row selection circuit 11 and the column selection circuit 12 apply a voltage (Vf + iΔV) to the selected memory cell MC. For example, the row selection circuit 11 and the column selection circuit 12 apply a voltage (Vf + iΔV) to the selected word line WL and a voltage VSS to the selected bit line BL. The voltage Vf and ΔV can be set to arbitrary values, but for example, the voltage (Vf + iΔV) applied to the selected memory cell MC is set to a value sufficiently lower than the threshold voltage Vth of the switching element SEL and the voltage (write voltage and read voltage) applied to the selected memory cell MC at the time of the access operation. Thus, it is possible to suppress erroneous writing due to the voltage applied to the memory cell MC at the time of the high-resistance operation.

[0133] Furthermore, which of the selected word line WL and the selected bit line BL is made high at the time of applying a voltage to the selected memory cell MC can be arbitrarily selected. That is, the row selection circuit 11 and the column selection circuit 12 can also apply a voltage (Vf + iΔV) to the selected bit line BL and a voltage VSS to the selected word line WL.

[0134] In step ST94, the control circuit 18 calculates the resistance value based on the current flowing in the selected memory cell MC in step ST93 and determines whether the resistance value is equal to or greater than a threshold value Rth. The threshold value Rth is, for example, sufficiently (e.g., 3 orders of magnitude or more) greater than the resistance value of the memory cell MC in the state where the switching element SEL is short-circuited. That is, the threshold value Rth is set to a value that can be considered as the size where the switching element SEL is considered to be broken. In a case where it is determined that the resistance value of the selected memory cell MC is equal to or greater than the threshold value Rth (step ST94; YES), the process proceeds to step ST96, and in a case where it is determined that the resistance value is less than the threshold value Rth (step ST94; NO), the process proceeds to step ST95.

[0135] In step ST95, the control circuit 18 increments the variable i and returns to the process of step ST93. Thus, the voltage after the step up of ΔV is applied to the selected memory cell MC until it is determined that the resistance value of the selected memory cell MC is equal to or greater than the threshold value Rth.

[0136] In step ST96, the control circuit 18 determines whether all of the defective memory cells MC have been selected. For example, the control circuit 18 determines whether the address of all of the defective memory cells MC included in the high-resistance command received from the memory controller 3 has been accessed. In a case where it is determined that there is a defective memory cell MC that has not been selected (step ST96; NO), the process returns to step ST91. Thus, steps ST91 to ST96 are repeated until the resistance value of all of the defective memory cells MC exceeds the threshold value Rth. On the other hand, in a case where it is determined that all of the defective memory cells MC have been selected (step ST96; YES), the process ends.

[0137] The high-resistivity process is now complete.

[0138] Figure 12 This is a timing diagram used to explain the high-resistivity operation in the magnetic storage device according to the embodiments. Figure 12 In the form of time series Figure 11 The relationship between the voltage applied to the selected memory cell MC in steps ST93 (and ST94) and the resistance value of the defective memory cell MC selected at that time. Furthermore, it indicates the case where the selected memory cell MC becomes highly resistive due to the application of the voltage at the (j+1)th time (j is a natural number).

[0139] like Figure 12 As shown, at time t0, the variable is set to "0", and voltage Vf is applied to the selected memory cell MC. At this time, the switching element SEL of the selected faulty memory cell MC is short-circuited. Therefore, a large current flows in the selected memory cell MC, and the resistance value of the selected memory cell MC becomes a very small value relative to the threshold Rth.

[0140] Similarly, at times t1 and t2, variable i is set to "1" and "2" respectively, and voltages (Vf+ΔV) and (Vf+2ΔV) are applied to the selected memory cell MC. Figure 12 In the example, even in this case, the resistance value of the selected memory cell MC hardly increases. That is, the switching element SEL of the selected faulty memory cell MC remains short-circuited.

[0141] At time tj, variable i is set to j, and voltage (Vf + jΔV) is applied to the selected memory cell MC. Consequently, the partially short-circuited fuse of the switching element SEL in the selected faulty memory cell MC is drastically energized to the point of being disconnected or essentially disconnected, resulting in a rapidly increasing resistance. Therefore, almost no current flows in the selected memory cell MC (only about 1 / 1000th of the current flowing in the selected memory cell MC between times t0 and t2), and the resistance of the selected memory cell MC exceeds the threshold value Rth.

[0142] At time tj, the control circuit 18 confirms that the switching element SEL in the selected faulty memory cell MC has become highly resistive, and applies a voltage VSS to the selected memory cell MC. Thus, the high-resistance operation ends.

[0143] Figure 13 This is a schematic diagram used to illustrate the high-resistivity operation in the magnetic storage device according to the embodiment. Figure 13The storage unit MC <k+1, m, n> is an abnormal storage unit MC, and the address information <k+2, m> of the word line WL <k+2, m> and the address information <k+1, n> of the bit line BL <k+1, n> are stored in a group associated with the abnormal storage unit MC <k+1, m, n> in the abnormal storage unit table 5.

[0144] As shown in FIG. 6, in a case where the storage unit MC <k+1, m, n> is selected as an abnormal storage unit MC that is an object of the high-resistance change, the group of the selected word line WL and the selected bit line BL is the word line WL <k+2, m> and the bit line BL <k+1, n>. Figure 13

[0145] The row selection circuit 11 and the column selection circuit 12 apply a voltage (Vf+iΔV) to the selected word line WL <k+2, m> and apply a voltage VSS to the selected bit line BL <k+1, n>. Thus, a potential difference |Vf+iΔV| is generated in the selected storage unit MC <k+1, m, n>, and the switching element SEL in the selected storage unit MC can be made high-resistance.

[0146] In addition, the row selection circuit 11 and the column selection circuit 12 apply a voltage (Vf+iΔV) / 2 to all the word lines WL except the selected word line WL and to all the bit lines BL except the selected bit line BL. Thus, a potential difference |Vf+iΔV| / 2 is generated in the storage units MC <k+2, m, n>, MC <k+2, m, n+1>, MC <k+1, m+1, n>, MC <k+1, m, n+1>, MC <k, m+1, n>, and MC <k, m, n> in the illustrated storage units MC, and these storage units MC become a semi-selected state. However, the potential difference |Vf+iΔV| / 2 is sufficiently small to be considered as not making the switching element SEL high-resistance. Thus, unintended high-resistance of the normal switching element SEL in the semi-selected storage unit MC can be suppressed.

[0147] In addition, no potential difference is generated in the storage units MC <k+2, m+1, n>, MC <k+2, m+1, n+1>, MC <k+1, m+1, n+1>, MC <k, m, n+1>, and MC <k, m+1, n+1> in the illustrated storage units MC, and these storage units MC become a non-selected state. Thus, unintended high-resistance of the normal switching element SEL in the non-selected storage unit MC can be suppressed.

[0148] By the operation as described above, the selected storage unit MC <k+1, m, n> can be selectively made high-resistance in the high-resistance change operation.

[0149] 1.3. Effects related to the present embodiment

[0150] ​According to the embodiment, the control circuit 18 selects the storage unit MC in which the switching element SEL is determined to be defective in the high-resistance operation. The row selection circuit 11 and the column selection circuit 12 apply the voltage Vf+iΔV while increasing the variable i until the resistance value of the selected storage unit MC becomes the threshold value Rth or more. The threshold value Rth is set to a size of three or more orders of magnitude of the resistance value of the short-circuited switching element SEL. Thus, it is possible to high-resistance the short-circuited switching element SEL to a degree that can be considered to be wire-broken. The short-circuited switching element SEL is always in the on state, and the high-resistance switching element SEL is always considered to be in the off state, and thus it is possible to suppress the current flow through the defective storage unit MC in the access operation in which the other storage unit MC is the access target. Thus, it is possible to reduce the number of storage units MC that become unusable.

[0151] In addition, in the high-resistance operation, the voltage Vf+iΔV is applied as a constant voltage to the selected storage unit MC. Thus, it is possible to apply the potential difference required to wire-break the switching element SEL. In addition, in the write operation, a voltage for flowing the current Ic0 or Ic1 as a constant current is applied to the selected storage unit MC. According to such a constant current method, a large amount of current flows even with a low voltage in the storage unit MC including the short-circuited switching element SEL, and thus it is difficult to apply a voltage to the storage unit MC to a degree that can wire-break the switching element SEL. According to the embodiment, the control circuit 18 applies the voltage Vf+iΔV to the selected storage unit MC using a low voltage method. Thus, it is possible to apply a voltage to the short-circuited switching element SEL to a degree that can wire-break the switching element SEL.

[0152] In addition, the row selection circuit 11 and the column selection circuit 12 apply the voltage (Vf+iΔV) / 2 while increasing the variable i to the semi-selected storage unit MC. The voltage (Vf+iΔV) / 2 is set to a degree that does not wire-break the normal switching element SEL in the semi-selected storage unit MC. Thus, it is possible to selectively wire-break the defective switching element SEL in the selected storage unit MC without wire-breaking the normal switching element SEL in the semi-selected storage unit MC.

[0153] In addition, the row selection circuit 11 and the column selection circuit 12 apply the voltage VSS regardless of the variable i to the non-selected storage unit MC. Thus, it is possible to selectively wire-break the defective switching element SEL in the selected storage unit MC without wire-breaking the normal switching element SEL in the non-selected storage unit MC.

[0154] Furthermore, when the access operation of magnetic storage device 2 reaches or exceeds threshold Nth, storage controller 3 issues a scan command and sends it to magnetic storage device 2. Upon receiving the scan command, magnetic storage device 2 performs a scan operation to identify faulty storage cells MC. Upon receiving notification of the address information of the identified faulty storage cell MC, storage controller 3 issues a high-resistance command containing the address information of the faulty storage cell MC and sends it to magnetic storage device 2. Upon receiving the high-resistance command, magnetic storage device 2 performs a high-resistance operation. Thus, storage system 1 can periodically increase the resistance of faulty storage cells MC that accumulate with increasing usage. Therefore, the number of unusable storage cells MC can be suppressed.

[0155] 2. Variations

[0156] Furthermore, various modifications can be applied to the above-described implementation methods.

[0157] 2.1 First Variation

[0158] For example, in the above embodiment, the case of selectively making the resistance of faulty memory cells MC identified by the scanning operation high has been described, but it is not limited to this. For example, the high resistance operation may also be performed without being based on the result of the scanning operation. In addition, the high resistance operation may be performed on multiple memory cells MC at the same time.

[0159] Figure 14 This is a flowchart illustrating a series of operations up to the point where the resistance of a faulty memory cell in the magnetic storage device according to the first variation of the embodiment becomes high, and is consistent with the embodiments. Figure 7 Corresponding. In Figure 14 In, omitted in Figure 7 Steps ST50 and ST70, as described above, are replaced by step ST90A.

[0160] like Figure 14 As shown, in step ST10, when the magnetic storage device 2 receives an access command from the storage controller 3, it performs an access operation.

[0161] In step ST30, the storage controller 3 determines whether the number of times the access action is executed is greater than or equal to the threshold Nth. If the number of times the access action is executed is greater than or equal to the threshold Nth (step ST30; yes), the process proceeds to step ST90A; if the number of times the access action is less than the threshold Nth (step ST30; no), the process returns to step ST10.

[0162] In step ST90A, the storage controller 3 issues a high-resistivity command and sends it to the magnetic storage device 2. The high-resistivity command in step ST90A, for example, does not contain address information for the faulty memory cell MC. When the magnetic storage device 2 receives the high-resistivity command from the storage controller 3, it performs the high-resistivity operation for the faulty memory cell MC without based on the address information.

[0163] The above completes the series of actions until the faulty storage cell MC within the magnetic storage device 2 becomes highly resistive.

[0164] Figure 15 This is a flowchart illustrating the high-resistivity operation in the magnetic storage device according to the first variation of the embodiment, and is consistent with the embodiment. Figure 11 Corresponding. In Figure 15 In, omitted in Figure 11 Steps ST91 and ST96, as described above, are replaced by step ST93A.

[0165] In step ST92, the control circuit 18 initializes variable i to "0" (i = 0).

[0166] In step ST93A, row selection circuit 11 and column selection circuit 12 apply a voltage (Vf+iΔV) to all memory cells MC. For example, row selection circuit 11 and column selection circuit 12 apply a voltage (Vf+iΔV) to all word lines WL and a voltage VSS to all bit lines BL. As described above, the voltage (Vf+iΔV) is sufficiently low compared to the threshold voltage Vth of the switching element SEL, therefore, the normal switching element SEL is in the off state. Thus, no current flows in the normal memory cell MC. On the other hand, a large current based on this voltage (Vf+iΔV) flows in the short-circuited switching element SEL, making the switching element SEL highly resistive.

[0167] In step ST94, the control circuit 18 calculates the resistance value based on the current flowing in all memory cells MC in step ST93, and determines whether the resistance value is above the threshold Rth. If it is determined that the resistance value of the memory cell MC to be selected is less than the threshold Rth (step ST94; No), the process proceeds to step ST95; if it is determined that it is above the threshold Rth (step ST94; Yes), the process ends.

[0168] In step ST95, control circuit 18 increments variable i, returning to the processing in step ST93A. Thus, the voltage increased by ΔV is applied to all memory cells MC until the calculated resistance value is determined to be above the threshold Rth (i.e., until all faulty memory cells MC present in all memory cells MC are made highly resistive).

[0169] By the above operation, the high-resistance operation can be performed on all defective memory cells MC in the memory cell array 10.

[0170] 2.2 Second Modified Example

[0171] Note that, for example, in the above-described embodiment, the case where the constant voltage is increased and repeatedly applied to the defective memory cell MC at the time of the high-resistance operation is described, but the present application is not limited to this. For example, the same value of voltage (not increased) can be repeatedly applied to the defective memory cell MC at the time of the high-resistance operation.

[0172] Figure 16 is a flowchart for describing the high-resistance operation in the magnetic storage device according to the second modified example of the embodiment, and corresponds to Figure 11 in the embodiment. Figure 16 In Figure 11 the steps ST92 and ST95 described in

[0173] In step ST91, the control circuit 18 selects the defective memory cell MC as an object of the high-resistance operation on the basis of the address information of the defective memory cell MC included in the high-resistance command when the high-resistance command is accepted.

[0174] In step ST93B, the row selection circuit 11 and the column selection circuit 12 apply the voltage Vf to the selected memory cell MC. For example, the row selection circuit 11 and the column selection circuit 12 apply the voltage Vf to the selected word line WL and apply the voltage VSS to the selected bit line BL.

[0175] In step ST94, the control circuit 18 calculates the resistance value on the basis of the current flowing in the selected memory cell MC in step ST93B and determines whether the resistance value is equal to or greater than the threshold value Rth. When it is determined that the resistance value of the selected memory cell MC is equal to or greater than the threshold value Rth (step ST94; Yes), the process proceeds to step ST96, and when it is determined that the resistance value is less than the threshold value Rth (step ST94; No), the process returns to step ST93B. Thus, the certain voltage Vf is applied to the selected memory cell MC until it is determined that the resistance value of the selected memory cell MC is equal to or greater than the threshold value Rth.

[0176] In step ST96, the control circuit 18 determines whether all of the defective memory cells MC are selected. In a case where it is determined that there is a defective memory cell MC that is not selected (step ST96; No), the process returns to step ST91. Thus, steps ST91, ST93B, ST94, and ST96 are repeated until the resistance values of all of the defective memory cells MC exceed the threshold value Rth. On the other hand, in a case where it is determined that all of the defective memory cells MC are selected (step ST96; Yes), the process ends.

[0177] By acting as above, the high-resistance action ends.

[0178] 3. Other

[0179] In the above-described embodiment, a case where the scan action and the high-resistance action are performed after the access action is performed a predetermined number of times is described, but is not limited thereto. For example, the storage controller 3 can perform the scan action and the high-resistance action at the time of startup of the magnetic storage device 2 (or the storage system 1), or can perform the scan action and the high-resistance action periodically. In a case where the scan action and the high-resistance action are performed periodically, the storage controller 3 can issue a command for a new scan action and a high-resistance action, for example, when an elapsed time from when the scan action and the high-resistance action were performed not long ago becomes above a threshold value.

[0180] In addition, the scan action and the high-resistance action can also be performed during the manufacturing period of the magnetic storage device 2 (for example, before the magnetic storage device 2 is shipped, and after a chip burn-in test for the magnetic storage device 2 ends). In a case where the scan action and the high-resistance action are performed during the manufacturing period of the magnetic storage device 2, the scan command and the high-resistance command can be issued from a tester (not shown), for example.

[0181] In addition, in the above-described modification example, a case where the high-resistance action is performed on all of the memory cells MC in the array 10 is described, but is not limited thereto. For example, the high-resistance action can also be performed on a part of the plurality of memory cells MC in the array 10, per layer, per column, per row, or the like. More specifically, for example, in a case where the high-resistance action is performed per layer, the voltage Vf+iΔV is applied to all of the wirings (word lines WL or bit lines BL) above the memory cells MC belonging to the layer that is the target of the high-resistance action, and the voltage VSS is applied to all of the wirings below. Thus, it is possible to apply the voltage Vf+iΔV to all of the memory cells MC belonging to the layer that is the target of the high-resistance action, while applying the voltage VSS to all of the memory cells belonging to other layers. By acting as above, it is possible to realize the high-resistance action that is performed per layer.

[0182] In addition, in the above-described embodiment and modification, the case where it is determined whether the resistance value of the selected memory cell MC is equal to or higher than the threshold value in the high-resistance operation is described, but is not limited thereto. For example, the memory controller 3 can determine whether the current value flowing in the selected memory cell MC is less than the threshold value. The threshold value set in this case can be set to a value of the order of 3 smaller than the current flowing in the memory cell MC including the short-circuited switching element SEL, for example.

[0183] In addition, in the above-described embodiment and modification, the case where the constant voltage method using the applied voltage Varb is used to determine the defective memory cell MC in the scan operation is described, but is not limited thereto, and the constant current method can be used. In this case, the determination operation for determining the defective memory cell MC can be determined based on whether a voltage of a predetermined size is applied.

[0184] In addition, in the above-described embodiment and modification, the case where the magnetoresistive element MTJ is provided below the switching element SEL is described for the memory cell MC, but the magnetoresistive element MTJ can be provided above the switching element SEL. In addition, the upper limit relationship between the magnetoresistive element MTJ and the switching element SEL can be set to be opposite in the case where the layer address k is even and in the case where the layer address k is odd.

[0185] In addition, in the above-described embodiment and modification, the case where the magnetoresistive element MTJ is a top free type element in which the storage layer SL is provided above the reference layer RL is described for the magnetoresistive element MTJ, but is not limited thereto. For example, the magnetoresistive element MTJ can be a bottom free type in which the storage layer SL is provided below the reference layer RL. In this case, the direction of the write current of the data "1" and the data "0" is opposite to that of the top free type described in the above-described embodiment. Figure 5

[0186] The above-described embodiments of the present application are described, but these embodiments are presented as examples, and are not intended to limit the scope of the application. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made within the scope of the application without departing from the spirit of the application. These embodiments and modifications are included in the scope and spirit of the application, and are included in the scope of the application and equivalents thereof recited in the claims.​

Claims

1. A magnetic storage device comprising: a first storage unit; and a control circuit, the first storage unit including a first magnetoresistive element and a first switching element connected in series, the control circuit configured to repeatedly apply a first voltage to the first storage unit until a first condition is satisfied in a first operation, the first storage unit connected between a first wiring and a second wiring, the magnetic storage device further comprising a second storage unit connected between the first wiring and a third wiring, the second storage unit including a second magnetoresistive element and a second switching element connected in series, the control circuit configured to repeatedly apply a second voltage lower than the first voltage to the second storage unit until the first condition is satisfied in the first operation.

2. The magnetic storage device according to claim 1, the control circuit configured to repeatedly apply the first voltage to the first storage unit while increasing the first voltage until the first condition is satisfied in the first operation.

3. The magnetic storage device according to claim 1, the first condition including that a resistance value of the first storage unit becomes at least a first threshold value.

4. The magnetic storage device according to claim 1, the first voltage being set independently of the resistance value of the first storage unit.

5. The magnetic storage device according to claim 1, the magnetic storage device further comprising a third storage unit connected between the third wiring and a fourth wiring, the third storage unit including a third magnetoresistive element and a third switching element connected in series, the control circuit configured to repeatedly apply a third voltage lower than the second voltage to the third storage unit until the first condition is satisfied in the first operation.

6. The magnetic storage device according to claim 5, the second voltage being an intermediate value of the first voltage and the third voltage.

7. The magnetic storage device according to claim 5, the third voltage being set independently of the first voltage and the second voltage.

8. The magnetic storage device according to claim 1, the control circuit configured to execute the first operation when a first command is accepted.

9. A magnetic storage device comprising: a first storage unit connected between a first wiring and a second wiring, a second storage unit connected between the first wiring and a third wiring; a third storage unit connected between the third wiring and a fourth wiring; and a control circuit, the first storage unit including a first magnetoresistive element and a first switching element connected in series, the second storage unit including a second magnetoresistive element and a second switching element connected in series, the third storage unit including a third magnetoresistive element and a third switching element connected in series, the control circuit configured to repeatedly apply a first voltage to each of the first storage unit, the second storage unit, and the third storage unit until a first condition is satisfied in a first operation.

10. The magnetic storage device according to claim 9, ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The first condition includes that resistance values of the first storage unit, the second storage unit, and the third storage unit are at least a threshold value.

11. A storage system comprising: a storage controller; and a magnetic storage device including a storage unit array including a plurality of storage units and a control circuit, each of the plurality of storage units includes a magnetoresistive effect element and a switching element connected in series, the control circuit is configured to, when a first command is accepted from the storage controller, repeatedly apply a first voltage to a first storage unit of the plurality of storage units, repeatedly apply a second voltage lower than the first voltage to a second storage unit of the plurality of storage units, until a first condition is satisfied, the first storage unit is connected between a first wiring and a second wiring, the second storage unit is connected between the first wiring and a third wiring.

12. The storage system according to claim 11, the storage controller is configured to, when a second condition is satisfied, issue a second command, the control circuit is configured to, when the second command is accepted from the storage controller, determine the first storage unit from the plurality of storage units, output address information of the determined first storage unit to the storage controller.

13. The storage system according to claim 12, the first command includes address information of the first storage unit.

14. The storage system according to claim 12, the second condition includes that a number of write operations or read operations on data of the magnetic storage device is at least a second threshold value.

15. The storage system according to claim 12, the second condition includes that the magnetic storage device has been activated.

16. The storage system according to claim 12, the second condition includes that a predetermined period has elapsed from issuance of a second command immediately before the second command.

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