Semiconductor memory device

Abstract

An embodiment provides a semiconductor memory device capable of rapidly setting a select gate line to a desired voltage. The semiconductor memory device of this embodiment includes: a plurality of memory cells; word lines connected to the gates of the plurality of memory cells; bit lines electrically connected to one end of the plurality of memory cells via a plurality of select gate transistors respectively connected to one end of the plurality of memory cells; two external select gate lines respectively connected to the gates of the two select gate transistors at both ends of a block; one or more internal select gate lines connected to the gates of one or more select gate transistors other than the two ends of the block; and a voltage generation circuit capable of individually controlling the voltage supply to the external and internal select gate lines when reading data recorded in the plurality of memory cells.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2020-156299 (filed on September 17, 2020). This application includes all contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0004] In recent years, semiconductor memory devices such as NAND (Not And) flash memory have tended to achieve three-dimensional structures due to the requirements of miniaturization and large capacity. In addition, in NAND flash memory, sometimes the memory cell transistors are SLC (Single Level Cell) capable of storing 1 bit (2-value) data. Moreover, sometimes the memory cell transistors are configured as MLC (Multi Level Cell) capable of storing 2 bits (4-value) data, TLC (Triple Level Cell) capable of storing 3 bits (8-value) data, or QLC (Quad Level Cell) capable of storing 4 bits (16-value) data.

[0005] When reading data from such a memory cell transistor, multiple voltages must be prepared and the voltage supplied to the memory cell transistor must be switched. Therefore, in order to improve the read speed, the transition to the desired target voltage must be made faster. Summary of the Invention

[0006] This embodiment provides a semiconductor memory device capable of rapidly setting the selected gate line to a desired voltage.

[0007] The semiconductor memory device of the embodiment includes: a plurality of memory cells; word lines connected to the gates of the plurality of memory cells; bit lines electrically connected to one end of the plurality of memory cells via a plurality of select gate transistors respectively connected to one end of the plurality of memory cells; two external select gate lines respectively connected to the gates of the two select gate transistors at both ends of the block; one or more internal select gate lines connected to the gates of one or more select gate transistors other than the two ends of the block; and a voltage generation circuit capable of individually controlling the voltage supply to the external select gate lines and the internal select gate lines when reading data recorded in the plurality of memory cells. Attached Figure Description

[0008] Figure 1This is a block diagram illustrating an example configuration of a memory system in an implementation method.

[0009] Figure 2 This is a block diagram illustrating an example of the configuration of a non-volatile memory in an implementation.

[0010] Figure 3 This is a diagram illustrating an example of the block configuration of a three-dimensional NAND memory cell array 23.

[0011] Figure 4 It is a graph showing the potential changes of each wiring in the write operation (programming operation).

[0012] Figure 5 This is an explanatory diagram used to illustrate the select gate lines (SGDs) in a block BLK.

[0013] Figure 6 The graph illustrates USTRDIS by taking time on the horizontal axis and voltage on the vertical axis.

[0014] Figure 7 It is a graph showing the potential changes of each wiring in the write operation (programming operation).

[0015] Figure 8 It is to utilize and Figure 6 The same description is used to illustrate the problems during USTRDIS.

[0016] Figure 9 This is a block diagram showing a partial configuration of the voltage generation circuit 28.

[0017] Figure 10 This is a block diagram illustrating an example of the configuration of the line decoder 25.

[0018] Figure 11 It means Figure 9 The circuit diagram shows an example of the specific configuration of the drivers 42-45.

[0019] Figure 12 It means Figure 9 The circuit diagram shows an example of the specific configuration of MUX(inner)46.

[0020] Figure 13 It means Figure 9 The circuit diagram shows an example of the specific configuration of MUX(outer)47.

[0021] Figure 14 This diagram is used to illustrate the effects of the implementation method.

[0022] Figure 15 This is a circuit diagram showing the SGD_usel(outer) driver used in the second embodiment of the present invention.

[0023] Figure 16 This is an explanatory diagram used to illustrate the operation of the implementation method.

[0024] Figure 17 This is an explanatory diagram used to illustrate the operation of the implementation method.

[0025] Figure 18 This is a circuit diagram representing the SGD_usel(inner) driver.

[0026] Figure 19 This is a block diagram illustrating the third embodiment of the present invention.

[0027] Figure 20 This is a graph that uses time on the horizontal axis and voltage on the vertical axis to represent the voltage changes of the outer select gate line SGD (outer) and the inner select gate line SGD (inner) during USTRDIS. Detailed Implementation

[0028] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0029] (First Embodiment)

[0030] In this embodiment, by supplying an overdrive voltage higher than the target voltage in the voltage generation circuit, and by varying the resistance value of the overdrive voltage supply circuit according to the type of gate line selected, the voltage variation applied to the selected gate line is uniform regardless of the type of gate line selected, and the target voltage can be reached in a short time.

[0031] (The structure of a memory system)

[0032] Figure 1 This is a block diagram illustrating an example configuration of a memory system according to an embodiment. The memory system of this embodiment includes a memory controller 1 and non-volatile memory 2. The memory system can be connected to a host device. The host device is, for example, a personal computer, a mobile terminal, or other electronic device.

[0033] The non-volatile memory 2 is a semiconductor storage device that stores data non-volatilely, such as a NAND flash memory. In this embodiment, the non-volatile memory 2 is described as a NAND memory having a storage cell transistor capable of storing 3 bits per transistor, i.e., a 3-bit / Cell (TLC: Triple Level Cell) NAND memory, but it is not limited to this. The non-volatile memory 2 is three-dimensional.

[0034] The memory controller 1 controls the writing of data to the non-volatile memory 2 based on write requests from the host. Additionally, the memory controller 1 controls the reading of data from the non-volatile memory 2 based on read requests from the host. The memory controller 1 includes RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Check and Correct) circuit 14, and a memory interface 15. The RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15 are interconnected via an internal bus 16.

[0035] The host interface 13 outputs requests received from the host, write data as user data, etc., to the internal bus 16. In addition, the host interface 13 sends user data read from the non-volatile memory 2, responses from the processor 12, etc., back to the host.

[0036] The memory interface 15 controls the writing of user data to and from the non-volatile memory 2 based on the instructions of the processor 12.

[0037] Processor 12 provides overall control over memory controller 1. Processor 12 may be, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or the like. Upon receiving a request from the host via host interface 13, processor 12 performs control according to that request. For example, based on a request from the host, processor 12 instructs memory interface 15 to write user data and parity data to non-volatile memory 2. Additionally, based on a request from the host, processor 12 instructs memory interface 15 to read user data and parity data from non-volatile memory 2.

[0038] Processor 12 determines the storage area (hereinafter referred to as memory area) on non-volatile memory 2 for user data stored in RAM 11. User data is stored in RAM 11 via internal bus 16. Processor 12 determines the memory area for data written in page units, i.e., page data. In this specification, user data stored in one page of non-volatile memory 2 is defined as unit data. Unit data is encoded as codewords and stored in non-volatile memory 2, for example.

[0039] Furthermore, encoding is not always necessary. Memory controller 1 can also store unit data in non-volatile memory 2 without encoding, but... Figure 1The following is an example of an encoding configuration. When the memory controller 1 does not perform encoding, the page data is identical to the unit data. Furthermore, a codeword can be generated based on a single unit data, or it can be generated based on segmented data formed by dividing the unit data. Alternatively, a codeword can be generated using multiple units of data.

[0040] Processor 12 determines the memory region of non-volatile memory 2 as the write target for each unit of data. Physical addresses are allocated within the memory regions of non-volatile memory 2. Processor 12 uses physical addresses to manage the memory regions as write targets for each unit of data. Processor 12 specifies the physical address of the determined memory region and instructs memory interface 15 to write user data to non-volatile memory 2. Processor 12 manages the mapping between logical addresses (host-managed logical addresses) and physical addresses of user data. Upon receiving a read request containing a logical address from the host, processor 12 specifies the physical address corresponding to the logical address, assigns the physical address, and instructs memory interface 15 to read the user data.

[0041] ECC circuit 14 encodes user data stored in RAM 11 to generate codewords. Additionally, ECC circuit 14 decodes codewords read from non-volatile memory 2.

[0042] RAM11 temporarily stores user data received from the host until it is stored in non-volatile memory 2, or temporarily stores data read from non-volatile memory 2 until it is sent to the host. RAM11 is, for example, a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0043] exist Figure 1 The diagram illustrates a configuration where the memory controller 1 includes both an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 can also be integrated into the memory interface 15. Alternatively, the ECC circuit 14 can be integrated into the non-volatile memory 2.

[0044] Upon receiving a write request from the host, the memory controller 1 operates as follows: The processor 12 temporarily stores the write data in RAM 11. The processor 12 reads the data stored in RAM 11 and inputs it to the ECC circuit 14. The ECC circuit 14 encodes the input data and assigns the codeword to the memory interface 15. The memory interface 15 writes the input codeword to the non-volatile memory 2.

[0045] Upon receiving a read request from the host, the memory controller 1 operates as follows: The memory interface 15 assigns the codeword read from the non-volatile memory 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in RAM 11. The processor 12 then sends the data stored in RAM 11 to the host via the host interface 13.

[0046] (The structure of non-volatile memory)

[0047] Figure 2 This is a block diagram illustrating an example of the configuration of the non-volatile memory in this embodiment. The non-volatile memory 2 includes a logic control circuit 21, an input / output circuit 22, a memory cell array 23, a sense amplifier 24, a line decoder 25, a register 26, a sequence generator 27, a voltage generation circuit 28, an input / output pad group 32, a logic control pad group 34, and a power input terminal group 35.

[0048] The memory cell array 23 comprises multiple blocks. Each block BLK comprises multiple memory cell transistors (memory cells). In the memory cell array 23, multiple bit lines, multiple word lines, and source lines are provided to control the voltage applied to the memory cell transistors. The specific structure of the block BLK will be described below.

[0049] The input / output pad group 32 is equipped with multiple terminals (pads) corresponding to signals DQ<7:0> and data strobe signals DQS and / DQS in order to transmit and receive signals containing data between the input / output pad group 32 and the memory controller 1.

[0050] The logic control pad group 34 has multiple terminals (pads) corresponding to the chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, and write protection signal / WP in order to transmit and receive various signals with the memory controller 1.

[0051] The / CE signal enables selection of non-volatile memory 2. The CLE signal latches instructions sent in the form of the DQ signal into the instruction register. The ALE signal latches addresses sent in the form of the DQ signal into the address register. The WE signal enables writing. The RE signal enables reading. The WP signal disables writing and erasing. The R / B signal indicates whether non-volatile memory 2 is in a ready state (able to accept commands from external sources) or a busy state (unable to accept commands from external sources). Memory controller 1 can understand the status of non-volatile memory 2 by receiving the R / B signal.

[0052] The power input terminal group 35 is equipped with multiple terminals for inputting power supply voltages Vcc, VccQ, Vpp, and ground voltage Vss to supply various operating power supplies to the non-volatile memory 2 from the outside. The power supply voltage Vcc is the circuit power supply voltage generally supplied externally as the operating power supply, for example, an input voltage of approximately 3.3V. The power supply voltage VccQ is, for example, an input voltage of 1.2V. The power supply voltage VccQ is used when transmitting and receiving signals between the memory controller 1 and the non-volatile memory 2. The power supply voltage Vpp is a power supply voltage higher than the power supply voltage Vcc, for example, an input voltage of 12V.

[0053] The logic control circuit 21 and the input / output circuit 22 are connected to the memory controller 1 via a NAND bus. The input / output circuit 22 transmits and receives signals DQ (e.g., DQ0 to DQ7) with the memory controller 1 via the NAND bus.

[0054] The logic control circuit 21 receives external control signals (e.g., chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, and write protection signal / WP) from the memory controller 1 via the NAND bus. The " / " in the signal name indicates active low. Additionally, the logic control circuit 21 sends a ready / busy signal / RB to the memory controller 1 via the NAND bus.

[0055] Register 26 includes an instruction register, an address register, and a status register. The instruction register temporarily stores instructions. The address register temporarily stores addresses. The status register temporarily stores data needed for the operation of non-volatile memory 2. Register 26 may be constructed from SRAM, for example.

[0056] The sequence generator 27 receives instructions from register 26 and controls the non-volatile memory 2 according to the order based on those instructions.

[0057] The voltage generation circuit 28 receives a power supply voltage from the external source of the non-volatile memory 2 and uses this power supply voltage to generate multiple voltages required for write, read, and erase operations. The voltage generation circuit 28 supplies the generated voltages to the memory cell array 23, the sense amplifier 24, and the line decoder 25, etc.

[0058] The row decoder 25 receives the row address from register 26 and decodes it. Based on the decoded row address, the row decoder 25 performs word line selection. Furthermore, the row decoder 25 transmits multiple voltages required for write, read, and erase operations to the selected block.

[0059] The sense amplifier 24 receives the column address from the register 26 and decodes the column address. The sense amplifier 24 has a sense amplifier component group 24A connected to each bit line. The sense amplifier component group 24A selects any bit line based on the decoded column address. Furthermore, when reading data, the sense amplifier component group 24A detects and amplifies the data read from the memory cell transistor to the bit line. Additionally, when writing data, the sense amplifier component group 24A transmits the write data to the bit line.

[0060] The sensing amplifier 24 has a data register 24B. When reading data, the data register 24B temporarily stores the data detected by the sensing amplifier component group 24A and transmits it serially to the input / output circuit 22. Conversely, when writing data, the data register 24B temporarily stores the data serially transmitted from the input / output circuit 22 and transmits it to the sensing amplifier component group 24A. The data register 24B is composed of SRAM or the like.

[0061] (Block structure of a storage cell array)

[0062] Figure 3 This is a diagram illustrating an example of the block configuration of a three-dimensional NAND memory cell array 23. Figure 3 This represents one block BLK among the multiple blocks that make up the storage cell array 23. The other blocks in the storage cell array also have the same characteristics. Figure 3 The same structure. Furthermore, this embodiment can also be applied to two-dimensional memory cell arrays.

[0063] As shown in the figure, block BLK, for example, contains 5 string components (SU0 to SU4). Furthermore, each string component SU contains multiple NAND strings NS. Each NAND string NS contains 8 memory cell transistors MT (MT0 to MT7) and select gate transistors ST1 and ST2. While the number of memory cell transistors MT in the NAND string NS is 8, it is not limited to 8; for example, it could be 32, 48, 64, or 96. Select gate transistors ST1 and ST2 are represented as one transistor in the electrical circuit, but their structure can be the same as the memory cell transistors. Alternatively, for example, to improve cutoff characteristics, multiple select gate transistors can be used as select gate transistors ST1 and ST2. Furthermore, dummy cell transistors can be placed between the memory cell transistors MT and the select gate transistors ST1 and ST2.

[0064] The memory cell transistor MT is configured in series between the select gate transistors ST1 and ST2. The memory cell transistor MT7 on one side is connected to the select gate transistor ST1, and the memory cell transistor MT0 on the other side is connected to the select gate transistor ST2.

[0065] The gates of the select gate transistors ST1 of each string assembly SU0 to SU4 are respectively connected to select gate lines SGD0 to SGD4 (hereinafter, without distinction, they are referred to as select gate lines SGD). On the other hand, the gates of select gate transistors ST2 are commonly connected to the same select gate line SGS among multiple string assemblies SU within the same block BLK. In addition, the gates of memory cell transistors MT0 to MT7 within the same block BLK are commonly connected to word lines WL0 to WL7. That is, word lines WL0 to WL7 and select gate lines SGS are commonly connected among multiple string assemblies SU0 to SU4 within the same block BLK, while select gate lines SGD are independent for each string assembly SU0 to SU4, even if they are within the same block BLK.

[0066] The gates of the memory cell transistors MT0 to MT7 that constitute the NAND string NS are connected to word lines WL0 to WL7, respectively. The gates of the memory cell transistors MTi located in the same row within block BLK are connected to the same word line WLi. Furthermore, in the following description, the NAND string NS will sometimes be referred to simply as "string".

[0067] Each NAND string NS is connected to its corresponding bit line. Therefore, each memory cell transistor MT is connected to the bit line via the select gate transistor ST or other memory cell transistor MT contained in the NAND string NS. As described above, the data of memory cell transistors MT within the same block BLK is erased together. On the other hand, data reading and writing are performed in units of memory cell groups MG (or in units of pages). In this specification, a group of memory cell transistors MT connected to one word line WLi and belonging to one string component SU is defined as a memory cell group MG. In this embodiment, the non-volatile memory 2 is a TLC NAND memory capable of storing 3 bits (8 values) of data. Therefore, one memory cell group MG can store 3 pages of data. The 3 bits that each memory cell transistor MT can store correspond to these 3 pages.

[0068] (Write action)

[0069] When writing multi-valued data to a memory cell transistor MT, the threshold voltage of the memory cell transistor MT is set to the value corresponding to the data value. If a programming voltage VPGM and a bit line voltage Vbl are applied to the memory cell transistor MT, electrons are injected into the charge accumulation film of the memory cell transistor MT, causing the threshold voltage to rise. The amount of electron injection can be increased by increasing the programming voltage VPGM, thereby increasing the threshold voltage of the memory cell transistor MT. However, due to the differences in memory cell transistors MT, even when the same programming voltage VPGM is applied, the amount of electron injection will be different in each memory cell transistor MT. The temporarily injected electrons are retained until the erase operation is performed. Therefore, the programming voltage VPGM is gradually increased while the programming and verification operations are performed (loop) multiple times, in a manner that does not exceed the range of the threshold voltage that can be tolerated for the threshold voltage set for each memory cell transistor MT (hereinafter referred to as the target region).

[0070] The verification action is a read action performed as part of the write action. Figure 4 This is a graph showing the potential changes of each wiring during the write operation (programming operation). Furthermore, regarding... Figure 4 The voltages shown are also generated by the voltage generation circuit 28 controlled by the sequence generator 27.

[0071] Programming actions are performed based on the programming voltages and bit line voltages applied to the word lines and bit lines. (The word lines are not programmed.) Figure 4 The block BLK to which voltage is applied (selected WL, non-selected WL) is the non-selected BLK that is not the object to be written. Figure 4 (Next paragraph). Furthermore, since the bit line voltage is applied to the memory cell transistor MT by turning on the select gate transistor ST1 connected to the bit line BL, the string components SU in the block BLK (select BLK) where the select gate line SGD is not applied are non-select SUs that are not intended for writing. Figure 4 (Middle section). Additionally, regarding the non-selection of SU when choosing BLK ( Figure 4 (Middle section), or the select gate line SGD can be set to, for example, 5V before the programming voltage VPGM is applied, thereby turning on the select gate transistor ST1.

[0072] Regarding the string component SU (selected SU) of the write object as the block BLK (selected BLK) to be written ( Figure 4 (Upper section), before applying the programming voltage VPGM, such as Figure 4 As shown on the left side of the upper section, setting the select gate line SGD to, for example, 5V turns on the select gate transistor ST1. However, during programming, the select gate line SGS is, for example, 0V. Therefore, the select gate transistor ST2 is turned off. On the other hand, as... Figure 4As shown on the right side of the upper section, when the programming voltage VPGM is applied, the select gate line SGD is set to, for example, 2.5V. Therefore, the on / off state of the select gate transistor ST1 is determined by the bit line voltage connected to the bit line BL of the select gate transistor ST1.

[0073] As described above, the sense amplifier 24 transmits data to each bit line BL. A ground voltage Vss, for example 0V, is applied as the bit line voltage Vbl_L to the bit line BL assigned a "0" data. A write inhibit voltage Vinhibit (e.g., 2.5V) is applied as the BL bit line voltage Vbl_H to the bit line assigned a "1" data. Therefore, when the programming voltage VPGM is applied, the select gate transistor ST1 connected to the bit line BL assigned a "0" data is turned on, and the select gate transistor ST1 connected to the bit line BL assigned a "1" data is turned off. The memory cell transistor MT connected to the turned-off select gate transistor ST1 becomes write inhibited.

[0074] The memory cell transistor MT connected to the select gate transistor ST1, which is in the on state, injects electrons into the charge accumulation film according to the voltage applied to the word line WL. The memory cell transistor MT connected to the word line WL, to which a voltage VPASS is applied as the word line voltage, is always in the on state regardless of the threshold voltage, but does not inject electrons into the charge accumulation film. On the other hand, the memory cell transistor MT connected to the word line WL, to which a programming voltage VPGM is applied as the word line voltage, injects electrons into the charge accumulation film according to the programming voltage VPGM.

[0075] In other words, the line decoder 25 selects any word line WL in the selection block BLK, applies a programming voltage VPGM to the selected word line, and applies a voltage VPASS to the other word lines (non-selected word lines) WL. The programming voltage VPGM is a high voltage used to inject electrons into the charge accumulation film through tunneling, and VPGM > VPASS. By controlling the voltage of the word line WL using the line decoder 25 and supplying data to each word line BL using the sense amplifier 24, the write operation (programming operation) is performed to each memory cell transistor MT of the memory cell array 23.

[0076] (Read the action aloud)

[0077] Data read from the multi-valued memory cell transistors is performed by applying a readout voltage to the select word line WL using the line decoder 25, and sensing the data read out to the bit line BL using the sensing amplifier 24 to determine whether the readout data is "0" or "1". Furthermore, to turn on the memory cell transistors connected to the non-select word line WL, the line decoder 25 applies a sufficiently high voltage VREAD to the non-select word line WL to enable each memory cell transistor to conduct. Additionally, regarding adjacent word lines, to facilitate the conduction of the memory cell transistors connected to adjacent word lines, a voltage VREADK slightly higher than VREAD can be applied.

[0078] In addition, the line decoder 25 applies a voltage VSG_sel to the select gate line SGD (hereinafter referred to as SGD_sel) of the string component (select string component) constituting the readout object in the string component SU, which is used to turn on the select gate transistor ST1, and applies a voltage VSG_usel to the select gate line SGD (hereinafter referred to as SGD_usel) of the string component (non-select string component) that is not a readout object, which is used to turn off the select gate transistor ST1.

[0079] The line decoder 25 applies a readout voltage to the select word line and a voltage VREAD or VEREDK to the non-select word line. During readout, the sense amplifier 24 fixes the bit line BL to a fixed voltage (e.g., 0.5V) and charges the sense node SEN (not shown) within the sense amplifier assembly group 24A to a predetermined precharge voltage Vpre higher than the voltage of the bit line BL. In this state, the logic control circuit 21 connects the sense node SEN to the bit line BL. As a result, current flows from the sense node SEN to the bit line BL, and the voltage of the sense node SEN gradually decreases.

[0080] The voltage at the sensing node SEN varies depending on the threshold voltage state of the memory cell transistor connected to the corresponding bit line BL. Specifically, when the threshold voltage of the memory cell transistor is lower than the read voltage, the transistor is on, allowing a larger cell current to flow through it, and the voltage at the sensing node SEN decreases more rapidly. Conversely, when the threshold voltage of the memory cell transistor is higher than the read voltage, the transistor is off, allowing a smaller or no cell current to flow through it, and the voltage at the sensing node SEN decreases more slowly.

[0081] The write state of the memory cell transistor is determined by utilizing the difference in the rate of voltage decrease at the sensing node SEN, and the result is stored in the data latch circuit. For example, at the first time point after a predetermined first period elapsed from the start of discharge from the point where the charge at the sensing node SEN begins to be discharged, it is determined whether the voltage at the sensing node SEN is low (hereinafter, "L") or high (hereinafter, "H"). For example, if the threshold voltage of the memory cell transistor is lower than the read voltage, the memory cell transistor is fully turned on, and a large cell current flows through the memory cell transistor. Therefore, the voltage at the sensing node SEN decreases rapidly, and the voltage drop is relatively large; at the first time point, the sensing node SEN becomes "L".

[0082] Furthermore, when the threshold voltage of the memory cell transistor is higher than the read voltage, the memory cell transistor is in the off state, and the cell current flowing to the memory cell transistor is very small, or there is no cell current flowing to the memory cell transistor. Therefore, the voltage of the sensing node SEN decreases very slowly, and the voltage drop is relatively small. At the first time point, the sensing node SEN remains "H".

[0083] In this way, by applying a readout voltage to the select word line using the line decoder 25 while monitoring the state of the sensing node SEN using the sensing amplifier circuit 32, it is determined whether the threshold voltage of the memory cell transistor is higher or lower than the readout voltage. Therefore, by setting the voltage between each level as the readout voltage and applying it to the select word line WL, the level of each memory cell transistor can be determined, and the data assigned to each level can be read out.

[0084] For example, data can be allocated to eight target regions of a TLC, and each memory cell transistor in a TLC can store 3 bits of data. Each memory cell transistor is written to at any of the Er, A, B, ..., G levels representing the eight target regions. During reading, the data value of each memory cell transistor can be determined by applying voltages VrA to VrG.

[0085] (Select gate line SGD)

[0086] Figure 5 This is an explanatory diagram used to illustrate the select gate lines (SGDs) in a block BLK. Figure 5 The planar shape of a portion of block BLK is shown on the left side of the paper, and the cross-sectional shape cut by line AA is shown on the right side of the paper. Figure 5 The circles represent memory holes 334 that make up the NAND string. Insulating layer 351 will... Figure 5 The block shown is separated from the other blocks. Figure 5The example illustrates a configuration within a single block BLK comprising five string components SU0 to SU4, each containing five select gate lines SGD0 to SGD4 separated by insulating layer 352. Figure 5 In the example on the right, the insulating layer 352 extends to the select gate line SGD of the 3rd layer and separates each select gate line SGD0 to SGD4 from each other.

[0087] A single string assembly contains multiple memory slots 334 that form NAND strings. The number of NAND strings (memory slots) in a single string assembly is extremely large. Figure 5 (Only 16 are shown in the image). To reduce size, the memory holes 334 are serrated. Each memory hole 334 within a single string assembly is connected to bit lines BL0, BL1, ... (hereinafter, these bit lines are referred to as bit lines BL unless otherwise distinguished) via contact plugs 339. Furthermore, in Figure 5 The left side of the attached diagram is for easy observation, and only a portion of the bit line BL and a portion of the contact plug 339 are shown.

[0088] like Figure 5 As shown, each bit line BL0, BL1, ... is connected to a memory hole 334 for each string via a contact plug 339. Furthermore, in order to connect each bit line BL to a memory hole 334 for each string, the contact plug 339 is offset in a direction orthogonal to the extension direction of the bit line BL.

[0089] Multiple NAND strings NS are formed on substrate 330. Specifically, select gate lines (SGS), multiple word lines (WL), and multiple select gate lines (SGD) are deposited on substrate 330 using an insulating film. Furthermore, memory vias 334 are formed that penetrate these select gate lines SGS, word lines WL, and select gate lines SGD to reach substrate 330. On the side of memory vias 334, a barrier insulating film (not shown), a charge storage film (charge storage region), and a gate insulating film are sequentially formed, and conductive pillars (not shown) are embedded within memory vias 334. These conductive pillars may include, for example, polysilicon and function as regions forming channels when the memory cell transistors MT and select gate transistors ST1 and ST2 included in the NAND strings NS are operated. In other words, the gate line SGD, the conductive pillars, and the insulating film between them function as the gate selection transistor ST1, the word line WL, the conductive pillars, and the insulating film between them function as the memory cell transistor MT, and the gate line SGS, each conductive pillar, and the insulating film between them function as the gate selection transistor ST2.

[0090] In addition, Figure 5The image shows that the memory hole 334 is a cylindrical shape with the same diameter, but in reality it has a tapered shape that narrows towards the substrate 330. In addition, depending on the manufacturing process, the memory hole 334 and the conductive post may sometimes have a multi-segment tapered shape that expands in diameter midway through the tapered shape and then narrows towards the substrate 330.

[0091] However, in the formation region of the insulating layer 352 dividing each selected gate line (SGD), it is not necessary to form memory holes 334. However, for manufacturing reasons, memory holes 334 are formed in a state of uniformly positioned configuration. For this reason, memory holes 334 are also formed in the formation region of the insulating layer 352. Therefore, as Figure 5 As shown, each select gate line SGD has a cutout 340 at its boundary with an adjacent select gate line SGD, which cuts through the area forming the memory hole 334. In contrast, the select gate lines SGD at both ends of each block BLK do not have cutouts 340 at the ends of the block BLK that form the area forming the memory hole 334.

[0092] Each block BLK has two select gate lines SGD0 and SGD4 (hereinafter also referred to as external select gate lines SGD(outer)) at both ends, with a notch 340 on only one end. The remaining three select gate lines SGD1 to SGD3 (hereinafter also referred to as internal select gate lines SGD(inner)) of each block BLK have notches 340 at both ends. Therefore, the internal select gate line SGD(inner) is narrower than the external select gate line SGD(outer), and correspondingly, its resistance value is larger than that of the external select gate line SGD(outer).

[0093] Furthermore, in the following description, the external select gate line SGD(outer) of the select string component will be referred to as SGD_sel(outer), and the external select gate line SGD(outer) of the non-select string component will be referred to as SGD_usel(outer). Additionally, the internal select gate line SGD(inner) of the select string component will be referred to as SGD_sel(inner), and the internal select gate line SGD(inner) of the non-select string component will be referred to as SGD_usel(inner).

[0094] (USTRDIS (Non-selective string discharge))

[0095] Figure 6 This is a graph that uses time on the horizontal axis and voltage on the vertical axis to illustrate USTRDIS. Figure 6 This illustrates an example where the external select gate line SGD(outer) is selected, but the internal select gate line SGD(inner) is not selected. Figure 6The single-dot dashed line represents the voltage change of SGD_sel(outer), and the dashed line represents the voltage change of SGD_usel(inner).

[0096] As described above, during readout, a voltage VSG_sel is applied to SGD_sel, which constitutes the select string assembly, to turn on the select gate transistor ST1, and a voltage VSG_usel (e.g., 0V) is applied to SGD_usel, which constitutes the non-select string assembly, to turn off the select gate transistor ST1. Prior to this readout operation, both SGD_sel and SGD_usel are executed by USTRDIS (non-select string discharge).

[0097] To prevent interference (false writes caused by unexpected rises in threshold voltage), USTRDIS performs full channel conduction before operation. That is, the read operation has a USTRDIS period and an actual read period (hereinafter referred to as the actual read period). During the USTRDIS period, SGD_sel and SGD_usel are set to the voltage VSG_sel that turns on the select gate transistor ST1.

[0098] like Figure 6 As shown, the USTRDIS period is first set before the actual readout period. A voltage VSG_sel is applied to SGD_sel(outer) and SGD_usel(inner). SGD_sel(outer) is maintained at voltage VSG_sel during the readout period. SGD_usel(inner) is reduced to the voltage VSG_usel (e.g., 0V) used to turn off the select gate transistor ST1.

[0099] In addition, Figure 6 The example shown illustrates how the non-select word line WL_usel is set to voltage Vread, while the select word line WL_sel changes to the voltage used to read A and F levels during the actual readout period.

[0100] Figure 7 and Figure 8 It is used to utilize and Figure 6 The same approach is used to illustrate the problems encountered during USTRDIS. In Figure 7 and Figure 8 In the diagram, a single-dot dashed line represents the voltage change of SGD_sel(outer), a solid line represents the voltage change of SGD_usel(outer), and a dashed line represents the voltage change of SGD_usel(inner).

[0101] In USTRDIS, SGD_sel and SGD_usel require a relatively long time to transition from 0V to the target voltage VSG_sel. Therefore, in order to shorten this time, the voltage generation circuit 28 generates an overdrive voltage at the transition moment that exceeds the level of the target voltage VSG_sel.

[0102] The overdrive voltage is a voltage that is greater than the target voltage VSG_sel in the positive direction. After applying this overdrive voltage, SGD_sel and SGD_usel reach the target voltage VSG_sel in a relatively short time.

[0103] However, as mentioned above, the resistance of the inner gate select line SGD(inner) is higher than that of the outer gate select line SGD(outer). Therefore, even if a drive voltage is applied to the inner gate select line SGD(inner), the time it takes for the inner gate select line SGD(inner) to reach the target voltage VSG is longer than that of the outer gate select line SGD(outer). Figure 7 (The tilt decreases). As a result, such as Figure 7 As shown, if the inner select gate line SGD(inner) is to reach the target voltage, then SGD_sel(outer) and SGD_usel(outer), which are the outer select gate lines SGD(outer), will exceed the target voltage VSG_sel, resulting in overshoot.

[0104] Figure 8 This illustrates an example where the overdrive time is shortened or the jump amount is reduced (i.e., the overdrive voltage is reduced) to suppress such overshoot. In this case, SGD_sel(outer) and SGD_usel(outer) do not produce overshoot, but SGD_usel(inner) does not reach the target voltage VSG_sel during USTRDIS. As a result, it is considered that electron elimination is not sufficient. Figure 7 and Figure 8 In any of these cases, there is a possibility that the result will be interfered with.

[0105] (Overdrive control)

[0106] Therefore, in this embodiment, the supply target for the overdrive voltage used to obtain the target voltage VGS_sel is determined by whether it is the external gate selection line SGD(outer) or the internal gate selection line SGD(inner), and the resistance value of the supply circuit for supplying the overdrive voltage is changed accordingly.

[0107] Figure 9 This is a block diagram showing a partial configuration of the voltage generation circuit 28. Additionally, Figure 10This is a block diagram illustrating an example of the configuration of the line decoder 25. Furthermore, in Figure 10 The diagram only shows a partial configuration of the voltage generation circuit 28.

[0108] exist Figure 10 In this circuit, voltage generation circuit 28 generates various voltages, including those required for programming and reading operations of the memory cell transistor MT. Voltage generation circuit 28 includes: a supply circuit 41 supplying voltage to signal lines SG0-SG4; an SG driver 28A supplying voltage to signal line SG5; and multiple CG drivers 28B supplying voltage to signal lines CG0-CG7 respectively. These signal lines SG0-SG5 and CG0-CG7 are branched by line decoder 25 and connected to the wiring of each block BLK. Specifically, signal lines SG0-SG4 function as global drain-side select gate lines and are connected via line decoder 25 to the select gate lines SGD0-SGD4, which are local select gate lines in each block BLK. Signal lines CG0-CG7 function as global word lines and are connected via line decoder 25 to the word lines WL0-WL7, which are local word lines in each block BLK. Signal line SG5 functions as a global source-side select gate line and is connected to the select gate line SGS, which serves as a local select gate line in each block BLK, via line decoder 25.

[0109] The voltage generation circuit 28 is controlled by the sequence generator 27 to generate various voltages. The SG driver (select gate line driver) 28A and the CG driver (word line driver) 28B supply the various generated voltages to the corresponding signal lines SG5 and CG0 to CG7, respectively.

[0110] The line decoder 25 has multiple switch circuit groups 25A corresponding to each block, and multiple block decoders 25B respectively configured corresponding to the multiple switch circuit groups 25A. Each switch circuit group 25A includes multiple transistors TR_SG0 to TR_SG4 connecting signal lines SG0 to SG4 to select gate lines SGD0 to SGD4, multiple transistors TR_CG0 to TR_CG7 connecting signal lines CG0 to CG7 to word lines WL0 to WL7, and a transistor TR_SG5 connecting signal line SG5 to select gate line SGS. Transistors TR_SG0 to TR_SG5 and transistors TR_CG0 to TR_CG7 are high-voltage transistors.

[0111] When each block decoder 25B is specified by the row address, it supplies the block selection signal BLKSEL to the gates of transistors TR_SG0 to TR_SG5 and transistors TR_CG0 to TR_CG7. Consequently, in the switching circuit group 25A that supplies the block selection signal BLKSEL from the block decoder 25B specified by the row address, transistors TR_SG0 to TR_SG5 and TR_CG0 to TR_CG7 are turned on. Therefore, the voltage supplied from the power generation circuit 28 to the signal lines SG0 to SG5 and CG0 to CG7 is supplied to the selection gate lines SGD0 to SGD4, SGS, and word lines WL0 to WL7 contained in the block BLK to be operated.

[0112] In other words, the voltage generation circuit 28 and the line decoder 25 are used to supply the read voltage VCGRV to the select word line WL and the voltage VREAD or VREADK to the non-select word line WL. Additionally, for example, the voltage VSG_sel is supplied to the select gate line SGD (SGD_sel) connected to the select gate transistor ST1 of the string component SU that is the target of the operation, and a voltage of 0V, VSG_usel, is supplied to the select gate line SGD (SGD_usel) connected to the select gate transistor ST1 of the string component SU that is not the target of the operation.

[0113] exist Figure 9 In this circuit, the voltage generation circuit 28 includes a voltage generation circuit 40 and a supply circuit 41. Furthermore, in... Figure 9 The diagram only shows the circuitry used to supply voltage to the selected gate line SGD. The voltage generation circuit 40 is composed of a charge pump circuit, etc., and generates various voltages. The supply circuit 41 includes an SGD_sel (inner) driver 42, an SGD_usel (inner) driver 43, an SGD_sel (outer) driver 44, an SGD_usel (outer) driver 45, a MUX (Multiplexer) (inner) 46, and a MUX (outer) 47.

[0114] Figure 11 It means Figure 9 The circuit diagram shows an example of the specific configuration of the drivers 42-45.

[0115] Drivers 42-45 each have multiple input terminals for inputting various input voltages, and can input various voltages from voltage generation circuit 40 via these input terminals. Each input terminal of drivers 42-45 is connected to an output terminal via switches T1, T2, ... configured on the respective supply paths of the various voltages. By selecting any one of switches T1, T2, ... to turn on, the voltage supplied to the supply path connected to the selected switch appears at the output terminal.

[0116] Drivers 42 and 43 are drivers corresponding to SGD_inner. Driver 42 outputs the voltage VSG_sel applied to the selected gate line SGD_sel from the output terminal, and driver 43 outputs the voltage VSG_usel applied to the unselected gate line SGD_usel from the output terminal.

[0117] Drivers 44 and 45 are drivers corresponding to the external select gate line SGD(outer). Driver 44 outputs the voltage VSG_sel applied to the selected select gate line SGD_sel from the output terminal, and driver 45 outputs the voltage VSG_usel applied to the unselected select gate line SGD_usel from the output terminal.

[0118] In this embodiment, in drivers 44 and 45, which correspond to the external select gate line SGD(outer), a resistor R1 is provided on the voltage supply path. This resistor R1 is used to suppress the slope (voltage rise rate) of the voltage applied to the external select gate line SGD(outer). Furthermore, as the resistor R1, a metal wire is used, and the effective resistance value can be increased by making the metal wire thinner.

[0119] During USTRDIS, the voltage generation circuit 40 applies an overdrive voltage to drivers 42 and 44 to obtain the target voltage VSG_sel, and applies the selected gate line SGD voltage VSG_sel during the actual readout period. Additionally, during USTRDIS, drivers 43 and 45 apply the target voltage VSG_sel, and during the actual readout period, apply the voltage VSG_usel when the selected gate line SGD is not selected. Furthermore, the overdrive voltage output from the voltage generation circuit 40 during USTRDIS is a voltage higher than VSG_sel.

[0120] Figure 12 and Figure 13 They represent respectively Figure 9 The circuit diagram shows an example of the specific configuration of MUX(inner)46 and MUX(outer)47.

[0121] exist Figure 12In this configuration, the MUX(inner)46 has six switches T11 to T16 along its voltage supply path. The inputs of switches T11, T13, and T15 are supplied with a voltage VSG_sel from the SGD_sel(inner) driver 42, and the inputs of switches T12, T14, and T16 are supplied with a voltage VSG_usel from the SGD_usel(inner) driver 43. The outputs of switches T15 and T16 are commonly connected to the select gate line SGD1(inner). Additionally, the outputs of switches T13 and T14 are commonly connected to the select gate line SGD2(inner), and the outputs of switches T11 and T12 are commonly connected to the select gate line SGD3(inner).

[0122] By selecting one of switches T15 and T16 to turn on, the voltage supplied to the selected switch is supplied to SDG1 (inner). Similarly, by selecting one of switches T13 and T14 to turn on, the voltage supplied to the selected switch is supplied to SDG2 (inner), and by selecting one of switches T11 and T12 to turn on, the voltage supplied to the selected switch is supplied to SDG3 (inner).

[0123] exist Figure 13 In this configuration, MUX(outer)47 has four switches T17 to T20 along its voltage supply path. A voltage VSG_sel from the SGD_sel(outer) driver 44 is applied to the inputs of switches T17 and T19, and a voltage VSG_usel from the SGD_usel(outer) driver 45 is applied to the inputs of switches T18 and T19. The outputs of switches T19 and T20 are commonly connected to the select gate line SGD0(outer). Additionally, the outputs of switches T17 and T18 are commonly connected to the select gate line SGD4(outer).

[0124] By selecting one of switches T19 and T20 to be turned on, the voltage supplied to the selected switch is supplied to SDG0 (outer). Similarly, by selecting one of switches T17 and T18 to be turned on, the voltage supplied to the selected switch is supplied to SDG4 (outer).

[0125] Next, refer to Figure 14 The operation of this implementation method will be explained. Figure 14 It is to utilize and Figure 6 The same description is used to illustrate the effects of the implementation methods during USTRDIS. In Figure 14In the diagram, a single-dot dashed line represents the voltage change of SGD_sel(outer), a solid line represents the voltage change of SGD_usel(outer), and a dashed line represents the voltage change of SGD_usel(inner).

[0126] Now, data is read from the memory cell transistors that are written using a prescribed code. Information about the various voltages required for data readout is stored in the memory (not shown) of the sequence generator 27. Based on this information, the sequence generator 27 causes the voltage generation circuit 28 to generate the voltage required for readout.

[0127] In other words, the voltage generation circuit 28 is controlled by the sequence generator 27 to generate an overdrive voltage during USTRDIS, which is supplied to drivers 42-45. Drivers 42-45 turn on switch T1, select the overdrive voltage, and output it. The selection gate lines SGD1-SGD3, which are supplied with the overdrive voltage by drivers 42 and 43 respectively, have larger resistance values ​​compared to the selection gate lines SGD0 and SGD4, which are supplied with the overdrive voltage by drivers 44 and 45 respectively. However, since resistor R1 is provided in the voltage supply path of drivers 44 and 45, the voltage rise rate of selection gate lines SGD0 and SGD4 is suppressed. In this way, the voltage change of the inner selection gate line SGD(inner) can be made approximately the same as the voltage change of the outer selection gate line SGD(outer), and the voltage rise rate of selection gate lines SGD0-SGD4 can be fixed.

[0128] like Figure 14 As shown, the voltages of SGD(inner) and SGD(outer) during USTRDIS change at approximately the same rate of rise. As a result, SGD(outer) does not overshoot, and SGD(outer) and SGD(inner) reach the target voltage VSG_sel in a short time using the same voltage change.

[0129] Thus, in this embodiment, by varying the resistance value of the overdrive voltage supply circuit according to the type of selected gate line, the voltage applied to the selected gate line can be uniform regardless of the type of selected gate line, and the target voltage can be reached in a short time.

[0130] (Second Implementation)

[0131] Figure 15 This is a circuit diagram showing the SGD_usel(outer) driver used in the second embodiment of the present invention. Figure 15 It is a replacement Figure 11 The SGD_usel(outer) driver 45 is used in this embodiment, and the other hardware configurations are the same as in the first embodiment.

[0132] When selecting an external select gate line SGD(outer) in block BLK, the other external select gate lines SGD(outer) in that block BLK are not selected. On the other hand, when selecting an internal select gate line SGD(inner) in block BLK, neither of the two external select gate lines SGD(outer) in that block BLK is selected. Therefore, the non-selection voltage VSG_usel from the voltage generation circuit 40 may be supplied to one external select gate line SGD(outer) or to both external select gate lines SGD(outer), depending on the selection state.

[0133] In other words, Figure 11 The output of the SGD_usel(outer) driver 45 can be supplied to one external select gate line SGD(outer) via only one of the switches T18 and T20 of the MUX(outer) 47, or to both external select gate lines SGD(outer) via both switches T18 and T20 of the MUX(outer) 47. In other words, the load on the driver 45 varies depending on the selection state SGD_usel(outer), making it impossible to achieve a uniform voltage rise rate for the external select gate line SGD(outer). Therefore, in this embodiment, the SGD_usel(outer) driver 50 is used instead of the SGD_usel(outer) driver 45.

[0134] SGD_usel(outer) driver 50 is a pair Figure 11 The SGD_usel(outer) driver 45 is equipped with a NOR circuit 51 and a switch TO, and resistors R2 and R3 are used instead of resistor R1. The NOR circuit 51 is input with a signal String Add[0] indicating whether to apply voltage VSG_usel to the selected gate line SGD0, and a signal String Add[4] indicating whether to apply voltage VSG_usel to the selected gate line SGD5. The NOR circuit 51 performs a NOR operation on the two inputs and outputs the result to the switch TO.

[0135] A series circuit of resistors R3 and R2 is provided on the voltage supply path between the output terminal of voltage generation circuit 40 and switch T1. Switch TO is connected across resistor R3. When the operation result of NOR circuit 51 is logic "1", switch TO is turned on, short-circuiting resistor R3. When the operation result of NOR circuit 51 is logic "0", switch TO is turned off.

[0136] Next, refer to Figure 16 and Figure 17 The operation of this implementation method will be explained. Figure 16 and Figure 17 This is an explanatory diagram used to illustrate the operation of the implementation method.

[0137] Now, assume that select gate line SGD0 is selected and select gate line SGD4 is not selected. That is, in this case, the SGD_usel(outer) driver 50 only needs to supply voltage VSG_usel to one external select gate line SGD(outer). Figure 16 As shown, in this case, signal String Add[0] is "H" and signal String Add[4] is "L". The output of NOR circuit 51 is "L" (logic value "0"), switch circuit TO is open, and resistor R3 is not short-circuited. That is to say, as Figure 16 As indicated by the arrow, a series circuit of resistors R3 and R2 is connected in the voltage supply path between the output terminal of the voltage generation circuit 40 and the switch T1. These two resistors R3 and R2 are used to suppress the voltage change rate of the external selected gate line SGD (outer).

[0138] Additionally, it is set that both select gate lines SGD0 and SGD4 are not selected. That is, in this case, the SGD_usel(outer) driver 50 supplies voltage VSG_usel to the two external select gate lines SGD(outer). For example... Figure 17 As shown, in this case, the signal String Add is [0], and String Add[4] are both "L". The output of NOR circuit 51 becomes "H" (logic value "1"), the switch circuit TO is turned on, and the resistor R3 is short-circuited. That is to say, as Figure 17 As indicated by the arrow, only resistor R2 is connected in the voltage supply path between the output of voltage generation circuit 40 and switch T1. As a result, the voltage change rate of the externally selected gate line SGD (outer) tends to increase.

[0139] Thus, in this embodiment, the resistance value of the SGD_usel(outer) driver is switched depending on whether the SGD_usel(outer) driver supplies voltage VSG_usel to one external select gate line SGD(outer) or to two external select gate lines SGD(outer). Even when either select gate line SGD is selected, the voltage change rate of the non-selected external select gate line SGD(outer) can be kept constant.

[0140] Furthermore, the resistance values ​​of resistors R2 and R3 can also be configured to be set and changed.

[0141] (Example of variation)

[0142] Figure 18 This is a circuit diagram representing the SGD_usel(inner) driver. Figure 18 It is a replacement Figure 11 The SGD_usel(inner) driver 43 used in this embodiment has the same other hardware configuration as in the first or second embodiment.

[0143] When the external select gate line SGD(outer) in the selection block BLK is selected, none of the three internal select gate lines SGD(inner) in the BLK are selected. On the other hand, when the internal select gate lines SGD(inner) in the selection block BLK are selected, two of the internal select gate lines SGD(inner) in the BLK are not selected. Therefore, the non-selection voltage VSG_usel from the voltage generation circuit 40 may be supplied to the two internal select gate lines SGD(inner) or to all three internal select gate lines SGD(inner), depending on the selection state.

[0144] In other words, Figure 11 The output of the SGD_usel(inner) driver 43 can be supplied to two internal select gate lines SGD(inner) via two switches T12, T14, and T16 of the MUX(inner) 46, or to all three internal select gate lines SGD(inner) via all switches T12, T14, and T16 of the MUX(inner) 46. In other words, the load on the SGD_usel(inner) driver 43 varies depending on the selection state, making it impossible to achieve a uniform voltage rise rate for the internal select gate lines SGD(inner). Therefore, in this embodiment, the SGD_usel(inner) driver 60 is used instead of the SGD_usel(inner) driver 43.

[0145] SGD_usel(inner) driver 60 is a pair Figure 11The SGD_usel(inner) driver 43 is composed of an additional NOR circuit 61, switch TO, resistor R4, and resistor R5. The NOR circuit 61 is input with a signal String Add[1] indicating whether to apply voltage VSG_usel to the selected gate line SGD1, a signal String Add[2] indicating whether to apply voltage VSG_usel to the selected gate line SGD2, and a signal String Add[3] indicating whether to apply voltage VSG_usel to the selected gate line SGD3. The NOR circuit 613 performs the input NOR operation and outputs the operation result to switch TO.

[0146] A series circuit of resistors R5 and R4 is provided on the voltage supply path between the output of voltage generation circuit 40 and switch T1. Switch T0 is connected across resistor R5. When the operation result of NOR circuit 61 is logic "1", it becomes on, short-circuiting resistor R5. When the operation result of NOR circuit 61 is logic "0", switch circuit T0 is off. Furthermore, the resistance ratio of resistors R5 and R4 is set, for example, to 1:2. Moreover, the resistance ratio of resistors R5 and R4 can take into account all resistance values ​​from the back end of the driver to the internal select gate line SGD (inner), but the resistance values ​​of resistors R5 and R4 are dominant, or only the resistance values ​​of resistors R5 and R4 can be considered. Additionally, the resistance values ​​of resistors R5 and R4 can be configured to be changeable.

[0147] Furthermore, a driver for the external gate selection line (SGD) can also be used. Figure 15 The SGD_usel(outer) driver 50.

[0148] Next, the operation of this implementation method will be explained.

[0149] Now, assume that one of the internal select gate lines SGD(inner) is selected, and the other two internal select gate lines SGD(inner) are not selected. That is, in this case, the SGD_usel(inner) driver 60 only needs to supply the voltage VSG_usel to the two internal select gate lines SGD(inner). In this case, any one of the signals String Add[1] to String Add[3] is "H", and the output of the NOR circuit 61 becomes "L" (logic value "0"). The switch circuit TO is open, and the resistor R5 is not short-circuited. That is, a series circuit of resistors R5 and R4 is connected on the voltage supply path between the output of the voltage generation circuit 40 and the switch T1. These two resistors R5 and R4 are used to suppress the voltage change rate of the internal select gate line SGD(inner).

[0150] Furthermore, it is assumed that the select gate lines SGD0 to SGD3 are not selected. That is, in this case, the SGD_usel(inner) driver 60 supplies voltage VSG_usel to the three internal select gate lines SGD(inner). In this case, signals String Add[1] to String Add[3] are all "L", and the output of the NOR circuit 61 becomes "H" (logic value "1"). As a result, the switch circuit TO becomes on, and the resistor R5 is short-circuited. That is, only the resistor R4 is connected on the voltage supply path between the output of the voltage generation circuit 40 and the switch T1. As a result, the voltage change rate of the internal select gate line SGD(inner) is prone to increase.

[0151] Thus, in this embodiment, the SGD_usel(inner) driver switches the resistance value of the SGD_usel(inner) driver depending on whether the voltage VSG_usel is supplied to the two internal select gate lines SGD(inner) or the three internal select gate lines SGD(inner). Even when any select gate line SGD is selected, the voltage change rate of the non-selected internal select gate line SGD(inner) can be kept constant.

[0152] (Third Implementation)

[0153] Figure 19 This is a block diagram illustrating the third embodiment of the present invention. This embodiment is based on... Figure 11 The voltage generating circuit 40 uses voltage generating circuits 71 and 72 instead of drivers 73 and 74, which is different from the first embodiment. However, the other configurations are the same as the first embodiment.

[0154] In this embodiment, during USTRDIS, by making the overdrive period (overdrive period) of the overdrive voltage applied to the external select gate line SGD(outer) different from the overdrive period of the internal select gate line SGD(inner), overshoot can be suppressed, and the voltage applied to the select gate line can reach the target voltage in a short time regardless of the type of select gate line.

[0155] The SGD_sel(outer) driver 73 has the same configuration as the SGD_sel(inner) driver 42, and the SGD_usel(outer) driver 74 has the same configuration as the SGD_usel(inner) driver 43. The voltage generation circuits 71 and 72 have the same configuration as the voltage generation circuit 40.

[0156] Next, refer to Figure 20 The operation of this implementation method will be explained. Figure 20 This is a graph showing the voltage changes of the outer and inner selected gate lines SGD (outer and inner) during USTRDIS, with the horizontal axis representing time and the vertical axis representing voltage. The left side shows the characteristics in the comparative example, and the right side shows the characteristics in this embodiment.

[0157] Figure 20 The comparative example illustrates applying the same overdrive voltage to both the external select gate line SGD(outer) and the internal select gate line SGD(inner) during USTRDIS. As described above, in this case, because the resistance value of the internal select gate line SGD(inner) is larger than that of the external select gate line SGD(outer), the external select gate line SGD(outer) experiences an overshoot in order for the internal select gate line SGD(inner) to reach the target voltage.

[0158] In contrast, in this embodiment, voltage generation circuit 71 and voltage generation circuit 72 generate overdrive voltages of the same voltage level, but the overdrive periods are different. That is, voltage generation circuit 71 generates overdrive voltage for a relatively long period, while voltage generation circuit 72 generates overdrive voltage for a shorter period than voltage generation circuit 71.

[0159] The output of voltage generation circuit 71 is supplied to SGD_sel(inner) drivers 42 and 43, and the output of voltage generation circuit 72 is supplied to SGD_sel(outer) drivers 73 and 74. SGD_sel(inner) driver 42 and driver 73 have the same configuration. The output of SGD_sel(inner) driver 42 differs from that of SGD_sel(outer) driver 73 only in the overdrive period. The overdrive voltage applied to the external selected gate line SGD(outer) is applied for a relatively short period, while the overdrive voltage applied to the internal selected gate line SGD(inner) is applied for a longer period.

[0160] Similarly, the outputs of SGD_usel(inner) driver 43 and SGD_usel(outer) driver 74 differ only in the overdrive period. The overdrive voltage applied to the external select gate line SGD(outer) is applied for a relatively short period, while the overdrive voltage applied to the internal select gate line SGD(inner) is applied for a longer period.

[0161] like Figure 20As shown, the overdrive voltage applied to the external select gate line SGD(outer) is for a relatively short period, while the overdrive voltage applied to the internal select gate line SGD(inner) is for a longer period. As a result, the external select gate line SGD(outer), due to its smaller resistance, reaches the target voltage relatively quickly, with a shorter overdrive period and no overshoot. Conversely, the internal select gate line SGD(inner), with its longer overdrive period, reaches the target voltage in a relatively short time.

[0162] Thus, in this embodiment, by making the overdrive periods of the external select gate line SGD(outer) and the internal select gate line SGD(inner) different, it is possible to prevent overshoot of the external select gate line SGD(outer) and enable the external select gate line SGD(outer) and the internal select gate line SGD(inner) to reach the target voltage relatively quickly.

[0163] In this embodiment, examples of different overdrive periods have been described, but the overdrive voltage value may also be different when used for external select gate SGD (outer) and when used for internal select gate SGD (inner).

[0164] This invention is not limited to the described embodiments, and various changes can be made during the implementation phase without departing from its spirit. Furthermore, the embodiments encompass inventions at various stages, and various inventions can be extracted through appropriate combinations of the disclosed constituent elements. For example, even if several constituent elements are deleted from all the constituent elements shown in the embodiments, if the problems described in the "Problems to be Solved by the Invention" column are solved and the effects described in the "Effects of the Invention" column are obtained, the structure with the deleted constituent elements can be extracted as an invention.

[0165] [Explanation of Symbols]

[0166] 1. Memory controller

[0167] 2. Non-volatile memory

[0168] 12 processors

[0169] 13 Host Interface

[0170] 15. Memory Interface

[0171] 21 Logic Control Circuit

[0172] 22 Input / Output Circuit

[0173] 23-cell storage array

[0174] 24 Sensing Amplifier

[0175] 24A Sensing Amplifier Component Group

[0176] 25-line decoder

[0177] 26 Registers

[0178] 27 Sequence Generator

[0179] 28 Voltage Generation Circuit

[0180] 32 Input / Output Pad Group

[0181] 40 Voltage Generation Circuit

[0182] 41 Supply Circuit

[0183] 42 SGD_sel(inner) driver

[0184] 43 SGD_usel(inner) driver

[0185] 44 SGD_sel(outer) driver

[0186] 45 SGD_usel(outer) driver

[0187] 46 MUX (inner)

[0188] 47 MUX (outer).

Claims

1. A semiconductor memory device comprising: Multiple storage units; Word lines are connected to the gates of the plurality of memory cells; Bit lines are electrically connected to one end of the plurality of memory cells through a plurality of select gate transistors, the plurality of select gate transistors including two external select gate transistors and one or more internal select gate transistors located between the two external select gate transistors; Two external select gate lines are respectively connected to the gates of the two external select gate transistors; Two or more internal select gate lines are respectively connected to the gate of one or more internal select gate transistors; as well as The voltage generation circuit independently supplies a first voltage to the external select gate line and a second voltage to the internal select gate line when reading data recorded in the plurality of memory cells.

2. The semiconductor memory device according to claim 1, wherein The voltage rise rates of the first voltage and the second voltage are controlled to be different.

3. The semiconductor memory device according to claim 2, wherein... The voltage generation circuit includes: an external select gate line driver for supplying voltage to the external select gate line; and an internal select gate line driver for supplying voltage to the internal select gate line. The resistance value on the voltage supply path of the driver for the external gate line is greater than the resistance value on the voltage supply path of the driver for the internal gate line.

4. The semiconductor memory device according to claim 1, wherein The application period of the overdrive voltage supplied to the external select gate line and the internal select gate line is controlled to be different.

5. The semiconductor memory device according to claim 4, wherein The voltage generation circuit includes: an external selection gate line voltage generation circuit that generates a voltage supplied to the external selection gate line; and an internal selection gate line voltage generation circuit that generates a voltage supplied to the internal selection gate line. The application period of the overdrive voltage of the external gate line voltage generation circuit is shorter than that of the internal gate line voltage generation circuit.

6. The semiconductor memory device according to claim 1, wherein The voltage generation circuit includes an external selection gate line driver that generates the voltage supplied to the external selection gate line. The external select gate line driver controls the voltage supply based on the number of external select gate lines corresponding to memory cells that are not read from among the plurality of memory cells.

7. The semiconductor memory device according to claim 6, wherein The external select gate line driver changes the resistance value on the voltage supply path when the number of external select gate lines corresponding to memory cells that are not the read objects is 1 or 2.

8. The semiconductor memory device according to claim 1, wherein The voltage generation circuit has a driver for the internal selection gate line that generates the voltage supplied to the internal selection gate line. The driver for the internal select gate line controls the voltage supply based on the number of internal select gate lines corresponding to memory cells that are not read from among the plurality of memory cells.

9. The semiconductor memory device according to claim 8, wherein In the driver for the internal select gate line, the more internal select gate lines that correspond to memory cells that are not the read objects, the smaller the resistance value on the voltage supply path.

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