Multi-layer Stacked High-bandwidth Memory Packaging Method and Packaging Structure

Abstract

The present invention provides a method and a packaging structure for a multi-layer stacked high-bandwidth memory package. The method provides a buffer chip and a plurality of first memory chips, and all the above chips are provided with a plurality of conductive vias. A first conductive bump and a second conductive bump are sequentially formed at positions corresponding to the conductive vias on the first surface of the first memory chip. A first pad is formed at a position corresponding to the conductive via on the second surface of the first memory chip. Through a thermocompression bonding process, the second conductive bumps and the first pads of every two adjacent first memory chips are nested, and the plurality of first memory chips are sequentially and insulatingly stacked on the buffer chip. Through a reflow soldering process, the stacked plurality of first memory chips and the buffer chip are reflow soldered. A plastic encapsulation layer is formed, and the plastic encapsulation layer wraps the plurality of first memory chips and the buffer chip. By means of two-step soldering process in the present invention, the second conductive bumps and the first pads are nested, which can reduce the deformation of the second conductive bumps and achieve ultra-fine pitch interconnection.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and particularly relates to a multi-layer stacked high-bandwidth memory packaging method and a packaging structure. Background Art

[0002] For enterprise applications such as data centers, large-capacity high-speed storage has become a necessity. To meet this demand, high bandwidth memory (HBM) has emerged. As Figure 1 shown, HBM uses through-silicon vias (TSVs) 12 to vertically interconnect several memory chips 11, and data interaction with the outside world is carried out through the underlying buffer chip 10. Due to the advantages of high density and short vertical interconnection distance of TSVs, the data transmission speed is greatly improved.

[0003] Currently, the multi-layer chip stacking of HBM adopts the thermal compression bonding (TCB) process. Through rapid heating, the micro-bumps 14 are connected to the back pads 13 of the chips, and the back pads 13 of the chips are connected to the through-silicon vias 12 of the chips. Currently, the composition of the micro-bumps 14 is mainly a copper-tin structure, while the main component of the back pads 13 of the chips is a nickel-gold structure. The final stacked structure is protected by a plastic encapsulation layer 15.

[0004] In the case of using copper-tin micro-bumps, due to the deformability of tin during reflow, in order to prevent short circuits between micro-bumps, the spacing between micro-bumps and the height of tin need to be strictly controlled. Currently, the spacing is above 40um. When the spacing is reduced to below 25um, due to the too small amount of tin, it is completely converted into an intermetallic compound under hot carrier conditions, resulting in reliability failure.

[0005] In order to increase the storage capacity and data throughput speed, it is necessary to increase the number of stacked chips and the number of pins. However, in the current structure of micro-bumps, due to the limitations of bump height and spacing, the room for continuous improvement is limited. To solve this problem, currently, a multi-chip stacking technology based on hybrid bonding is being developed, but hybrid bonding requires a high-precision chemical mechanical polishing process, which is costly, and hybrid bonding has high requirements for the surface flatness of chips, and it is difficult to control the yield in actual production.

[0006] In view of the above problems, it is necessary to propose a multi-layer stacked high-bandwidth memory packaging method and a packaging structure that are reasonably designed and can effectively solve the above problems. Summary of the Invention

[0007] The present invention aims to at least solve one of the technical problems existing in the prior art, and provides a multi-layer stacked high-bandwidth memory packaging method and a packaging structure.

[0008] One aspect of the present invention provides a method for packaging a multi-layer stacked high-bandwidth memory, the method comprising:

[0009] Providing a buffer chip and a plurality of first memory chips, both the buffer chip and the plurality of first memory chips being provided with a plurality of conductive vias;

[0010] At positions corresponding to the conductive vias on the surface of the first memory chip facing the buffer chip, a first conductive bump and a second conductive bump are sequentially formed;

[0011] Forming a first pad at a position corresponding to the conductive via on the surface of the first memory chip facing away from the buffer chip;

[0012] Through a thermocompression bonding process, the second conductive bumps and the first pads of every two adjacent first memory chips are nested to stack the plurality of first memory chips on the buffer chip in sequence in an insulating manner;

[0013] Through a reflow soldering process, the stacked plurality of first memory chips and the buffer chip are reflow soldered;

[0014] Forming a plastic encapsulation layer that encapsulates the buffer chip and the plurality of first memory chips.

[0015] Optionally, the step of nesting the second conductive bumps and the first pads of every two adjacent first memory chips through a thermocompression bonding process includes:

[0016] Forming a protrusion on the first pad;

[0017] Through a thermocompression bonding process, the protrusions of every two adjacent first memory chips are pressed into the second conductive bumps.

[0018] Optionally, the melting point of the first conductive bump is greater than the melting point of the second conductive bump, and the temperature of the thermocompression bonding process is less than the melting point of the second conductive bump.

[0019] Optionally, the step of reflow soldering the stacked plurality of first memory chips and the buffer chip through a reflow soldering process includes:

[0020] In an acidic gas environment, through a reflow soldering process, the stacked plurality of first memory chips and the buffer chip are reflow soldered.

[0021] Optionally, the step of sequentially forming a first conductive bump and a second conductive bump at positions corresponding to the conductive vias on the surface of the first memory chip facing the buffer chip includes:

[0022] A first passivation layer and a first dielectric layer are sequentially formed on a first surface of the first memory chip;

[0023] A photoresist layer is formed on the first dielectric layer, and the photoresist layer is patterned to form a plurality of first openings, and the plurality of first openings respectively correspond to the plurality of conductive vias;

[0024] The first conductive bumps and the second conductive bumps are sequentially formed at the plurality of first openings;

[0025] The photoresist layer is removed.

[0026] Optionally, a surface of the second conductive bump protrudes from a surface of the photoresist layer; before removing the photoresist layer, the method further includes:

[0027] The second conductive bump is ground so that a surface of the second conductive bump is flush with the surface of the photoresist layer.

[0028] Optionally, forming the first pad at a position corresponding to the conductive via on a surface of the first memory chip facing away from the buffer chip includes:

[0029] A second passivation layer is formed on a second surface of the first memory chip, and the second passivation layer is patterned to form a plurality of second openings, and the plurality of second openings correspond to the plurality of conductive vias;

[0030] The first pad is formed at the plurality of second openings.

[0031] Optionally, a third passivation layer and a second dielectric layer are provided on a surface of the buffer chip facing away from the first memory chip, and a plurality of conductive protrusions are provided on the second dielectric layer, and the plurality of conductive protrusions correspond to and are electrically connected to the plurality of conductive vias;

[0032] A fourth passivation layer and a second pad are provided on a surface of the buffer chip facing the first memory chip, wherein the second pad is nested with the second conductive bump on the first memory chip close to the buffer chip.

[0033] Optionally, when forming the encapsulation layer, the encapsulation layer wraps the plurality of first memory chips and the buffer chip, the method further includes:

[0034] Encapsulation material is filled between the plurality of first memory chips and between the first memory chip and the buffer chip, and the encapsulation material wraps the first pad, the second pad, the first conductive bump and the second conductive bump.

[0035] Another aspect of the present invention provides a multi-layer stacked high-bandwidth memory packaging structure, which is formed by using the packaging method described above.

[0036] For the multi-layer stacked high-bandwidth memory packaging method and packaging structure of the present invention, the packaging method provides a buffer chip and a plurality of first memory chips, and both the buffer chip and the plurality of first memory chips are provided with a plurality of conductive vias. Through the thermocompression bonding process, the second conductive bumps and the first pads of every two adjacent first memory chips are nested to stack the plurality of first memory chips on the buffer chip in sequence in an insulated manner. Through the reflow soldering process, the stacked plurality of first memory chips and the buffer chip are reflow soldered. By the two-step soldering process of the present invention, the second conductive bumps and the first pads are nested, which can reduce the deformation of the second conductive bumps, thereby reducing the pitch of the second conductive bumps and realizing ultra-fine pitch interconnection. Description of the Drawings

[0037] Figure 1 is a schematic structural diagram of a multi-layer stacked high-bandwidth memory packaging structure in the prior art;

[0038] Figure 2 is a schematic flow diagram of a multi-layer stacked high-bandwidth memory packaging method according to an embodiment of the present invention;

[0039] Figure 3 is a schematic structural diagram of the nesting of the second conductive bump and the first pad according to another embodiment of the present invention;

[0040] Figure 4 is a schematic structural diagram of the first pad according to another embodiment of the present invention;

[0041] Figures 5 to 11 is a schematic diagram of the packaging process in a multi-layer stacked high-bandwidth memory packaging method according to another embodiment of the present invention. Detailed Embodiments

[0042] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the drawings and specific embodiments.

[0043] As Figure 2 shown, one aspect of the present invention provides a multi-layer stacked high-bandwidth memory packaging method S100, and the packaging method S100 includes:

[0044] S110. Provide a buffer chip and a plurality of first memory chips, and both the buffer chip and the plurality of first memory chips are provided with a plurality of conductive vias.

[0045] Specifically, as Figure 10 and Figure 11As shown, a buffer chip 110 and a plurality of first memory chips 120 are provided. Among them, both the buffer chip 110 and the plurality of first memory chips 120 are provided with a plurality of conductive vias 130. Further preferably, the plurality of conductive vias 130 can be through-silicon vias. The vertical electrical interconnection of the through-silicon vias is realized by using the through-silicon via technology, reducing the package height. In this embodiment, the first memory chip 120 uses a dynamic random access memory chip, or it can also be other memory chips, which is not specifically limited in this embodiment.

[0046] S120. At the positions corresponding to the conductive vias on the surface of the first memory chip facing the buffer chip, a first conductive bump and a second conductive bump are sequentially formed.

[0047] Specifically, step S120 includes the following steps.

[0048] First, a first passivation layer and a first dielectric layer are sequentially formed on the surface of the first memory chip facing the buffer chip.

[0049] As Figure 5 shown, on the surface of the first memory chip 120 facing the buffer chip 110, that is, on the front surface of the first memory chip 120, a first passivation layer 121 and a first dielectric layer 122 are sequentially coated. Among them, the material of the first passivation layer 121 can be silicon dioxide, and the material of the first dielectric layer 122 can be polyimide (PI), polybenzoxazole (PBO), etc. In this embodiment, the material of the first dielectric layer 122 is polyimide (PI). The coating method is usually wafer spin coating, which is not specifically limited in this embodiment.

[0050] Second, a photoresist layer is formed on the first dielectric layer, and the photoresist layer is patterned to form a plurality of first openings, and the plurality of first openings respectively correspond to the plurality of conductive vias.

[0051] Specifically, a photoresist layer 123 is coated on the surface of the first dielectric layer 122, and the photoresist layer 123 is patterned by exposure and development to form a plurality of first openings (not marked in the figure), where the plurality of first openings respectively correspond to the plurality of conductive vias 130 on the first memory chip 120.

[0052] Third, the first conductive bump and the second conductive bump are sequentially formed at the plurality of first openings.

[0053] Specifically, as Figure 5As shown, a first conductive bump 124 and a second conductive bump 125 are sequentially formed at a plurality of first openings through an electroplating process. The first conductive bump 124 and the second conductive bump 125 are electrically connected to the conductive through-hole 130. In this embodiment, the material of the first conductive bump 124 can be a metal copper material, and the material of the second conductive bump 125 can be a metal tin material. Using a metal tin material for the second conductive bump 125 can keep the packaging cost at a relatively low level.

[0054] Finally, remove the photoresist layer.

[0055] As Figure 6 shown, the photoresist layer 123 can be removed by dry plasma etching and wet cleaning. This embodiment does not specifically limit the method for removing the photoresist.

[0056] Exemplarily, the surface of the second conductive bump protrudes from the surface of the photoresist layer; before removing the photoresist layer, the method further includes:

[0057] Grind the second conductive bump so that the surface of the second conductive bump is flush with the surface of the photoresist layer.

[0058] Specifically, when the first conductive bump 124 and the second conductive bump 125 are sequentially formed at a plurality of first openings through an electroplating process, the surface of the second conductive bump 125 protrudes from the surface of the photoresist layer 123. At this time, before removing the photoresist layer 123, the surface of the second conductive bump 125 also needs to be ground so that the height of the second conductive bump 125 is the same as the height of the photoresist layer 123. As Figure 7 shown, that is to say, the second conductive bump 125 has a columnar structure, which can be a cylindrical structure or a prismatic structure. The original form of the second conductive bump 125 is a columnar structure, different from the spherical shape of the traditional conductive bump. In this way, the lateral width can be reduced under the same volume.

[0059] S130. Form a first pad at a position corresponding to the conductive through-hole on the surface of the first memory chip facing away from the buffer chip.

[0060] It should be noted that when the thickness of the first memory chip 120 is very thin and a plurality of conductive through-holes 130 can be exposed, the first memory chip 120 does not need to be thinned. However, in this embodiment, as Figure 8 shown, the first memory chip 120 first needs to be thinned to expose the conductive through-holes 130 on the first memory chip 120.

[0061] Specifically, step S130 includes the following steps.

[0062] First, thin the surface of the first memory chip facing away from the buffer chip.

[0063] Specifically, as Figure 8 shown, thin the surface of the first memory chip 120 facing away from the buffer chip 110, that is, the back surface of the first memory chip 120, to expose a plurality of conductive vias 130 on the back surface of the first memory chip 120. The thinning process can be carried out by grinding or other methods, which are not specifically limited in this embodiment.

[0064] Secondly, form a second passivation layer on the surface of the first memory chip facing away from the buffer chip, and pattern the second passivation layer to form a plurality of second openings corresponding to the plurality of conductive vias.

[0065] Specifically, as Figure 9 shown, perform a back via process on the back surface of the thinned first memory chip 120 to fabricate the second passivation layer 126, and pattern the second passivation layer 126 by photolithography to form a plurality of second openings (not marked in the figure). Among them, the plurality of second openings are correspondingly arranged with the plurality of conductive vias 130. In this embodiment, the material of the second passivation layer 126 can be silicon dioxide or other materials that can play a passivation role, which are not specifically limited in this embodiment.

[0066] Finally, form the first pad at the plurality of second openings.

[0067] Specifically, as Figure 9 shown, form the first pad 127 by electroplating at the plurality of second openings. The shape of the first pad 127 is as Figure 3 and Figure 4 shown. Generally, the cross-section of the first pad 127 is circular or square. In this embodiment, the first pad 127 is a copper pad and has a cylindrical structure. The material of the first pad 127 can be selected according to actual needs, which are not specifically limited in this embodiment.

[0068] It should be noted that the topmost chip can be the first memory chip 120 or other chips. In this embodiment, the topmost chip is also the first memory chip 120. The thickness of the topmost first memory chip 120 is thicker than that of the first memory chips 120 in other layers, mainly to protect the multiple first memory chips 120 in other layers. Therefore, no conductive vias are provided in the topmost first memory chip 120. And only the surface of the topmost first memory chip 120 facing the buffer chip 110 is provided with a first conductive bump 124 and a second conductive bump 125, and the first conductive bump 124 and the second conductive bump 125 are nested and connected with the first pads 127 on the first memory chip 120 in its adjacent layer.

[0069] S140. Through a thermocompression bonding process, the second conductive bumps and the first pads of every two adjacent first memory chips are nested to stack the multiple first memory chips on the buffer chip in sequence and insulatingly.

[0070] Specifically, as Figure 3 shown, through the thermocompression bonding process, the second conductive bump 125 and the first pad 127 of every two adjacent first memory chips 120 are nested. Then, as Figure 10 shown, the thermocompression bonding process is used to stack the multiple first memory chips 120 on the buffer chip 110 in sequence and insulatingly. When stacking the multiple first memory chips 120 to form a stacked module, multiple stacked modules should be formed by stacking the multiple first memory chips 120. Therefore, it is necessary to first divide the multiple stacked modules to form independent first memory chip stacked modules, and then stack the multiple independent first memory chip stacked modules on the buffer chip 110 through the thermocompression bonding process.

[0071] It should be noted that through the thermocompression bonding process, the second conductive bump 125 and the first pad 127 of every two adjacent first memory chips 120 are nested, and then the multiple first memory chips 120 can also be stacked on the substrate in sequence and insulatingly.

[0072] Exemplarily, the step of nesting the second conductive bumps and the first pads of every two adjacent first memory chips through the thermocompression bonding process includes:

[0073] First, a protrusion is formed on the first pad.

[0074] Specifically, a photoresist layer is coated on the first pad 127, and the first pad 127 is patterned by photolithography and etching processes to form a protrusion 127a in the central area of the first pad 127. The size of the protrusion 127a is generally 3um - 5um, and the height of the protrusion 127a is below 5um. In this embodiment, the protrusion 127a is in the shape of a square prism.

[0075] Secondly, through a thermocompression bonding process, the protrusions of every two adjacent first memory chips are pressed into the second conductive bumps.

[0076] Specifically, as Figure 3 shown, a protrusion 127a is formed on the first pad 127. Through the thermocompression bonding process, the protrusions 127a of every two adjacent first memory chips 120 are pressed into the second conductive bumps 125.

[0077] Exemplarily, the melting point of the first conductive bump 124 is greater than that of the second conductive bump 125, and the temperature of the thermocompression bonding process is less than the melting point of the second conductive bump 125.

[0078] Specifically, the temperature of the thermocompression bonding process is lower than the melting point of the second conductive bump 125.

[0079] In this embodiment, since the second conductive bump is a tin bump, it is generally set to 180°C to 210°C. This temperature can ensure the low modulus of the tin bump, enable the protrusion 127a to be embedded in the tin bump, fix two adjacent first memory chips 120, and at the same time, the shape of the tin bump remains basically unchanged.

[0080] Exemplarily, as Figure 10 and Figure 11 shown, a third passivation layer 111 and a second dielectric layer 112 are provided on the surface of the buffer chip 110 facing away from the first memory chip 120. The third passivation layer 111 and the second dielectric layer 112 are patterned to form a plurality of openings, and a plurality of conductive protrusions 113 are formed at the plurality of openings. The plurality of conductive protrusions 113 correspond to and are electrically connected to a plurality of conductive vias 130, and the plurality of multi-point protrusions 113 are electrically connected to the outside.

[0081] A fourth passivation layer 114 and a second pad 115 are provided on the surface of the buffer chip 110 facing the first memory chip 120. Among them, the second pad 115 is nested with the second conductive bump 125 on the first memory chip 120 close to the buffer chip 110. In this embodiment, the second pad 115 on the buffer chip 110 and the first pad 127 on the first memory chip 120 are the same pads, and both are formed with protrusions 127a. The first pad 125 can also be a pad different from the first pad 127, and this embodiment does not make specific limitations.

[0082] It should be noted that the materials of the third passivation layer 111 and the fourth passivation layer 114 are not specifically limited in this embodiment, as long as they are materials that can play a passivation role. The material of the second dielectric layer 112 can be polyimide (PI), polybenzoxazole (PBO), etc. In this embodiment, the material of the second dielectric layer 122 is polyimide (PI). The coating method is usually wafer spin coating, which is not specifically limited in this embodiment.

[0083] S150. Through a reflow soldering process, the multiple first memory chips and the buffer chips that have been stacked are reflow soldered.

[0084] Exemplarily, the step of reflow soldering the multiple first memory chips and the buffer chips that have been stacked through a reflow soldering process includes:

[0085] In an acidic gas environment, through a reflow soldering process, the multiple first memory chips and the buffer chips that have been stacked are reflow soldered.

[0086] Specifically, as Figure 10 shown, the multiple first memory chips 120 and the buffer chips 110 that have completed stacking are fed into an acidic reflow furnace for reflow. In an acidic gas environment, without melting, the oxides of the second conductive bumps 125 can be completely removed, that is, the oxides of the tin bumps are removed. Since the second conductive bumps 125 and the first pads 127 have been soldered, during the reflow in the acidic reflow furnace, the second conductive bumps 125, that is, the tin bumps, have relatively small deformation and will not become shorter. During the entire reflow process, under the action of the upper and lower surface tensions, the second conductive bumps 125 can basically maintain their columnar shape unchanged, which can reduce the pitch of the tin bumps and achieve a connection with a center pitch of less than 20 μm.

[0087] It should be noted that the acidic gas can be carbon dioxide, chlorine, hydrogen sulfide, hydrogen chloride, sulfur dioxide, etc., which is not specifically limited in this embodiment.

[0088] S160. A molding layer is formed, and the molding layer wraps the multiple first memory chips and the buffer chips.

[0089] As Figure 11 shown, the multiple first memory chips 120 and the buffer chips 110 that have completed reflow soldering are molded with a molding compound to form a molding layer 140, obtaining a packaged body of the memory chips. The packaged body is cut to form a high-bandwidth memory package. Among them, the molding method can be film layer vacuum lamination or traditional molding process, which is not specifically limited in this embodiment. After molding, cutting is performed to form the final independent multi-layer stacked high-bandwidth memory package structure.

[0090] Exemplarily, when forming the encapsulation layer 140, encapsulant is filled between multiple first memory chips 120 and between the first memory chip 120 and the buffer chip 110. The encapsulant wraps the first pad 127, the second pad 115, the first conductive bump 124, and the second conductive bump 125. By using encapsulant to replace the existing non-conductive adhesive and filling it between the buffer and the first memory chip, and between adjacent first memory chips above and below, short circuits between the pads and the second conductive bumps are prevented. Since the encapsulant is lower in price than the non-conductive adhesive, the production cost is saved.

[0091] The multi-layer stacked high-bandwidth memory encapsulation method of the present invention provides a buffer chip and multiple first memory chips, and both the buffer chip and the multiple first memory chips are provided with multiple conductive vias. Through the thermocompression bonding process, the second conductive bumps and the first pads of every two adjacent first memory chips are nested to stack the multiple first memory chips on the buffer chip in sequence in an insulated manner; through the reflow soldering process, the stacked multiple first memory chips and the buffer chip are reflow soldered; by the two-step soldering process of the present invention, the second conductive bumps and the pads are nested, which can reduce the deformation of the second conductive bumps, so that the pitch of the second conductive bumps can be reduced, realizing interconnection with a center pitch below 20um.

[0092] As Figure 11 shown, on the other hand, the present invention provides a multi-layer stacked high-bandwidth memory encapsulation structure 100. The encapsulation structure 100 includes a buffer chip 110, an encapsulation layer 140, and multiple first memory chips 120. Among them, both the buffer chip 110 and the multiple first memory chips 120 are provided with multiple conductive vias 130, and the multiple conductive vias 130 can be through-silicon vias.

[0093] As Figure 3 shown, at the position corresponding to the conductive via 130 on the first surface of the first memory chip 120, a first conductive bump 124 and a second conductive bump 125 are sequentially arranged. In this embodiment, the first conductive bump 124 can be a copper bump, and the second conductive bump 125 can be a tin bump. Further preferably, as Figure 3 shown, the second conductive bump 125 has a columnar structure, that is, the tin bump has a columnar structure, which can be a cylindrical structure or a prismatic structure. The original form of the second conductive bump 125 is a columnar structure, different from the spherical shape of the traditional conductive bump, so that the lateral width can be reduced under the same volume. At the position corresponding to the conductive via 130 on the second surface of the first memory chip 120, a first pad 127 is provided. In this embodiment, the first pad 127 is a copper pad, and the pad 127 has a cylindrical structure.

[0094] As Figure 11As shown, the second conductive bumps 125 and the first pads 127 of every two adjacent first memory chips 120 are nested and connected, so that a plurality of first memory chips 120 are insulated and stacked on the buffer chip 110.

[0095] It should be noted that the second conductive bumps 125 and the first pads 127 of every two adjacent first memory chips 120 are nested and connected through a thermocompression welding process, so that a plurality of first memory chips 120 are insulated and stacked on the buffer chip 110. The stacked plurality of first memory chips 120 and the buffer chip 110 are put into an acidic reflow furnace for reflow. In an acidic gas environment, without melting, the oxides of the second conductive bumps 125 can be completely removed, that is, the oxides of the tin bumps are removed. Since the second conductive bumps 125 and the first pads 127 are already welded, during reflow, the deformation of the second conductive bumps 125, that is, the tin bumps, is relatively small and the situation of shortening will not occur. During the entire reflow process, under the action of the upper and lower surface tensions, the tin bumps can basically maintain their morphological invariance, so that the pitch of the tin bumps can be reduced to achieve a connection with a center pitch of less than 20um.

[0096] As Figure 11 shown, the encapsulation layer 140 wraps a plurality of first memory chips 120 and the buffer chip 110. Among them, the encapsulation method can be film layer vacuum lamination or traditional encapsulation process, which is not specifically limited in this embodiment. After encapsulation, cutting is performed to form the final independent multi-layer stacked high-bandwidth memory encapsulation structure.

[0097] Exemplarily, as Figure 3 shown, a protrusion 127a is provided on the side of the first pad 127 facing the second conductive bump 125, and a groove 125a is provided on the side of the second conductive bump 125 facing the first pad 127, and the protrusion 127a is inserted into the groove 125a. As Figure 4 shown, the size of the protrusion 127a is generally 3um - 5um, and the protrusion height is below 5um. In this embodiment, the protrusion 127a is in the shape of a quadrangular prism, that is, the cross-section is a square.

[0098] The multi-layer stacked high-bandwidth memory encapsulation structure provided by the present invention is fabricated by using the encapsulation method described above. The encapsulation structure of the present invention reduces the deformation of the second conductive bumps and narrows the pitch of the second conductive bumps through the nested connection of the second conductive bumps and the first pads of every two adjacent first memory chips, and the nested connection of the second pads of the buffer chip and the second conductive bumps on the first memory chips. The nested connection between the pads and the second conductive bumps can achieve an interconnection with a center pitch below 20um.

[0099] It is understandable that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present invention. However, the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A method for packaging a multi-layer stacked high-bandwidth memory, characterized in that, The method includes: providing a buffer chip and a plurality of first memory chips, wherein the buffer chip and the plurality of first memory chips are each provided with a plurality of conductive vias; forming a first conductive bump and a second conductive bump in sequence at positions corresponding to the conductive vias on the surface of the first memory chip facing the buffer chip, wherein the second conductive bump has a columnar structure; forming a first pad at a position corresponding to the conductive via on the surface of the first memory chip facing away from the buffer chip; by means of a thermocompression bonding process, nesting the second conductive bumps and the first pads of every two adjacent first memory chips to reduce deformation of the second conductive bumps, realizing ultra-fine pitch interconnection, and then insulating and stacking the plurality of first memory chips on the buffer chip in sequence; wherein the specific process of nesting the second conductive bump and the first pad includes: forming a protrusion on the first pad; by means of a thermocompression bonding process, pressing the protrusions of every two adjacent first memory chips into the second conductive bumps; wherein the melting point of the first conductive bump is greater than the melting point of the second conductive bump, and the temperature of the thermocompression bonding process is less than the melting point of the second conductive bump; in an acidic gas environment, performing reflow soldering on the stacked plurality of first memory chips and the buffer chip through a reflow soldering process; forming a molding layer that wraps the plurality of first memory chips and the buffer chip.

2. The method according to claim 1, characterized in that, The forming of the first conductive bump and the second conductive bump in sequence at positions corresponding to the conductive vias on the surface of the first memory chip facing the buffer chip includes: forming a first passivation layer and a first dielectric layer in sequence on the surface of the first memory chip facing the buffer chip; forming a photoresist layer on the first dielectric layer, patterning the photoresist layer to form a plurality of first openings, and the plurality of first openings respectively correspond to the plurality of conductive vias; forming the first conductive bump and the second conductive bump in sequence at the plurality of first openings; removing the photoresist layer.

3. The method according to claim 2, characterized in that, The surface of the second conductive bump protrudes from the surface of the photoresist layer; before removing the photoresist layer, the method further includes: grinding the second conductive bump so that the surface of the second conductive bump is flush with the surface of the photoresist layer.

4. The method according to any one of claims 1 to 3, characterized in that, The forming of the first pad at a position corresponding to the conductive via on the surface of the first memory chip facing away from the buffer chip includes: forming a second passivation layer on the surface of the first memory chip facing away from the buffer chip, patterning the second passivation layer to form a plurality of second openings, and the plurality of second openings correspond to the plurality of conductive vias; forming the first pad at the plurality of second openings.

5. The method according to any one of claims 1 to 3, characterized in that, The surface of the buffer chip facing away from the first memory chip is provided with a third passivation layer and a second dielectric layer, and a plurality of conductive protrusions are provided on the second dielectric layer, and the plurality of conductive protrusions correspond to and are electrically connected to the plurality of conductive vias; A fourth passivation layer and a second pad are disposed on a surface of the buffer chip facing the first memory chip, wherein the second pad is nested with the second conductive bump on the first memory chip close to the buffer chip.

6. The method according to claim 5, characterized in that, Forming the encapsulation layer, the encapsulation layer wrapping the plurality of first memory chips and the buffer chip, the method further comprising: Filling encapsulation materials between the plurality of first memory chips and between the first memory chip and the buffer chip, the encapsulation materials wrapping the first pad, the second pad, the first conductive bump, and the second conductive bump.

7. A multi-layer stacked high-bandwidth memory packaging structure, characterized in that, Manufactured and formed by using the packaging method according to any one of claims 1 to 6.

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