Semiconductor memory device

Abstract

Embodiments provide a semiconductor storage device capable of improving heat retention of a semiconductor storage element. The semiconductor storage device of the present embodiment includes a first wiring extending in a first direction; a second wiring extending in a second direction intersecting the first direction; a first semiconductor element extending in a third direction intersecting the first direction and the second direction, connected to the first wiring and the second wiring, and having a first selector layer and a first resistance change layer; a first insulator extending in the second direction and the third direction, adjacent to the first semiconductor element in the first direction; and a second insulator extending in the second direction and the third direction, and including an air gap arranged between the first semiconductor element and the first insulator.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2020-146832 (filed on September 1, 2020). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of this disclosure relate to semiconductor memory devices. Background Technology

[0004] A semiconductor memory device is proposed that integrates resistance-changing semiconductor memory elements such as ReRAM (Resistive Random Access Memory), Alloy PCM (Phase Change Memory), iPCM (Interfacial Phase Change Memory), and CBRAM (Conduction Bridge RAM) on a semiconductor substrate. These resistance-changing semiconductor memory elements function as non-volatile memory elements that store information by using a phase change film and changing the resistance value of the phase change film through heating. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor storage device that can improve the thermal insulation of semiconductor storage elements.

[0006] The semiconductor memory device of this embodiment includes: a first wiring extending along a first direction; a second wiring extending along a second direction intersecting the first direction; a first semiconductor element extending along a third direction intersecting the first and second directions, connected to the first wiring and the second wiring, and having a first selector layer and a first resistance variation layer; a first insulator extending along the second and third directions and adjacent to the first semiconductor element in the first direction; and a second insulator extending along the second and third directions and including an air gap disposed between the first semiconductor element and the first insulator. Attached Figure Description

[0007] Figure 1 This is a block diagram of a semiconductor memory device according to one embodiment.

[0008] Figure 2 This is a circuit diagram illustrating the configuration of a memory cell array in a semiconductor memory device according to one embodiment.

[0009] Figure 3is a perspective view showing the configuration of a memory cell array of an embodiment.

[0010] Figure 4A is a plan view showing the configuration of a memory cell of a semiconductor storage device of an embodiment.

[0011] Figure 4B is a sectional view showing the configuration of a memory cell of a semiconductor storage device of an embodiment.

[0012] Figure 4C is a sectional view showing the configuration of a memory cell of a semiconductor storage device of an embodiment.

[0013] Figure 5 is a sectional view showing a manufacturing method of a memory cell of a semiconductor storage device of an embodiment.

[0014] Figure 6 is a sectional view showing a manufacturing method of a memory cell of a semiconductor storage device of an embodiment.

[0015] Figure 7 is a sectional view showing a manufacturing method of a memory cell of a semiconductor storage device of an embodiment.

[0016] Figure 8 is a sectional view showing a manufacturing method of a memory cell of a semiconductor storage device of an embodiment.

[0017] Figure 9 is a sectional view showing a manufacturing method of a memory cell of a semiconductor storage device of an embodiment.

[0018] Figure 10 is a sectional view showing a manufacturing method of a memory cell of a semiconductor storage device of an embodiment.

[0019] Figure 11 is a sectional view showing a manufacturing method of a memory cell of a semiconductor storage device of an embodiment.

[0020] Figure 12 is a sectional view showing a manufacturing method of a memory cell of a semiconductor storage device of an embodiment.

[0021] Figure 13 is a sectional view showing a manufacturing method of a memory cell of a semiconductor storage device of an embodiment.

[0022] Figure 14 is a sectional view showing a manufacturing method of a memory cell of a semiconductor storage device of an embodiment.

[0023] Figure 15is a cross-sectional view showing a manufacturing method of a memory cell of a semiconductor storage device according to an embodiment.

[0024] Figure 16 is a cross-sectional view showing a manufacturing method of a memory cell of a semiconductor storage device according to an embodiment.

[0025] Figure 17 is a cross-sectional view showing a manufacturing method of a memory cell of a semiconductor storage device according to an embodiment.

[0026] Figure 18 is a cross-sectional view showing a manufacturing method of a memory cell of a semiconductor storage device according to an embodiment.

[0027] Figure 19A is a cross-sectional view showing a configuration of a memory cell of a semiconductor storage device according to an embodiment.

[0028] Figure 19B is a cross-sectional view showing a configuration of a memory cell of a semiconductor storage device according to an embodiment.

[0029] Figure 20A is a cross-sectional view showing a configuration of a memory cell of a semiconductor storage device according to an embodiment.

[0030] Figure 20B is a cross-sectional view showing a configuration of a memory cell of a semiconductor storage device according to an embodiment.

[0031] Figure 21A is a cross-sectional view showing a configuration of a memory cell of a semiconductor storage device according to an embodiment.

[0032] Figure 21B is a cross-sectional view showing a configuration of a memory cell of a semiconductor storage device according to an embodiment.

[0033] Figure 22A is a cross-sectional view showing a configuration of a memory cell of a semiconductor storage device according to a modification.

[0034] Figure 22B is a cross-sectional view showing a configuration of a memory cell of a semiconductor storage device according to a modification.

[0035] Figure 22C is an enlarged cross-sectional view showing a configuration of a memory cell of a semiconductor storage device according to a modification.

[0036] Figure 23A is a plan view showing a configuration of a memory cell of a semiconductor storage device according to a modification.

[0037] Figure 23B is a plan view showing a configuration of a memory cell of a semiconductor storage device according to a modification.

[0038] Reference Signs

[0039] 1 semiconductor storage device, 110 lower electrode layer, 120 selector layer, 130 intermediate electrode layer, 140 barrier metal layer, 150 resistance change layer, 160 barrier metal layer, 170 upper electrode layer, 210 third insulating layer, 220 fourth insulator, 230 fourth insulating layer, 240 second sacrificial layer, 250 third insulator, 260 partition, 310 first insulating layer, 320 second insulator, 330 second insulating layer, 340 first sacrificial layer, 350 first insulator. DETAILED DESCRIPTION

[0040] Hereinafter, the semiconductor storage device of the present embodiment will be specifically described with reference to the drawings. In addition, in the following description, the same reference signs are attached to the constituent elements having substantially the same functions and configurations, and repeated description will be made only in necessary cases. Further, the embodiment shown below exemplifies a device, a method for embodying the technical idea, and the technical idea of the embodiment is not specified to the material, the shape, the configuration, the arrangement, and the like of the constituent members described below. The technical idea of the embodiment can be applied to various modifications in the claims.

[0041] The drawings are schematically shown in the width, the thickness, the shape, and the like of each part in order to make the description more clear, but are only one example, and do not limit the explanation of the present application. In the present specification and each drawing, the same reference signs are attached to the elements having the same functions as those explained in the aforementioned drawings, and repeated description is omitted.

[0042] The plurality of films formed by the same process have the same layer configuration, and are composed of the same material. In the present specification, even in the case where the plurality of films respectively exert different functions or effects, the plurality of films formed by the same process as described above are respectively treated as films present in the same layer.

[0043] [First Embodiment]

[0044] [Configuration of Semiconductor Storage Device]

[0045] The configuration of the semiconductor storage device of the present embodiment will be described. In the drawings referred to below, the X direction corresponds to the extension direction of the word line, the Y direction corresponds to the extension direction of the bit line, and the Z direction corresponds to the vertical direction perpendicular to the surface of the semiconductor substrate. In addition, in each drawing below, the constituent elements such as the insulator layer (interlayer insulating film), the wiring, the contact, and the like are appropriately omitted in order to easily observe each drawing.

[0046] Figure 1is a block diagram of a semiconductor storage device of the present embodiment. The semiconductor storage device 1 of the present embodiment is provided with a memory cell array 11, a row decoder 12 and a column decoder 13 that select a desired memory cell MC from the memory cell array 11, an upper block decoder 14 that imparts a row address and a column address to these decoders 12, 13, a power supply 15 that supplies power to each part of the semiconductor storage device 1, and a control circuit 16 that controls them.

[0047] The memory cell array 11 is provided with a plurality of memory cells MC that each store one bit or a plurality of bits of data. The memory cell array 11 is configured so that, by applying a prescribed voltage to a desired bit line BL and a word line WL selected by the row decoder 12 and the column decoder 13, a desired memory cell MC can be accessed (data erased / written / read out).

[0048] Figure 2 is an equivalent circuit diagram showing the configuration of a portion of the memory cell array 11. The memory cell array 11 is provided with a plurality of bit lines BL, a plurality of word lines WL1, WL2, and a plurality of memory cells MC1, MC2 connected to these bit lines BL and word lines WL1, WL2. These memory cells MC1, MC2 are connected to the row decoder 12 via the word lines WL1, WL2, and to the column decoder 13 via the bit lines BL. The memory cells MC1, MC2 each store, for example, one bit of data. Further, a plurality of memory cells MC1, MC2 connected to a common word line WL1, WL2 store, for example, one page of data.

[0049] The memory cells MC1, MC2 are configured in series with the selector SEL through a phase change film PCM. The phase change film PCM can take two states of a crystalline state of low resistance and an amorphous state of high resistance according to a current pattern (heating pattern), and thus functions as a variable resistance element. By making the two states of resistance values correspond to information of "0" and "1", the phase change film PCM can function as a memory cell. Further, the selector SEL of the memory cell MC1, MC2 functions as a rectifying element. Therefore, hardly any current flows in the word lines WL1, WL2 other than the selected word line WL1, WL2.

[0050] In addition, hereinafter, the configuration including a plurality of bit lines BL, a plurality of word lines WL1, and a plurality of memory cells MC1 corresponding to the first layer of the memory cell array 11 will be referred to as a memory mat MM0. Similarly, the configuration including a plurality of bit lines BL, a plurality of word lines WL2, and a plurality of memory cells MC2 corresponding to the second layer of the memory cell array 11 will be referred to as a memory mat MM1.

[0051] Figure 3 This is a schematic perspective view showing the configuration of a portion of the memory cell array 11. In this example, the memory cell array 11 is a so-called cross-point type memory cell array. That is, above the semiconductor substrate SB, there are multiple word lines WL1 arranged at predetermined intervals in the Y direction parallel to the upper surface of the semiconductor substrate SB and extending parallel to the X direction parallel to the upper surface of the semiconductor substrate SB and intersecting the Y direction. Furthermore, above the multiple word lines WL1, there are multiple bit lines BL arranged at predetermined intervals in the X direction and extending parallel to the Y direction. Also, above the multiple bit lines BL, there are multiple word lines WL2 arranged at predetermined intervals in the Y direction and extending parallel to the X direction. Furthermore, memory cells MC1 are respectively provided at the intersections of the multiple word lines WL1 and the multiple bit lines BL. Similarly, memory cells MC2 are respectively provided at the intersections of the multiple bit lines BL and the multiple word lines WL2. In this embodiment, the memory cells MC1 and MC2 are prismatic, but they can also be cylindrical.

[0052] [Structure of a Semiconductor Component]

[0053] Figures 4A-4C This diagram illustrates the configuration of the memory cell (semiconductor element) MC1 in the semiconductor memory device 1 of this embodiment. Figure 4A An example top view of memory cell MC1 in the XY plane is shown. Figure 4B It shows along Figure 4A An example of a cross-sectional view of memory cell MC1 in the YZ plane along line A-A'. Figure 4C It shows along Figure 4A An example of a cross-sectional view of memory cell MC1 in the XZ plane along line B-B'. Figures 4A-4C In the diagram, a memory cell MC1 is shown, but it is connected in the XY direction to a memory cell MC1 of the same configuration to form a memory cluster MM0. Similarly, in the Z direction, it is connected in the Z direction to a memory cell MC2 of the same configuration to form a memory cluster MM1.

[0054] like Figures 4A-4CAs shown, the memory cell MC1 includes a word line (first wiring) WL1 extending in the X direction (first direction) disposed on the semiconductor substrate SB side, a bit line (second wiring) BL extending in the Y direction (second direction) disposed on the side opposite the semiconductor substrate SB, a memory cell (semiconductor element) MC1 disposed between the word line WL1 and the bit line BL, an insulator disposed between the memory cell MC1 and the bit line BL, a heat insulating layer disposed between the insulator and the memory cell MC1, and an insulating layer disposed so as to surround the heat insulating layer.

[0055] The memory cell MC1 includes a lower electrode layer 110, a selector layer 120, an intermediate electrode layer 130, a barrier metal layer 140, a resistance change layer 150 (phase change film PCM), a barrier metal layer 160, and an upper electrode layer 170, which are sequentially stacked in a Z direction (third direction) intersecting the X direction and the Y direction from the word line WL1 side toward the bit line BL side. The word line WL1, the bit line BL, the lower electrode layer 110, the intermediate electrode layer 130, and the upper electrode layer 170 can be composed of, for example, a conductive material such as tungsten (W), titanium (Ti), or polysilicon. The barrier metal layers 140 and 160 can be composed of, for example, a conductive material such as titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The selector layer 120 can be composed of, for example, a non-ohmic element such as a pin diode composed of a p-type semiconductor layer, an intrinsic semiconductor layer, and an n-type semiconductor layer. The resistance change layer 150 can be composed of, for example, a chalcogenide material such as a Ge-Sb-Te-based (GST-based) material containing germanium (Ge), antimony (Sb), and tellurium (Te). The distance between adjacent memory cells MC1 can be, for example, about 14 nm in the X or Y direction.

[0056] An insulator is disposed between the adjacent memory cells MC1. The insulator includes a first insulator 350 adjacent to the memory cell MC1 in the X direction, and a third insulator 250 adjacent to the memory cell MC1 in the Y direction. The first insulator 350 extends in the Y direction, and is adjacent to the plurality of memory cells MC1 arranged in the Y direction in the X direction. The first insulator 350 extends in the Z direction from the same position as the lower electrode layer 110 to the same position as the bit line BL. The third insulator 250 is adjacent to each of the memory cells MC1 in the Y direction with substantially the same width as the memory cell MC1 in the X direction. The third insulator 250 extends in the Z direction from the same position as the word line WL1 to the same position as the upper electrode layer 170. Here, the first insulator 350 and the third insulator 250 are referred to as an insulator without distinction. The insulator can be composed of, for example, an insulator such as a silicon oxide film to which carbon is added (SiOC film). The thickness of the first insulator 350 in the X direction and the thickness of the third insulator 250 in the Y direction can be, for example, about 6 nm.

[0057] A heat insulating layer is disposed between the memory cell MC1 and the insulator. The heat insulating layer includes a second insulator 320 disposed between the memory cell MC1 and the first insulator 350, and a fourth insulator 220 disposed between the memory cell MC1 and the third insulator 250. The second insulator 320 extends in the Y direction, and is adjacent to the plurality of memory cells MC1 arranged in the Y direction in the X direction. The second insulator 320 extends in the Z direction from the same position as the lower electrode layer 110 to the same position as the bit line BL. The fourth insulator 220 is adjacent to each of the memory cells MC1 in the Y direction with substantially the same width as the memory cell MC1 in the X direction. The fourth insulator 220 extends in the Z direction from the same position as the word line WL to the same position as the upper electrode layer 170.

[0058] That is, the second insulator 320 and the fourth insulator 220 are disposed in a manner of surrounding the side surface of the memory cell MC1. Here, the second insulator 320 and the fourth insulator 220 are referred to as a heat insulating layer without distinction. In the present embodiment, the second insulator 320 and the fourth insulator 220 are air gaps, in other words, air layers. The thickness of the second insulator 320 in the X direction and the thickness of the fourth insulator 220 in the Y direction can be, for example, about 2 nm.

[0059] The semiconductor storage device 1 of the present embodiment can improve the heat resistance of the memory cell MC1, and can improve the heat retention property by disposing the heat insulating layer as an air layer in a manner of surrounding the side surface of the memory cell MC1. Further, the semiconductor storage device 1 can improve the withstand voltage of the memory cell MC1 by disposing the heat insulating layer as an air layer in a manner of surrounding the side surface of the memory cell MC1.

[0060] The insulating layer is arranged so as to surround the thermal insulation layer. The insulating layer includes a first insulating layer 310, a second insulating layer 330, a third insulating layer 210, and a fourth insulating layer 230. The first insulating layer 310 is arranged between the memory cell MC1 and the second insulator 320. The second insulating layer 330 is arranged between the first insulator 350 and the second insulator 320. The first insulating layer 310 extends in the Y direction and is arranged in contact with the second insulator 320. The first insulating layer 310 is arranged in contact with the plurality of memory cells MC1, the fourth insulator 220, and the third insulator 250 arranged in the Y direction on the side opposite the second insulator 320. The first insulating layer 310 is also arranged in contact with the third insulating layer 210 and the fourth insulating layer 230 described later on the side opposite the second insulator 320. The second insulating layer 330 extends in the Y direction and is arranged in contact with the second insulator 320. The second insulating layer 330 is arranged in contact with the first insulator 350 on the side opposite the second insulator 320. The first insulating layer 310 and the second insulating layer 330 extend in the Z direction from the same position as the lower electrode layer 110 to the same position as the bit line BL. The first insulating layer 310 is arranged in contact with the upper surface of the word line WL1 in a region in which the memory cell MC1 is not arranged. The second insulating layer 330 is arranged in contact with the first insulating layer 310 in a region in which the memory cell MC1 is not arranged on the word line WL1. That is, the bottom surface and the side surface of the second insulator 320 are surrounded by the first insulating layer 310 and the second insulating layer 330. The bottom surface and the side surface of the first insulator 350 are surrounded by the second insulating layer 330. The first insulating layer 310 and the second insulating layer 330 may, for example, be composed of silicon nitride (SiN) or silicon oxide (SiO). It is preferable that the first insulating layer 310 and the second insulating layer 330 be composed of the same material. The thickness of the first insulating layer 310 and the second insulating layer 330 in the X direction may, for example, be about 1 nm.

[0061] The third insulating layer 210 is provided between the memory cell MC1 and the fourth insulator 220. The fourth insulating layer 230 is provided between the third insulator 250 and the fourth insulator 220. The third insulating layer 210 is provided so as to be in contact with the memory cell MC1 and the fourth insulator 220 with substantially the same width as the memory cell MC1 in the X direction. The fourth insulating layer 230 is provided so as to be in contact with the third insulator 250 and the fourth insulator 220 with substantially the same width as the memory cell MC1 in the X direction. The third insulating layer 210 and the fourth insulating layer 230 are connected to the first insulating layer 310. The third insulating layer 210 and the fourth insulating layer 230 extend in the Z direction from the same position as the word line WL to the same position as the upper electrode layer 170. The third insulating layer 210 is provided so as to be in contact with the upper surface of the semiconductor substrate SB in a region where the memory cell MC1 is not provided. The fourth insulating layer 230 is provided so as to be in contact with the third insulating layer 210 in a region where the memory cell MC1 is not provided on the semiconductor substrate SB. That is, the side surface of the memory cell MC1 is surrounded by the first insulating layer 310 and the third insulating layer 210. The bottom surface and the side surface of the third insulator 250 are surrounded by the first insulating layer 310 and the fourth insulating layer 230. The bottom surface and the side surface of the fourth insulator 220 are surrounded by the first insulating layer 310, the third insulating layer 210, and the fourth insulating layer 230. The third insulating layer 210 and the fourth insulating layer 230 can be composed of, for example, silicon nitride (SiN) or silicon oxide (SiO). It is preferable that the third insulating layer 210 and the fourth insulating layer 230 be composed of the same material. It is preferable that the third insulating layer 210 and the fourth insulating layer 230 be composed of the same material as the first insulating layer 310 and the second insulating layer 330. The thickness of the third insulating layer 210 and the fourth insulating layer 230 in the Y direction can be, for example, about 1 nm.

[0062] In the semiconductor storage device 1 of the present embodiment, the resistance change layer 150 becomes an amorphous state (high resistance, reset state) due to heating above the melting temperature and rapid cooling. Further, the resistance change layer 150 becomes a crystallized state (low resistance, set state) by being heated to a temperature lower than the melting temperature and higher than the crystallization temperature and slowly cooled. Thus, since the resistance change layer 150 repeatedly performs reset / set operations by melting / solidification based on heating / cooling, temperature control greatly affects the performance and reliability of the semiconductor storage device. The semiconductor storage device 1 of the present embodiment can improve the heat retention property of the memory cell MC1 by providing the heat insulating layer which is sandwiched by the insulating layers adjacent to the side surface of the memory cell MC1. By improving the heat retention property of the memory cell MC1, the reset current can be reduced, and power consumption can be suppressed. Further, by improving the heat retention property of the memory cell MC1, heat conduction to the adjacent memory cell MC1 can be suppressed, and erroneous operation can be suppressed.

[0063] [Manufacturing method of semiconductor storage device]

[0064] Next, a manufacturing method of a semiconductor storage device according to the present embodiment will be described. Figures 5-18 A manufacturing method of a semiconductor storage device according to the present embodiment will be described. Figure 5 is a cross-sectional view of a YZ plane indicating a step of forming a layered structure in the manufacturing method of a semiconductor storage device according to the present embodiment. As shown in Figure 5 above the semiconductor substrate SB, a layered structure including a word line WL1, a lower electrode layer 110, a selector layer 120, an intermediate electrode layer 130, a barrier metal layer 140, a resistance change layer 150, a barrier metal layer 160, and an upper electrode layer 170 is formed. Each layer is formed in order, for example, by a method such as ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), or the like. Further, above the upper electrode layer 170, a hard mask HM1 is formed by lithography.

[0065] Figure 6 is a cross-sectional view of a YZ plane indicating a step of dividing (first cutting) the layered structure in the manufacturing method of a semiconductor storage device according to the present embodiment. As shown in Figure 6 for example, by anisotropic etching such as RIE (Reactive Ion Etching), a part of the layered structure is removed in the Z direction from the upper electrode layer 170 to the word line WL1. The layered structure is selectively etched by using the linear hard mask HM1 extending in the X direction, and thus is divided in the Y direction. In the region where the layered structure is removed, a part of the semiconductor substrate SB is exposed.

[0066] Figure 7 is a cross-sectional view of a YZ plane indicating a step of forming an insulating layer and a heat insulating layer in the manufacturing method of a semiconductor storage device according to the present embodiment. As shown in Figure 7As shown, first, the third insulating layer 210 is formed in a manner of covering the stacked structure and the semiconductor substrate SB. Next, the second sacrificial layer 240 is formed in a manner of being in contact with the third insulating layer 210. Then, the second sacrificial layer 240 is removed by anisotropic etching such as RIE or the like, above the stacked structure and above the semiconductor substrate SB, to expose the upper surface of the third insulating layer 210. Next, the fourth insulating layer 230 is formed in a manner of being in contact with the second sacrificial layer 240 and the third insulating layer 210. By the above, the second sacrificial layer 240 is enclosed by the third insulating layer 210 and the fourth insulating layer 230, and is disposed at the side surface of the stacked structure. Here, the second sacrificial layer 240, the third insulating layer 210, and the fourth insulating layer 230 can be formed by CVD or the like, for example. The third insulating layer 210 and the fourth insulating layer 230 can be silicon nitride (SiN) films, and the second sacrificial layer 240 can be an amorphous silicon film. Alternatively, the third insulating layer 210 and the fourth insulating layer 230 can be silicon oxide (SiO) films, and the second sacrificial layer 240 can be a silicon nitride (SiN) film. The third insulating layer 210 and the fourth insulating layer 230 can be any combination of materials as long as a selectivity ratio with the second sacrificial layer 240 can be obtained in the etching process of the second sacrificial layer 240 described later. Further, the third insulator 250 is formed in a manner of burying the stacked structure after being divided by etching, respectively.

[0067] Figure 8 FIG. 18 is a cross-sectional view of a YZ plane showing a step of removing the third insulator 250, the third insulating layer 210, and the fourth insulating layer 230 on the stacked structure in the manufacturing method of the semiconductor storage device of the present embodiment. As shown, the third insulator 250, the third insulating layer 210, and the fourth insulating layer 230 are removed by CMP (Chemical Mechanical Polishing) or the like in a manner of being exposed by the hard mask HM1 on the stacked structure. Thereby, the upper surfaces of the third insulating layer 210, the second sacrificial layer 240, and the fourth insulating layer 230, which surround the side surface of the stacked structure, are exposed. Figure 8

[0068] Figure 9 FIG. 19 is a cross-sectional view of a YZ plane showing a step of further forming the third insulator 250 in the manufacturing method of the semiconductor storage device of the present embodiment. As shown, the third insulator 250 is further formed on the stacked structure. Figure 9

[0069] Figure 10 FIG. 20 is a cross-sectional view of a YZ plane showing a step of removing the third insulator 250 and the hard mask HM1 on the stacked structure in the manufacturing method of the semiconductor storage device of the present embodiment. As shown, the third insulator 250 and the hard mask HM1 are removed by CMP (Chemical Mechanical Polishing) or the like. Figure 10 ​​The third insulator 250 and the hard mask HM1 are removed by CMP (Chemical Mechanical Polishing) or the like, as shown in a manner that the upper electrode layer 170 on the stacked structure is exposed. Thereby, the upper surface of the third insulating layer 210, the second sacrificial layer 240, and the fourth insulating layer 230, which surround the side surface of the stacked structure, are exposed.

[0070] Figure 11 is a cross-sectional view of the YZ plane that shows a step of removing the second sacrificial layer 240 in the manufacturing method of the semiconductor storage device of the present embodiment. As shown in Figure 11 , the second sacrificial layer 240 is removed by wet etching. As for the etching removal of the second sacrificial layer 240, for example, in a case where the third insulating layer 210 and the fourth insulating layer 230 are silicon nitride (SiN) films and the second sacrificial layer 240 is amorphous silicon film, it is preferable to use wet etching based on trimethyl 2-hydroxyethyl ammonium hydroxide (TMY). Further, in a case where the third insulating layer 210 and the fourth insulating layer 230 are silicon oxide (SiO) films and the second sacrificial layer 240 is silicon nitride (SiN) film, it is preferable to use wet etching based on phosphoric acid. By selectively removing the second sacrificial layer 240 as described above, the fourth insulator 220 composed of an air layer surrounded by the third insulating layer 210 and the fourth insulating layer 230 can be formed.

[0071] Figure 12 is a cross-sectional view of the YZ plane that shows a step of forming the bit line BL in the manufacturing method of the semiconductor storage device of the present embodiment. As shown in Figure 12 , the bit line BL is formed on the stacked structure in which the upper electrode layer 170 is exposed. Figure 13 shows a cross-sectional view in the XZ plane along the C-C' line shown in Figure 12 .

[0072] Figure 14 is a cross-sectional view of the XZ plane that shows a step of forming the hard mask HM2 in the manufacturing method of the semiconductor storage device of the present embodiment. As shown in Figure 14 , the hard mask HM2 is formed on the bit line BL by photolithography.

[0073] Figure 15 is a cross-sectional view of the XZ plane that shows a step of dividing (second time cutting) the stacked structure in the manufacturing method of the semiconductor storage device of the present embodiment. As shown in Figure 15As shown, for example, by anisotropic etching such as RIE (Reactive Ion Etching), a part of the stacked structure is removed in the Z direction from the bit line BL to the lower electrode layer 110. The stacked structure is selectively etched by using a linear hard mask HM2 extending in the Y direction, and is thereby divided in the X direction. In the region where the stacked structure is removed, a part of the word line WL1 is exposed.

[0074] Figure 16 is a cross-sectional view of an XZ plane showing a step of forming an insulating layer and a thermal insulation layer in the manufacturing method of the semiconductor storage device of the present embodiment. As shown, Figure 16 first, a first insulating layer 310 is formed so as to cover the stacked structure and the word line WL. Next, a first sacrificial layer 340 is formed so as to be in contact with the first insulating layer 310. Then, for example, by anisotropic etching such as RIE, the first sacrificial layer 340 above the stacked structure and above the word line WL is removed to expose the upper surface of the first insulating layer 310. Next, a second insulating layer 330 is formed so as to be in contact with the first sacrificial layer 340 and the first insulating layer 310. By the above formation, the first sacrificial layer 340 is enclosed by the first insulating layer 310 and the second insulating layer 330, and is disposed at the side surface of the stacked structure. Here, the first sacrificial layer 340, the first insulating layer 310, and the second insulating layer 330 can be formed, for example, by CVD or the like. The first insulating layer 310 and the second insulating layer 330 can be silicon nitride (SiN) films, and the first sacrificial layer 340 can be an amorphous silicon film. Further, the first insulating layer 310 and the second insulating layer 330 can be silicon oxide (SiO) films, and the first sacrificial layer 340 can be a silicon nitride (SiN) film. The first insulating layer 310 and the second insulating layer 330 are preferably made of the same material as the third insulating layer 210 and the fourth insulating layer 230. The first sacrificial layer 340 is preferably made of the same material as the second sacrificial layer 240. Further, a first insulator 350 is formed so as to bury the stacked structure divided by etching, respectively.

[0075] Figure 17 is a cross-sectional view of an XZ plane showing a step of removing the first insulator 350, the first insulating layer 310, the second insulating layer 330, and the hard mask HM2 from the stacked structure in the manufacturing method of the semiconductor storage device of the present embodiment. As shown, Figure 17 The first insulator 350, the first insulating layer 310, the second insulating layer 330, and the hard mask HM2 are removed by CMP (Chemical Mechanical Polishing) or the like to expose the bit line BL on the stacked structure. Thereby, the upper surfaces of the first insulating layer 310, the first sacrificial layer 340, and the second insulating layer 330 that surround the side surface of the stacked structure are exposed.

[0076] Figure 18 This is a cross-sectional view of the XZ plane showing the process of removing the first sacrificial layer 340 in the manufacturing method of the semiconductor memory device according to this embodiment. Figure 18 As shown, the first sacrificial layer 340 is removed by wet etching. Regarding the etching removal of the first sacrificial layer 340, for example, when the first insulating layer 310 and the second insulating layer 330 are silicon nitride (SiN) films and the first sacrificial layer 340 is an amorphous silicon film, wet etching based on trimethyl-2-hydroxyethylammonium hydroxide (TMY) is preferred. Furthermore, when the first insulating layer 310 and the second insulating layer 330 are silicon oxide (SiO) films and the first sacrificial layer 340 is a silicon nitride (SiN) film, wet etching based on phosphoric acid is preferred. By selectively removing the first sacrificial layer 340 in this way, a second insulator 320 consisting of an air layer surrounded by the first insulating layer 310 and the second insulating layer 330 can be formed. Using the above method, it is possible to manufacture... Figures 4A-4C The semiconductor memory device 1 shown is configured as follows.

[0077] Although not illustrated, it is possible to form a stacked structure including a lower electrode layer 110, a selector layer 120, an intermediate electrode layer 130, a barrier metal layer 140, a resistance variation layer 150, a barrier metal layer 160, an upper electrode layer 170, and a word line WL2, to achieve the same effect as... Figures 5-18 The same method is used to form memory cells MC2 connected in the Z direction.

[0078] The semiconductor memory device 1 manufacturing method of this embodiment forms a heat insulation layer surrounded by an insulating layer in a manner that is in contact with the side of the memory cell MC1, thereby enabling the easy formation of a heat insulation layer close to the side of the memory cell MC1.

[0079] [Second Implementation]

[0080] use Figure 19A as well as Figure 19B The configuration of the semiconductor memory device according to the second embodiment of the present invention will be described. Figure 19A as well as Figure 19B This diagram illustrates the configuration of the memory cell (semiconductor element) MC1 in the semiconductor memory device 1 of this embodiment. Figure 19A An example of a cross-sectional view of memory cell MC1 in the YZ plane is shown. Figure 19B An example cross-sectional view of memory cell MC1 in the XZ plane is shown. Additionally, for the top view of memory cell MC1 in the XY plane, due to... Figure 4A The same is therefore omitted here. Figure 19A as well as Figure 19BIn the present embodiment, one memory cell MC1 is shown, but a memory cluster MM0 is formed by connecting memory cells MC1 of the same configuration in the XY direction. Also, in the Z direction, a memory cluster MM1 is formed by connecting memory cells MC2 of the same configuration by sharing a bit line BL.

[0081] The semiconductor storage device 1 of the present embodiment is the same as the semiconductor storage device 1 of the first embodiment except that the heat insulating layer is composed of an air layer and a sacrificial layer, and thus the description is omitted for the common parts.

[0082] As shown in FIG. 1, the memory cell MC1 includes a word line (first wiring) WL1 extending in the X direction (first direction) disposed on the semiconductor substrate SB side, a bit line (second wiring) BL extending in the Y direction (second direction) disposed on the side opposite to the semiconductor substrate SB opposite to the word line WL1, a memory cell (semiconductor element) MC1 disposed between the word line WL1 and the bit line BL, an insulator disposed between the side surfaces of the plurality of memory cells MC1, a heat insulating layer disposed between the insulator and the memory cell MC1, and an insulating layer disposed so as to surround the heat insulating layer. Figure 19A Figure 19B The heat insulating layer is disposed between the memory cell MC1 and the insulator. The heat insulating layer includes a first sacrificial layer 340 and a second insulator 320 disposed between the memory cell MC1 and the first insulator 350, and a second sacrificial layer 240 and a fourth insulator 220 disposed between the memory cell MC1 and the third insulator 250.

[0083] The first sacrificial layer 340 extends in the Y direction and is adjacent to the plurality of memory cells MC1 arranged in the Y direction in the X direction. The first sacrificial layer 340 extends in the Z direction from the same position as the lower electrode layer 110 to the same position as the selector layer 120. The second insulator 320 is disposed so as to be in contact with and overlap the first sacrificial layer 340 above the first sacrificial layer 340. The second insulator 320 also extends in the Y direction and is adjacent to the plurality of memory cells MC1 arranged in the Y direction in the X direction. The second insulator 320 extends in the Z direction from the same position as the intermediate electrode layer 130 to the same position as the bit line BL.

[0084] The first sacrificial layer 340 extends in the Y direction and is adjacent to the plurality of memory cells MC1 arranged in the Y direction in the X direction. The first sacrificial layer 340 extends in the Z direction from the same position as the lower electrode layer 110 to the same position as the selector layer 120. The second insulator 320 is disposed so as to be in contact with and overlap the first sacrificial layer 340 above the first sacrificial layer 340. The second insulator 320 also extends in the Y direction and is adjacent to the plurality of memory cells MC1 arranged in the Y direction in the X direction. The second insulator 320 extends in the Z direction from the same position as the intermediate electrode layer 130 to the same position as the bit line BL.

[0085] ​The second sacrificial layer 240 is arranged adjacent to each of the memory cells MC1 in the Y direction with substantially the same width as the memory cells MC1 in the X direction. The second sacrificial layer 240 extends in the Z direction from the same position as the word line WL to the same position as the selector layer 120. Above the second sacrificial layer 240, a fourth insulator 220 is arranged so as to contact and overlap the second sacrificial layer 240. The fourth insulator 220 is also arranged adjacent to each of the memory cells MC1 in the Y direction with substantially the same width as the memory cells MC1 in the X direction. The fourth insulator 220 extends in the Z direction from the same position as the intermediate electrode layer 130 to the same position as the upper electrode layer 170.

[0086] That is, the first sacrificial layer 340 and the second sacrificial layer 240 are arranged so as to surround the side surfaces from the lower electrode layer 110 to the selector layer 120 of the memory cell MC1. The second insulator 320 and the fourth insulator 220 are arranged so as to surround the side surfaces from the intermediate electrode layer 130 to the upper electrode layer 170 of the memory cell MC1. Here, the first sacrificial layer 340, the second sacrificial layer 240, the second insulator 320, and the fourth insulator 220 are collectively referred to as a heat insulating layer. In the present embodiment, the first sacrificial layer 340 and the second sacrificial layer 240 are amorphous silicon layers or silicon nitride layers, and the second insulator 320 and the fourth insulator 220 are air layers. The thickness of the first sacrificial layer 340 and the second insulator 320 in the X direction and the thickness of the second sacrificial layer 240 and the fourth insulator 220 in the Y direction can be, for example, about 2 nm.

[0087] The semiconductor storage device 1 of the present embodiment can improve the heat resistance of the memory cell MC1 and can improve the heat retention property by arranging the heat insulating layer so as to surround the side surfaces of the memory cell MC1. Further, the semiconductor storage device 1 can improve the withstand voltage of the memory cell MC1 by arranging the heat insulating layer so as to surround the side surfaces of the memory cell MC1. In particular, the semiconductor storage device 1 can effectively improve the heat retention property by arranging the heat insulating layer, which is an air layer, so as to surround the side surfaces of the intermediate electrode layer 130 to the upper electrode layer 170 of the memory cell MC1.

[0088] The insulating layer is arranged so as to surround the insulating layer. The insulating layer includes a first insulating layer 310, a second insulating layer 330, a third insulating layer 210, and a fourth insulating layer 230. The first insulating layer 310 is arranged between the memory cell MC1 and the first sacrificial layer 340 and the second insulator 320. The second insulating layer 330 is arranged between the first insulator 350 and the first sacrificial layer 340 and the second insulator 320. The first insulating layer 310 extends in the Y direction and is arranged in contact with the first sacrificial layer 340 and the second insulator 320. The first insulating layer 310 is arranged in contact with the plurality of memory cells MC1 arranged in the Y direction, the second sacrificial layer 240, the fourth insulator 220, and the third insulator 250 on the side opposite the first sacrificial layer 340 and the second insulator 320. The first insulating layer 310 is further arranged in contact with the third insulating layer 210 and the fourth insulating layer 230 described later on the side opposite the first sacrificial layer 340 and the second insulator 320. The second insulating layer 330 extends in the Y direction and is arranged in contact with the first sacrificial layer 340 and the second insulator 320. The second insulating layer 330 is arranged in contact with the first insulator 350 on the side opposite the first sacrificial layer 340 and the second insulator 320. The first insulating layer 310 and the second insulating layer 330 extend in the Z direction from the same position as the lower electrode layer 110 to the same position as the bit line BL. The first insulating layer 310 is arranged in contact with the upper surface of the word line WL1 in a region where the memory cell MC1 is not arranged. The second insulating layer 330 is arranged in contact with the first insulating layer 310 in a region where the memory cell MC1 is not arranged on the word line WL1. That is, the bottom surface of the first sacrificial layer 340 and the side surface of the first sacrificial layer 340 and the second insulator 320 are surrounded by the first insulating layer 310 and the second insulating layer 330. The bottom surface and the side surface of the first insulator 350 are surrounded by the second insulating layer 330.

[0089] The third insulating layer 210 is arranged between the memory cell MC1 and the second sacrificial layer 240 and the fourth insulator 220. The fourth insulating layer 230 is arranged between the third insulator 250 and the second sacrificial layer 240 and the fourth insulator 220. The third insulating layer 210 is arranged so as to be in contact with the memory cell MC1, the second sacrificial layer 240, and the fourth insulator 220 with substantially the same width as the memory cell MC1 in the X direction. The fourth insulating layer 230 is arranged so as to be in contact with the third insulator 250, the second sacrificial layer 240, and the fourth insulator 220 with substantially the same width as the memory cell MC1 in the X direction. The third insulating layer 210 and the fourth insulating layer 230 are connected to the first insulating layer 310. The third insulating layer 210 and the fourth insulating layer 230 extend in the Z direction from the same position as the word line WL to the same position as the upper electrode layer 170. The third insulating layer 210 is arranged so as to be in contact with the upper surface of the semiconductor substrate SB in a region where the memory cell MC1 is not arranged. The fourth insulating layer 230 is arranged so as to be in contact with the third insulating layer 210 in a region where the memory cell MC1 is not arranged on the semiconductor substrate SB. That is, the side surface of the memory cell MC1 is surrounded by the first insulating layer 310 and the third insulating layer 210. The bottom surface and the side surface of the third insulator 250 are surrounded by the first insulating layer 310 and the fourth insulating layer 230. The bottom surface of the second sacrificial layer 240 and the side surface of the second sacrificial layer 240 and the fourth insulator 220 are surrounded by the first insulating layer 310, the third insulating layer 210, and the fourth insulating layer 230.

[0090] The semiconductor storage device 1 of the present embodiment can improve the heat retention property of the memory cell MC1 by arranging the heat insulating layer that is sandwiched by the insulating layers in contact with the side surface of the memory cell MC1. In particular, by arranging the heat insulating layer as an air layer in a manner of surrounding the side surface from the intermediate electrode layer 130 to the upper electrode layer 170 of the memory cell MC1, the heat retention property can be effectively improved. By improving the heat retention property of the memory cell MC1, the reset current can be reduced, and the power consumption can be suppressed. Furthermore, by improving the heat retention property of the memory cell MC1, the heat conduction to the adjacent memory cell MC1 can be suppressed, and the malfunction can be suppressed. On the other hand, by arranging the heat insulating layer as an amorphous silicon layer or a silicon nitride layer in a manner of surrounding the side surface from the lower electrode layer 110 to the selector layer 120 of the memory cell MC1, the first insulating layer 310, the second insulating layer 330, the third insulating layer 210, and the fourth insulating layer 230 can be prevented from being distorted (flexed), and the second insulator 320 and the fourth insulator 220 can be maintained.

[0091] As for the manufacturing method of the semiconductor storage device of the present embodiment, the process of removing the second sacrificial layer 240 ( Figure 11 ) and the process of removing the first sacrificial layer 340 ( Figure 18) by appropriately adjusting the etching conditions, it is possible to manufacture Figure 19A and Figure 19B the semiconductor storage device 1 shown in FIGS. 1A and IB, and thus the description thereof is omitted here.

[0092] The manufacturing method of the semiconductor storage device 1 of the present embodiment, by leaving a part of the second sacrificial layer 240 between the third insulating layer 210 and the fourth insulating layer 230 in the process (a) of removing the second sacrificial layer 240 in the first embodiment, thereby makes it possible to suppress the third insulating layer 210 and the fourth insulating layer 230 from being distorted (flexed) in the process (b) of dividing (second dicing) the stacked structure, and makes it possible to maintain the fourth insulator 220. Figure 11 Figure 15 The manufacturing method of the semiconductor storage device 1 of the present embodiment, by leaving a part of the first sacrificial layer 340 between the first insulating layer 310 and the second insulating layer 330 in the process (a) of removing the first sacrificial layer 340, thereby makes it possible to suppress the first insulating layer 310 and the second insulating layer 330 from being distorted (flexed) in the subsequent processes, and makes it possible to maintain the second insulator 320. Figure 18

[0093] [Third Embodiment]

[0094] The configuration of the semiconductor storage device of the third embodiment of the present application will be described using Figure 20A and Figure 20B . Figure 20A and Figure 20B are diagrams showing the configuration of a memory cell (semiconductor element) MC1 of the semiconductor storage device 1 of the present embodiment. Figure 20A An example of a cross-sectional view of the memory cell MC1 in the YZ plane is shown. Figure 20B An example of a cross-sectional view of the memory cell MC1 in the XZ plane is shown. In Figure 20A and Figure 20B , one memory cell MC1 is shown, but a memory cluster MM0 is configured by connecting the memory cells MC1 of the same configuration in the XY direction. Similarly, a memory cluster MM1 is configured by connecting the memory cells MC2 of the same configuration in the Z direction by sharing the bit line BL.

[0095] The semiconductor storage device 1 of the present embodiment is the same as the semiconductor storage device 1 of the first embodiment except that the second sacrificial layer 240 is provided instead of the fourth insulator 220, and thus the description of the common parts is omitted.

[0096] As shown in Figure 20A and Figure 20B , the semiconductor storage device 1 of the present embodiment is the same as the semiconductor storage device 1 of the first embodiment except that the second sacrificial layer 240 is provided instead of the fourth insulator 220, and thus the description of the common parts is omitted.​As shown, the memory cell MC1 includes a word line (first wiring) WL1 extending in the X direction (first direction) disposed on the semiconductor substrate SB side, a bit line (second wiring) BL extending in the Y direction (second direction) disposed on the side opposite the semiconductor substrate SB with respect to the word line WL1, a memory cell (semiconductor element) MC1 disposed between the word line WL1 and the bit line BL, an insulator disposed between the sides of the plurality of memory cells MC1, a heat insulating layer disposed between the insulator and the memory cell MC1, and an insulating layer disposed so as to surround the heat insulating layer.

[0097] The heat insulating layer is disposed between the memory cell MC1 and the insulator. The heat insulating layer includes a second insulator 320 disposed between the memory cell MC1 and the first insulator 350, and a second sacrificial layer 240 disposed between the memory cell MC1 and the third insulator 250.

[0098] The second insulator 320 extends in the Y direction, adjacent to the plurality of memory cells MC1 arranged in the Y direction in the X direction. The second insulator 320 extends in the Z direction from the same position as the lower electrode layer 110 to the same position as the bit line BL. The second sacrificial layer 240 is adjacent to each memory cell MC1 in the Y direction with substantially the same width as the memory cell MC1 in the X direction. The second sacrificial layer 240 extends in the Z direction from the same position as the word line WL to the same position as the upper electrode layer 170.

[0099] That is, the second insulator 320 and the second sacrificial layer 240 are disposed so as to surround the sides of the memory cell MC1. Here, the second insulator 320 and the second sacrificial layer 240 are referred to as the heat insulating layer without distinction. In the present embodiment, the second insulator 320 is an air layer, and the second sacrificial layer 240 is an amorphous silicon layer or a silicon nitride layer. The thickness of the second insulator 320 in the X direction and the thickness of the second sacrificial layer 240 in the Y direction can be, for example, about 2 nm.

[0100] The semiconductor storage device 1 of the present embodiment can improve the heat resistance of the memory cell MC1 and improve the heat retention property by disposing the heat insulating layer so as to surround the sides of the memory cell MC1. Further, the semiconductor storage device 1 can improve the voltage resistance of the memory cell MC1 by disposing the heat insulating layer so as to surround the sides of the memory cell MC1. In particular, the semiconductor storage device 1 can effectively improve the heat retention property by disposing the heat insulating layer, which is an air layer, so as to surround the sides of the memory cell MC1.

[0101] The insulating layer is arranged so as to surround the insulating layer. The insulating layer includes a first insulating layer 310, a second insulating layer 330, a third insulating layer 210, and a fourth insulating layer 230. The first insulating layer 310 is arranged between the memory cell MC1 and the second insulator 320. The second insulating layer 330 is arranged between the first insulator 350 and the second insulator 320. The first insulating layer 310 extends in the Y direction and is arranged in contact with the second insulator 320. The first insulating layer 310 is arranged in contact with the plurality of memory cells MC1, the second sacrificial layer 240, and the third insulator 250 arranged in the Y direction on the side opposite the second insulator 320. The first insulating layer 310 is further arranged in contact with the third insulating layer 210 and the fourth insulating layer 230 described later on the side opposite the second insulator 320. The second insulating layer 330 extends in the Y direction and is arranged in contact with the second insulator 320. The second insulating layer 330 is arranged in contact with the first insulator 350 on the side opposite the second insulator 320. The first insulating layer 310 and the second insulating layer 330 extend in the Z direction from the same position as the lower electrode layer 110 to the same position as the bit line BL. The first insulating layer 310 is arranged in contact with the upper surface of the word line WL1 in a region where the memory cell MC1 is not arranged. The second insulating layer 330 is arranged in contact with the first insulating layer 310 in a region where the memory cell MC1 is not arranged on the word line WL1. That is, the bottom surface and the side surface of the second insulator 320 are surrounded by the first insulating layer 310 and the second insulating layer 330.

[0102] The bottom surface and the side surface of the first insulator 350 are surrounded by the second insulating layer 330.

[0103] A third insulating layer 210 is disposed between the memory cell MC1 and the second sacrificial layer 240. A fourth insulating layer 230 is disposed between the third insulator 250 and the second sacrificial layer 240. The third insulating layer 210, with a width approximately the same as that of the memory cell MC1 in the X direction, is grounded to both the memory cell MC1 and the second sacrificial layer 240. The fourth insulating layer 230, with a width approximately the same as that of the memory cell MC1 in the X direction, is grounded to both the third insulator 250 and the second sacrificial layer 240. The third insulating layer 210 and the fourth insulating layer 230 are connected to the first insulating layer 310. The third insulating layer 210 and the fourth insulating layer 230 extend in the Z direction from the same position as the word line WL to the same position as the upper electrode layer 170. In areas where the memory cell MC1 is not disposed, the third insulating layer 210 is grounded to the upper surface of the semiconductor substrate SB. In areas on the semiconductor substrate SB where the memory cell MC1 is not disposed, the fourth insulating layer 230 is grounded to the third insulating layer 210. That is, the side of memory cell MC1 is surrounded by the first insulating layer 310 and the third insulating layer 210. The bottom and side of the third insulator 250 are surrounded by the first insulating layer 310 and the fourth insulating layer 230. The bottom and side of the second sacrificial layer 240 are surrounded by the first insulating layer 310, the third insulating layer 210, and the fourth insulating layer 230.

[0104] The semiconductor memory device 1 of this embodiment improves the thermal insulation performance of the memory cell MC1 by configuring a heat insulation layer sandwiched between an insulating layer and the side surface of the memory cell MC1. In particular, by configuring the heat insulation layer as an air layer sandwiching the side surface of the memory cell MC1, the thermal insulation performance is effectively improved. By improving the thermal insulation performance of the memory cell MC1, the reset current can be reduced, and power consumption can be suppressed. Furthermore, by improving the thermal insulation performance of the memory cell MC1, heat conduction to adjacent memory cells MC1 can be suppressed, thereby suppressing malfunctions.

[0105] Regarding the manufacturing method of the semiconductor memory device in this embodiment, the process of removing the second sacrificial layer 240 in the first embodiment is omitted. Figure 11 ), capable of manufacturing Figure 20A as well as Figure 20B The semiconductor memory device 1 shown is therefore omitted here.

[0106] The manufacturing method of the semiconductor memory device 1 in this embodiment, through the process of removing the second sacrificial layer 240 in the first embodiment ( Figure 11 In the process of dividing the laminated structure (second cutting), a second sacrificial layer 240 remains between the third insulating layer 210 and the fourth insulating layer 230, thereby enabling the process of dividing the laminated structure (second cutting) to achieve this. Figure 15The third insulating layer 210 and the fourth insulating layer 230 are inhibited from being distorted (flexed) in the direction of the arrow (A) in FIG. 21.

[0107] [Fourth Embodiment]

[0108] Using Figure 21A and Figure 21B The configuration of the semiconductor storage device of the fourth embodiment of the present application will be described. Figure 21A and Figure 21B is a view showing the configuration of a memory cell (semiconductor element) MC1 of the semiconductor storage device 1 of the present embodiment. Figure 21A An example of a cross-sectional view of the memory cell MC1 in the YZ plane is shown. Figure 21B An example of a cross-sectional view of the memory cell MC1 in the XZ plane is shown. Figure 21A and Figure 21B In the first and second embodiments, one memory cell MC1 is shown, but memory cells MC1 of the same configuration are connected in the XY direction to constitute a memory cluster MM0. Similarly, memory cells MC2 of the same configuration are connected by sharing bit lines BL in the Z direction to constitute a memory cluster MM1.

[0109] The semiconductor storage device 1 of the present embodiment is the same as the semiconductor storage device 1 of the first embodiment except that the second insulator 320 and the first sacrificial layer 340 are provided and the fourth insulator 220 is replaced by the second sacrificial layer 240, and thus the description will be omitted for the common parts.

[0110] As shown in Figure 21A and Figure 21B , the memory cell MC1 includes a word line (first wiring) WL1 extending in the X direction (first direction) provided on the semiconductor substrate SB side, a bit line (second wiring) BL extending in the Y direction (second direction) provided on the side opposite to the semiconductor substrate SB opposite to the word line WL1, a memory cell (semiconductor element) MC1 provided between the word line WL1 and the bit line BL, an insulator provided between the sides of a plurality of memory cells MC1, a thermal isolation layer provided between the insulator and the memory cell MC1, and an insulating layer provided so as to surround the thermal isolation layer.

[0111] The thermal isolation layer is provided between the memory cell MC1 and the insulator. The thermal isolation layer includes the first sacrificial layer 340 and the second insulator 320 provided between the memory cell MC1 and the first insulator 350, and the second sacrificial layer 240 provided between the memory cell MC1 and the third insulator 250.

[0112] The first sacrificial layer 340 extends in the Y direction, and is adjacent to the plurality of memory cells MC1 arranged in the Y direction in the X direction. The first sacrificial layer 340 extends in the Z direction from the same position as the lower electrode layer 110 to the same position as the selector layer 120. Above the first sacrificial layer 340, the second insulator 320 is arranged so as to contact and overlap the first sacrificial layer 340. The second insulator 320 also extends in the Y direction, and is adjacent to the plurality of memory cells MC1 arranged in the Y direction in the X direction. The second insulator 320 extends in the Z direction from the same position as the intermediate electrode layer 130 to the same position as the bit line BL. The second sacrificial layer 240 is adjacent to each of the memory cells MC1 in the Y direction, with substantially the same width as the memory cells MC1 in the X direction. The second sacrificial layer 240 extends in the Z direction from the same position as the word line WL to the same position as the upper electrode layer 170.

[0113] That is, the first sacrificial layer 340 and the second insulator 320, and the second sacrificial layer 240 are arranged so as to surround the side surfaces of the memory cells MC1. Here, when the first sacrificial layer 340, the second insulator 320, and the second sacrificial layer 240 are not distinguished, they are referred to as heat insulating layers. In the present embodiment, the second insulator 320 is an air layer, and the first sacrificial layer 340 and the second sacrificial layer 240 are amorphous silicon layers or silicon nitride layers. The thickness of the first sacrificial layer 340 and the second insulator 320 in the X direction, and the thickness of the second sacrificial layer 240 in the Y direction, for example, can be about 2 nm.

[0114] The semiconductor storage device 1 of the present embodiment can improve the heat resistance of the memory cells MC1, and can improve the heat retention property, by arranging the heat insulating layers so as to surround the side surfaces of the memory cells MC1. Furthermore, the semiconductor storage device 1 can improve the withstand voltage of the memory cells MC1, by arranging the heat insulating layers so as to surround the side surfaces of the memory cells MC1. In particular, by arranging the heat insulating layers that are air layers so as to sandwich the side surfaces from the intermediate electrode layer 130 to the bit line BL of the memory cells MC1, the heat retention property can be effectively improved.

[0115] The insulating layer is arranged so as to surround the insulating layer. The insulating layer includes a first insulating layer 310, a second insulating layer 330, a third insulating layer 210, and a fourth insulating layer 230. The first insulating layer 310 is arranged between the memory cell MC1 and the first sacrificial layer 340 and the second insulator 320. The second insulating layer 330 is arranged between the first insulator 350 and the first sacrificial layer 340 and the second insulator 320. The first insulating layer 310 extends in the Y direction and is arranged in contact with the first sacrificial layer 340 and the second insulator 320. The first insulating layer 310 is arranged in contact with the plurality of memory cells MC1 arranged in the Y direction, the second sacrificial layer 240, and the third insulator 250 on the side opposite the first sacrificial layer 340 and the second insulator 320. The first insulating layer 310 is further arranged in contact with the third insulating layer 210 and the fourth insulating layer 230 described later on the side opposite the first sacrificial layer 340 and the second insulator 320. The second insulating layer 330 extends in the Y direction and is arranged in contact with the first sacrificial layer 340 and the second insulator 320. The second insulating layer 330 is arranged in contact with the first insulator 350 on the side opposite the first sacrificial layer 340 and the second insulator 320. The first insulating layer 310 and the second insulating layer 330 extend in the Z direction from the same position as the lower electrode layer 110 to the same position as the bit line BL. The first insulating layer 310 is arranged in contact with the upper surface of the word line WL1 in a region where the memory cell MC1 is not arranged. The second insulating layer 330 is arranged in contact with the first insulating layer 310 in a region where the memory cell MC1 is not arranged on the word line WL1. That is, the bottom surface of the first sacrificial layer 340 and the side surface of the first sacrificial layer 340 and the second insulator 320 are surrounded by the first insulating layer 310 and the second insulating layer 330. The bottom surface and the side surface of the first insulator 350 are surrounded by the second insulating layer 330.

[0116] A third insulating layer 210 is disposed between the memory cell MC1 and the second sacrificial layer 240. A fourth insulating layer 230 is disposed between the third insulator 250 and the second sacrificial layer 240. The third insulating layer 210, with a width approximately the same as that of the memory cell MC1 in the X direction, is grounded to both the memory cell MC1 and the second sacrificial layer 240. The fourth insulating layer 230, with a width approximately the same as that of the memory cell MC1 in the X direction, is grounded to both the third insulator 250 and the second sacrificial layer 240. The third insulating layer 210 and the fourth insulating layer 230 are connected to the first insulating layer 310. The third insulating layer 210 and the fourth insulating layer 230 extend in the Z direction from the same position as the word line WL to the same position as the upper electrode layer 170. In areas where the memory cell MC1 is not disposed, the third insulating layer 210 is grounded to the upper surface of the semiconductor substrate SB. In areas on the semiconductor substrate SB where the memory cell MC1 is not disposed, the fourth insulating layer 230 is grounded to the third insulating layer 210. That is, the side of memory cell MC1 is surrounded by the first insulating layer 310 and the third insulating layer 210. The bottom and side of the third insulator 250 are surrounded by the first insulating layer 310 and the fourth insulating layer 230. The bottom and side of the second sacrificial layer 240 are surrounded by the first insulating layer 310, the third insulating layer 210, and the fourth insulating layer 230.

[0117] The semiconductor memory device 1 of this embodiment improves the thermal insulation performance of the memory cell MC1 by configuring a heat insulation layer sandwiched between an insulating layer and the side of the memory cell MC1, which is grounded to the ground. In particular, the heat insulation layer, which serves as an air layer, is configured to sandwich the side of the memory cell MC1 from the intermediate electrode layer 130 to the bit line BL, thereby effectively improving the thermal insulation performance. By improving the thermal insulation performance of the memory cell MC1, the reset current can be reduced, and power consumption can be suppressed. Furthermore, by improving the thermal insulation performance of the memory cell MC1, heat conduction to adjacent memory cells MC1 can be suppressed, thereby suppressing malfunctions.

[0118] Regarding the manufacturing method of the semiconductor memory device in this embodiment, the process of removing the second sacrificial layer 240 in the first embodiment is omitted. Figure 11 ), and in the process of removing the first sacrificial layer 340 ( Figure 18 By appropriately adjusting the etching conditions, it is possible to manufacture... Figure 21A as well as Figure 21B The semiconductor memory device 1 shown is therefore omitted here.

[0119] The manufacturing method of the semiconductor memory device 1 in this embodiment involves the process of removing the second sacrificial layer 240 in the first embodiment. Figure 11In the process of dividing the laminated structure (second cutting), a second sacrificial layer 240 remains between the third insulating layer 210 and the fourth insulating layer 230, thereby enabling the process of dividing the laminated structure (second cutting) to achieve this. Figure 15 The twisting (bending) of the third insulating layer 210 and the fourth insulating layer 230 is suppressed during the process of removing the first sacrificial layer 340. Figure 18 In the process, a portion of the first sacrificial layer 340 remains between the first insulating layer 310 and the second insulating layer 330, thereby suppressing the twisting (bending) of the first insulating layer 310 and the second insulating layer 330 in subsequent processes and maintaining the second insulator 320.

[0120] [Variation Example 1]

[0121] use Figures 22A-22C The configuration of the semiconductor memory device of Modification 1 of the present invention will be described. Figures 22A-22C This is a diagram showing the configuration of the memory cell (semiconductor element) MC1 of the semiconductor memory device 1 in this modified example. Figure 22A An example of a cross-sectional view of memory cell MC1 in the YZ plane is shown. Figure 22B An example of a cross-sectional view of memory cell MC1 in the XZ plane is shown. Figure 22C It shows the result of Figure 22B The dashed line shows an example of an enlarged cross-sectional view of memory cell MC1 in the area indicated by the dashed line. Figures 22A-22C The diagram shows a memory cell MC1, but it is connected in the XY direction to a memory cell MC1 of the same configuration to form a memory cluster MM0. Similarly, in the Z direction, it is connected in the Z direction to a memory cell MC2 of the same configuration to form a memory cluster MM1.

[0122] The semiconductor memory device 1 of this modified example is the same as the semiconductor memory device 1 of the first embodiment, except that a spacer 260 is disposed at the upper end of the fourth insulator 220. Therefore, the description of the common parts is omitted.

[0123] like Figures 22A-22C As shown, the memory cell MC1 includes: a word line (first wiring) WL1 disposed on the semiconductor substrate SB and extending in the X direction (first direction); a bit line (second wiring) BL disposed opposite to the word line WL1 on the side opposite to the semiconductor substrate SB and extending in the Y direction (second direction); the memory cell (semiconductor element) MC1 disposed between the word line WL1 and the bit line BL; an insulator disposed between the sides of the plurality of memory cells MC1; a heat insulation layer disposed between the insulator and the memory cell MC1; and an insulating layer disposed in a manner surrounding the heat insulation layer.

[0124] A thermal barrier layer is provided between the memory cell MC1 and the insulator. The thermal barrier layer includes a second insulator 320 provided between the memory cell MC1 and the first insulator 350, and a fourth insulator 220 provided between the memory cell MC1 and the third insulator 250.

[0125] The second insulator 320 extends in the Y direction, and is adjacent to the plurality of memory cells MC1 arranged in the Y direction in the X direction. The second insulator 320 extends in the Z direction from the same position as the lower electrode layer 110 to the same position as the bit line BL. The fourth insulator 220 is adjacent to each of the memory cells MC1 in the Y direction with substantially the same width as the memory cell MC1 in the X direction. The fourth insulator 220 extends in the Z direction from the same position as the word line WL to the same position as the barrier metal layer 160.

[0126] The partition 260 is provided at the upper end portion of the fourth insulator 220 provided between the memory cell MC1 and the third insulator 250. The partition 260 is provided at the same position as the upper electrode layer 170 in the Z direction. The partition 260 is surrounded by the first insulating layer 310, the third insulating layer 210, and the fourth insulating layer 230 together with the fourth insulator 220. The partition 260 is in contact with the third insulating layer 210 and the fourth insulating layer 230 at least in the upper end portion. The upper surface of the partition 260 is in contact with the bit line BL. The partition 260 is adjacent to the upper electrode layer 170 of the memory cell MC1 in the Y direction with substantially the same width as the upper electrode layer 170 of the memory cell MC1 in the X direction, with the third insulating layer 210 interposed therebetween.

[0127] In the Figure 22C In the

[0128] The semiconductor storage device 1 of the present embodiment can suppress the distortion (flexion) of the third insulating layer 210 and the fourth insulating layer 230, and can maintain the fourth insulator 220 by providing the partition 260 at the upper end portion of the fourth insulator 220.

[0129] As for the manufacturing method of the semiconductor storage device of the present embodiment, the process of removing the second sacrificial layer 240 in the first embodiment Figure 11) and then the insulating film is removed by CMP (Chemical Mechanical Polishing) or the like to expose the upper electrode layer 170 on the stacked structure, thereby enabling the semiconductor storage device 1 to be manufactured Figures 22A-22C The semiconductor storage device 1 of the present embodiment is configured as shown in FIG. 1, and thus the description thereof is omitted here.

[0130] The manufacturing method of the semiconductor storage device 1 of the present embodiment, after the process of removing the second sacrificial layer 240 in the first embodiment ( Figure 11 ), forms a partition 260 between the third insulating layer 210 and the fourth insulating layer 230, thereby enabling the third insulating layer 210 and the fourth insulating layer 230 to be inhibited from being distorted (flexed) in the process of dividing (second cutting) the stacked structure ( Figure 15 ).

[0131] [Modified Example 2]

[0132] The semiconductor storage device of the present modified example is configured as shown in FIG. 1. Figure 23A Figure 23B The semiconductor storage device of the present modified example is configured as shown in FIG. 1. Figure 23A Figure 23B FIG. 1 is a view showing the configuration of a memory cell (semiconductor element) MC1 of the semiconductor storage device 1 of the present modified example. Figure 23A FIG. 1 is a view showing the configuration of a memory cell (semiconductor element) MC1 of the semiconductor storage device 1 of the present modified example. Figure 23B FIG. 1 is a view showing the configuration of a memory cell (semiconductor element) MC1 of the semiconductor storage device 1 of the present modified example. Figure 23A Figure 23B In the first embodiment and the second embodiment, one memory cell MC1 is shown, but a memory cluster MM0 is configured by connecting the memory cells MC1 of the same configuration in the XY direction, and a memory cluster MM1 is configured by connecting memory cells MC2 of the same configuration in the Z direction by sharing a bit line BL.

[0133] The semiconductor storage device of the present modified example is the same as the semiconductor storage device of the first embodiment except for the size and shape of the insulating layer, the heat insulating layer, and the insulator, and thus the description of the common parts is omitted.

[0134] As shown in FIG. 1, the semiconductor storage device 1 of the present modified example is configured as shown in FIG. 1. Figure 23A ​​​As shown, the memory cell MC1 includes a word line (first wiring) WL1 extending in the X direction (first direction) disposed on the semiconductor substrate SB side, a bit line (second wiring) BL extending in the Y direction (second direction) disposed on the side opposite the semiconductor substrate SB with respect to the word line WL1, a memory cell (semiconductor element) MC1 disposed between the word line WL1 and the bit line BL, an insulator disposed between the sides of the plurality of memory cells MC1, a thermal insulation layer disposed between the insulator and the memory cell MC1, and an insulating layer disposed so as to surround the thermal insulation layer.

[0135] The insulator is disposed between adjacent memory cells MC1. The insulator includes a first insulator 350a adjacent to the memory cell MC1 in the X direction, and a third insulator 250a adjacent to the memory cell MC1 in the Y direction. The first insulator 350a extends in the Y direction and is adjacent to the plurality of memory cells MC1 arranged in the Y direction in the X direction. The third insulator 250a is adjacent to each memory cell MC1 in the Y direction with substantially the same width as the memory cell MC1 in the X direction.

[0136] The thermal insulation layer is disposed between the memory cell MC1 and the insulator. The thermal insulation layer includes a second insulator 320a disposed between the memory cell MC1 and the first insulator 350a, and a fourth insulator 220a disposed between the memory cell MC1 and the third insulator 250a.

[0137] The second insulator 320a extends in the Y direction and is adjacent to the plurality of memory cells MC1 arranged in the Y direction in the X direction. The fourth insulator 220a is adjacent to each memory cell MC1 in the Y direction with a width smaller than the memory cell MC1 in the X direction. Here, the second insulator 320a and the fourth insulator 220a are disposed so as to surround the sides of the memory cell MC1. Therefore, the second insulator 320a is recessed in the direction of the fourth insulator 220a by an amount in which the width of the fourth insulator 220a is shortened.

[0138] The insulating layer is disposed so as to surround the thermal insulation layer. The insulating layer includes a first insulating layer 310a, a second insulating layer 330a, a third insulating layer 210a, and a fourth insulating layer 230a. The third insulating layer 210a is disposed between the memory cell MC1 and the fourth insulator 220a. The fourth insulating layer 230a is disposed between the third insulator 250a and the fourth insulator 220a. The third insulating layer 210a is disposed so as to be in contact with the memory cell MC1 and the fourth insulator 220a with a width smaller than the memory cell MC1. The fourth insulating layer 230a is disposed so as to be in contact with the third insulator 250a and the fourth insulator 220a with a width smaller than the memory cell MC1.

[0139] A first insulating layer 310a is disposed between the memory cell MC1 and the second insulator 320a. A second insulating layer 330a is disposed between the first insulator 350a and the second insulator 320a. The first insulating layer 310a extends along the Y direction and is grounded to the plurality of memory cells MC1, the third insulating layer 210a, the fourth insulator 220a, the fourth insulating layer 230a, and the third insulator 250a arranged in the Y direction. The widths of the third insulating layers 210a, 220a, and 230a are smaller than the widths of the memory cells MC1 and the third insulator 250a. Therefore, the first insulating layer 310a is recessed into the direction of the third insulating layers 210a, 220a, and 230a by an amount that the widths of the third insulating layers 210a, 220a, and 230a decrease.

[0140] The first insulating layer 310a extends along the Y direction and is grounded to the second insulator 320a. The second insulating layer 330a extends along the Y direction and is grounded to the second insulator 320a. On the side opposite to the second insulator 320a, the second insulating layer 330a is grounded to the first insulator 350a. Therefore, the second insulator 320a, the second insulating layer 330a, and the first insulator 350a are also recessed towards the third insulating layer 210a, the fourth insulating layer 220a, and the fourth insulating layer 230a by an amount that the widths of the third insulating layer 210a, the fourth insulating layer 220a, and the fourth insulating layer 230a decrease. That is, the side of the memory cell MC1 is surrounded by the first insulating layer 310a and the third insulating layer 210a. The bottom surface and the side surface of the third insulator 250a are surrounded by the first insulating layer 310a and the fourth insulating layer 230a. The bottom and sides of the fourth insulator 220a are surrounded by the first insulating layer 310a, the third insulating layer 210a, and the fourth insulating layer 230a.

[0141] exist Figure 23B In a variation, the width of the third insulator 250b is smaller than that of the memory cell MC1. The insulators are disposed between adjacent memory cells MC1. The insulators include a first insulator 350b adjacent to the memory cell MC1 in the X direction and a third insulator 250b adjacent to the memory cell MC1 in the Y direction. The first insulator 350b extends along the Y direction and is adjacent to the plurality of memory cells MC1 arranged in the Y direction in the X direction. The third insulator 250b, with a width smaller than that of the memory cell MC1 in the X direction, is adjacent to each memory cell MC1 in the Y direction.

[0142] A thermal isolation layer is disposed between the memory cell MC1 and the insulator. The thermal isolation layer includes a second insulator 320b disposed between the memory cell MC1 and the first insulator 350b, and a fourth insulator 220b disposed between the memory cell MC1 and the third insulator 250b.

[0143] The second insulator 320b extends in the Y direction, and is adjacent to the plurality of memory cells MC1 arranged in the Y direction in the X direction. The fourth insulator 220b is adjacent to each of the memory cells MC1 in the Y direction with a width smaller than the memory cell MC1 in the X direction. Here, the second insulator 320b and the fourth insulator 220b are disposed so as to surround the side surface of the memory cell MC1. Therefore, the second insulator 320b is recessed toward the fourth insulator 220b by an amount in which the width of the fourth insulator 220b is shortened.

[0144] An insulating layer is disposed so as to surround the thermal isolation layer. The insulating layer includes a first insulating layer 310b, a second insulating layer 330b, a third insulating layer 210b, and a fourth insulating layer 230b. The third insulating layer 210b is disposed between the memory cell MC1 and the fourth insulator 220b. The fourth insulating layer 230b is disposed between the third insulator 250b and the fourth insulator 220b. The third insulating layer 210b is disposed so as to be in contact with the memory cell MC1 and the fourth insulator 220b with a width smaller than the memory cell MC1. The fourth insulating layer 230b is disposed so as to be in contact with the third insulator 250b and the fourth insulator 220b with a width smaller than the memory cell MC1.

[0145] The first insulating layer 310b is disposed between the memory cell MC1 and the second insulator 320b. The second insulating layer 330b is disposed between the first insulator 350b and the second insulator 320b. The first insulating layer 310b extends in the Y direction, and is disposed so as to be in contact with the plurality of memory cells MC1 arranged in the Y direction, the third insulating layer 210b, the fourth insulator 220b, the fourth insulating layer 230b, and the third insulator 250b. The third insulating layer 210b, the fourth insulator 220b, the fourth insulating layer 230b, and the third insulator 250b have a width smaller than the memory cell MC1. Therefore, the first insulating layer 310b is recessed toward the third insulating layer 210b, the fourth insulator 220b, the fourth insulating layer 230b, and the third insulator 250b by an amount in which the width of the third insulating layer 210b, the fourth insulator 220b, the fourth insulating layer 230b, and the third insulator 250b is shortened.

[0146] The second insulator 320b extends along the Y direction and is grounded to the first insulating layer 310b. The second insulating layer 330b extends along the Y direction and is grounded to the second insulator 320b. On the side opposite to the second insulator 320b, the second insulating layer 330b is grounded to the first insulator 350b. Therefore, the second insulator 320b, the second insulating layer 330b, and the first insulator 350b are also recessed towards the third insulating layer 210b, the fourth insulating layer 220b, the fourth insulating layer 230b, and the third insulating layer 250b by an amount that the widths of the third insulating layer 210b, the fourth insulating layer 220b, the fourth insulating layer 230b, and the third insulating layer 250b decrease. That is, the side of the memory cell MC1 is surrounded by the first insulating layer 310b and the third insulating layer 210b. The bottom surface and the side surface of the third insulator 250b are surrounded by the first insulating layer 310b and the fourth insulating layer 230b. The bottom and sides of the fourth insulator 220b are surrounded by the first insulating layer 310b, the third insulating layer 210b, and the fourth insulating layer 230b.

[0147] Regarding the manufacturing method of the semiconductor memory device in this variation, through the process of dividing the stacked structure (second cutting) Figure 15 By appropriately adjusting the etching conditions, it is possible to manufacture... Figure 23A as well as Figure 23B The semiconductor memory device 1 shown is therefore omitted here.

[0148] While embodiments and variations of the present invention have been described, these embodiments and variations are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: a first wiring extending in a first direction; a second wiring extending in a second direction intersecting the first direction; a first semiconductor element extending in a third direction intersecting the first direction and the second direction, connected to the first wiring and the second wiring, and having a first selector layer and a first resistance change layer; a first insulator extending in the second direction and the third direction, adjacent to the first semiconductor element in the first direction; a second insulator extending in the second direction and the third direction, and including an air gap disposed between the first semiconductor element and the first insulator; a first insulating layer extending in the second direction and the third direction, and disposed between the first semiconductor element and the second insulator, in contact with the first semiconductor element and the second insulator; and a second insulating layer extending in the second direction and the third direction, and disposed between the first insulator and the second insulator, in contact with the first insulator and the second insulator.

2. The semiconductor memory device according to claim 1, wherein the second insulator is provided at the same position as the first resistance change layer in the third direction.

3. The semiconductor memory device according to claim 2, wherein the second insulator further includes an amorphous silicon layer or a silicon nitride layer at the same position as the first selector layer in the third direction.

4. The semiconductor memory device according to claim 1, wherein the second insulator is a heat insulating layer.

5. The semiconductor memory device according to claim 1, further comprising: a third insulator extending in the third direction, adjacent to the first semiconductor element in the second direction, and disposed in contact with the first insulating layer; and a fourth insulator extending in the third direction, and including an air gap disposed between the first semiconductor element and the third insulator, in contact with the first insulating layer.

6. The semiconductor memory device according to claim 5, wherein the fourth insulator is provided at the same position as the first resistance change layer in the third direction.

7. The semiconductor memory device according to claim 6, wherein the fourth insulator further includes an amorphous silicon layer or a silicon nitride layer at the same position as the first selector layer in the third direction.

8. The semiconductor memory device according to claim 5, further comprising: a third insulating layer extending in the third direction, and disposed between the first semiconductor element and the fourth insulator, in contact with the first semiconductor element and the fourth insulator, and connected to the first insulating layer; and a fourth insulating layer extending in the third direction, and disposed between the third insulator and the fourth insulator, in contact with the third insulator and the fourth insulator, and connected to the first insulating layer.

9. The semiconductor memory device according to claim 8, further comprising: a third wiring extending in the first direction, adjacent to the first wiring across the third insulator in the second direction. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ a second semiconductor element extending in the third direction, connected to the third wiring and the second wiring, disposed in contact with the first insulator, and having a second selector layer and a second resistance variable layer; and a fifth insulator extending in the third direction and including an air gap disposed between the second semiconductor element and the third insulator.

10. The semiconductor memory device according to claim 9, the fifth insulator is provided at the same position as the second resistance variable layer in the third direction.

11. The semiconductor memory device according to claim 10, the fifth insulator further includes an amorphous silicon layer or a silicon nitride layer at the same position as the second selector layer in the third direction.

12. The semiconductor memory device according to any one of claims 9 to 11, further comprising: a fifth insulating layer extending in the third direction, disposed in contact with the second semiconductor element and the fifth insulator between the second semiconductor element and the fifth insulator, and connected to the first insulating layer; and a sixth insulating layer extending in the third direction, disposed in contact with the third insulator and the fifth insulator between the third insulator and the fifth insulator, and connected to the first insulating layer.

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