Semiconductor device, storage device, and method of manufacturing a transistor

Abstract

An embodiment provides a semiconductor device, a storage device, and a method for manufacturing a transistor that can stably improve characteristics. The semiconductor device of the embodiment includes a substrate, a gate insulating film on the substrate, a stacked semiconductor layer, and a metal layer on or above the stacked semiconductor layer. The stacked semiconductor layer has: a first layer formed on the gate insulating layer and including polycrystalline semiconductor doped with phosphorus; a second layer formed on the first layer and including polycrystalline semiconductor doped with carbon; and a third layer formed on the second layer and including polycrystalline semiconductor doped with phosphorus or undoped with phosphorus. The phosphorus content of the third layer is less than that of the first layer, or the third layer does not contain phosphorus.

Description

[0001] [Related Application]

[0002] This application claims priority based on Japanese Patent Application No. 2020-157386 (filing date: September 18, 2020). This application incorporates the entire contents of the base application by reference thereto. Technical Field

[0003] The present invention relates to a semiconductor device, a storage device, and a method for manufacturing a transistor. Background Art

[0004] In order to highly integrate a semiconductor memory device, a three-dimensional stacked non-volatile memory device in which memory cells are three-dimensionally stacked has been proposed. The three-dimensional stacked non-volatile memory device has, for example, a structure in which a memory cell array and a peripheral circuit serving as a control circuit for the memory cells are stacked. The peripheral circuit uses CMOS (Complementary Metal Oxide Semiconductor), etc. The transistors used in CMOS deteriorate in characteristics due to manufacturing steps and the like. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor device, a storage device, and a method for manufacturing a transistor capable of stably improving characteristics.

[0006] The semiconductor device of the embodiment includes a substrate, a gate insulating film on the substrate, a stacked semiconductor layer, and a metal layer on or above the stacked semiconductor layer. The stacked semiconductor layer has: a first layer formed on the gate insulating layer and containing polycrystalline semiconductor doped with phosphorus; a second layer formed on the first layer and containing polycrystalline semiconductor doped with carbon; and a third layer formed on the second layer and containing polycrystalline semiconductor doped with phosphorus or not doped with phosphorus. The phosphorus content of the third layer is less than the phosphorus content of the first layer, or the third layer does not contain phosphorus. Description of the Drawings

[0007] Figure 1 It is a cross-sectional view showing a gate electrode in the semiconductor device of the embodiment.

[0008] Figure 2 It is showing Figure 1 A cross-sectional view of a modified example of the gate electrode shown.

[0009] Figure 3 (a) to (f) are diagrams showing Figure 1 The manufacturing steps of the gate electrode shown.

[0010] Figure 4This is a cross-sectional view of a CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor) representing a semiconductor device as an embodiment.

[0011] Figure 5 (a) to Figure 7 (o) represents Figure 4 a diagram showing the manufacturing steps of the CMOSFET shown.

[0012] Figure 8 This is a block diagram showing the configuration of a semiconductor memory device according to an embodiment.

[0013] Figure 9 This represents Figure 8 a circuit diagram showing the circuit configuration of a memory cell array of the semiconductor memory device shown.

[0014] Figure 10 This is a cross-sectional view of a semiconductor memory device according to an embodiment. Detailed Embodiment

[0015] Hereinafter, with reference to the drawings, a semiconductor device and a semiconductor memory device according to an embodiment will be described. In addition, in each embodiment, there are cases where substantially the same constituent parts are denoted by the same reference numerals and the related description parts are omitted. The drawings are schematic, and the relationship between the thickness and the planar dimensions, the thickness ratio of each part, etc. may be different from the actual situation.

[0016] (First Embodiment / Gate Electrode)

[0017] Figure 1 This is a cross-sectional view showing the structure of a gate electrode in a semiconductor device according to an embodiment. Figure 1 The gate electrode 100 shown is provided on a gate insulating layer 120 formed on one surface of a semiconductor substrate 110. As the semiconductor substrate 110, for example, a silicon substrate can be used. The gate insulating layer 120 can be, for example, silicon oxide (SiO). The gate electrode 100 includes a laminated semiconductor layer 130 having a three-layer structure, a metal layer 150, and, as needed, a TSI (Through Silicon oxide Insertion) layer 140.

[0018] A stacked semiconductor layer 130 with a three-layer structure is formed on the gate insulating layer 120. The stacked semiconductor layer 130 sequentially includes, from the side close to the gate insulating layer 120: a first layer 131 including polycrystalline semiconductor doped with phosphorus (P); a second layer 132 including polycrystalline semiconductor doped with carbon (C); and a third layer 133 including polycrystalline semiconductor doped with P or undoped with P. As the polycrystalline semiconductor in the first layer 131, the second layer 132, and the third layer 133 of the stacked semiconductor layer 130, polysilicon can be used, for example.

[0019] C doped in the second layer 132 has the effect of capturing P to suppress mutual diffusion. However, as shown in the following manufacturing steps ( Figure 2 ), an oxide film 160 is formed to suppress etching residues. If the oxide film 160 is formed directly above the second layer 132, the oxide film 160 will be difficult to strip. Therefore, the third layer 133 is inserted above the second layer 132 to facilitate the stripping of the oxide film 160.

[0020] The third layer 133 has the effect of suppressing the increase in the interface resistance between the stacked semiconductor layer 130 and the following metal layer 150. However, if the P doping amount in the third layer 133 is too large, the TSI layer 140 as the following oxide layer will be accelerated in oxidation. Therefore, the P doping amount of the third layer 133 is set to be less than the P doping amount of the first layer 131. That is, the phosphorus content of the third layer 133 is less than the phosphorus content of the first layer 131.

[0021] On the third layer 133 of the stacked semiconductor layer 130, a TSI layer 140 is formed as needed. The TSI layer 140 has the effect of preventing impurities from diffusing to the following metal layer 150. The TSI layer 140 can use silicon oxide (SiO), for example. However, depending on the constituent material of the metal layer 150, as Figure 2 shown, the TSI layer 140 can also be omitted, and the metal layer 150 can be directly provided on the stacked semiconductor layer 130.

[0022] A metal layer 150 is formed on the TSI layer 140. As the metal layer 150, for example, a laminate sequentially stacked with tungsten silicide (WSi) / titanium nitride (TiN), or titanium (Ti) / titanium nitride (TiN) / tungsten (W) can be used from the side close to the TSI layer 140.

[0023] If the metal layer 150 is WSi / TiN, there is a risk of impurities diffusing into the WSi at the interface. Therefore, it is preferable to insert the TSI layer 140. However, in the case where the metal layer 150 is Ti / TiN / W, there is no W at the interface, so the TSI layer 140 is not required. Figure 2The gate electrode 100 shown, for example, has a stacked film of Ti / TiN / W as the metal layer 150, thereby omitting the formation of the TSI layer 140.

[0024] The gate electrode 100 is manufactured as described below. According to Figure 3 the manufacturing steps of the gate electrode 100 will be described. As Figure 3 (a) shows, a semiconductor substrate 110 is prepared. As Figure 3 (b) shows, a gate insulating layer 120 is formed on one surface of the semiconductor substrate 110.

[0025] Subsequently, as Figure 3 (c) shows, a first layer 131, a second layer 132, and a third layer 133 are sequentially formed on the gate insulating layer 120 to form a stacked semiconductor layer 130. As Figure 3 (d) shows, an oxide film 160 is formed on the third layer 133. The oxide film 160 can be, for example, silicon oxide (SiO).

[0026] Next, after forming the oxide film 160, as Figure 3 (e) shows, the upper portion 133a of the third layer 133 together with the oxide film 160 is removed. As the removal method, mechanical etching (CMP) or chemical etching can be used. Chemical etching can be, for example, CDE (Chemical Dry Etching), RIE (Reactive Ion Etching), or wet etching. Additionally, multiple removal methods among these can be combined and used.

[0027] Next, as Figure 3 (f) shows, a TSI layer 140 is formed on the third layer 133, and a metal layer 150 is formed on the TSI layer 140, thereby obtaining Figure 1 the gate electrode 100 shown. Figure 2 The gate electrode 100 shown is obtained by directly forming a metal layer 150 on the third layer 133.

[0028] (Second Embodiment / Semiconductor Device)

[0029] The semiconductor device as the second embodiment is, for example, a CMOSFET. Figure 4 It is a cross-sectional view showing an example of the second embodiment. Figure 4 The CMOSFET shown has an N-channel MOSFET (hereinafter sometimes simply referred to as "NMOS transistor (TrN)") and a P-channel MOSFET (hereinafter sometimes simply referred to as "PMOS transistor (TrP)"). In addition, Figure 4The X direction is set as the gate width direction, the Y direction is set as the gate length direction, and the Z direction is set as the direction intersecting the X direction and the Y direction for explanation.

[0030] Near the surface of the semiconductor substrate 110, a P-type well region PW, an N-type well region NW, and an element isolation region STI for electrically separating the N-type well region NW from the P-type well region PW are formed. The element isolation region STI can use, for example, silicon oxide (SiO).

[0031] An NMOS (N-Channel Metal Oxide Semiconductor) transistor TrN is provided in the P-type well region PW, and a PMOS (P-Channel Metal Oxide Semiconductor) transistor TrP is provided in the N-type well region NW.

[0032] As the gate electrode GCn of the NMOS transistor TrN, the gate electrode 100 can be used. The upper surface of the metal layer 150 is covered by the insulating layer 55. The side surface of the metal layer 150 is covered by the insulating layer 56n. The insulating layer 56n functions as the sidewall of the gate electrode 100 of the NMOS transistor TrN. A part of the insulating layer 55 is open, and the gate electrode 100 is connected to the contact plug C0 through the opening of the insulating layer 55.

[0033] In addition, n + type impurity diffusion regions NP1 and NP2 are provided in the P-type well region PW, and they are doped with, for example, phosphorus (P). n + The n-type impurity diffusion region NP1 and + the n-type impurity diffusion region NP2 are arranged at intervals along the Y direction. n + The n-type impurity diffusion regions NP1 and NP2 function as the source (source diffusion layer) and drain (drain diffusion layer) of the NMOS transistor TrN. n + The n-type impurity diffusion regions NP1 and NP2 are respectively connected to the contact plugs CS.

[0034] The contact plugs CS and C0 have a conductive layer 58 formed on the bottom surface and the side surface of the contact hole, and a conductive layer 59 buried in the contact hole in contact with the conductive layer 58. The conductive layer 58 functions as a barrier metal and can use a laminated structure of titanium (Ti) and titanium nitride (TiN). The conductive layer 59 can use, for example, tungsten (W).

[0035] The PMOS transistor TrP is not particularly limited and can adopt a general structure. For example, near the surface of the N-type well region NW, p +Impurity diffusion regions PP1 and PP2, and a gate insulating layer 120p of a gate electrode GCp is provided in a region between them. p + The impurity diffusion regions PP1 and PP2 are doped with, for example, boron (B). p + The impurity diffusion regions PP1 and PP2 function as a source (source diffusion layer) and a drain (drain diffusion layer) of a PMOS transistor TrP.

[0036] In addition, a boron (B)-doped polysilicon layer 180 is provided between the gate insulating layer 120p and a metal layer 150p. Further, an upper surface of the metal layer 150p is covered with an insulating layer 55. Side surfaces of the metal layer 150p are covered with an insulating layer 56p. The insulating layer 56p functions as a sidewall of the gate electrode GCp of the PMOS transistor (TrP). A part of the insulating layer 55 is open, and the gate electrode GCp is connected to a contact plug C0 through the opening of the insulating layer 55. p + The impurity diffusion regions PP1 and PP2 are respectively connected to contact plugs CS.

[0037] A conductor layer is connected to upper surfaces of the contact plugs CS and C0 ( Figure 4 not shown in the figure, see Figure 10 the symbol D0 in Figure 4 ). This conductor layer functions as a wiring between the PMOS transistor TrP and the NMOS transistor TrN shown in

[0038] and other transistors or external connection terminals. + The impurity diffusion regions NP1 and NP2 and p + The impurity diffusion regions PP1 and PP2 are respectively electrically connected to the conductor layer through the contact plugs CS. In addition, the NMOS transistor TrN and the PMOS transistor TrP are covered with an insulating layer 31.

[0039] The CMOSFET is manufactured as follows, for example. Refer to Figure 5 , Figure 6 and Figure 7 to describe the manufacturing steps of the CMOSFET. First, as shown in Figure 5 (a), a semiconductor substrate 110 is prepared, and then, as shown in Figure 5 (b), a gate insulating layer 120 is formed on one surface thereof. In addition, Figure 4 the P-type well region PW, the N-type well region NW, n + the impurity diffusion regions NP1 and NP2, p+ The illustrations of the impurity diffusion regions PP1 and PP2 are omitted.

[0040] As Figure 5 shown in (c), the first layer 131, the second layer 132, and the third layer 133 are sequentially formed on the gate insulating layer 120, thereby forming the stacked semiconductor layer 130. As Figure 5 shown in (d), an oxide film 160 is formed on the third layer 133. The oxide film 160 is formed, for example, by thermal oxidation.

[0041] Subsequently, as Figure 5 shown in (e), a termination layer 170 is formed. The termination layer 170 can use, for example, silicon nitride (SiN). As Figure 5 shown in (f), the side where the PMOS transistor TrP will be formed later is removed. As a removal method, for example, RIE can be used.

[0042] As Figure 6 shown in (g), the gate insulating layer 120p of the PMOS transistor TrP is formed, and then a boron (B)-doped polysilicon layer 180 is formed on the gate insulating layer 120p. The B-doped polysilicon layer 180 is formed not only on the gate insulating layer 120p on the side where the PMOS transistor TrP will be formed later (PMOS transistor TrP side), but also on the termination layer 170 on the side where the NMOS transistor TrN will be provided later (NMOS transistor TrN side). As Figure 6 shown in (h), a termination layer 190 is formed on the B-doped polysilicon layer 180. For example, the termination layer 190 can use SiN.

[0043] As Figure 6 shown in (i), the B-doped polysilicon layer 180 on the NMOS transistor TrN side is removed by RIE. As Figure 6 shown in (j), the STI trench 200 that separates the NMOS transistor TrN and the PMOS transistor TrP is formed.

[0044] As Figure 7 shown in (k), a filler 201 is filled into the STI trench 200. The filler 201 can use, for example, SiO. After filling the filler 201 into the STI trench 200, a part of the termination layer 170, a part of the termination layer 190, and a part of the filler 201 are removed. As a removal method, CMP can be used. As Figure 7 shown in (l), the termination layer 170 on the NMOS transistor TrN side and the termination layer 190 on the PMOS transistor TrP side are removed. As a removal method, wet etching can be used.

[0045] As Figure 7As shown in (m), the upper portions of the oxide film 160 of the NMOS transistor TrN and the third layer 133 of the three-layer polycrystalline semiconductor layer 130 are removed. As a removal method, wet etching can be used. As Figure 7 As shown in (n), a TSI layer 140 is formed on the third layer 133 on the NMOS transistor TrN side and the boron-doped polycrystalline silicon layer 180 on the PMOS transistor TrP side. As Figure 7 As shown in (o), a metal layer 150 is formed on the TSI layer 140.

[0046] Steps required for forming the NMOS transistor TrN side and the PMOS transistor TrP side are added, such as dividing the metal layer 150 between the NMOS transistor TrN side and the PMOS transistor TrP side, etc., to fabricate a CMOSFET, but the related diagrams are omitted.

[0047] In step (e) of the manufacturing steps, if the third layer 133 is not formed and a termination (SiN) layer 170 is directly formed on the second layer 132, abnormal oxidation may occur at the interface between the second layer 132 and the termination layer 170 when heated in subsequent steps. This abnormal oxidation is considered to be caused by carbon (C) contained in the second layer 132 capturing phosphorus (P) doped in the first layer 131, and etching residues, etc. will be generated when etching (step (l)) is performed after forming the STI (fill 201). These etching residues may cause an increase in the leakage current of the transistor. In addition, the etching residues may cause a short circuit between the gate electrodes 100 (GCn), etc., thus becoming a main factor for reducing the manufacturing yield.

[0048] Therefore, in the gate electrode 100 of the embodiment, a third layer 133 having a lower P concentration than the first layer 131 is provided on the second layer 132. Since the third layer 133 uses polycrystalline silicon doped with a low concentration of P or undoped P, etc., segregation of P in the thermal step can be suppressed. As a result, generation of etching residues can be prevented. As a result, generation of defects caused by the etching residues can be suppressed, and thus the performance of the transistor can be improved. Furthermore, by reducing the etching residues, the yield of the transistor can also be improved.

[0049] (Third Embodiment / Semiconductor Memory Device)

[0050] The CMOSFET of the semiconductor device of the second embodiment can be used, for example, in a control circuit of a three-dimensional stacked non-volatile memory device in which memory cell transistors are three-dimensionally stacked on a semiconductor substrate. However, the use of the semiconductor device of the second embodiment is not limited to this, and it can be used in various semiconductor devices. Regarding the semiconductor memory device of the third embodiment, refer to Figure 8 、 Figure 9 and Figure 10To illustrate a three-dimensional stacked NAND flash memory.

[0051] Figure 8 FIG. is a block diagram showing the overall configuration of a three-dimensional stacked NAND flash memory according to the third embodiment. As Figure 8 shown, the semiconductor memory device 1 is controlled by an external memory controller 2, for example. The semiconductor memory device 1 includes a memory cell array 10, an instruction register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0052] The memory cell array 10 includes a plurality of blocks BLK0 to BLK(L−1) (L is an integer of 2 or more). A block BLK is an aggregate of a plurality of memory cell transistors (hereinafter sometimes simply referred to as "memory cells") that non-volatilely store data, and is used as an erasure unit of data, for example. A plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. Each memory cell transistor is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described below.

[0053] The instruction register 11 stores an instruction CMD received by the semiconductor memory device 1 from the memory controller 2. The instruction CMD includes commands for causing the sequencer 13 to perform read operations, write operations, erase operations, etc., for example. The address register 12 stores address information ADD received by the semiconductor memory device 1 from the memory controller 2. The address information ADD includes, for example, a block address BA, a page address PA, and a column address CA. For example, the block address BA, the page address PA, and the column address CA are used for selecting a block BLK, a word line, and a bit line, respectively.

[0054] The sequencer 13 controls the overall operation of the semiconductor memory device 1. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, the sense amplifier module 16, etc. based on the instruction CMD stored in the instruction register 11, thereby performing read operations, write operations, erase operations, etc.

[0055] The driver module 14 generates voltages to be used in read operations, write operations, erase operations, etc. Then, the driver module 14 applies the generated voltages to signal lines corresponding to selected word lines based on the page address PA stored in the address register 12, for example.

[0056] The row decoder module 15 selects one block BLK corresponding to the inside of the memory cell array 10 based on the block address BA stored in the address register 12. Then, the row decoder module 15 transmits, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0057] In a write operation, the sense amplifier module 16 applies a desired voltage to each bit line according to the write data DAT received from the memory controller 2. Further, in a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line, and transmits the determination result as the read data DAT to the memory controller 2.

[0058] The communication between the semiconductor memory device 1 and the memory controller 2 supports, for example, the NAND interface. For example, in the communication between the semiconductor memory device 1 and the memory controller 2, an instruction latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, a ready / busy signal RBn, and an input / output signal I / O are used.

[0059] The instruction latch enable signal CLE is a signal indicating that the input / output signal I / O received by the semiconductor memory device 1 is an instruction CMD. The address latch enable signal ALE is a signal indicating that the signal I / O received by the semiconductor memory device 1 is address information ADD. The write enable signal WEn is a signal that commands the semiconductor memory device 1 to input the input / output signal I / O. The read enable signal REn is a signal that commands the semiconductor memory device 1 to output the input / output signal I / O.

[0060] The ready / busy signal RBn is a signal that notifies the memory controller 2 whether the semiconductor memory device 1 is in a ready state where it can accept commands from the memory controller 2 or in a busy state where it cannot accept commands.

[0061] The input / output signal I / O is, for example, an 8-bit wide signal and can include an instruction CMD, address information ADD, data DAT, and the like.

[0062] The semiconductor memory device 1 and the memory controller 2 described above can also be combined to form one semiconductor device. As such a semiconductor device, for example, a memory card such as an SD card or an SSD (Solid State Drive) can be cited.

[0063] Next, Figure 9 is used to explain the circuit configuration of the memory cell array 10. Figure 9 The example of represents block BLK0, and the circuit configurations of other blocks BLK are the same. As Figure 9 shown, the block BLK includes, for example, four string units SU0 to SU3. Each string unit SU includes a plurality of NAND strings NS.

[0064] A plurality of NAND strings NS are respectively associated with bit lines BL0 to BL(N−1) (N is an integer of 2 or more). Each NAND string NS includes, for example, memory cell transistors MC0 to MC7, and selection transistors ST1 and ST2.

[0065] The memory cell transistor MC includes a control gate and a charge storage layer, and stores data non-volatilely. Hereinafter, when it is not limited to which one of the memory cell transistors MC0 to MC7, it is denoted as the memory cell transistor MC. In addition, the memory cell transistor MC may be a MONOS type using an insulating film for the charge storage layer, or an FG type using a conductor layer for the charge storage layer. Hereinafter, in the embodiment, the MONOS type will be described as an example.

[0066] The selection transistor ST1 is used to select the string unit SU during various operations. In each NAND string NS, the drain of the selection transistor ST1 is connected to the associated bit line BL. The source of the selection transistor ST1 is connected to one end of the serially connected memory cell transistors MC0 to MC7. The other ends of the serially connected memory cell transistors MC0 to MC7 are connected to the drain of the selection transistor ST2.

[0067] In the same block BLK, the sources of the selection transistors ST2 are commonly connected to the source line SL. The gates of the selection transistors ST1 in the string units SU0 to SU3 are respectively commonly connected to the selection gate lines SGD0 to SGD3. The control gates of the memory cell transistors MC0 to MC7 are respectively commonly connected to the word lines WL0 to WL7. The gates of the selection transistors ST2 are commonly connected to the selection gate line SGS.

[0068] In the circuit configuration of the memory cell array 10 described above, a plurality of NAND strings NS assigned the same column address CA are commonly connected to the same bit line BL among a plurality of blocks BLK. The source line SL is commonly connected among a plurality of blocks BLK.

[0069] In addition, the circuit configuration of the memory cell array 10 included in the semiconductor memory device 1 of the embodiment is not limited to the configuration described above. For example, the number of memory cell transistors MC, and selection transistors ST1 and ST2 included in each NAND string NS can be designed to be any number respectively. The number of string units SU included in each block BLK can be designed to be any number.

[0070] Next, Figure 10 , the cross-sectional structure of the memory cell array 10 will be described. As Figure 10As shown, an insulating layer 31 is formed on a semiconductor substrate 100. The insulating layer 31 can be made of, for example, silicon oxide (SiO). A circuit region UA is provided within the insulating layer 31, and a memory cell array 10 is provided on the insulating layer 31. Circuits for use by, for example, a sense amplifier module 16 are formed in the circuit region UA.

[0071] First, the configuration of the memory cell array 10 will be described. A conductor layer 32 that functions as a source line SL is provided on the insulating layer 31. For example, the conductor layer 32 is formed in a plate shape that extends along an XY plane substantially parallel to the semiconductor substrate 100. The conductor layer 32 is formed using a conductive material, and the conductive material includes, for example, a metal material or a semiconductor material.

[0072] Eleven insulating layers 33 and ten conductor layers 34 are alternately stacked on the conductor layer 32. The insulating layer 33 can be made of, for example, SiO. The ten conductor layers 34 function as a select gate line SGS, word lines WL0 to WL7, and a select gate line SGD in order from the bottom. For example, the conductor layer 34 is formed in a plate shape that extends along the X direction. The conductor layer 34 is formed using a conductive material, and the conductive material includes, for example, a metal material.

[0073] A plurality of memory pillars MP are provided that penetrate (pass through) the ten conductor layers 34 and reach the conductor layer 32 at the bottom surface. The memory pillars MP extend along a Z direction that is substantially perpendicular to the semiconductor substrate 100 and intersects the X and Y directions. One memory pillar MP corresponds to one NAND string NS. The memory pillar MP includes a block insulating film 35, a charge storage layer 36, a tunnel insulating film 37, a semiconductor layer 38, a core layer 39, and an overlying layer 40.

[0074] More specifically, holes corresponding to the memory pillars MP are formed in such a way as to penetrate the ten conductor layers 34 and reach the conductor layer 32 at the bottom surface. The block insulating film 35, the charge storage layer 36, and the tunnel insulating film 37 are sequentially stacked on the side surfaces of the holes. Moreover, the semiconductor layer 38 is formed in such a way that its side surface is in contact with the tunnel insulating film 37 and its bottom surface is in contact with the conductor layer 32. The semiconductor layer 38 is a region where the channels of the memory cell transistors MC and the select transistors ST1 and ST2 are formed. Thus, the semiconductor layer 38 functions as a signal line that connects the current paths of the select transistor ST2, the memory cell transistors MC0 to MC7, and the select transistor ST1. A core layer 39 is provided within the semiconductor layer 38. Moreover, an overlying layer 40 whose side surface is in contact with the tunnel insulating film 37 is formed on the semiconductor layer 38 and the core layer 39.

[0075] The block insulating film 35, the tunnel insulating film 37, and the core layer 39 can be made of SiO, for example. The charge storage layer 36 can be made of silicon nitride (SiN), for example. The semiconductor layer 38 and the overlying layer 40 can be made of polysilicon, for example.

[0076] The storage pillar MP is combined with eight conductor layers 34 that respectively function as word lines WL0 to WL7, and functions as storage unit transistors MC0 to MC7. Similarly, the storage pillar MP is combined with two conductor layers 34 that respectively function as the selection gate lines SGD and SGS, and functions as selection transistors ST1 and ST2.

[0077] A contact plug CP is formed on the overlying layer 40. A conductor layer (not shown) that functions as a bit line BL is formed on the contact plug CP. The contact plug CP is formed using a conductive material, and the conductive material can be a metal material, for example.

[0078] In addition, in Figure 10 this example, three storage pillars MP are arranged along the Y direction, but actually the storage pillars MP can be arranged arbitrarily.

[0079] The circuit region UA includes a semiconductor device having the PMOS transistor TrP and the NMOS transistor TrN. As described above, it is possible to suppress the generation of defects caused by etching residues.

[0080] In addition, the PMOS transistor TrP and the NMOS transistor TrN can also be used for, for example, the instruction register 11, the address register 12, the sequencer 13, the driver module 14, the row decoder module 15, and the sense amplifier module 16.

[0081] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalents.

[0082] [Description of Reference Numerals]

[0083] 1 Semiconductor memory device

[0084] 2 Storage controller

[0085] 10 Storage cell array

[0086] 11 Instruction register

[0087] 12 Address register

[0088] 13 Sequencer

[0089] 14 Driver Module

[0090] 15 Row Decoder Module

[0091] 16 Sense Amplifier Module

[0092] 58,59 Conductor Layers

[0093] 35 Block Insulating Film

[0094] 36 Charge Storage Layer

[0095] 37 Tunnel Insulating Film

[0096] 100 Gate Electrode

[0097] 110 Semiconductor Substrate

[0098] 120,120p Gate Insulating Layer

[0099] 130 3 - layer Polycrystalline Semiconductor Layer

[0100] 131 Layer 1

[0101] 132 Layer 2

[0102] 133 Layer 3

[0103] 140 TSI Layer

[0104] 150,150p Metal Layer

[0105] 160 Oxide Film

Claims

1. A semiconductor device, comprising: A substrate; A gate insulating layer on the substrate; A stacked semiconductor layer having: a first layer formed on the gate insulating layer and containing polycrystalline semiconductor doped with phosphorus; a second layer formed on the first layer and containing polycrystalline semiconductor doped with carbon; and a third layer formed on the second layer and containing polycrystalline semiconductor doped with phosphorus or undoped with phosphorus; and A metal layer on or above the stacked semiconductor layer; and The phosphorus content of the third layer is less than that of the first layer, or the third layer does not contain phosphorus.

2. The semiconductor device according to claim 1, wherein There is also an oxide layer between the third layer and the metal layer.

3. The semiconductor device according to claim 2, wherein The metal layer is a laminate having a tungsten silicide layer and a titanium nitride layer sequentially arranged from the side of the stacked semiconductor layer.

4. The semiconductor device according to claim 2, wherein The metal layer is formed on the third layer, and The metal layer is a laminate having a titanium layer, a titanium nitride layer, and a tungsten layer sequentially arranged from the side of the stacked semiconductor layer.

5. The semiconductor device according to claim 1, wherein The semiconductor device further has an NMOS transistor and a PMOS transistor, The substrate further has a P-type well and an N-type well, The NMOS transistor is formed on the P-type well and includes the gate insulating layer, the stacked semiconductor layer, and the metal layer, The PMOS transistor is formed on the N-type well.

6. The semiconductor device according to claim 5, wherein The P-type well has a first N-type diffusion layer and a second N-type diffusion layer, The first N-type diffusion layer and the second N-type diffusion layer are spaced apart from each other along the surface of the substrate, The gate insulating layer is formed between the first N-type diffusion layer and the second N-type diffusion layer.

7. The semiconductor device according to claim 5, wherein The substrate includes a separation portion that electrically separates the P-type well and the N-type well.

8. The semiconductor device according to claim 7, wherein The side surfaces of the gate insulating layer, the stacked semiconductor layer, and the metal layer are each covered with an insulating layer.

9. A storage device, having: One or more memory cell transistors; and Peripheral circuits including NMOS transistors and capable of controlling the memory cell transistors; The NMOS transistor includes: A gate insulating layer formed on a substrate; A stacked semiconductor layer having: a first layer formed on the gate insulating layer and containing polycrystalline semiconductor doped with phosphorus; a second layer formed on the first layer and containing polycrystalline semiconductor doped with carbon; and a third layer formed on the second layer and containing polycrystalline semiconductor doped with phosphorus or undoped with phosphorus; and A metal layer on or above the stacked semiconductor layer; and The phosphorus content of the third layer is less than that of the first layer, or it does not contain phosphorus.

10. The storage device according to claim 9, wherein The peripheral circuits further include PMOS transistors, The substrate includes a P-type well and an N-type well, The NMOS transistor is formed on the P-type well region. The PMOS transistor is formed on the N-type well region.

11. The storage device according to claim 10, wherein the P-type well region and the N-type well region are electrically separated from each other by a separation portion.

12. The storage device according to claim 11, wherein the NMOS transistor and the PMOS transistor are adjacent to each other across the separation portion.

13. The storage device according to claim 10, wherein the P-type well region includes a first N-type diffusion layer and a second N-type diffusion layer separated from each other along the surface of the substrate, and the gate insulating layer is located on the surface between the first N-type diffusion layer and the second N-type diffusion layer.

14. The storage device according to claim 10, wherein the storage device further includes a wiring that extends along a first direction parallel to the substrate and is electrically connected to one or more of the storage unit transistors, and the NMOS transistor and the PMOS transistor are arranged along the first direction.

15. The storage device according to claim 9, wherein the storage device further includes a storage column that extends along a second direction in which the first layer, the second layer, and the third layer are stacked, and the storage column is used as a part of the storage unit transistor.

16. A method for manufacturing a transistor, wherein a gate insulating layer is formed on a substrate; a stacked semiconductor layer including a first layer, a second layer, and a third layer is formed. The first layer is formed on the gate insulating layer and includes polycrystalline semiconductor doped with phosphorus. The second layer is formed on the first layer and includes polycrystalline semiconductor doped with carbon. The third layer is formed on the second layer and includes polycrystalline semiconductor doped with phosphorus or undoped with phosphorus; a metal layer is formed on or above the third layer; and the phosphorus content of the third layer is less than that of the first layer or does not contain phosphorus.

17. The method for manufacturing a transistor according to claim 16, wherein after forming the stacked semiconductor layer and before forming the metal layer, an oxide film is provided on the third layer, a groove is formed through the gate insulating layer, the stacked semiconductor layer, and the oxide film, the oxide film is removed.

18. The method for manufacturing a transistor according to claim 17, wherein the substrate includes a P-type well region and an N-type well region, after providing the oxide film, all layers formed on or above the N-type well region are removed, and before forming the metal layer, another gate insulating layer and a polycrystalline semiconductor layer are provided on the N-type well region.

19. The method for manufacturing a transistor according to claim 16, wherein the metal layer is formed directly above the third layer, and the metal layer is a laminate having a titanium layer, a titanium nitride layer, and a tungsten layer sequentially arranged from the side of the stacked semiconductor layer.

20. The method for manufacturing a transistor according to claim 16, wherein before forming the metal layer, an oxide layer is formed on the third layer, and the metal layer includes a laminate having a titanium layer, a titanium nitride layer, and a tungsten layer sequentially arranged from the side of the stacked semiconductor layer.

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