Semiconductor device

Abstract

A semiconductor device of an embodiment includes a first electrode, a second electrode, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a first active region of the first conductivity type, and a third electrode. The first semiconductor layer is provided between the first electrode and the second electrode. The second semiconductor layer is provided over the first semiconductor layer. The first active region is adjacent to the second semiconductor layer in a second direction. The first active region has a first upper portion and a second lower portion. An average value of a width of the first lower portion in the second direction is larger than an average value of a width of the first upper portion in the second direction. The third semiconductor layer is electrically connected to the second electrode. The third electrode is provided between the first active region with an insulating film interposed.

Description

[0001] Related Application

[0002] This application takes priority from Japanese Patent Application No. 2020-157903 (Filing date: September 18, 2020). This application incorporates the entire contents of the base application by reference thereto. TECHNICAL FIELD

[0003] Embodiments of the present application relate to a semiconductor device. BACKGROUND

[0004] A MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) having a semiconductor portion including silicon carbide (SiC) sometimes has a Schottky diode (SBD) arranged in parallel in order to suppress the operation of a parasitic diode. In such a semiconductor device, further improvement in reliability is also demanded. SUMMARY

[0005] Embodiments of the present application provide a semiconductor device capable of improving reliability.

[0006] The semiconductor device of the embodiment has a first electrode, a second electrode, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a first active region of the first conductivity type, and a third electrode. The first semiconductor layer is provided between the first electrode and the second electrode. The second semiconductor layer is provided between the first semiconductor layer and the second electrode. The first active region is adjacent to the second semiconductor layer in a second direction orthogonal to a first direction from the first electrode toward the second electrode. The first active region has a first upper portion and a first lower portion. The first upper portion is located between the first semiconductor layer and the second electrode. The first lower portion is located between the first semiconductor layer and the first upper portion. An average value of a width of the first lower portion in the second direction is larger than an average value of a width of the first upper portion in the second direction. The third semiconductor layer is provided between the second semiconductor layer and the second electrode. The third semiconductor layer is electrically connected to the second electrode. The third electrode is provided between the first active region, the second semiconductor layer, and the third semiconductor layer and the second electrode through an insulating film and an insulating layer.

[0007] A semiconductor device of an embodiment has a first electrode, a second electrode, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and an active region of the first conductivity type. The first semiconductor layer is provided between the first electrode and the second electrode. The second semiconductor layer is provided between the first semiconductor layer and the second electrode. The active region is adjacent to the second semiconductor layer in a second direction orthogonal to a first direction from the first electrode toward the second electrode. The active region has an upper portion and a lower portion. The upper portion is provided between the first semiconductor layer and the second electrode. The upper portion is in contact with the second electrode. The lower portion is between the first semiconductor layer and the upper portion. An average value of a width of the lower portion in the second direction is larger than an average value of a width of the upper portion in the second direction. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a plan view that shows a semiconductor device of a first embodiment.

[0009] Figure 2 is an enlarged plan view that shows Figure 1 a region A of

[0010] Figure 3 is a cross-sectional view that shows B-B' line of Figure 2

[0011] Figure 4 is an enlarged cross-sectional view that shows a MOSFET of a semiconductor device of a first modification of the first embodiment.

[0012] Figure 5 is an enlarged cross-sectional view that shows a MOSFET of a semiconductor device of a second modification of the first embodiment.

[0013] Figure 6 is an enlarged cross-sectional view that shows a MOSFET of a semiconductor device of a third modification of the first embodiment. DETAILED DESCRIPTION

[0014] Hereinafter, each embodiment will be described with reference to the drawings.

[0015] In addition, the drawings are schematic illustrations, and the relationship between the thickness and the width of each portion, the ratio of the sizes between portions, and the like are not necessarily consistent with reality. Furthermore, in the case of showing the same portions, there are cases in which the sizes and the ratios of the portions are different from each other depending on the drawings. Also, in the present specification and each drawing, the same reference numerals are applied to the same elements as those in the drawings already described, and detailed description is appropriately omitted.

[0016] (First Embodiment)

[0017] ​Figure 1 is a plan view showing the semiconductor device of the present embodiment. Figure 2 is a plan view showing Figure 1 is an enlarged plan view of the region A of Figure 3 is Figure 2 is a cross-sectional view of the B-B' line shown in Figures 1-3 The protective film and the wiring layer are omitted.

[0018] As shown in Figures 1-3 , the semiconductor device 100 of the present embodiment is used for controlling current, for example, a power semiconductor device to which a voltage of about 3.3 kV is applied. As shown in Figure 1 , Figure 3 , a first electrode 21 is provided on the lower surface of the semiconductor device 100. A second electrode 22 and a pad 23a are provided on the upper surface of the cell region of the semiconductor device 100. The second electrode 22 is larger than the gate pad 23a. A terminal insulating film 60 is provided on the upper surface of the terminal region of the semiconductor device 100. As shown in Figure 2 , the semiconductor device 100 is alternately arranged with a plurality of MOSFETs 100m and a plurality of SBDs 100s.

[0019] As shown in Figure 3 , the MOSFET 100m has a gate control portion 100ml and a parasitic diode portion 100m2. The gate control portion 100ml causes current to flow into an external device connected thereto and controls the amount of current. The parasitic diode portion 100m2 is a body diode formed on both sides of the gate control portion 100ml and causes current to flow from a source electrode to a drain electrode. The SBD 100s is a diode constituted by the source electrode and the drain electrode of the MOSFET 100m and the semiconductor portion 10 therebetween.

[0020] The semiconductor device 100 has a semiconductor portion 10, a first electrode 21, a second electrode 22, a third electrode 23, an insulating film 31, a contact 41, and insulating layers 51 and 52.

[0021] The first electrode 21 is, for example, a drain electrode. The first electrode 21 is substantially plate-shaped and formed on, for example, the entire lower surface of the semiconductor device 100. The first electrode 21 contains, for example, aluminum (Al).

[0022] The semiconductor portion 10 contains, for example, silicon carbide (SiC). The semiconductor portion 10 has an n + -type buffer layer 18, an n - -type drift layer 11 (first semiconductor layer), a p-type base layer 12 (second semiconductor layer), an n + -type source layer 13 (third semiconductor layer), a p + -type contact layer 14 (fourth semiconductor layer), and an n-type semiconductor layer 15. In addition, "n+ "Type" indicates a higher carrier concentration than "n-type". - "Type" indicates that the carrier concentration is lower than that of "n-type". The same applies to p-type.

[0023] n - Type drift layer 11 is set at n + Above type 18 buffer layer. - The n-type drift layer 11 is composed of n-type semiconductors, but the impurity concentration varies locally. For example... Figure 3 As shown, n - The drift layer 11 has a first active region D and a second active region E. n - The portion of the drift layer 11 excluding the first active region D and the second active region E is designated as the first region U. The first region U, for example, is composed of n... - It is composed of semiconductors of various types.

[0024] The first active region D is the region in which current flows in the gate control section 100m1. The second active region E is the region in which current flows in the SBD 100s. The first active region D and the second active region E are, for example, made of n-type semiconductors and separated from each other by a p-type substrate layer 12.

[0025] The first region U is located beneath the first active region D, the second active region E, and the p-type substrate 12. For example... Figure 3 As shown, the upper surface Ub of the first region U is in contact with the lower surface 12a of the p-type substrate 12. The boundary surface Bd, which serves as the boundary between the first active region D and the first region U, is the lower surface of the first active region D. The boundary surface Bd is in contact with the end edge 12ad on the first active region D side of the lower surface 12a of the p-type substrate 12. The boundary surface Bd is, for example, the region located between the two end edges 12ad on both sides of the first active region D.

[0026] Similarly, the boundary surface Be between the second active region E and the first region U is the lower surface of the second active region E. The boundary surface Be is in contact with the end edge 12ae on the second active region E side of the lower surface 12a of the p-type substrate 12. For example, the boundary surface Be is the region located between the two end edges 12ae on both sides of the second active region E. For example, the boundary surface Bd and the boundary surface Be form a flat surface that is continuous with the lower surface 12a of the p-type substrate 12.

[0027] like Figure 3 As shown, the p-type substrate 12 is disposed in the n-type MOSFET 100m and SBD 100s. - Above the type drift layer 11, located at n - Between the first active region D and the second active region E of the drift layer 11.

[0028] n+ Source layer 13 is the source layer of the MOSFET 100m. + The source layer 13 is disposed on top of the p-type substrate 12, and is separated from the n-type substrate 12 by the p-type substrate 12. - The first active region D and the second active region E of the drift layer 11 are separated.

[0029] p + A p-type contact layer 14 is disposed on the p-type base layer 12 in the parasitic diode section 100m2. + Type contact layer 14 is the contact layer of the parasitic diode section 100m2.

[0030] Contact 41 is, for example, an ohmic contact in the parasitic diode section 100m2. Contact 41 is provided at p + The contact 41 is formed, for example, by a self-aligned silicide, containing, for example, nickel (Ni) and silicon (Si).

[0031] like Figure 1 , Figure 3 As shown, the second electrode 22 is, for example, a source electrode. The second electrode 22 is disposed on the semiconductor portion 10. The second electrode 22 is connected to the p-type substrate layer 12 and the n-type substrate layer 10. + Source layer 13. Furthermore, the second electrode 22 and n - The second active region E of the drift layer 11 is connected to the upper surface E10. The second electrode 22 is connected to the contact 41. The second electrode 22 contains, for example, aluminum.

[0032] The insulating film 31 is, for example, a gate insulating film. The insulating film 31 and n - p-type drift layer 11 (first active region D), p-type basal layer 12, and n ... + The upper surface of the source layer 13 is in contact with it. Specifically, the insulating film 31 is in contact with the upper surface D10 of the first active region D.

[0033] The third electrode 23 is, for example, a gate electrode. The third electrode 23 is disposed on the insulating film 31. The third electrode 23 is separated from the first active region D, the p-type substrate 12, and the n-type substrate 12 by the insulating film 31. + Type source and electrode layers 13 are opposite. For example... Figure 3 As shown, the third electrode 23 is separated from the second electrode 22 by an insulating layer 51. The third electrode 23 is electrically connected to the pad 23a.

[0034] The shape of the first active region D is described in detail below.

[0035] like Figure 2 , Figure 3As shown, a direction in which the MOSFET 100m extends in plan view is set as a direction Y, a direction orthogonal to the direction Y and from the first electrode 21 toward the second electrode 22 is set as a direction Z, and a direction orthogonal to the direction Y and the direction Z is set as a direction X. Hereinafter, the width refers to the length along the direction X.

[0036] As shown, the cross-sectional shape of the first active region D orthogonal to the direction Y is substantially trapezoidal. The first active region D has an upper surface D10 and a boundary surface Bd as a lower surface. In the first active region D, the width of the upper surface D10 as the upper side of the trapezoid is narrower than the width of the boundary surface Bd as the lower side of the trapezoid. Figure 3 The first active region D is set as follows, and the shape of the first active region D is further described.

[0037] As shown, the first lower portion D20 and the first upper portion D30 of the first active region D in the case where the first active region D is divided into two equal parts upward and downward are set. As shown, first, a line, that is, a bisector DL passing through a position bisecting the length of the direction Z of the first active region D and parallel to the direction X is set. The first lower portion D20 is a portion below the bisector DL in the first active region D, and the first upper portion D30 is a portion above the bisector DL in the first active region D. Further, an internal boundary surface D40 dividing the first lower portion D20 and the first upper portion D30 is a surface including the bisector DL in the first active region D. The width of the internal boundary surface D40 is the same as, for example, the length of the lower side of the first upper portion D30, and the same as, for example, the length of the upper side of the first lower portion D20.

[0038] Figure 3 Using the above setting, the following can be confirmed. Figure 3 The width of the upper surface D10 of the first active region D is narrower than the width of the boundary surface Bd. Further, in the first active region D, the average of the widths of the first upper portion D30 is smaller than the average of the widths of the first lower portion D20. The average of the widths is, for example, the sum of the widths of the portions or the configurations measured one by one at positions uniformly dispersed in the Z direction divided by the number of the measurement positions.

[0039] Figure 3 The width of the upper surface D10 is smaller than the average of the widths of the first upper portion D30. Further, the width of the upper surface D10 is narrower than the width of the internal boundary surface D40.

[0040] The width of the boundary surface Bd is greater than the average of the widths of the first lower portion D20. Further, the width of the boundary surface Bd is greater than the width of the internal boundary surface D40.

[0041] The width of the upper surface D10 is smaller than the average of the widths of the first upper portion D30. Further, the width of the upper surface D10 is narrower than the width of the internal boundary surface D40.

[0042] The width of the boundary surface Bd is greater than the average of the widths of the first lower portion D20. Further, the width of the boundary surface Bd is greater than the width of the internal boundary surface D40. ​​

[0043] As Figure 3 illustrated, the shape of the second active region E in the present embodiment is substantially the same as that of the first active region D. The cross-sectional shape of the second active region E orthogonal to the direction Y is substantially trapezoidal. The second active region E has an upper surface E10 and a boundary surface Be as a lower surface. In the second active region E, the width of the upper surface E10 as the upper side of the trapezoid is narrower than the width of the boundary surface Be as the lower side of the trapezoid.

[0044] Further, the second active region E is also described in the same manner as the first active region D. The second active region R is provided with a bisector EL, a second lower portion E20 and a second upper portion E30, and an internal boundary surface E40.

[0045] According to the above setting, the following cases can be confirmed.

[0046] In the second active region E, the width of the upper surface E10 is narrower than the width of the boundary surface Be. Further, in the second active region E, the average of the width of the second upper portion E30 is smaller than the average of the width of the second lower portion E20. Further, the width of the upper surface E10 of the second active region E is smaller than the average of the width of the second upper portion E30 and smaller than the average of the width of the internal boundary surface E40. Moreover, the width of the boundary surface Be is larger than the average of the width of the second lower portion E20 and larger than the average of the width of the internal boundary surface E40.

[0047] In the semiconductor device 100 of the present embodiment, the first active region D and the second active region E are substantially the same shape, but can be different shapes. Further, the cross-sectional shape of the first active region D and the second active region E can not be substantially trapezoidal. For example, the cross-sectional shape of one of the first active region D and the second active region E can be a shape using a rectangle or an oblong. In at least one of the first active region D and the second active region E, as long as the shape of the XY cross section is such that the average of the width of the upper portion is smaller than the average of the width of the lower portion. For example, it is preferable that the width of the upper surface D10, E10 be narrower than the width of the boundary surface Bd, Be, and the width of the internal boundary surface D40, E40 dividing the upper portion D30, E30 and the lower portion D20, E20 be wider than the upper surface D10, E10 and narrower than the boundary surface Bd, Be.

[0048] Furthermore, in this embodiment, the changes in the width of the active regions D and E are evaluated based on the average width of the upper part D30, E30 and the lower part D20, E20 when the active regions D and E are divided into upper and lower equal parts by the bisecting line DL, and the width of the internal boundary surface D40. However, it is not limited to this. The changes in the width of the active regions can also be evaluated based on the average width of the part of the active region D up to one-third of its height being designated as the upper part and the rest being designated as the lower part, and its internal boundary surface.

[0049] like Figure 3 As shown, in this embodiment, the first active region D and the second active region E are formed into a roughly trapezoidal shape through a multi-stage process such as multi-step epitaxial growth, ion implantation, and etching, but are not limited to this. Furthermore, the lateral boundary surfaces Pd and Pe of the first active region D and the p-type substrate 12 may not be roughly planar. The lateral boundary surfaces Pd and Pe may also be multi-step.

[0050] The operation and effects of the semiconductor device 100 of this embodiment will be described below.

[0051] In this embodiment, the semiconductor device 100 has SBD 100s arranged in parallel with MOSFET 100m.

[0052] First, during forward operation, a relatively positive potential is applied to the second electrode 22, and a relatively negative potential is applied to the first electrode 21. Since the operating voltage of the SBD 100s is lower than that of the MOSFET 100m, current preferentially flows into the SBD 100s first, and no current flows in the MOSFET 100m. In the SBD 100s, electrons flow from the first electrode 21 through the first region U and the second active region E to the second electrode 22. As a result, the operation of the parasitic diode section 100m2 is suppressed to a predetermined voltage. During this period, hole injection generated by the parasitic diode section 100m2 is suppressed, and the bipolar operation of electron and hole flow in the MOSFET 100m is suppressed. As a result, the semiconductor device 100 can suppress the expansion of crystal defects in the silicon carbide-containing semiconductor section 10 and suppress the deterioration of device characteristics such as the forward voltage and leakage characteristics between the MOSFET 100m and the drain-source voltage.

[0053] In the off state of the gate control section 100m1 during reverse operation, the second electrode 22 is applied with a relatively negative potential, the first electrode 21 is applied with a relatively positive potential, and the third electrode 23 is applied with a relatively negative potential. In the off state, the electric field strength of the insulating film 31 increases. Figure 3As shown, in detail, the insulating film 31 becomes the largest electric field in the center. In contrast, by narrowing the width of the upper surface D10 of the first active region D, the electric field strength of the insulating film 31 can be moderated, thereby suppressing insulation breakdown. Further, the width of the upper surface D10 of the first active region D is made narrower than the width of the boundary surface Bd, and the p-type base layer 12 is inclined to the lateral boundary surface Pd of the first active region D. Thus, the depletion layer in the first active region D can be inclined similarly to the lateral boundary surface Pd, and the depletion layer can be gradually connected. Thus, the abrupt change in the static capacitance between the third electrode 23 and the first electrode 21 of the MOSFET 100m is suppressed, and the generation of noise at the time of switching is suppressed.

[0054] In the on state of the gate control portion 100ml at the time of reverse operation, the second electrode 22 is applied with a relatively negative potential, the first electrode 21 is applied with a relatively positive potential, and the third electrode 23 is applied with a relatively positive potential. Thus, as shown in FIG. 6, in the p-type base layer 12, the region directly below the third electrode 23 and between the n-type source layer 13 and the first active region D forms a channel. The electrons supplied from the n-type source layer 13 flow into the first electrode 21 through the channel. At this time, although the channel length is lengthened in the portion in which the upper surface D10 of the first active region D is narrowed, the boundary surface Bd as the lower surface is widened, and the width of the current path is widened, thereby suppressing the rise in on-resistance. Figure 4 + As shown, in the p-type base layer 12, the region directly below the third electrode 23 and between the n + The electrons supplied from the n-type source layer 13 flow into the first electrode 21 through the channel. At this time, although the channel length is lengthened in the portion in which the upper surface D10 of the first active region D is narrowed, the boundary surface Bd as the lower surface is widened, and the width of the current path is widened, thereby suppressing the rise in on-resistance.

[0055] It is assumed that, in the case where the width of the first active region D is substantially uniform, the suppression of the electric field strength of the insulating film due to the narrowing of the width and the suppression of the on-resistance due to the increase in the width are in a so-called trade-off relationship, but the semiconductor device 100 of the present embodiment solves both problems by narrowing the upper surface D10 of the first active region D and expanding the boundary surface Bd.

[0056] In the second active region E of the SBD 100s, the upper surface E10 is narrowed and the boundary surface Be as the lower surface is expanded. Thus, in the SBD 100s, since the junction surface of the second electrode 22 and the second active region E is narrowed, the leakage current is reduced, and the operating voltage is lowered by expanding the boundary surface Be. By lowering the operating voltage of the SBD 100s, the activation of the SBD 100s is made earlier than that of the parasitic diode portion 100m2, and the activation of the parasitic diode portion 100m2 is suppressed. Thus, the expansion of the crystal defects of the semiconductor portion is effectively suppressed.

[0057] ​Assuming that, in a case where the width of the second active region E is substantially uniform, the reduction in the leakage current due to the narrowing of the width is in a so-called trade-off relationship with the reduction in the operating voltage due to the increase in the width, the semiconductor device 100 of the present embodiment solves both problems by narrowing the upper surface D10 of the first active region D and expanding the boundary surface Bd.

[0058] As above, the semiconductor device 100 of the present embodiment can improve the reliability and the operation performance.

[0059] (First Modification of the First Embodiment)

[0060] In the semiconductor device 101 of the present modification, for example, the width of the first upper portion D31 of the first active region D1 is further reduced, and the width of the first lower portion D21 is further increased, so that the difference between the width of the first upper portion D31 and the width of the first lower portion D21 is increased. That is, the cross-sectional shape of the first upper portion D31 and the cross-sectional shape of the first lower portion D21 are each substantially trapezoidal, and the length of the lower edge of the first upper portion D31 is shorter than the length of the upper edge of the first lower portion D21.

[0061] Figure 4 is an enlarged cross-sectional view of a MOSFET of the semiconductor device of the present modification. Figure 3 The same positions as Figure 4 are shown, and the protective film and the wiring layer are omitted.

[0062] The width of the upper surface D11 of the first active region D1 in the present modification is also narrower than the width of the boundary surface Bd1 that is the lower surface. To further explain the shape of the first active region D1, the first active region D1 is set as follows.

[0063] As Figure 4 shown, a bisector line DL is set in the first active region D1, and the first lower portion D21, the first upper portion D31, and the internal boundary surface D41 are set.

[0064] Using the above setting, it can be confirmed that the following cases. Figure 5

[0065] In the first active region D1, the width of the first upper portion D31 is made smaller than the width of the first upper portion D30 of the first embodiment, and the width of the first lower portion D21 is made larger than the width of the first lower portion D20 of the first embodiment. Due to this, the internal boundary surface D41 of the first upper portion D31 and the first lower portion D21 is formed with a notch surface D61. The side boundary surface Pd1 has one step due to the notch surface D61.

[0066] ​In the first active region D1, the width of the first upper portion D31 is narrower than the width of the first lower portion D21. In the first active region D1, the average of the width of the first upper portion D31 is smaller than the average of the width of the first lower portion D21.

[0067] The width of the upper surface D11 is smaller than the average of the width of the first upper portion D31. Further, the width of the upper surface D11 is smaller than the width of the internal boundary surface D41.

[0068] The width of the boundary surface Bd1 as the lower surface is larger than the average of the width of the first lower portion D21. Alternatively, the width of the boundary surface Bd1 is larger than the average of the width of the internal boundary surface D41.

[0069] The second active region in the present modification is the same shape as the first active region D1.

[0070] According to the present modification, in the first active region D1, the upper surface D11 can be further narrowed, and the boundary surface Bd1 can be further enlarged. Thereby, the effect of the first embodiment can be further enhanced.

[0071] The configuration, operation, and effect other than the above in the present modification are the same as the first embodiment.

[0072] (Second Modification of the First Embodiment)

[0073] In the semiconductor device 102 of the present modification, the semiconductor portion 10 contains silicon Si, for example, and the first active region D2 is formed by heat diffusion after ion implantation of impurities at two positions in the direction Z in the semiconductor portion 10.

[0074] Figure 5 is an enlarged sectional view of the MOSFET of the semiconductor device of the present modification. Figure 3 The same positions as Figure 5 are shown, and the protective film and the wiring layer are omitted.

[0075] The first active region D2 in the present modification is also set in the same manner, and the shape will be described below.

[0076] As shown in Figure 5 , the first upper portion D32 and the first lower portion D22 are formed by heat diffusion of impurities, and thus the width of the central portion in the direction Z is the widest. That is, the cross-sectional shape of the first upper portion D32 is an oblong circle, the cross-sectional shape of the first lower portion D22 is also an oblong circle, and the maximum diameter of the first upper portion D32 is smaller than the maximum diameter of the first lower portion D22. As shown in Figure 6 , the internal boundary surface D42 of the first upper portion D32 and the first lower portion D22 is a necked surface D62. The side boundary surface Pd2 is a curved surface that is necked due to the necked surface D62.

[0077] Further, in the first active region D2, the width of the first upper portion D32 is narrower than the width of the first lower portion D22. In the first active region D2, the average of the width of the first upper portion D32 is smaller than the average of the width of the first lower portion D22.

[0078] The width of the upper surface D12 is smaller than the average of the width of the first upper portion D32. Further, since the internal boundary surface D42 is the necked surface D62, it cannot be said that the width of the upper surface D12 is smaller than the width of the internal boundary surface D42.

[0079] On the other hand, it cannot be said that the width of the boundary surface Bd2 is larger than the average of the width of the first lower portion D22. Further, since the internal boundary surface D42 is the necked surface D62, it cannot be said that the width of the boundary surface Bd2 is larger than the width of the internal boundary surface D42.

[0080] Further, the first active region D1 in the present modification example is formed in two stages by implanting impurities at two positions in the direction Z in the semiconductor portion 10, but is not limited thereto, and for example, can be formed in three or more stages by implanting impurities at three or more positions in the direction Z.

[0081] The first active region D2 in the present modification example is formed by thermal diffusion of impurities, and thus the width of the central portion in the direction Z is widest in the first upper portion D32 and the first lower portion D22. Thereby, even if the upper surface D12 of the first active region D2 is narrowed, the width of the central portion in the direction Z is widened, and the current path is widened. Thereby, the on-resistance of the MOSFET 102m can be reduced, and the operating voltage of the SBD 100s can be lowered.

[0082] As described above, the semiconductor device 102 of the present modification example can also improve reliability and operation performance.

[0083] The configuration, operation, and effects other than the above in the present modification example are the same as those of the first embodiment.

[0084] (Third Modification of the First Embodiment)

[0085] In the semiconductor device 103 of the present modification example, the semiconductor portion 10 contains, for example, silicon carbide, and the first active region D3 is formed, for example, by ion implanting impurities at three positions in the direction Z in the semiconductor portion 10 and then thermally diffusing them.

[0086] Figure 6 is an enlarged sectional view of the MOSFET of the semiconductor device of the present modification example. Figure 3 The same positions as Figure 6 are shown, and the protective film and the wiring layer are omitted.

[0087] As​ As shown, the first active region D3 is formed by ion-implanting impurities at three positions in the direction Z and thermally diffusing them. In this modification, since the diffusion of the impurities is less, the cross-sectional shape of the first active region D3 becomes, for example, a shape in which three substantially rectangular shapes are overlapped.

[0088] In the first active region D3, the upper portion located at the uppermost is narrowest in width, the lower portion located at the lowermost is widest in width, and the bisector DL is located at the approximate center of the portion therebetween. The side boundary surface Pd3 is, for example, a 3-step shape.

[0089] The first active region D3 in this modification is also set similarly, and the shape will be described below.

[0090] In the first active region D3, the average of the widths of the first upper portion D33 is smaller than the average of the widths of the first lower portion D23.

[0091] The width of the upper surface D13 is smaller than the average of the widths of the first upper portion D33. Further, the width of the upper surface D13 is smaller than the average of the widths of the internal boundary surface D43.

[0092] The width of the boundary surface Bd3 cannot be said to be larger than the average of the widths of the first lower portion D23. Further, the width of the boundary surface Bd3 is larger than the average of the widths of the internal boundary surface D43.

[0093] The second active region in this modification is the same shape as the first active region D3.

[0094] In this modification, the first active region D3 can be formed, for example, by an epitaxial growth method.

[0095] The configuration, operation, and effects other than the above in this modification are the same as those of the first embodiment.

[0096] According to the embodiment of the present application, a semiconductor device capable of improving reliability can be provided.

[0097] The embodiments of the present application have been described above with reference to specific examples. However, the embodiments of the present application are not limited to these specific examples. For example, as to the specific configuration, material, and the like of the semiconductor portions, the plurality of electrodes, and the insulating film in the MOSFET and the SBD included in the semiconductor device, a person skilled in the art can appropriately select from the known range to implement the present application similarly, as long as the same effects can be obtained, and is included in the scope of the present application. As long as the gist of the present application is included, an embodiment in which two or more elements in the specific examples are combined within a range that can be technically implemented is also included in the scope of the present application.

Claims

1. A semiconductor device comprising: First electrode; Second electrode; A first semiconductor layer of a first conductivity type is disposed between the first electrode and the second electrode; A second semiconductor layer of a second conductivity type is disposed between the first semiconductor layer and the second electrode; A third semiconductor layer of a first conductivity type is disposed between the second semiconductor layer and the second electrode, and is electrically connected to the second electrode; as well as The third electrode is disposed between the first semiconductor layer and the second electrode, between the second semiconductor layer and the second electrode, and between the third semiconductor layer and the second electrode, separated by an insulating film and an insulating layer. The first semiconductor layer has: First area; A first active region is disposed on the first region, is in contact with the second semiconductor layer and the insulating film, and is separated from the second electrode; A second active region is disposed on the first region, and is connected to the second semiconductor layer and the second electrode, but separated from the first active region by the second semiconductor layer. The first active region has: The first upper part is located between the first region and the second electrode; A first lower portion, located between the first region and the first upper portion, has an average width in a second direction orthogonal to a first direction from the first electrode toward the second electrode that is greater than the average width of the first upper portion in the second direction. The second active region has: The second upper part is connected to the second electrode; The second lower portion is located between the first region and the second upper portion, and the average width of the second lower portion in the second direction is greater than the average width of the second upper portion in the second direction. The width of the upper surface of the first active region that is in contact with the insulating film is smaller than the average width of the first upper region. The first region is located below the first active region and the second semiconductor layer, and the upper surface of the first region is in contact with the lower surface of the first active region and the second semiconductor layer.

2. The semiconductor device as claimed in claim 1, The width of the upper surface of the first active region that is in contact with the insulating film is smaller than the width of the inner boundary surface between the first upper part and the first lower part.

3. The semiconductor device as described in claim 1 or 2, The width of the upper surface of the first active region that is in contact with the insulating film is smaller than the width of the first boundary surface between the first active region and the first region.

4. The semiconductor device as claimed in claim 1 or 2, The width of the second boundary surface between the second active region and the first region is greater than the average width of the second lower part.

5. The semiconductor device as claimed in claim 1 or 2, The width of the second boundary surface between the second active region and the first region is greater than the width of the inner boundary surface between the second upper part and the second lower part.

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