Semiconductor device

Abstract

A semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a second semiconductor layer of the first conductivity type, a plurality of electrodes, and a first insulating film. The second semiconductor layer is provided over the first semiconductor layer and contains a first-conductivity-type impurity at a lower concentration than a first-conductivity-type impurity of the first semiconductor layer. The third semiconductor layer is provided over the second semiconductor layer and has a first surface on the opposite side of the second semiconductor layer. The plurality of electrodes extends inside a plurality of trenches from the first surface to the second semiconductor layer. The plurality of first insulating films is provided between the plurality of electrodes and the second and third semiconductor layers, respectively. The plurality of electrodes includes a first electrode group arranged in a column at a first distance apart in a first direction on the first surface and a second electrode group arranged in a column at the first distance apart in the first direction and at a second distance apart from the first electrode group in a second direction.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2020-156337 (filed on September 17, 2020). This application includes all contents of that basic application by reference. Technical Field

[0003] The implementation involves a semiconductor device. Background Technology

[0004] Semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and diodes are used in power converters such as inverters. For example, a diode is connected in reverse parallel with an IGBT as a so-called FWD (Free Wheeling Diode). Improving the characteristics of the FWD is crucial for increasing the efficiency of such power converters. Summary of the Invention

[0005] The implementation provides a semiconductor device that reduces switching losses and improves reverse withstand voltage.

[0006] The semiconductor device of the embodiment includes a first semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a second semiconductor layer of the first conductivity type, a plurality of electrodes, and a first insulating film. The second semiconductor layer is disposed on the first semiconductor layer and contains a lower concentration of first conductivity type impurities than the first semiconductor layer. The third semiconductor layer is disposed above the second semiconductor layer and has a first surface extending in a first direction and a second direction intersecting the first direction on a side opposite to the first semiconductor layer. The plurality of electrodes extend within a trench on the second semiconductor layer, the trench having a depth from the first surface to the second semiconductor layer. The first insulating film is disposed between one of the plurality of electrodes and the third semiconductor layer, and between the first electrode and the second semiconductor layer. The plurality of electrodes includes: a first electrode group arranged in a row, each spaced a first distance apart in the first direction; and a second electrode group arranged in a row, each spaced a first distance apart in the first direction, and spaced a second distance apart from the first electrode group in the second direction. The first distance is longer than the second distance. Attached Figure Description

[0007] Figure 1A and Figure 1B This is a schematic diagram illustrating a semiconductor device used in an embodiment.

[0008] Figures 2A-2Cis a graph showing characteristics of a semiconductor device of an embodiment.

[0009] Figure 3 is a graph showing another characteristic of a semiconductor device of an embodiment.

[0010] Figure 4A and Figure 4B is a schematic view showing a trench configuration of a semiconductor device of an embodiment.

[0011] Figure 5A and Figure 5B is a schematic view showing a trench configuration of a semiconductor device of a modification of an embodiment.

[0012] Figure 6A and Figure 6B is a schematic view showing a trench configuration of a semiconductor device of another modification of an embodiment.

[0013] Figure 7A and Figure 7B is a schematic cross-sectional view showing a semiconductor device of a modification of an embodiment.

[0014] Figure 8 is a schematic view showing a method of arranging a wiring of a semiconductor device of another modification of an embodiment.

[0015] Figure 9A and Figure 9B is a schematic view showing a method of arranging a wiring of a semiconductor device of an embodiment.

[0016] Figure 10 is a schematic view showing another example of a method of arranging a wiring of a semiconductor device of an embodiment. DETAILED DESCRIPTION

[0017] Hereinafter, an embodiment will be described with reference to the drawings. The same parts are denoted by the same reference numerals in the drawings and detailed description thereof will be appropriately omitted, and different parts will be described. In addition, the drawings are schematic or conceptual, and the relationship between the thickness and the width of each part, the ratio of the size between parts, and the like are not necessarily the same as that in reality. In addition, even in the case of showing the same parts, there are cases where the sizes and the ratios of the parts are shown differently from each other depending on the drawings.

[0018] Further, the arrangement and the structure of each part will be described using the X axis, the Y axis, and the Z axis shown in each drawing. The X axis, the Y axis, and the Z axis are orthogonal to each other and respectively represent the X direction, the Y direction, and the Z direction. In addition, sometimes the Z direction is described as the upper side and the opposite direction thereof is described as the lower side.

[0019] Figure 1A and Figure 1BThis is a schematic diagram illustrating the semiconductor device 1 of the embodiment. Figure 1A It is a cross-sectional view along the XZ plane. Figure 1B It means along Figure 1A The top view of the cross section of line AA shown.

[0020] Semiconductor device 1 is, for example, a diode. Semiconductor device 1 is used, for example, integrated with an IGBT. Furthermore, the embodiments shown below are illustrative and not limited thereto.

[0021] like Figure 1A As shown, semiconductor device 1 includes a first semiconductor layer 11 of a first conductivity type, a second semiconductor layer 12 of a first conductivity type, and a third semiconductor layer 13 of a second conductivity type. The second semiconductor layer 12 is disposed on the first semiconductor layer 11. The third semiconductor layer 13 is disposed on the second semiconductor layer 12. The second semiconductor layer 12 contains a lower concentration of first conductivity type impurities than the first conductivity type impurities in the first semiconductor layer 11.

[0022] The first semiconductor layer 11 is, for example, an n-type cathode layer. The third semiconductor layer 13 is, for example, a p-type anode layer. In the following description, the first conductivity type will be referred to as n-type, and the second conductivity type will be referred to as p-type.

[0023] The semiconductor device 1 also includes an electrode 30. The electrode 30 is disposed within a trench AT having a depth from the surface of the third semiconductor layer 13 to the second semiconductor layer 12. The electrode 30 extends within both the third semiconductor layer 13 and the second semiconductor layer 12. The electrode 30 is, for example, conductive polycrystalline silicon. The electrode 30 is electrically insulated from the third semiconductor layer 13 and the second semiconductor layer 12, for example, by an insulating film 33. The insulating film 33 is disposed between the electrode 30 and the third semiconductor layer 13, and between the electrode 30 and the second semiconductor layer 12. The insulating film 33 is, for example, a silicon oxide film.

[0024] The first semiconductor layer 11 is electrically connected to the electrode 10 (cathode). The third semiconductor layer 13 is electrically connected to the electrode 20 (anode). Additionally, the electrode 30 is electrically connected to the electrode 20, for example, at the same potential as the third semiconductor layer 13. However, the implementation is not limited to this; for example, the electrode 30 may also be electrically connected to other electrodes (not shown) and biased to a different potential than the third semiconductor layer 13.

[0025] like Figure 1B As shown, multiple electrodes 30 are provided, each disposed inside a plurality of trenches AT. For example, a portion of the plurality of electrodes 30 constitutes a plurality of columns arranged in the Y direction, and the columns of electrodes 30 arranged in the Y direction are arranged in the X direction.

[0026] The plurality of trench ATs are configured such that, under a prescribed reverse bias applied between the first semiconductor layer 11 and the third semiconductor layer 13, for example, 1 V, the region of the second semiconductor layer 12 existing between the adjacent trench ATs is depleted. That is, the maximum width WM between the adjacent trench ATs is set such that the current path between the adjacent trench ATs is pinched off.

[0027] For example, at an arbitrary point on the second semiconductor layer 12, when a straight line containing the point on the XY plane is drawn, the length of the line segment containing the point pinched between the different trench ATs is the distance between the adjacent trench ATs. The distance between the trench ATs, the interval, and the length of the trench are measured with reference to the position of the side wall of the trench AT or the outer edge of the insulating film 33 possessed by the trench AT. The maximum value of the distance between the adjacent trench ATs on the second semiconductor layer 12 is the maximum width WM.

[0028] Figures 2A-2C and Figure 3 is a graph showing the characteristics of the semiconductor device 1 according to the embodiment. Figures 2A-2C is a cross-sectional view from the surface between the adjacent trench ATs to the bottom of the trench in the case where the depth of the trench AT is, for example, 5.5 μm. Figures 2A-2C respectively show the depletion layer in the third semiconductor layer 13 and in the second semiconductor layer 12 under a prescribed reverse bias, for example, 1 V. Figure 3 is a graph showing the reverse withstand voltage of the semiconductor device 1.

[0029] As shown in Figures 2A-2C , the interval between the adjacent trench ATs (see FIG. 1) is 1.6 micrometers (hereinafter, μm), 2.0 μm, and 2.5 μm, respectively. The equipotential surfaces shown in each of the graphs show the extension of the depletion layer.

[0030] If the interval between the adjacent trench ATs is 1.6 μm, 2.0 μm, as shown in Figure 2A and Figure 2B , the portion of the second semiconductor layer 12 between the adjacent trench ATs is depleted. On the other hand, if the interval between the adjacent trench ATs is 2.5 μm, as shown in Figure 2C , the second semiconductor layer 12 contains a portion that is not depleted between the adjacent trench ATs.

[0031] Figure 3 is a graph showing the relationship between the interval of the adjacent trench ATs and the reverse withstand voltage (breakdown voltage). As shown in Figure 3 , the wider the WM, the lower the breakdown voltage.

[0032] The semiconductor device 1 of the embodiment has the electrode 30 with a trench structure in order to secure the reverse withstand voltage and the withstand voltage between the anode and the cathode. However, by providing the electrode 30, the area in the X-Y plane of the second semiconductor layer 12 becomes narrow. Therefore, compared with the case where the electrode 30 is not provided, the conduction path of the carrier becomes narrow, and the carrier density (density of electrons and holes) in the third semiconductor layer 13 becomes high.

[0033] For example, in a power conversion device such as an inverter, it is desirable to improve the characteristics of the on-voltage (voltage drop in the on state), the recovery time (time to extinction of the recovery current at the time of reverse recovery), the safe operating area at the time of recovery (operating area that is not destroyed even if a voltage is applied in a state where a reverse recovery current is flowing), the current and voltage oscillation at the time of recovery, and the like. Among these, it is important to shorten the recovery time and to expand the safe operating area at the time of recovery.

[0034] In the semiconductor device 1, the trench AT in which the electrode 30 is arranged is provided, whereby a uniform avalanche phenomenon can be generated at the bottom thereof, and the breakdown withstand voltage can be improved. Further, by making the interval WM between the adjacent trenches AT narrower than the interval at which pinch-off occurs at the time of application of a reverse bias, the reverse withstand voltage can be improved.

[0035] However, by forming the trench AT, the carrier density in the second semiconductor layer 12 and the third semiconductor layer 13 becomes high. Therefore, the recovery characteristics deteriorate in the transition from the on state to the off state, and the recovery loss becomes large compared with the case where the electrode 30 is not provided.

[0036] Therefore, in the semiconductor device 1, by reducing the occupancy ratio of the trench AT in the X-Y cross section of the third semiconductor layer 13, the density of the holes injected from the third semiconductor layer 13 to the second semiconductor layer 12 is reduced. Thereby, it is possible to suppress the reduction in the reverse withstand voltage and the breakdown withstand voltage, and it is possible to reduce the recovery loss.

[0037] Figure 4A and Figure 4B is a schematic plan view illustrating the structure of the semiconductor device 1 of the embodiment. Figure 4A and Figure 4B is a plan view illustrating the arrangement of the trench AT. Further, in the arrangement diagram of the trench AT shown below, the electrode 30, the insulating film 33, and the third semiconductor layer 13 are omitted.

[0038] As Figure 4AAs shown, the trench AT has, for example, an X-Y cross section of a rectangle whose sides extend in the X direction and the Y direction. The plurality of trenches AT are arranged in the Y direction to form a column and in the X direction to form a row, and thus are arranged in a matrix shape. The trenches AT adjacent in the X direction are arranged with a space WDX. The trenches AT adjacent in the Y direction are arranged with a space WDY. The length LY of the trench AT in the Y direction is longer than the length LX in the X direction. The space WM between the trenches AT adjacent, for example, becomes the largest in the diagonal direction of the arrangement of the plurality of trenches AT. The diagonal direction refers to a direction obtained by adding LX+WDX in the X direction and LY+WDY in the Y direction. The largest space WM is, for example, a distance between end portions of the trenches AT close in the diagonal direction, and is 2 μm or less.

[0039] In Figure 4B In the example shown, the trenches AT included in a first column arranged in the Y direction among the plurality of trenches AT are arranged in a manner that is side by side with a space between the trenches AT of a second column adjacent to the first column in the X direction. The space WDY between the trenches AT adjacent in the Y direction is narrower than the length LY of the trench AT in the Y direction. Further, WDX is, for example, 1 μm or less. In this case, the space WM between the trenches AT adjacent in the Y direction becomes the largest. The space WM between the trenches AT adjacent is, for example, 2 μm or less.

[0040] Figure 5A and Figure 5B is a schematic view of a structure of a semiconductor device 1 of a modification example of the embodiment. Figure 5A and Figure 5B is a plan view illustrating the arrangement of the trenches AT.

[0041] As Figure 5A shown, the trenches AT included in a first column arranged in the Y direction among the plurality of trenches AT are arranged in a manner that is arranged in a space between the trenches AT of a second column adjacent to the first column in the X direction. The space WDY between the trenches AT adjacent in the Y direction is larger than the length LY of the trench AT in the Y direction. Further, WDX is, for example, 1 μm or less. In this case as well, the space WM between the trenches AT adjacent in the Y direction becomes the largest. The space WM between the trenches AT adjacent is, for example, 2 μm or less.

[0042] As Figure 5B shown, the trench AT can also be provided, for example, with an X-Y cross section of a circle. The trenches AT are arranged, for example, in a diagonal direction of the arrangement thereof. The space WM between the trenches AT adjacent in the diagonal direction is, for example, 2 μm or less.

[0043] Figure 6A and Figure 6Bis a schematic view of a structure of a semiconductor device 1 according to another modification of the embodiment. Figure 6A and Figure 6B is a plan view illustrating a configuration of the trench AT.

[0044] As Figure 6A illustrated, the trench AT may, for example, also be provided with a circular cross section in the X-Y plane. The trench AT is provided in a manner of surrounding a portion of the third semiconductor layer 13 and a portion of the second semiconductor layer 12. The trenches AT are arranged, for example, in a diagonal direction of the configuration thereof. The interval WM between the trenches AT adjacent in the diagonal direction is, for example, 2 μm or less. Further, the inner diameter of the trench AT is, for example, 2 μm or less.

[0045] As Figure 6B illustrated, the trench AT has, for example, a hexagonal cross section in the X-Y plane. The trenches AT are arranged, for example, in a diagonal direction of the configuration thereof. The interval WM between the trenches AT adjacent in the diagonal direction is, for example, 2 μm or less. Further, the inner diameter of the trench is, for example, 2 μm or less. In addition, the outer shape of the cross section of the trench AT is not limited to a hexagon, and can be another polygon.

[0046] In the configuration of the trench AT described above, the total of the X-Y cross-sectional areas of the trenches AT is preferably narrower than the area in the X-Y plane of the third semiconductor layer 13, for example. Thereby, the density of the holes injected from the third semiconductor layer 13 to the second semiconductor layer 12 can be reduced, and the carrier density in the second semiconductor layer 12 can be reduced.

[0047] Figure 7A and Figure 7B are schematic views of semiconductor devices 2 and 3 according to modifications of the embodiment.

[0048] In Figure 7A the semiconductor device 2 illustrated, the trench AT is provided with a cross section having an inverted taper shape in which the X-direction width of the bottom portion in the second semiconductor layer 12 is wider than the X-direction width of the portion in the third semiconductor layer 13 in the X-Z plane. The electrode 30 provided inside the trench AT also has the same X-Z cross-sectional shape.

[0049] In the semiconductor device 2, the interval WM in the X-direction is ensured between the bottom surfaces of the adjacent trenches AT. The interval WM is the interval pinched off under a reverse bias. In contrast, the X-direction width of the third semiconductor layer 13 is wider than the interval WM between the bottom surfaces of the trenches AT.

[0050] In Figure 7BIn the illustrated semiconductor device 3, the trench AT is provided so that the width in the X direction of the portion located in the second semiconductor layer 12 is wider than the width in the X direction of the portion located in the upper portion of the third semiconductor layer 13. The electrode 30 provided inside the trench AT also has the same X-Z sectional shape.

[0051] In the semiconductor device 3, the interval WM in the X direction is ensured between the portions of the adjacent trenches AT located in the second semiconductor layer 12. The interval WM is the interval pinched off under a reverse bias. In contrast, the width in the X direction of the upper portion of the third semiconductor layer 13 is wider than the interval WM.

[0052] Thus, in the semiconductor devices 2 and 3, the plurality of trenches AT are configured so that the interval WM of the bottoms of the adjacent trenches AT is narrower than the pinched-off interval. Since the interval of the upper portion of the third semiconductor layer 13 is larger than WM, the carrier density can be reduced by increasing the occupancy of the third semiconductor layer 13 in the X-Y plane.

[0053] Figure 8 is a schematic view showing a method of providing the wiring 40 of the semiconductor device 4 according to the embodiment.

[0054] The semiconductor device 4 is the same as the semiconductor device 1 shown in Fig. 1 in that the third semiconductor layer 13 and the electrode 30 are electrically connected by the wiring 40. The wiring 40 is, for example, a metal film provided above the third semiconductor layer 13, the electrode 30, and the insulating film 33. The wiring 40 is connected to the anode electrode 20. The semiconductor devices according to the embodiment can be provided with the wiring 40 as in Figure 8 .

[0055] Figure 9A and Figure 9B is a schematic view showing a method of providing the wiring of the semiconductor device 5 according to the embodiment. In the semiconductor device 5 according to the embodiment, different potentials can be applied to the third semiconductor layer 13 and the electrode 30. The semiconductor device 5 has an insulating film 50, a wiring 40A, and a wiring 40B in addition to the structure of the semiconductor device 1. Figure 9A is a schematic plan view showing an example in which the wirings 40A and 40B are provided in the structure of the semiconductor device shown in Figure 4A . Figure 9B is a sectional view along the B-B line shown in Figure 9A .

[0056] The insulating film 50 is provided above the third semiconductor layer 13, the electrode 30, and the insulating film 33. The wiring 40A (indicated by a single-dot chain line in Figure 9A ) is provided so as to extend in the X direction on the insulating film 50. The plurality of wirings 40A are connected to the electrode 20A extending in the Y direction.

[0057] The wiring 40A is connected to the plurality of electrodes 30 via the contact 30c (indicated by a diagonal line in Figure 9A the drawing) of the through insulating film 50. The wiring 40A is electrically separated from the third semiconductor layer 13.

[0058] The wiring 40B is provided on the insulating film 50 so as to extend in the X direction. The wiring 40B (indicated by a broken line in Figure 9A the drawing) is connected to the third semiconductor layer 13 via the contact 30c of the through insulating film 50. The plurality of wirings 40B are connected to the electrodes 20B extending in the Y direction. The wiring 40B is electrically separated from the electrodes 30. The wiring 40A and the wiring 40B are provided separately in the Y direction and are electrically insulated. The wiring 40A and the wiring 40B are provided alternately with each other in the Y direction. The wiring 40A and the wiring 40B are, for example, metal films.

[0059] Figure 10 is a schematic view showing another example of a method of providing the wiring 40 of the semiconductor device 5 according to the embodiment. Figure 10 is a schematic plan view showing an example in which the wirings 40A and 40B are provided in the structure of the semiconductor device shown in Figure 4B . In Figure 10 , the contact of the wiring 40B is omitted.

[0060] As shown in Figure 10 , by providing the contact 30c of the wiring 40A at the Y direction end portion of the trench AT, it is possible to increase the proportion of the contact area with respect to the occupied area of the wiring 40A, as compared with the case in which the contact 30c is provided at the center of the trench AT.

[0061] The several embodiments of the present application have been described, but these embodiments are presented as examples and are not intended to limit the scope of the application. These new embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made within the scope of the gist of the application. These embodiments and modifications thereof are included in the scope or gist of the application, and are included in the scope of the application and equivalents thereof recited in the claims.

Claims

1. A semiconductor device comprising: First semiconductor layer of first conductivity type; The second semiconductor layer of the first conductivity type is disposed on the first semiconductor layer and contains a first conductivity type impurity with a lower concentration than the first conductivity type impurity of the first semiconductor layer; A third semiconductor layer of a second conductivity type is disposed above the second semiconductor layer, the third semiconductor layer being located on the opposite side of the second semiconductor layer, and having a first surface extending in a first direction and a second direction intersecting the first direction; Multiple electrodes are disposed on the second semiconductor layer, and the multiple electrodes extend inside multiple trenches, the depth of which is from the first surface to the depth in the second semiconductor layer; as well as A first insulating film is disposed between one of the plurality of electrodes and the third semiconductor layer, and between the one of the plurality of electrodes and the second semiconductor layer. The plurality of electrodes includes a first electrode group and a second electrode group. The plurality of trenches in the first electrode group are arranged in a row on the first surface, each spaced a first distance apart in the first direction. The plurality of trenches in the second electrode group are arranged in a row on the first surface, spaced apart by the first distance in the first direction. The plurality of trenches in the second electrode group are spaced a second distance from the first electrode group in the second direction on the first surface. For each of the plurality of trenches, the maximum spacing between the trenches adjacent to it is below the distance at which the second semiconductor layer is partially depleted between the two adjacent trenches when a predetermined voltage is applied between the first and third semiconductor layers. The combined cross-sectional area of ​​the plurality of trenches in the first surface is narrower than the area of ​​the first surface of the third semiconductor layer.

2. The semiconductor device according to claim 1, wherein, The plurality of grooves have a first length in the first direction and a second length in the second direction. The second length is shorter than the first length.

3. The semiconductor device according to claim 1, wherein, The plurality of grooves have a first length in the first direction. The first distance is narrower than the first length of the plurality of trenches in the first electrode group and the second electrode group.

4. The semiconductor device according to claim 1, wherein, When a predetermined voltage is applied between the first semiconductor layer and the third semiconductor layer, and between the first semiconductor layer and the plurality of electrodes, the current path of the second semiconductor layer between the plurality of electrodes is interrupted.

5. The semiconductor device according to claim 1, wherein, The first distance is less than 2 micrometers.

6. The semiconductor device according to claim 1, wherein, The area of ​​the third semiconductor layer in the first surface is greater than the sum of the areas of the plurality of first insulating films and the plurality of electrodes at the same level as the first surface.

7. The semiconductor device according to claim 1, wherein, The first electrode group and the second electrode group are adjacent to each other in the second direction, and each electrode of the second electrode group is disposed in a position adjacent to the space between the electrodes of the first electrode group that are adjacent to each other in the first direction in the second direction.

8. The semiconductor device according to claim 1, wherein, It also has: The second electrode is electrically connected to the first semiconductor layer; A second insulating film is disposed above the first surface; A first wiring is disposed above the first surface and electrically connected to the third semiconductor layer, having multiple portions extending along the second direction; as well as Multiple second wirings are disposed on the second insulating film, electrically connected to the multiple electrodes, separated from the first wirings in the first direction, and extending in the second direction.

9. The semiconductor device according to claim 1, wherein, The first electrode group and the second electrode group are separated by a third distance in the third semiconductor layer in the first direction, which is shorter than the first distance.

10. The semiconductor device according to claim 7, wherein, In a cross-section parallel to the first surface, the groove has a circular cross-sectional shape.

11. The semiconductor device according to claim 7, wherein, In a cross-section parallel to the first surface, the groove has a polygonal cross-sectional shape.

12. The semiconductor device according to claim 1, wherein, The trench is configured to surround a portion of both the second semiconductor layer and the third semiconductor layer.

13. The semiconductor device according to claim 1, wherein, The first spacing between adjacent trenches in the second semiconductor layer is narrower than the second spacing between adjacent trenches in the third semiconductor layer.

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