Filter with approximate multiplication capability and method thereof

Abstract

The present application discloses a filter with approximate multiplication capability and a method thereof. The filter with approximate multiplication capability includes at least one first multiplication approximation unit for approximating at least one first multiplication operation corresponding to at least one first coefficient using at least one first bitwise shift operation; and at least one second multiplication approximation unit for approximating at least one second multiplication operation corresponding to at least one second coefficient using multiple second bitwise shift operations and at least one addition operation. The present application can simplify arithmetic operations, reduce the demand for hardware resources and computing cycles, and reduce power consumption.

Description

Technical Field

[0001] The present application relates to a filter and method for an application-specific integrated circuit (ASIC), and more particularly to a filter and method for the ASIC capable of approximating multiplication operations. Background Art

[0002] The bi-quadratic (BiQuad) filter is a second-order filter commonly used in signal processing. In the discrete time domain, the input / output relationship of the bi-quadratic filter can be expressed as Formula 1 (Eq. 1):

[0003] y(n)=b0x(n)+b1x(n-1)+b2x(n-2)-a1y(n-1)-a2y(n-2)…Eq.1

[0004] By properly choosing the coefficients [a1, a2, b0, b1, b2], a biquad filter can be constructed based on a specific set of parameters such as sampling frequency, center / cutoff frequency f C , Q-factor, and gain to operate as a low-pass, high-pass, band-pass, peaking, notch, low-shelf, or high-shelf filter.

[0005] For example, see Figure 1 , Figure 1 Figure 2 shows the amplitude and phase responses of a biquad filter. Figure 1 As shown, when the discrete-time signal is sampled at a rate of 48 kilo-samples per second (ksps), a biquad filter with coefficients in Table 3 can be operated as a second-order low-pass filter with f C =1439.244251 Hz, Q = 0.7071, and a DC gain of unity.

[0006] Table 3

[0007] <![CDATA[a1=-1.734863758990959]]> <![CDATA[a2=0.766113758997616]]> <![CDATA[b0=0.007812500001664]]> <![CDATA[b1=0.015625000003329]]> <![CDATA[b2=0.007812500001664]]>

[0008] However, the above-mentioned biquad filter may require five multiplications, four additions, and multiple register allocation operations. Floating-point multiplication (especially the 64-bit double-precision floating-point numbers required for the coefficients shown in Table 3) is an expensive operation that not only requires a lot of hardware resources and computing cycles, but also consumes a lot of power.

[0009] Therefore, it is necessary to improve the existing technology. Summary of the Invention

[0010] Therefore, the main purpose of this application is to provide a filter and method that can approximate multiplication operations to improve the shortcomings of the prior art.

[0011] One embodiment of the present application discloses a filter, which includes at least one first multiplication approximation unit for approximating at least one first multiplication operation corresponding to at least one first coefficient using at least one first bit-by-bit shift operation; and at least one second multiplication approximation unit for approximating at least one second multiplication operation corresponding to at least one second coefficient using multiple second bit-by-bit shift operations and at least one addition operation.

[0012] One embodiment of the present application discloses a method, comprising approximating at least one first multiplication operation corresponding to at least one first coefficient using at least one first bitwise shift operation; and approximating at least one second multiplication operation corresponding to at least one second coefficient using multiple second bitwise shift operations and at least one addition operation.

[0013] An embodiment of the present application discloses a filter, comprising at least one first multiplication approximation unit for approximating at least one first multiplication operation corresponding to at least one first coefficient using at least one first bitwise shift operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 shows the amplitude and phase responses of a biquad filter;

[0015] Figure 2 Schematic diagram of a pair of second-order filters in direct form II;

[0016] Figure 3 1 is a schematic diagram of a biquad filter according to a first embodiment of the present application;

[0017] Figure 4 This is an embodiment of the present application Figure 3 Schematic diagram of the conversion of the multiplication approximation unit of the biquad filter shown;

[0018] Figure 5 This is an embodiment of the present application Figure 3 Schematic diagram of the amplitude response and phase response of the biquad filter shown;

[0019] Figure 6 is a schematic diagram of another biquad filter according to an embodiment of the present application;

[0020] Figure 7 is a schematic diagram of an all-pole filter and an all-zero filter.

[0021] Figure Number:

[0022] 20, 30, 60: biquad filter;

[0023] 300, 302, 304, 306, 308: multiplication approximation unit;

[0024] z -1 : Delay device;

[0025] x(n), y(n): signal. DETAILED DESCRIPTION

[0026] Since multiple stages of biquad filters can be used in a system, a 2M-order filter can be produced by cascading M stages of biquad filters. In this arrangement, the input of one stage is derived from the output of the previous stage, and its output is connected to the input of the next stage.

[0027] Please refer to Figure 2 , Figure 2 FIG. 2 is a schematic diagram of a conventional biquad filter 20 in direct-form II. Figure 2 As shown, since x(n) is the input signal, y(n) is the output signal, z -1 It is a delay device, so the data processing flow of the signal of the biquad filter 20 can be expressed as:

[0028] n=0;

[0029] do{

[0030] s2(n)=s1(n-1);

[0031] s1(n)=u(n-1);

[0032] u(n)=x(n)–a1s1(n)–a2s2(n);

[0033] y(n)=b0u(n)+b1s1(n)+b2s2(n);

[0034] n=n+1;

[0035] }

[0036] In this case, each iteration of the biquad filter 20 processing requires five multiplications, four additions, and multiple register allocation operations. As mentioned above, floating-point multiplications are expensive operations that not only require a large amount of hardware resources and computation cycles, but also consume a large amount of power. Silicon area, computation cycles, and power are all precious resources in digital systems, so it is highly desirable to have a biquad filter implementation that minimizes the use of floating-point multiplications.

[0037] When designing a biquad filter in an application-specific integrated circuit (ASIC), arithmetic operations are performed with finite precision. All variables and constants are represented using a finite number of bits. Inevitably, there is a discrepancy between the ideal design goal and the actual result produced by a particular digital implementation. Choosing the appropriate precision, or equivalent number of bits, to represent each coefficient in the design is crucial. The present application aims to implement a biquad filter that greatly simplifies arithmetic operations, thereby requiring fewer hardware resources, while still achieving the same results as floating-point arithmetic operations.

[0038] Please refer to Figure 3 and Figure 4 . Figure 3 is a schematic diagram of a biquad filter 30 according to an embodiment of the present application. Figure 4 This is an embodiment of the present application Figure 3 FIG. 3 is a schematic diagram showing the conversion of the multiplication approximation units 300, 302, 304, 306, and 308 of the biquad filter 30. Figure 3 and Figure 4 As shown, the multiplication approximation units 304, 306, and 308 respectively approximate the multiplication operations corresponding to at least one coefficient b0, b1, and b2 using bit-wise shift operations, while the multiplication approximation units 300 and 302 respectively approximate the multiplication operations corresponding to at least one coefficient a1 and a2 using bit-wise shift operations and addition operations. In this way, the present application can use bit-wise shift operations to approximate multiplication operations to save hardware resources.

[0039] Specifically, by selecting an appropriate corner frequency (f C ) and a quality factor (Q), the multiplication of coefficients b0, b1, and b2 is equivalent to a bitwise shift operation as shown in Table 4 below (f s is the sampling frequency). Since the bit-by-bit shift operation can be implemented by routing in an ASIC design, the resulting multiplication operation is implemented without using logic gates, taking up no silicon space, and consuming no power. In other words, the first implementation step of the biquad filter 30 involves selecting a suitable combination of corner frequencies f C and the quality factor Q, and converts the floating-point multiplications of the correlation coefficients b0, b1, and b2 into cost-free (bit-by-bit) rewiring of an ASIC. Then, in the second implementation step of the biquad filter 30, the coefficients b0, b1, and b2 are fine-tuned so that each of the two floating-point multiplications of the correlation coefficients a1 and a2 is converted into a bit-by-bit shift operation and two to three fixed-point addition operations.

[0040] Table 4

[0041]

[0042] Specifically, consider the corner frequency f at 48ksps C ≈1439.24 Hz and a quality factor Q≈0.707, the coefficients of the multiplication operation are approximated in the following manner (the coefficients of Table 3 are converted into the 4th row of Table 4, which approximates each coefficient by a term (e.g., b0, b1, b2) or the sum of multiple terms (e.g., a1, a2), each of which contains only one "1" in its binary expression):

[0043] a1=-1.734863758990959≈-(1.734375)=-(01.101111) b

[0044] =(0.01) b +(0.000001) b -(010.0) b

[0045] a2=0.766113758997616≈0.765625=(0.110001) b

[0046] =(01.0) b -(0.01) b +(0.000001) b

[0047] b0=0.007812500001664≈0.0078125=(0.0000001) b

[0048] b1=0.015625000003329≈0.015625=(0.000001) b

[0049] b2=0.007812500001664≈0.0078125=(0.0000001) b

[0050] The symbol () b It is the two's-complement binary representation of a number. For example, 1.25 = (01.01) b , 0.15625 = (0.00101) b wait.

[0051] like Figure 4 As shown, instead of floating-point multiplication, the multiplication of –a1s1(n) can be calculated as:

[0052] –a1s1(n)=s1(n)×(010.0) b –s1(n)×(0.01) b –s1(n)×(0.000001) b

[0053] =[s1(n) binary expression shifted left by 1 bit]

[0054] –[s1(n) binary expression shifted right by 2 bits]

[0055] –[s1(n) binary expression shifted right by 6 bits]

[0056] Thus, 3 costless bitwise rewirings will solve any multiplication needs, and it only requires 2 integer additions to approximate floating-point multiplications. And so on, Figure 2 The multiplication operation of –a2s2(n) can be done by Figure 4 The two addition operations shown are obtained.

[0057] For the multiplication operations corresponding to coefficients b0, b1, b2, since the coefficients b0, b1, b2 are each approximated by a number having only one "1" in the binary expression, each multiplication operation can be obtained by only one costless bitwise shift operation; for example, b0u(n)≈u(n)×(0.0000001) b = u(n) right shifted by 7 bits. All six multiplications of the biquad filter are transformed by shift operations and addition operations as shown in Figure 4 .

[0058] like Figure 3 As shown, by using approximate values ​​for all filter coefficients and replacing multiplications with shift and addition operations, Figure 2 The biquad filter 20 can be significantly simplified as Figure 3 The biquad filter 30 shown does not use any multipliers. It is worth mentioning that in hardware implementation, the shift operation does not require any hardware components, only the reconfiguration of the (wiring of) the data bus, thus occupying no hardware resources and consuming no power.

[0059] It should be noted that the corner frequency f C ≈1439.24Hz is relative to the sampling rate of 48Ksps. The same set of parameters above can produce a corner frequency f at a sampling rate of 768Ksps C ≈23,028Hz, generating a corner frequency f at a sampling rate of 960Ksps C≈28,785Hz, generating a corner frequency f at a sampling rate of 1536Ksps C ≈46,056Hz or a corner frequency f at a sampling rate of 3072Ksps C ≈92,111.63Hz, etc. (i.e., with the same f C / f s ).

[0060] Please refer to Figure 5 , Figure 5 Schematic diagram of the amplitude response and phase response of the biquad filter 30 according to the embodiment of the present application. Figure 5 As shown, simulations of biquad filter 30 using 24-bit fixed-point arithmetic show a frequency response that matches well with biquad filter 20 employing double-precision floating-point arithmetic. The solid curve shows the frequency response of biquad filter 20 when all calculations are performed in double-precision floating-point arithmetic, while the dashed curve shows the frequency response of biquad filter 30 employing only the shift operations and 24-bit fixed-point addition operations detailed above.

[0061] The precision used for variables in the simulation is 16-bit word-length / 15-bit fraction-length for inputs and outputs, and 24-bit word-length / 17-bit fraction-length for the state and accumulator. The error between the two curves in the amplitude and phase responses is negligible.

[0062] In summary, the procedure for selecting the filter coefficients [a1, a2, b0, b1, b2] to significantly simplify the implementation of a digital biquad filter involves:

[0063] (1) Approximate each coefficient by a term (e.g., b0, b1, b2) or a sum of terms (e.g., a1, a2), where each term contains only one "1" in its binary expression.

[0064] (2) The representation of the sum of terms should include as few terms as possible. Each term corresponds to a shift operation in the simplified biquad filter 30.

[0065] (3) Verify that the coefficients used will produce a stable filter.

[0066] Please refer to Figure 6 , Figure 6 : is a schematic diagram of a biquad filter 60 according to an embodiment of the present invention. In this embodiment, in order to further simplify the implementation of the digital biquad, the filter coefficients a1 and a2 are approximated in different ways as follows (i.e., the number of shifts and the number of additions in different groups of bitwise shift operations correspond to the same specific group at the 48ksps corner frequency f C≈1439.24 Hz and quality factor Q≈0.707):

[0067] a1=-1.734863758990959≈-(1.75)=-(01.11) b =(0.01) b -(010.0) b

[0068] a2=0.766113758997616≈0.875=(0.111) b =(01.0) b -(0.001) b

[0069] Furthermore, to obtain a biquad filter 60 with unity DC gain, the coefficients b0, b1, b2 are scaled by a factor of 4:

[0070] b0≈4×0.0078125=(0.00001) b

[0071] b1≈4×0.015625=(0.0001) b

[0072] b2≈4×0.0078125=(0.00001) b

[0073] The multiplication operation corresponding to the coefficient a1 can be replaced by two shift operations and one addition operation, the multiplication operation corresponding to the coefficient a2 can be replaced by one shift operation and one addition operation, and each multiplication operation corresponding to the coefficient b0, b1 or b2 can be replaced by one shift operation. Figure 6 As shown, biquad filter 60 has two fewer addition operations and two fewer shift operations than biquad filter 30 .

[0074] It should be noted that the above embodiments are all for biquad filters. However, the method of using approximate filter coefficients to avoid the use of multipliers and simplify the implementation can be applied to other types of filters or digital signal processors that require multiplication operations. For example, by using similar principles, the replacement of multiplication coefficients can be applied to Figure 7 The all-poles filter shown on the left side of the figure, or Figure 7 An all-zero filter as shown in the right part of , which is also within the scope of this application.

[0075] In summary, the present application uses bit-by-bit shift operations to approximate multiplication operations to save hardware resources.

[0076] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A filter having an approximate multiplication capability, characterized in that: The filter comprises: at least one first multiplication approximation unit for approximating at least one first multiplication operation corresponding to at least one first coefficient using at least one first bitwise shift operation; and at least one second multiplication approximation unit for approximating at least one second multiplication operation corresponding to at least one second coefficient using a plurality of second bitwise shift operations and at least one addition operation; The values ​​of a first shift number, a second shift number, and a third shift number in the at least one shift number of the at least one first bitwise shift operation and a specific set of a corner frequency and a quality factor are selected from a row of values ​​in Table 1 below when the corner frequency and the quality factor vary by less than 1%. Table 1 The changes in the corner frequency and the quality factor in Table 1 are less than 1%.

2. The filter according to claim 1, wherein The at least one first bit-wise shift operation and the plurality of second bit-wise shift operations are implemented by wiring in an application specific integrated circuit.

3. The filter according to claim 1, wherein The at least one first multiplication approximation unit approximates each first coefficient of the at least one first coefficient into a first term that only includes one "1" in a first binary expression, and the at least one second multiplication approximation unit approximates each second coefficient of the at least one second coefficient into multiple second terms, and the first term and each second term of the multiple second terms only include one "1" in a second binary expression.

4. The filter according to claim 1, wherein The at least one shifting bit amount of the at least one first bit-by-bit shifting operation corresponds to the corner frequency and the quality factor of the specific set.

5. The filter according to claim 1, wherein When the corner frequency is substantially 1439.24 Hz at 48 kilosamples per second and the quality factor is substantially 0.707, the at least one first bitwise shift operation includes a first right shift of 7 bits, a first right shift of 6 bits, and a second right shift of 7 bits, a first operation step in the at least one second multiplication operation corresponds to a second right shift of 6 bits, a first right shift of 2 bits, a left shift of 1 bit, and two addition operations, and a second operation step in the at least one second multiplication operation corresponds to a third right shift of 6 bits, a second right shift of 2 bits, and an addition operation.

6. The filter according to claim 1, wherein When a corresponding first coefficient of the at least one first coefficient is scaled, the values ​​of the first shift bit number, the second shift bit number, and the third shift bit number selected from the values ​​of the row in Table 1 are adaptively adjusted.

7. The filter according to claim 6, wherein When the corner frequency is substantially 1439.24 Hz at 48 kilosamples per second and the quality factor is substantially 0.707, the at least one first bitwise shift operation includes a first right shift of 5 bits, a right shift of 4 bits, and a second right shift of 5 bits, a first operation step in the at least one second multiplication operation corresponds to a second right shift of 2 bits, a left shift of 1 bit, and an addition operation, and a second operation step in the at least one second multiplication operation corresponds to a right shift of 3 bits and an addition operation.

8. The filter according to claim 1, wherein The plurality of shift bit numbers of the plurality of second bit-wise shift operations and the at least one number of additions of the at least one addition operation of at least one group correspond to the corner frequency and the quality factor of the specific group.

9. A method having approximate multiplication capability, characterized in that: The method comprises: approximating at least one first multiplication operation corresponding to at least one first coefficient with at least one first bitwise shift operation; and approximating at least one second multiplication operation corresponding to at least one second coefficient using a plurality of second bitwise shift operations and at least one addition operation; The values ​​of a first shift number, a second shift number, and a third shift number in the at least one shift number of the at least one first bitwise shift operation and a specific set of a corner frequency and a quality factor are selected from a row of values ​​in Table 2 below when the corner frequency and the quality factor vary by less than 1%. Table 2 The changes in the values ​​of the corner frequency and the quality factor in Table 2 are less than 1%.

10. The method according to claim 9, wherein The at least one first bit-wise shift operation and the plurality of second bit-wise shift operations are implemented by wiring in an application specific integrated circuit.

11. The method according to claim 9, wherein Also includes: approximating each of the at least one first coefficients to a first term including only one "1" in a first binary expression; as well as approximating each of the at least one second coefficient into a plurality of second terms; The first term and each of the plurality of second terms include only one "1" in a second binary expression.

12. The method according to claim 9, wherein The at least one shifting bit amount of the at least one first bit-by-bit shifting operation corresponds to the corner frequency and the quality factor of the specific set.

13. The method according to claim 9, wherein When the corner frequency is substantially 1439.24 Hz at 48 kilosamples per second and the quality factor is substantially 0.707, the at least one first bitwise shift operation includes a first right shift of 7 bits, a first right shift of 6 bits, and a second right shift of 7 bits, a first operation step in the at least one second multiplication operation corresponds to a second right shift of 6 bits, a first right shift of 2 bits, a left shift of 1 bit, and two addition operations, and a second operation step in the at least one second multiplication operation corresponds to a third right shift of 6 bits, a second right shift of 2 bits, and an addition operation.

14. The method according to claim 9, wherein When a corresponding first coefficient of the at least one first coefficient is scaled, the values ​​of the first shift bit number, the second shift bit number, and the third shift bit number selected from the values ​​of the row in Table 2 are adaptively adjusted.

15. The method according to claim 14, wherein When the corner frequency is substantially 1439.24 Hz at 48 kilosamples per second and the quality factor is substantially 0.707, the at least one first bitwise shift operation includes a first right shift of 5 bits, a right shift of 4 bits, and a second right shift of 5 bits, a first operation step in the at least one second multiplication operation corresponds to a second right shift of 2 bits, a left shift of 1 bit, and an addition operation, and a second operation step in the at least one second multiplication operation corresponds to a right shift of 3 bits and an addition operation.

16. The method according to claim 9, wherein The plurality of shift bit numbers of the plurality of second bit-wise shift operations and the at least one number of additions of the at least one addition operation of at least one group correspond to the corner frequency and the quality factor of the specific group.

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