Latency-based instruction reservation in scheduler circuitry in a processor

Abstract

Latency-based instruction reservation clusters in a scheduler circuit in a processor are disclosed. The scheduler circuit includes a plurality of latency-based reservation circuits, each having an assigned producer instruction cycle latency. Producer instructions having the same cycle latency can be clustered in the same latency-based reservation circuit. Thus, the number of reservation entries is distributed among the plurality of latency-based reservation circuits to avoid or reduce the number of scheduler path connections and the increase in complexity in each reservation circuit to avoid or reduce the increase in scheduling latency. The number of scheduler path connections is reduced for a given number of reservation entries on a non-clustered selection circuit because the signals (e.g., wake-up signals, selection signals) used to schedule the instructions in each latency-based reservation circuit do not have to have the same clock cycle latency in order not to impact performance.

Description

TECHNICAL FIELD

[0001] The technology of this disclosure relates to computer processors (“processors”), and more specifically to scheduling of execution of instructions in an instruction pipeline in an instruction processing circuit in a processor. BACKGROUND

[0002] Microprocessors, also referred to as “processors,” perform computational tasks for a wide variety of applications. A conventional microprocessor includes a central processing unit (CPU) that includes one or more processor cores, also referred to as “CPU cores.” The CPU executes computer program instructions (“instructions”), also referred to as “software instructions,” to perform computations based on data and generate results that are produced values. Instructions that generate produced values are “producer” instructions. As an example, the produced values can then be stored in memory, provided as output to an input / output (“I / O”) device, or made available (i.e., communicatively) to another “consumer” instruction executed by the CPU as an input value for the consumer instruction to execute. Thus, the consumer instruction relies on the produced value produced by the producer instruction as an input value for the consumer instruction to execute. These producer and consumer instructions are also collectively referred to as dependent instructions.

[0003] An instruction pipeline is a processing technique whereby the throughput of instructions being executed by a processor can be increased by splitting the processing of each instruction into a series of steps. These steps are executed in one or more instruction pipelines that are composed of multiple stages in an instruction processing circuit in the processor. Optimal processor performance can be achieved if all stages in the instruction pipeline are able to process instructions simultaneously and sequentially as the instructions are ordered in the instruction pipeline. In addition, many modern processors are out-of-order processors that are not able to execute instructions based on the program order of the instructions, but are able to perform dataflow execution of instructions based on the availability of input data consumed by the instructions. Thus, an out-of-order processor can execute an instruction as soon as all of the input data that the instruction is to consume is produced. While dataflow order processing of instructions can cause the particular order in which the instructions are executed to be unpredictable, dataflow order execution in an out-of-order processor can achieve performance gains. For example, while input data to be consumed for an older instruction is being retrieved, an out-of-order processor can continue to execute more recently fetched instructions that are able to be executed immediately without having to “stall” (i.e., intentionally introduce processing delays). In this way, processor clock cycles that would otherwise not be utilized for instruction processing and execution can be effectively utilized by an out-of-order processor.

[0004] The instruction processing circuitry in a processor includes instruction fetch circuitry configured to fetch instructions to be executed from an instruction memory (e.g., system memory or instruction cache memory). As an example, the instruction memory can be provided in or as part of system memory in a processor-based system. The fetched instructions are decoded and inserted into an instruction pipeline in the instruction processing circuitry for pre-processing before reaching execution circuitry to be executed. The decoded instructions are also provided to reservation circuitry in a scheduler circuit. The scheduler circuit is configured to issue decoded instructions from the reservation circuitry to the execution circuitry to be executed once all source register operands (e.g., immediate values, values stored in memory, and values produced from producer instructions) are available and any structural hazards of the decoded instructions are resolved. For example, the scheduler circuit is responsible for ensuring that the necessary values for the operands of a decoded consumer instruction are available before issuing the decoded consumer instruction to the execution circuitry for execution. The execution circuitry is configured to execute the decoded instructions received from the scheduler circuit.

[0005] The scheduler circuit is configured to issue a wake-up signal to "wake up" a consumer instruction in response to issuing a producer instruction to the execution circuitry. The wake-up signal indicates that a produced value from execution of the issued producer instruction will be available, and thus the consumer instruction of the producer instruction can now be issued to the execution circuitry after the producer instruction. In other words, once a producer instruction is scheduled by the scheduler circuit to be issued from the reservation circuitry to the execution circuitry, it is known that a produced value from execution of the producer instruction will soon become available to its consumer instruction. Because the wake-up signal is generated in response to the producer instruction being issued, its consumer instruction can only be woken up at least one (1) clock cycle after the producer instruction, thereby guaranteeing that the producer instruction has executed before the consumer instruction is executed with the produced value of the consumer instruction. Thus, a critical timing path in the instruction processing circuitry in a processor is the wake-up path in the scheduler circuit to wake up instructions to be issued to the execution circuitry. The wake-up or scheduling latency of an instruction is the number of clock cycles after it is issued that its produced value is available for consumption by a consumer instruction. Some producer instructions are single-clock cycle ("single-cycle") latency producers, meaning that the execution circuitry can generate and make available a produced value for the producer instruction in one (1) clock cycle. Other producer instructions are multi-clock cycle latency producers, meaning that the execution circuitry generates and makes available a produced value for the producer instruction in more than one (1) clock cycle. An important part of the wake-up design in the scheduler circuit is to rely on consumer instructions of single-cycle latency producer instructions to be issued by the scheduler circuit in a back-to-back clock cycle with the producer instruction to reduce the scheduling latency.

[0006] Conventional scheduler circuitry includes a reservation circuit having "M" reservation entries to store M instructions waiting to be issued for execution. The scheduler circuitry also includes a selection circuit that controls when the M instructions in the reservation circuit are issued in issue lanes to be executed by execution circuitry. Each reservation entry in the reservation circuit is capable of receiving a wake-up signal from "K" producer instructions that are capable of being issued by the scheduler circuitry in each clock cycle. Thus, in this example, "M" is referred to as the instruction window size and "K" is referred to as the issue width of the execution circuitry or the number of issue lanes in which producer instructions can be issued to the execution circuitry to be executed. Generally, larger M entry size and larger K issue width are desirable to improve processor performance. As discussed above, an important part of the wake-up design in the scheduler circuitry is that a consumer instruction that depends on a single-cycle latency producer instruction can be issued within a back-to-back clock cycle with the producer instruction. The three (3) main components of the wake-up timing path in the scheduler circuitry that affect single-cycle wake-up are: (1) the propagation time (i.e., timing delay) to couple K wake-up signals from K issue lanes to the selection circuit due to the K producer instructions being issued in the issue lanes; (2) the propagation time through the selection circuit that employs a scheme to select K instructions from the M entries in the reservation circuit to issue; and (3) the propagation time to couple the K selection signals generated by the selection circuit to the M entries in the reservation circuit to select the K of the M entries to issue in the K issue lanes. It can be desirable to increase the instruction window size M in the reservation circuit in the instruction processing circuitry of a processor to improve processor performance. The larger the instruction window size, the more likely it is that K instructions are always ready to be issued in K issue lanes to maximize the efficiency of the execution circuitry. However, increasing the instruction window size M to improve performance adversely affects the latency of all three (3) components of the wake-up timing path. SUMMARY

[0007] Exemplary aspects disclosed herein include a latency-based instruction reservation cluster in a scheduler circuit in a processor. The processor includes an instruction processing circuit including a plurality of instruction processing stages configured to pipeline processing and execution of fetched instructions according to dataflow execution. A scheduler circuit is included in the instruction processing stages in the instruction processing circuit to schedule instructions to be executed to an execution circuit for execution. The scheduler circuit is responsible for issuing instructions to an issue lane for execution by the execution circuit once it is known that necessary values of the operand(s) of the instruction will be available at the time the instruction is executed. Thus, the scheduler circuit issues a consumer instruction once it is known that necessary produced value(s) from producer instruction(s) will be available before the consumer instruction is executed. The latency of a producer instruction is the number of clock cycles (“cycles”) after its issue that its produced value will be available for consumption by a consumer instruction. An ideal design of the scheduler circuit should be that a consumer instruction that depends on a single-cycle latency producer instruction can be issued in a back-to-back clock cycle with the producer instruction to improve performance. In addition, it can be desirable to increase the number of reservation entries in the scheduler circuit to improve scheduling performance as increasing reservation entries increases the likelihood that there will be enough instructions ready to be issued in each issue lane. However, increasing reservation entries in the scheduler circuit increases the number and complexity of the scheduling path connections in the scheduler circuit, which increases scheduling latency. The scheduling latency can increase such that all single-cycle latency producer instructions can not be issued by the scheduler circuit in a back-to-back clock cycle with the producer instruction.

[0008] Accordingly, in exemplary aspects disclosed herein, latency-based cluster scheduler circuitry ("cluster scheduler circuitry") is provided in instruction processing circuitry of a processor that includes multiple latency-based reservation circuits. Each latency-based reservation circuit has an assigned producer instruction cycle latency such that consumer instructions received in the scheduler circuitry that depend on a producer with a particular cycle latency can be clustered in the same latency-based reservation circuit. For example, consumer instructions that depend on a single cycle latency producer instruction will be clustered in the same latency-based reservation circuit that is designated with a one (1) clock cycle latency. As another example, consumer instructions that depend on a producer instruction with a three cycle latency will be clustered in another latency-based reservation circuit that is designated to reserve issue for three (3) clock cycle latency producer instructions. In this way, the number of reservation entries in the cluster scheduler circuitry is distributed among the multiple latency-based reservation circuits to avoid or reduce the number of scheduling path connections and the increase in complexity in each reservation circuit, thereby avoiding or reducing the increase in scheduling latency for a given number of reservation entries. The scheduling path connections are reduced for a given number of reservation entries on the non-clustered selection circuitry because the signals used to schedule the instruction signals (e.g., wake-up signals, selection signals) issued in each latency-based reservation circuit do not have to have the same clock cycle latency to avoid impacting performance. For example, a latency-based reservation circuit with an assigned cycle latency of two (2) clock cycles does not have to schedule a consumer instruction in back-to-back clock cycles with the issue of a producer instruction because the producer instruction will not generate a result in one (1) clock cycle. Accordingly, these signals used by the latency-based reservation circuits to schedule instructions can be isolated from each other at different cycle latencies, and thus only have to be coupled to their respective latency-based reservation circuits, thereby reducing the connection complexity. For example, a signal used to schedule instructions in a two (2) cycle latency based reservation circuit can have a clock cycle latency of two (2) clock cycles without impacting scheduling performance. However, a latency-based reservation circuit with an assigned cycle latency of one (1) clock cycle can only schedule a consumer instruction in back-to-back clock cycles with the issue of a producer instruction if the signal used to schedule such instructions does not have a clock cycle latency greater than one (1) clock cycle.

[0009] Accordingly, the latency-based instruction reservation clusters in the cluster scheduler circuit can allow the number of reservation entries in the scheduler circuit to increase while avoiding an increase in scheduling latency, or avoiding an increase in scheduling latency that is undesirable from a performance perspective. For example, the number of reservation entries in the scheduler circuit can be increased without risking that consumer instructions that depend on single-cycle latency producer instructions are not issued in back-to-back clock cycles. The total number of reservation entries in the scheduler circuit distributed across the plurality of latency-based reservation circuits can be increased according to any design parameters or goals to improve the performance of the processor compared to its performance if only one (1) non-clustered reservation circuit were provided in the scheduler circuit.

[0010] In one example, the pick circuits associated with respective latency-based reservation circuits in the cluster scheduler circuit are each configured to determine whether instructions in its associated latency-based reservation circuit are ready to be scheduled for execution based on the wake-up signals generated from the issue lane. The pick circuits associated with respective latency-based reservation circuits are also each configured to generate a pick signal to its associated latency-based reservation circuit in response to instructions being ready for execution to cause instructions ready to be executed in its associated latency-based reservation circuit to be inserted into the issue lane. In one example, to provide a signal for each latency-based reservation circuit to schedule instructions, each latency-based reservation circuit has a clock cycle latency within its respective latency-based reservation to not impact performance, the cluster scheduler circuit includes a plurality of wake-up signal registers, each wake-up signal register associated with a latency-based reservation circuit and configured to store a cycle latency wake-up signal generated from the issue lane for use by the respective pick circuit to wake up instructions in its respective latency-based reservation circuit. In another example, to provide a signal for each latency-based reservation circuit to schedule instructions, each latency-based reservation circuit has a clock cycle latency within its respective latency-based reservation to not impact performance, the cluster scheduler circuit includes a plurality of pick signal registers, each pick signal register associated with a latency-based reservation circuit and configured to store a cycle latency pick signal generated from the respective latency-based reservation circuit to pick which instructions from the latency-based reservation circuit are issued to the common issue lane.

[0011] In this regard, in one example aspect, a cluster scheduler circuit in a processor is disclosed that is configured to receive a plurality of instructions including producer instructions and consumer instructions to be scheduled for execution. The cluster scheduler circuit includes a first latency-based reservation circuit configured to receive a first consumer instruction dependent on a producer instruction having a single clock cycle latency among the plurality of instructions. The first latency-based reservation circuit is further configured to store the first consumer instruction in a first reservation entry among a plurality of first reservation entries and to select a plurality of first consumer instructions stored among the plurality of first reservation entries identified as having a publish state of publish ready. The cluster scheduler circuit further includes a first pick circuit coupled to the plurality of first reservation entries and a single clock cycle latency wake signal port. The first pick circuit is configured to receive a plurality of single clock cycle latency wake signals on the single clock cycle latency wake signal port, each single clock cycle latency wake signal associated with one of a plurality of publish lanes, the plurality of single clock cycle latency wake signals each indicating a publish state of a single clock cycle latency producer instruction in one of the plurality of publish lanes. The first pick circuit is further configured to determine whether the plurality of first consumer instructions are ready to be scheduled for execution in response to the plurality of single clock cycle latency wake signals being associated with single clock cycle latency producer instructions of the plurality of first consumer instructions having the publish state of publish ready. The first pick circuit is configured to identify the plurality of first consumer instructions having the publish state of publish ready. The cluster scheduler circuit further includes a second latency-based reservation circuit configured to receive a second consumer instruction dependent on a producer instruction having a same second clock cycle latency of at least two (2) clock cycles among the plurality of instructions. The second latency-based reservation circuit is further configured to store the second consumer instruction in a second reservation entry among a plurality of second reservation entries. The second latency-based reservation circuit is further configured to select a plurality of second consumer instructions stored among the plurality of second reservation entries identified as having a publish state of publish ready. The cluster scheduler circuit further includes a second pick circuit coupled to the plurality of second reservation entries and a second clock cycle latency wake signal port. The second pick circuit is configured to receive a plurality of second clock cycle latency wake signals on the second clock cycle latency wake signal port, each second clock cycle latency wake signal associated with one of the plurality of publish lanes. The plurality of second clock cycle latency wake signals each indicate a publish state of a second clock cycle latency producer instruction in one of the plurality of publish lanes. The second pick circuit is further configured to determine whether the plurality of second consumer instructions are ready to be scheduled for execution in response to the plurality of second clock cycle latency wake signals being associated with second clock cycle latency producer instructions of the plurality of second consumer instructions having the publish state of publish ready. The second pick circuit is further configured to identify the plurality of second consumer instructions having the publish state of publish ready.The cluster scheduler circuit also includes a plurality of issue arbitration circuits, each issue arbitration circuit coupled to an associated issue lane among the plurality of issue lanes and coupled to the first latency-based reservation circuit and the second latency-based reservation circuit. The plurality of issue arbitration circuits are each configured to pass instructions among the selected plurality of first consumer instructions and the selected plurality of second consumer instructions to its associated issue lane. The cluster scheduler circuit also includes a plurality of issue lane circuits including the plurality of issue lanes. Each issue lane circuit among the plurality of issue lane circuits is configured to generate, on a single-cycle-latency wake-up signal port, a single-cycle-latency wake-up signal among the plurality of single-cycle-latency wake-up signals having an issue-ready issue state in response to a single-cycle-latency producer instruction issued in the issue lane circuit.

[0012] In another example aspect, a method of scheduling a plurality of instructions including producer instructions and consumer instructions to be executed in an execution circuit in a processor is disclosed. The method includes receiving a first consumer instruction dependent on a producer instruction having a single clock cycle latency among the plurality of instructions. The method also includes storing the first consumer instruction in a first reservation entry among a plurality of first reservation entries. The method also includes receiving a plurality of single clock cycle latency wake signals each associated with one of a plurality of issue lanes, the plurality of single clock cycle latency wake signals each indicating an issue state of a single clock cycle latency producer instruction in one of the plurality of issue lanes. The method also includes determining whether the plurality of first consumer instructions are ready to be scheduled for execution in response to the plurality of single clock cycle latency wake signals being associated with the single clock cycle latency producer instruction of the plurality of first consumer instructions having an issue ready issue state. The method also includes identifying the plurality of first consumer instructions having the issue ready issue state. The method also includes selecting the plurality of first consumer instructions stored in the plurality of first reservation entries identified as having the issue ready issue state. The method also includes receiving a second consumer instruction dependent on a producer instruction having a same second clock cycle latency of at least two (2) clock cycles among the plurality of instructions. The method also includes storing the second consumer instruction in a second reservation entry among a plurality of second reservation entries. The method also includes receiving a plurality of second clock cycle latency wake signals each associated with one of the plurality of issue lanes, the plurality of second clock cycle latency wake signals each indicating an issue state of a second clock cycle latency producer instruction in one of the plurality of issue lanes. The method also includes selecting the plurality of second instructions stored in the plurality of second reservation entries identified as having the issue ready issue state. The method also includes determining whether the plurality of second consumer instructions are ready to be scheduled for execution in response to the plurality of second clock cycle latency wake signals being associated with the second clock cycle latency producer instruction of the plurality of second consumer instructions having the issue ready issue state. The method also includes identifying the plurality of second consumer instructions having the issue ready issue state. The method also includes passing instructions among the selected plurality of first consumer instructions and the selected plurality of second consumer instructions to their associated issue lanes. The method also includes generating a single clock cycle latency wake signal among the plurality of single clock cycle latency wake signals having the issue ready issue state in response to the issued single clock cycle latency producer instruction.

[0013] In another example aspect, a processor is disclosed that includes instruction processing circuitry including one or more instruction pipelines. The instruction processing circuitry includes cluster scheduler circuitry and execution circuitry. The instruction processing circuitry is configured to fetch a plurality of instructions from a memory into an instruction pipeline of the one or more instruction pipelines. The cluster scheduler circuitry is configured to receive the plurality of instructions including producer instructions and consumer instructions to be scheduled for execution. The cluster scheduler circuitry includes first latency-based reservation circuitry configured to receive a first consumer instruction dependent on a producer instruction having a single clock cycle latency among the plurality of instructions. The first latency-based reservation circuitry is further configured to store the first consumer instruction in a first reservation entry among a plurality of first reservation entries. The first latency-based reservation circuitry is further configured to select a plurality of first consumer instructions stored among the plurality of first reservation entries identified as having a release state of release ready. The cluster scheduler circuitry further includes first selection circuitry coupled to the plurality of first reservation entries and a single clock cycle latency wake signal port. The first selection circuitry is configured to receive a plurality of single clock cycle latency wake signals on the single clock cycle latency wake signal port, each single clock cycle latency wake signal associated with one of a plurality of release lanes, the plurality of single clock cycle latency wake signals each indicating a release state of a single clock cycle latency producer instruction in a release lane among the plurality of release lanes. The first selection circuitry is further configured to determine whether the plurality of first consumer instructions are ready to be scheduled for execution in response to the plurality of single clock cycle latency wake signals being associated with a plurality of single clock cycle latency producer instructions of the plurality of first consumer instructions having the release state of release ready. The first selection circuitry is further configured to identify the plurality of first consumer instructions having the release state of release ready. The cluster scheduler circuitry further includes second latency-based reservation circuitry configured to receive a second consumer instruction dependent on a producer instruction having a same second clock cycle latency of at least two (2) clock cycles among the plurality of instructions. The second latency-based reservation circuitry is further configured to store the second consumer instruction in a second reservation entry among a plurality of second reservation entries. The second latency-based reservation circuitry is further configured to select a plurality of second consumer instructions stored among the plurality of second reservation entries identified as having a release state of release ready. The cluster scheduler circuitry further includes second selection circuitry coupled to the plurality of second reservation entries and a second clock cycle latency wake signal port. The second selection circuitry is configured to receive a plurality of second clock cycle latency wake signals on the second clock cycle latency wake signal port, each second clock cycle latency wake signal associated with one of the plurality of release lanes, the plurality of second clock cycle latency wake signals each indicating a release state of a second clock cycle latency producer instruction in one of the plurality of release lanes.The second selection circuit is further configured to determine whether the plurality of second consumer instructions are ready to be dispatched for execution in response to the plurality of single-cycle-latency wake-up signals being associated with the plurality of second consumer instructions having an issue ready state of issue ready. The second selection circuit is further configured to identify the plurality of second consumer instructions having an issue ready state of issue ready. The cluster scheduler circuit further includes a plurality of issue arbitration circuits, each issue arbitration circuit coupled to an associated issue lane among the plurality of issue lanes and coupled to the first latency-based reservation circuit and the second latency-based reservation circuit. The plurality of issue arbitration circuits are each configured to pass instructions among the selected plurality of first consumer instructions and the selected plurality of second consumer instructions to its associated issue lane. The cluster scheduler circuit further includes a plurality of issue lane circuits including the plurality of issue lanes. Each issue lane circuit among the plurality of issue lane circuits is configured to generate a single-cycle-latency wake-up signal among the plurality of single-cycle-latency wake-up signals having an issue ready state of issue ready on a single-cycle-latency wake-up signal port in response to a single-cycle-latency producer instruction issued in the issue lane circuit.

[0014] Those skilled in the art will appreciate the scope of the present disclosure and practices additional aspects thereof upon reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings incorporated in and forming a part of the specification illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0016] Figure 1 is a diagram of an exemplary processor-based system including a processor having an instruction processing circuit including one or more instruction pipelines for processing computer instructions for execution, where the instruction processing circuit includes a scheduler circuit configured to store and schedule instructions for issue to an execution circuit for execution;

[0017] Figure 2A is a diagram of an exemplary non-clustered scheduler circuit that can be included in the instruction processing circuit of Figure 1 the instruction processing circuit of

[0018] Figure 2B-1 is a timing diagram illustrating Figure 2A reservation, issue, and execution of a single-cycle-latency producer instruction and consumer instructions in the non-clustered scheduler circuit of

[0019] Figure 2B-2 is a diagram illustratingFigure 2A a timing diagram illustrating exemplary clock cycle timing of reservation, issuance, and execution of single clock cycle latency producer instructions and consumer instructions in a cluster scheduler circuit in

[0020] Figure 3A is a schematic diagram of an exemplary latency-based instruction reservation cluster scheduler circuit ("cluster scheduler circuit") including a plurality of latency-based reservation circuits each configured to gather same cycle latency consumer instructions that are dispatched by a respective pick circuit to issue to a common issue channel for execution by an execution circuit, wherein the cluster scheduler circuit includes a plurality of wake signal registers each associated with a latency-based reservation circuit and configured to store a cycle delayed wake signal generated from the issue channel that is used by the respective pick circuit to wake instructions in its respective latency-based reservation circuit;

[0021] Figure 3B-1 is a timing diagram illustrating exemplary clock cycle timing of reservation, issuance, and execution of 3 clock cycle latency producer instructions and consumer instructions in a cluster scheduler circuit in Figure 3A

[0022] Figure 3B-2 is a timing diagram illustrating exemplary clock cycle timing of reservation, issuance, and execution of single clock cycle latency producer instructions and consumer instructions in a cluster scheduler circuit in Figure 3A

[0023] Figure 4A and Figure 4B is a flowchart illustrating an exemplary process of a cluster scheduler circuit in an instruction processing circuit in a processor that assigns consumer instructions to latency-based reservation circuits based on the cycle latency of their producer instructions and dispatches instructions in the latency-based reservation circuits to issue to a common issue channel for execution in an execution circuit;

[0024] Figure 5A is a diagram of another exemplary cluster scheduler circuit including a plurality of latency-based reservation circuits each configured to gather same cycle latency consumer instructions that are dispatched by a respective pick circuit to issue to a common issue channel for execution by an execution circuit, wherein the cluster scheduler circuit includes a plurality of pick signal registers each associated with a latency-based reservation circuit and configured to store a cycle delayed pick signal generated from the respective latency-based reservation circuit to pick which instructions in the latency-based reservation circuit are issued to the common issue channel;

[0025] Figure 5B-1 is a timing diagram illustrating exemplary clock cycle timing of reservation, issuance, and execution of single clock cycle latency producer instructions and consumer instructions in a cluster scheduler circuit in Figure 5A ​​is a timing diagram illustrating exemplary clock cycle timing of reservation, issuance, and execution of single clock cycle latency producer instructions and consumer instructions in a cluster scheduler circuit in

[0026] Figure 5B-2 is a timing diagram illustrating exemplary clock cycle timing of reservation, issuance, and execution of 3 clock cycle latency producer instructions and consumer instructions in a cluster scheduler circuit in Figure 5A

[0027] Figure 6A is a diagram of another exemplary cluster scheduler circuit including a plurality of latency-based reservation circuits, each circuit configured to gather same-cycle latency consumer instructions that are dispatched by a corresponding pick circuit to issue to a common issue channel for execution by an execution circuit, where the cluster scheduler circuit includes: a plurality of wake signal registers, similar to Figure 3A the cluster scheduler circuit in Figure 5A , each register associated with a corresponding latency-based reservation circuit; and a plurality of pick signal registers, similar to

[0028] Figure 6B-1 is a timing diagram illustrating exemplary clock cycle timing of reservation, issuance, and execution of single clock cycle latency producer instructions and consumer instructions in a cluster scheduler circuit in Figure 6A

[0029] Figure 6B-2 is a timing diagram illustrating exemplary clock cycle timing of reservation, issuance, and execution of 3 clock cycle latency producer instructions and consumer instructions in a cluster scheduler circuit in Figure 6A

[0030] Figure 7 is a block diagram of an exemplary processor-based system including a processor having an instruction processing circuit including a latency-based cluster scheduler circuit including a plurality of latency-based reservation circuits, each latency-based reservation circuit configured to gather same-cycle latency consumer instructions that are dispatched by a corresponding scheduler circuit to issue to a common issue channel for execution by an execution circuit, including but not limited to Figure 3A , Figure 5A and Figure 6A the latency-based cluster scheduler circuits in DETAILED DESCRIPTION

[0031] ​​​Exemplary aspects disclosed herein include a latency-based instruction reservation cluster in a scheduler circuit in a processor. The processor includes an instruction processing circuit including a plurality of instruction processing stages configured to pipeline processing and execution of fetched instructions according to dataflow execution. A scheduler circuit is included in the instruction processing stages in the instruction processing circuit to schedule instructions to be executed to an execution circuit for execution. The scheduler circuit is responsible for issuing instructions to an issue lane for execution by the execution circuit once it is known that necessary values of the operand(s) of the instruction will be available at the time the instruction is executed. Thus, the scheduler circuit issues a consumer instruction once it is known that necessary produced value(s) from producer instruction(s) will be available before the consumer instruction is executed. The latency of a producer instruction is the number of clock cycles ("cycles") after its issue that its produced value will be available for consumption by a consumer instruction. An ideal design of the scheduler circuit should be that a consumer instruction that depends on a single-cycle latency producer instruction can be issued in a back-to-back clock cycle with the producer instruction to improve performance. In addition, it can be desirable to increase the number of reservation entries in the scheduler circuit to improve scheduling performance as increasing reservation entries increases the likelihood that there will be enough instructions ready to be issued in each issue lane. However, increasing reservation entries in the scheduler circuit increases the number and complexity of the scheduling path connections in the scheduler circuit, which increases scheduling latency. The scheduling latency can increase such that all single-cycle latency producer instructions can not be issued by the scheduler circuit in a back-to-back clock cycle with the producer instruction.

[0032] Accordingly, in exemplary aspects disclosed herein, a latency-based cluster scheduler circuit ("cluster scheduler circuit") is provided in an instruction processing circuit of a processor that includes a plurality of latency-based reservation circuits. Each latency-based reservation circuit has an assigned producer instruction cycle latency such that consumer instructions received in the scheduler circuit that depend on a producer with a particular cycle latency can be clustered in the same latency-based reservation circuit. For example, consumer instructions that depend on a single cycle latency producer instruction will be clustered in the same latency-based reservation circuit that is designated with a one (1) clock cycle latency. As another example, consumer instructions that depend on a producer instruction with a three cycle latency will be clustered in another latency-based reservation circuit that is designated to reserve issue for three (3) clock cycle latency producer instructions. In this manner, the number of reservation entries in the cluster scheduler circuit is distributed among the plurality of latency-based reservation circuits to avoid or reduce the number of scheduling path connections and the increase in complexity in each reservation circuit, thereby avoiding or reducing the increase in scheduling latency for a given number of reservation entries. The scheduling path connections are reduced for a given number of reservation entries on the non-clustered selection circuit because the signals used to schedule the instructions issued in each latency-based reservation circuit (e.g., wake-up signals, selection signals) do not have to have the same clock cycle latency to avoid impacting performance. For example, a latency-based reservation circuit with an assigned cycle latency of two (2) clock cycles does not have to schedule a consumer instruction in back-to-back clock cycles with the issue of a producer instruction because the producer instruction will not generate a result in one (1) clock cycle. Accordingly, these signals used by the latency-based reservation circuits to schedule instructions can be isolated from each other at different cycle latencies, and thus only have to be coupled to their respective latency-based reservation circuits, thereby reducing the connection complexity. For example, a signal used to schedule instructions in a two (2) cycle latency based reservation circuit can have a clock cycle latency of two (2) clock cycles without impacting scheduling performance. However, a latency-based reservation circuit with an assigned cycle latency of one (1) clock cycle can only schedule a consumer instruction in back-to-back clock cycles with the issue of a producer instruction if the signal used to schedule such instructions does not have a clock cycle latency greater than one (1) clock cycle.

[0033] Figure 1 is a schematic diagram of an exemplary processor-based system 100 that includes a processor 102. As discussed in greater detail below, the processor 102 includes an instruction processing circuit 104 that includes one or more instruction pipelines 10-14 for processing computer instructions for execution NAs will be discussed in greater detail below, instruction processing circuit 104 includes a scheduler circuit 106 configured to store and schedule instructions to be issued to execution circuit 108 for execution. As will also be discussed in greater detail below, scheduler circuit 106 can be a latency-based instruction reservation cluster scheduler circuit (“cluster scheduler circuit”) that includes a plurality of latency-based reservation circuits, each configured to gather identical cycle latency consumer instructions that are scheduled for issue to a common issue lane for execution by execution circuit 108. The number of reservation entries required for a reservation to wait for its operands to be ready before being passed to execution circuit 108 for execution is distributed among the plurality of latency-based reservation circuits to avoid or reduce an increase in the number of scheduling path connections and complexity in each reservation circuit to avoid or reduce an increase in scheduling latency for a given number of reservation entries.

[0034] Reference is made to Figure 1 As an example, processor 102 can be an in-order or out-of-order processor (OoP). Processor 102 includes instruction processing circuit 104. Instruction processing circuit 104 includes instruction fetch circuit 110 configured to fetch instructions 112 from instruction memory 114. As an example, instruction memory 114 can be provided in or as part of system memory in processor-based system 100. Instruction cache 116 can also be provided in processor 102 to cache instructions 112 fetched from instruction memory 114 to reduce latency in instruction fetch circuit 110. Instruction fetch circuit 110 in this example is configured to provide instructions 112 as fetched instructions 112F to one or more instruction pipelines I0-I N As instructions 112F are pre-processed in instruction flow 118 in instruction processing circuit 104. Fetched instructions 112F in instruction flow 118 include producer instructions and consumer instructions that consume produced values as a result of execution of producer instructions by instruction processing circuit 104. Instruction pipelines I0-I N To pre-process and process fetched instructions 112F in a series of steps that can be executed concurrently to increase throughput before execution circuit 108 executes fetched instructions 112F. For example, fetched store-based instructions 112F identified in instruction flow 118 as having a store-forwarded load can be identified by store-forwarded load tracker circuit 120 in instruction processing circuit 104 before being executed to be forwarded for consumption by fetched load-based consumer instructions 112F.

[0035] Figure 1The instruction processing circuit 104 in the processor 102 in the system 100 also provides a control flow prediction circuit 122 (e.g., a branch prediction circuit) to speculate or predict the outcome of the predicate of fetched conditional control instructions 112F, such as conditional branch instructions, that affect the instruction control flow path of the instruction stream 118 being processed in the instruction pipeline I0-I N The instruction fetch circuit 110 can use the prediction of the control flow prediction circuit 122 to determine the next fetched instruction 112F to fetch based on the predicted target address. The instruction processing circuit 104 also includes an instruction decode circuit 124 configured to decode the fetched instruction 112F fetched by the instruction fetch circuit 110 into a decoded instruction 112D to determine the required instruction type and action. The required instruction type and action encoded in the decoded instruction 112D can also be used to determine in which instruction pipeline I0-I N the decoded instruction 112D should be placed. In this example, the decoded instruction 112D is placed in one or more of the instruction pipelines I0-I N and is next provided to a rename circuit 126 in the instruction processing circuit 104. The rename circuit 126 is configured to determine whether any register names in the decoded instruction 112D need to be renamed to break any register dependencies that would prevent parallel or out-of-order processing. The rename circuit 126 is configured to invoke a register map table (RMT) 128 to rename logical source register operands and / or write destination register operands of the decoded instruction 112D to available physical registers 130(1)-130(X) (P0, P1,..., P X ) in a physical register file (PRF) 132. The RMT 128 contains a plurality of mapping entries, each mapping to a respective logical register R0-R P (i.e., associated with). The mapping entries are configured to store information in the form of an address pointer to point to a physical register 130(1)-130(X) in the physical register file (PRF) 132. Each physical register 130(1)-130(X) in the PRF 132 contains a data entry configured to store data for a source and / or destination register operand of a decoded instruction 112D.

[0036] Figure 1 The instruction processing circuit 104 in the processor 102 in the system 100 also includes a register access circuit 134 prior to the scheduler circuit 106. The register access circuit 134 is configured to access the data stored in the physical registers 130(1)-130(X) in the PRF 132 based on the logical registers R0-R PThe mapping entries are used to access physical registers 130(1)-130(X) in PRF 132 to retrieve the generated value from the executed instruction 112E in execution circuit 108. Register access circuit 134 is also configured to provide the generated value retrieved from the executed decode instruction 112E as the source register operand for the decode instruction 112D to be executed. In addition, in instruction processing circuit 104, scheduler circuit 106 is provided in instruction pipeline I0-I N It is also configured to store the decoding instruction 112D in a reserved entry until all source register operands of the decoding instruction 112D are available. For example, the scheduler circuit 106 is responsible for publishing channels L0-L out of "K" publishing channels. K-1 The decoded consumer instruction 112D is sent to the execution circuit 108 to ensure that the necessary values ​​of the operands for the decoded consumer instruction 112D are available before execution. The scheduler circuit 106 sends the decoded instruction 112D, ready to be executed, to the execution circuit 108. This is done via channels L0-L. K-1 The number is usually less than the number of reserved entries in scheduler circuit 106, therefore scheduler circuit 106 uses circuitry to assign entries to distribution channels L0-L according to the distribution scheme. K-1 The decoded instruction 112D is prepared to be executed. The release scheme can be based on the delay of the producer instruction(s) that generate values ​​for the source operand of the decoded instruction 112D. For example, a producer instruction that can be executed by the execution circuit 108 and make its production data available in one (1) clock cycle is a producer instruction with a single clock cycle delay. The execution circuit 108 may include multiple execution stages to execute producer instructions that require more than one (1) clock cycle to execute. The source operand of the decoded instruction 112D may include an immediate value, a value stored in memory, and a value generated from other decoded instructions 112D, which will be regarded as a producer instruction for the consumer instruction. The execution circuit 108 is configured to execute the producer instructions from the scheduler circuit 106 in the release channels L0-L1. K-1 The decoding instruction 112D is issued in the instruction processing circuit 104. A write circuit 136 is also provided in the instruction processing circuit 104 to write back or commit the generated value from the execution instruction 112E to memory, such as PRF 132, cache memory or system memory.

[0037] Figure 2A This is a diagram of an exemplary scheduler circuit 200, which can be as follows: Figure 1An exemplary component of the scheduler circuit 200 is illustrated using the same method as the scheduler circuit 106 in the instruction processing circuit 104. The scheduler circuit 200 includes a reservation circuit 202, which in this example includes "M" reservation entries 204(0)-204(M-1). The reservation entries 204(0)-204(M-1) are configured to store received instructions in the instruction pipeline(s) until they are ready to be executed in the execution circuit 205. The scheduler circuit 200 is configured to issue instructions ready to be executed to the corresponding execution channels E0-E0 in the execution circuit 205. K-1 Coupled publishing channel L0-L K-1 One of them. The execution circuit 205 is designed to receive and simultaneously execute on K publishing channels L0-L K-1 The system dispatches "K" instructions and provides K execution channels E0-E0. K-1 To improve performance. Therefore, in this example, "M" refers to the command window size, and "K" refers to the release width or release channel L0-L. K-1 The number of times the producer instructions can be issued to the execution circuit 205 for execution. If the scheduler circuit 200 is as follows... Figure 1 If the scheduler circuit 106 is included as described above, then reserved entries 204(0)-204(M-1) will be configured to store data from instruction pipelines I0-I N The decoded instruction 112D is then passed to the execution circuit 108 for execution. Reserved entries 204(0)-204(M-1) store producer instructions and their consumer instructions. The scheduler circuit 200 ensures that the producer instructions and their consumer instructions are published on channels L0-L0. K-1 Before being published, it was published to the publication channel L0-L. K-1 The execution is carried out by the execution circuit 205. The scheduler circuit 200 is a synchronous circuit that is configured to operate and execute functions within the period of its processor's clock signal.

[0038] Continue to refer to Figure 2A The scheduler circuit 200 also includes a selection circuit 206 that tracks instructions in reservation entries 204(0)-204(M-1) to determine when such instructions are ready to be published. In this regard, each reservation entry 204(0)-204(M-1) is coupled to a ready circuit 208 in the selection circuit 206, as indicated by tracking lines 210(0)-210(M-1), each tracking line 210(0)-210(M-1) capable of transmitting tracking information about the instructions stored in the corresponding reservation entry 204(0)-204(M-1). The ready circuit 208 is also coupled to K publishing channel circuits 214(0)-214(K-1) in the corresponding publishing channels L0-L0.K-1 K wake-up signals 212(0)-212(K-1) are generated among the K wake-up signal ports 215. Each wake-up signal 212(0)-212(K-1) is associated with a respective issue lane L0-L K-1 Each issue lane circuit 214(0)-214(K-1) associated with a respective issue lane L0-L K-1 The producer instruction is issued among the issue lanes L0-L K-1 The wake-up signal 212(0)-212(K-1) indicates the issue state as issue-ready or issue-not-ready. When the producer instruction is issued by the scheduler circuit 200 among the issue lanes L0-L K-1 The ready circuit 208 in the pick circuit 206 is configured to compare the wake-up signal 212(0)-212(K-1) having the issue state indicating the issue-ready of the issued producer instruction to the M instructions in the respective reservation entry 204(0)-204(M-1) to determine whether any such instruction is ready to be executed. For example, if an instruction reservation entry 204(0)-204(M-1) is a consumer of the issued producer instruction, the indication of the issue of the producer instruction by the wake-up signal 212(0)-212(K-1) indicates that data from that producer instruction will become available and thus the consumer instruction can be issued if no other source operand is unavailable. The ready circuit 208 is configured to generate M instruction ready signals 216(0)-216(M-1) indicating whether the instructions in the respective reservation entry 204(0)-204(M-1) are ready to be issued based on comparing the wake-up signal 212(0)-212(K-1) of the issued producer instruction to the M instructions in the respective reservation entry 204(0)-204(M-1).

[0039] With continued reference to Figure 2AThe selection circuit 206 includes K selection circuits 218(0)-218(K-1) configured to receive the M instruction ready signals 216(0)-216(M-1) from the ready circuit 208 and generate corresponding K issue lane selection signals 220(0)-220(K-1) to identify the respective instructions in the reserved entries 204(0)-204(M-1) indicated by the issue state of the issue ready to be issued. If K is not equal to M, then providing the M instruction ready signals 216(0)-216(M-1) to the K selection circuits 218(0)-218(K-1) involves multiplexing of the signals. As discussed above, traditionally, K < M because the execution circuit, such as the execution circuit 205, is not typically designed to be able to execute M instructions at the same time and it is unlikely to be necessary to achieve the desired performance because M instructions can not be ready to issue every clock cycle. The K issue lane selection signals 220(0)-220(K-1) are provided to K issue select circuits 222(0)-222(K-1) in the reservation circuit 202 and each is coupled to a respective issue lane L0-L K-1 The issue select circuits 220(0)-220(K-1) are each coupled to the reserved entries 204(0)-204(M-1) such that if K is not equal to M, then the M reserved entries 204(0)-204(M-1) are multiplexed into the K issue select circuits 220(0)-220(K-1). The issue select circuits 222(0)-222(K-1) are configured to select an instruction from the reserved entries 204(0)-204(M-1) in response to the instruction having an issue ready identified in the respective issue lane selection signal 220(0)-220(K-1). The issue select circuits 222(0)-222(K-1) are each configured to provide the instruction identified in the respective issue lane selection signal 220(0)-220(K-1) to be issued to the respective associated issue lane L0-L K-1 for execution in the execution circuit 205. K-1

[0040] To further illustrate the issuance of instructions in the scheduler circuit 200 in Figure 2A , timing diagrams are provided in Figure 2B-1 and Figure 2B-2 . Figure 2B-1 is a timing diagram 224 illustrating exemplary clock cycle timing of the reservation, issuance, and execution of a single clock cycle latency producer instruction and a consumer instruction issued by the scheduler circuit 200 in Figure 2A . Figure 2B-2 is a timing diagram 226 illustrating exemplary clock cycle timing of the reservation, issuance, and execution of a single clock cycle latency producer instruction and a consumer instruction issued by the scheduler circuit 200 in Figure 2A ​Timing diagram 226 shows an exemplary clock cycle timing of the reservation, issuance, and execution of producer and consumer instructions over three (3) clock cycles issued by the scheduler circuit 200 in the middle.

[0041] refer to Figure 2B-1 Timing diagram 224 is shown in tabular form, which includes clock cycles 1, 2, 3, 4, and 5 along the X-axis and pipeline stages in the instruction processing circuitry along the Y-axis. The pipeline stages shown are reservations (RSV) for the reservation stage shown in scheduler circuit 200. Figure 2A The publishing channel L0-L K-1 The release phase shown is the release (ISSUE), and the execution phases A0-A2, which are illustrated as up to three (3) execution phases in execution circuit 205, executed over three (3) clock cycles. As previously mentioned... Figure 1 Some of the producer instructions discussed are single-clock-cycle delay instructions because the data they produce is generated by an execution circuit, such as execution circuit 205, in one execution phase and therefore in one (1) clock cycle. Other producer instructions are multi-clock-cycle delay instructions because the data they produce is generated by an execution circuit, such as execution circuit 205, in more than one execution phase and therefore in more than (1) clock cycles.

[0042] like Figure 2B-1 As shown, timing diagram 224 includes "P" in the clock cycle 1 release phase, representing Figure 2A The publishing channel L0-L K-1 The producer instruction previously issued by scheduler circuit 200. Delay = 1 means that the producer instruction is a (1) clock cycle delayed instruction. The consumer instruction represented by “C” of producer instruction P is also in clock cycle 1, which indicates that consumer instruction C is stored in the clock cycle 1. Figure 2A In the reserved circuit 202, reserved entries 204(0)-204(M-1) are used. In response to the producer instruction P, in clock cycle 1, in the publishing channels L0-L... K-1 In this process, a wake-up signal, represented by wake-up signal 212, is generated and transmitted to the selection circuit 206 in the scheduler circuit 200 to identify the producer instruction P, which indicates the published status. As shown in timing diagram 224 in clock cycle 2, the producer instruction P is shifted to... Figure 2A The first execution stage A0 in the execution circuit 205. Consumer instruction C is generated by... Figure 2A The scheduler circuit 200 is published to the publish channel L0-L in a back-to-back clock cycle with the producer instruction P. K-1. The ability to issue a consumer instruction that depends on a single clock cycle latency producer instruction in a back-to-back clock cycle is very efficient. Since the producer instruction P in this example is a single clock cycle latency producer instruction, the data generated by the execution of the producer instruction P is available to the consumer instruction C in clock cycle 2. Thus, the consumer instruction C can consume the data generated by the execution of the producer instruction P in clock cycle 3 in its execution.

[0043] Figure 2B-2 The timing diagram 226 in clock cycle 1 also includes the producer instruction P that was previously issued by the scheduler circuit 200 in clock cycle 0. Figure 2A The issue lanes L0-L K-1 The producer instruction P in clock cycle 1 in the issue stage means that the producer instruction P is not yet fully executed in the execution circuit 205 in the Figure 2B-2 The producer instruction P in clock cycle 1 in the issue stage means that the producer instruction P is not yet fully executed in the execution circuit 205 in the Figure 2A The producer instruction P in clock cycle 1 in the issue stage means that the producer instruction P is not yet fully executed in the execution circuit 205 in the Figure 2A The consumer instruction C in clock cycle 1 in the issue stage means that the consumer instruction C is stored in the reservation entries 204(0)-204(M-1) in the reservation circuit 202 in K-1 In response to the producer instruction P in clock cycle 1 in the issue lanes L0-L Figure 2B-2 The wake-up signal represented by the wake-up signal 212 is generated and communicated to the pick circuit 206 in the scheduler circuit 200 to identify the producer instruction P with the issue state indicating issued in clock cycle 2. Figure 2A The producer instruction P is shifted to the first execution stage A0 in the execution circuit 205 in clock cycle 2. The consumer instruction C is not issued by the scheduler circuit 200 in the issue lanes L0-L Figure 2A The producer instruction P is not yet fully executed in the execution circuit 205 in clock cycle 2. The consumer instruction C is not issued by the scheduler circuit 200 in the issue lanes L0-L K-1 The wake-up signal represented by the wake-up signal 212 is generated and communicated to the pick circuit 206 in the scheduler circuit 200 to identify the producer instruction P with the issue state indicating issued in clock cycle 2. Figure 2B-2 The wake-up signal 212 generated in clock cycle 1 is unnecessary since the data from the execution of the producer instruction does not occur until clock cycle 4. Thus, the wake-up signal 212 can be generated as late as clock cycle 3 and the data from the execution of the producer instruction is still available to the consumer instruction in clock cycle 4.

[0044] Referring back to the timing diagram 226 in clock cycle 3, the wake-up signal 212 is generated and communicated to the pick circuit 206 in the scheduler circuit 200 to identify the producer instruction P with the issue state indicating issued. The producer instruction P is shifted to the second execution stage A1 in the execution circuit 205 in clock cycle 4. The consumer instruction C is not issued by the scheduler circuit 200 in the issue lanes L0-L Figure 2AIt might be desirable to increase "M" to provide more reserved entries in scheduler circuit 200 and a larger "K" release width to improve performance. As discussed above, an important part of the wake-up design in scheduler circuit 200 is that scheduler circuit 200 can release consumer instructions that depend on single-cycle delay producer instructions in back-to-back clock cycles with producer instructions. The timing path affecting single-cycle wake-up... Figure 2A The three main components of the wake-up timing path in the scheduler circuit 200 are: (1) due to the publication channel L0-L K-1 Up to K producer instructions are published, thus coupling from K publish channels L0-L K-1 The delay of the K wake-up signals 212(0)-212(K-1) to the selection circuit 206; (2) the scheduling delay of the selection circuit 206 in selecting K instructions from M entries in the reserved entries 204(0)-204(M-1) in the reserved circuit 202 to publish; and (3) the scheduling delay of the K publishing channel selection signals 220(0)-220(K-1) published by the selection circuit 206 for the M entries in the reserved circuit 202 to cause the instructions (M<-1) in the M reserved entries 204(0)-204 to be published in the K publishing channels L0-L K-1 The delay in the release. It may be desirable to increase the instruction window size M in reserved circuit 202. The larger the instruction window size M, the more likely it is that K available instructions are always ready to be released on K release channels L0-L. K-1 The design was released to maximize the efficiency of the execution circuit 205. However, to improve performance, additional... Figure 2A The instruction window size M in the scheduler circuit 200 will adversely affect the delay of all three (3) components of the wake-up timing path in the scheduler circuit 200. Increasing the instruction window size M increases the number of endpoints to which K wake-up signals 212(0)-212(K-1) need to be broadcast in the pick circuit 206, which may increase the capacitive and resistive load in the wake-up timing path, thereby increasing the delay. In addition, increasing the number of K broadcast channels L0-L K-1 The increased number of wake-up signals 212(0)-212(K-1) coupled to the selection circuit 206 also increases the capacitive and resistive loads on the selection circuit 206 and in the wake-up timing path, which may increase the delay of the selection circuit 206.

[0045] and Figure 2A The reserved circuit in the scheduler circuit 200 is the opposite. Figure 3A This is a diagram of an exemplary delay-based instruction reservation cluster scheduler circuit 300 (“cluster scheduler circuit” 300) comprising multiple (N) delay-based reservation circuits 302(0)-302(N-1). It can be seen as follows...Figure 1 The cluster scheduler circuit 300 is employed in the same manner as the scheduler circuit 106 in the instruction processing circuit 104 in the FIG. 1A. As will be discussed in greater detail below, each latency-based reservation circuit 302(0)-302(N-1) is configured to gather identical periodic latency consumer instructions that are scheduled to issue to the issue lane for execution by the execution circuit. For example, consumer instructions that rely on a single clock cycle latency and thus have a single clock cycle latency can be gathered together in the same latency-based reservation circuit 302(0) that is designated to reserve for one (1) clock cycle latency consumer instructions reservations. For example, consumer instructions that rely on a three (3) clock cycle latency and thus have a three (3) clock cycle latency can be gathered together in another latency-based reservation circuit 302(N-1) that is designated to reserve for three (3) clock cycle latency consumer instructions. In this manner, the total number of reservation entries in the cluster scheduler circuit 300 can be distributed among the N latency-based reservation circuits 302(0)-302(N-1) to avoid or reduce the number of scheduling path connections and the increase in complexity of each latency-based reservation circuit 302(0)-302(N-1) to avoid or reduce the increase in scheduling latency for a given total number of reservation entries. For a given number of reservation entries on the non-clustered selection circuit, as Figure 2A The scheduler circuit 200 in the FIG. 1A, the number of scheduling path connections is reduced because the signals (e.g., wake-up signals, issue lane selection signals) used to schedule the instructions issued in each latency-based reservation circuit 302(0)-302(N-1) do not have to have the same clock cycle latency to avoid impacting performance. For example, if the latency-based reservation circuit 302(1) has an assigned periodic latency of two (2) clock cycles, the producer instructions in the reservation entries stored in the latency-based reservation circuit 302(1) do not have to issue consumer instructions in back-to-back clock cycles with the issue of the producer instructions because the producer instructions will not generate data in one (1) clock cycle.

[0046] Thus, the signals used to schedule instructions by the latency-based reservation circuits 302(0)-302(N-1) can be isolated from each other with different cycle latencies, thus requiring only coupling to their respective latency-based reservation circuits 302(0)-302(N-1), thereby reducing connection complexity. For example, signals for scheduling instructions in a reservation circuit based on a three (3) cycle latency can have a clock cycle latency of three (3) clock cycles without impacting scheduling performance. However, a latency-based reservation circuit 302(0)-302(N-1) with an assigned cycle latency of one (1) clock cycle can only schedule consumer instructions in back-to-back clock cycles with the issuance of producer instructions if the scheduling timing path for scheduling such instructions does not have a clock cycle latency greater than one (1) clock cycle.

[0047] In this regard, reference is made to Figure 3A , the cluster scheduler circuit 300 includes N latency-based reservation circuits 302(0)-302(N-1). In this example, the latency-based reservation circuit 302(0) includes “M0” reservation entries 304(0)(0)-304(0)(M0-1). In this example, the latency-based reservation circuit 302(N-1) includes “M N -1” reservation entries 304(N-1)(0)-304(N-1)(M N -1). Only two (2) latency-based reservation circuits 302(0)-302(N-1) are shown, but note that any number of N latency-based reservation circuits can be included in the cluster scheduler circuit 300. The reservation entries 304(0)(0)-304(0)(M0-1)-304(N-1)(0)-304(N-1)(M N -1) in the respective latency-based reservation circuits 302(0)-302(N-1) are configured to store received instructions, including consumer instructions, until ready to be executed in the execution circuit 305. The cluster scheduler circuit 300 is configured to issue instructions (including consumer instructions) ready to be executed to one of the issue channels L0-L K-1 coupled to the execution channels E0-E K-1 in the execution circuit 305. The execution circuit 205 is designed to be able to receive and execute concurrently “K” instructions dispatched in the common K issue channels L0-L K-1 , and provides K execution channels E0-E K-1 to improve performance. Thus, in this example, M0 is the instruction window size of the latency-based reservation circuit 302(0), M N-1 is the instruction window size of the latency-based reservation circuit 302(N-1) and "K" is referred to as the issue width or number of issue lanes L0-L K-1 in which producer instructions can be issued to the execution circuit 305 to be executed. Thus, the instruction window size of the entire cluster scheduler circuit 300 is divided among the latency-based reservation circuits 302(0)-302(N-1). If the cluster scheduler circuit 300 is included as in Figure 1

[0048] Figure 3A the scheduler circuit 106 in FIG. 1, the reservation entries 304(0)(0)-304(0)(M0-1)-304(N-1)(0)-204(N-1)(M N -1) will be configured to store decoded instructions 112D from the instruction pipeline I0-I N -1) will be configured to store decoded instructions 112D from the instruction pipeline I0-I N -1) will be configured to store decoded instructions 112D from the instruction pipeline I0-I K-1 For example, the latency-based reservation circuit 302(0) can be designated for reserving consumer instructions having a cycle latency of one (1) clock cycle, while the latency-based reservation circuit 302(N-1) can be designated for reserving consumer instructions having a cycle latency of three (3) clock cycles. The cluster scheduler circuit 300 ensures that a producer instruction is issued from its latency-based reservation circuit 302(0)-302(N-1) before its consumer instructions are issued in the issue lanes L0-L K-1 -1) to be executed by the execution circuit 305. The cluster scheduler circuit 300 is a synchronous circuit configured to operate and perform functions in the cycle of the clock signal of its processor.

[0048] With continued reference to Figure 3A each latency-based reservation circuit 302(0)-302(N-1) includes a respective selection circuit 306(0)-306(N-1) that tracks the instructions in the respective reservation entries 304(0)(0)-304(0)(M0-1)-304(N-1)(0)-304(N-1)(M N -1) to determine when such instructions are ready to be issued. In this regard, the reservation entries 304(0)(0)-304(0)(M0-1)-304(N-1)(0)-304(N-1)(M Neach of -1) to a respective ready circuit 308(0)-308(N-1) in a respective pick circuit 306(0)-306(N-1), as tracked by trace lines 310(0)(0)-310(M0-1)-310(N-1)(0)-310(N-1)(M N -1) as indicated by the trace lines, each trace line can convey trace information about instructions stored in the respective reservation entry 304(0)(0)-304(0)(M0-1) -304(N-1)(0)-304(N-1)(M N -1) to a respective ready circuit 308(0)-308(N-1) in a respective pick circuit 306(0)-306(N-1), as tracked by trace lines 310(0)(0)-310(M0-1)-310(N-1)(0)-310(N-1)(M K-1 -1) to a respective ready circuit 308(0)-308(N-1) in a respective pick circuit 306(0)-306(N-1), as tracked by trace lines 310(0)(0)-310(M0-1)-310(N-1)(0)-310(N-1)(M K-1 Each of the K publish lane circuits 314(0)-314(K-1) associated with a respective publish lane L0-L K-1 -1) to a respective ready circuit 308(0)-308(N-1) in a respective pick circuit 306(0)-306(N-1), as tracked by trace lines 310(0)(0)-310(M0-1)-310(N-1)(0)-310(N-1)(M

[0049] In this example, where the latency-based reservation circuit 302(N-1) is indicated for a three (3) cycle latency consumer instruction, the pickoff circuit 306(N-1) in the latency-based reservation circuit 302(N-1) is coupled to the wake-up signals 312(N-1)(0)-312(N-1)(K-1) from the wake-up latch circuit 313(N-1) that are delayed by two (2) clock cycles to avoid each pickoff circuit 306(0)-306(N-1) from becoming a load on the wake-up signals 312(N-1)(0)-312(N-1)(K-1) generated from the issue channel circuit 314(0)-314(K-1) that would otherwise increase the dispatch latency. In this example, N wake-up latch circuits 313(0)-313(N-1) are provided that are linked together in a daisy chain. As an example, the wake-up latch circuits 313(0)-313(N-1) can be latches or flip-flops. The wake-up latch circuit 313(0) latches the wake-up signals 312(N-1)(0)-312(N-1)(K-1) in the same clock cycle as the issue by the issue channel circuit 314(0)-314(K-1). The wake-up latch circuit 313(N-2) latches a clock cycle delayed version of the wake-up signals 312(0)(0)-312(0)(K-1) as the clock cycle delayed wake-up signals 312(N-2)(0)-312(N-2)(K-1). The wake-up latch circuit 313(N-1) latches another clock cycle delayed version of the wake-up signals 312(N-2)(0)-312(N-2)(K-1) as the clock cycle delayed wake-up signals 312(N-1)(0)-312(N-1)(K-1).

[0050] As discussed above and below with respect to Figure 3B-2As described, the selection circuit 306(N-1) of the latency-based reservation circuit 302(N-1) receiving the clock cycle delayed wake-up signals 312(N-1)(0)-312(N-1)(K-1) does not impact performance because the producer instructions allocated to store and aggregate in the latency-based reservation circuit 302(N-1) have a cycle latency such that the scheduled issuance of the clock cycle delayed wake-up signals 312(N-1)(0)-312(N-1)(K-1) does not delay the provision of data from executing the multi-cycle latency producer instructions to its consumer instructions. As an example, the clock cycle delay of the clock cycle delayed wake-up signals 312(N-1)(0)-312(N-1)(K-1) can be the same clock cycle delay as the cycle latency allocated to the latency-based reservation circuit 302(N-1). As another example, the clock cycle delay of the clock cycle delayed wake-up signals 312(N-1)(0)-312(N-1)(K-1) can be a shorter clock cycle delay than the cycle latency allocated to the latency-based reservation circuit 302(N-1). This would result in the selection circuit 306(N-1) for the latency-based reservation circuit 302(N-1) receiving the wake-up signals 312(N-1)(0)-312(N-1)(K-1) earlier than needed to impact performance. As another example, the clock cycle delay of the clock cycle delayed wake-up signals 312(N-1)(0)-312(N-1)(K-1) can be a greater clock cycle delay than the cycle latency allocated to the latency-based reservation circuit 302(N-1). This would result in the selection circuit 306(N-1) for the latency-based reservation circuit 302(N-1) receiving the wake-up signals 312(N-1)(0)-312(N-1)(K-1) later than needed which can impact performance.

[0051] To further illustrate Figure 3A the issuance of instructions in the cluster scheduler circuit 300, timing diagrams are provided in Figure 3B-1 and Figure 3B-2 . Figure 3B-1 is a timing diagram 324 illustrating exemplary clock cycle timing of the reservation, issuance, and execution of a single clock cycle latency producer instruction and consumer instruction issued by the cluster scheduler circuit 300 in Figure 3A . Figure 3B-2 is a timing diagram 326 illustrating exemplary clock cycle timing of the reservation, issuance, and execution of a three clock cycle latency producer instruction and consumer instruction issued by the latency-based reservation circuit 302(N-1) in the cluster scheduler circuit 300 in Figure 3A with an allocated latency of three (3) clock cycles.

[0052] Reference is made to Figure 3B-1, the timing diagram 324 is shown in tabular form including clock cycles 1, 2, 3, 4, and 5 along the X-axis and pipeline stages in the instruction processing circuit along the Y-axis. The pipeline stages shown are a reservation (RSV) for the reservation stage of the latency-based reservation circuit 302(0) in the cluster scheduler circuit 300, Figure 3A , an issue channel L0-L K-1 , an issue (ISSUE) for the issue stage shown in K-1 , and execution stages A0-A2 illustrating up to three (3) execution stages in the execution circuit 305 performed within three (3) clock cycles. As previously discussed, some producer instructions are single-clock cycle latency instructions because the data they produce is generated by an execution circuit such as the execution circuit 305 in one execution stage and thus in one (1) clock cycle. Other producer instructions are multi-clock cycle latency instructions because the data they produce is generated by an execution circuit such as the execution circuit 305 in more than one execution stage and thus in more than (1) clock cycle.

[0053] As shown in Figure 3B-1 , the timing diagram 324 includes a “P” in the clock cycle 1 issue stage, representing Figure 3A , a producer instruction previously issued by the pick circuit 306(0) in K-1 . Latency = 1 means that the producer instruction is a one (1) clock cycle latency instruction. The consumer instruction represented by “C” from the producer instruction P is also in clock cycle 1, indicating that the consumer instruction C is stored in the reservation entries 304(0)(0)-304(0)(M0-1) in the reservation circuit 302(0) in Figure 3A . In response to the producer instruction P in clock cycle 1 in the issue channel L0-L K-1 , a non-clock cycle delayed wake-up signal represented by the wake-up signal 312(0)() is generated and communicated to the pick circuit 306(0) in the latency-based reservation circuit 302(0) in the cluster scheduler circuit 300 assigned to single-clock cycle latency producer instructions to identify the producer instruction P having an issue state indicating issued. As shown in the timing diagram 324 in clock cycle 2, the producer instruction P is shifted to the first execution stage A0 in the execution circuit 305 in Figure 3A . The consumer instruction C is issued to the issue channel L0-L Figure 3A by the pick circuit 306(0) in K-1The ability to issue a consumer instruction that depends on a single clock cycle latency producer instruction in a back-to-back clock cycle is very efficient. Since the producer instruction P in this example is a single clock cycle latency producer instruction, the data generated by the execution of the producer instruction P is available to the consumer instruction C in clock cycle 2. Thus, the consumer instruction C can consume the data generated by the execution of the producer instruction P in clock cycle 3 in its execution.

[0054] Figure 3B-2 The timing diagram 326 in FIG. 3B also includes the producer instruction P that was previously issued by the pick circuit 306(N-1) in clock cycle 1 in FIG. 3A. Figure 3A The issue lane L0-L K-1 The producer instruction P in clock cycle 1 in the issue stage in FIG. 3B. Latency = 3 means that the producer instruction P in FIG. 3B is a three (3) clock cycle latency instruction, which means that the producer instruction P will not be fully executed until Figure 3A the third execution stage A2 in the execution circuit 305 in FIG. 3B. The consumer instruction C of the producer instruction P is also in clock cycle 1, which indicates that the consumer instruction C is stored in the Figure 3A the reservation entry 304(N-1)(0)-304(N-1)(M N -1) in the latency-based reservation circuit 302(N-1) in the cluster scheduler circuit 300 in FIG. 3B. In response to the producer instruction P in clock cycle 1 in the issue lane L0-L K-1 The wake-up signal 312(N-1)(0) is not generated as in FIG. 3A and is not transmitted to the pick circuit 306(N-1) in the latency-based reservation circuit 302(N-1) in the cluster scheduler circuit 300 to identify the producer instruction P with the issue state indicating issued. Figure 3B-2 The producer instruction P is shifted to the first execution stage A0 in the execution circuit 305 in FIG. 3B. The consumer instruction C is not Figure 3B-2 issued to the issue lane L0-L Figure 3A The timing diagram 326 in FIG. 3B also includes the producer instruction P that was previously issued by the pick circuit 306(N-1) in clock cycle 1 in FIG. 3A. Figure 3A The timing diagram 326 in FIG. 3B also includes the producer instruction P that was previously issued by the pick circuit 306(N-1) in clock cycle 1 in FIG. 3A. K-1Because producer instruction P has not yet been fully executed. In clock cycle 3, clock cycle delayed wake-up signal 312(N-1)(0) is generated and communicated to pick circuit 306(N-1) in latency-based reservation circuit 302(N-1) in cluster scheduler circuit 300 to identify producer instruction P having a release status indicating a release issued. Since producer instruction P in this example is a three (3) clock cycle latency producer instruction, data generated by execution of producer instruction P will only be available to consumer instruction C in clock cycle 4. Thus, consumer instruction C can consume in its execution the data generated by execution of producer instruction P in clock cycle 5. Thus, as shown in Figure 3B-2 clock cycle 3, and execution of the producer instruction in clock cycle 4 and release of the consumer instruction occurs in back-to-back clock cycles.

[0055] Referring back to cluster scheduler circuit 300 in Figure 3A wake-up signals 312(0)(0)-312(0)(K-1)-312(N-1)(0)-312(N-1)(K-1) indicate a release ready or a release not ready. When a producer instruction is released by cluster scheduler circuit 300 in release lanes L0-L K-1 this means that it will be executed by execution circuit 305 and its resulting data produced by the execution can be consumed by any consumer instruction of the producer instruction. Ready circuits 308(0)-308(N-1) in respective pick circuits 306(0)-306(N-1) are configured to compare respective wake-up signals 312(0)(0)-312(0)(K-1)-312(N-1)(0)-312(N-1)(K-1) having a release ready indicating a released producer instruction to the M instructions in respective reservation entries 304(0)(0)-304(0)(M0-1)-304(N-1)(0)-304(N-1)(M N -1) to determine whether any such instructions are ready to be executed. For example, if instruction reservation entries 304(0)(0)-304(0)(M0-1)-304(N-1)(0)-304(N-1)(M N-1) in which the corresponding latency-based reservation circuit 302(0)-302(N-1) issued the producer instruction, indicates that data from that producer instruction will become available, and thus the consumer instruction can be issued if no other source operand is unavailable. The ready circuit 308(0)-308(N-1) is configured to generate a corresponding M0-M N instructions ready to be issued in the corresponding reservation entry 304(0)(0)-304(0)(M0-1) - 304(N-1)(0)-304(N-1)(M N -1) based on a comparison of the corresponding received wake-up signal 312(0)(0)-312(0)(K-1) - 312(N-1)(0)-312(N-1)(K-1) of the issued producer instruction and the corresponding M0-M N instructions in the corresponding reservation entry 304(0)(0)-304(0)(M0-1) - 304(N-1)(0)-304(N-1)(M N -1). For example, the ready circuit 308(0)-308(N-1) can be a comparator circuit configured to compare the corresponding received wake-up signal 312(0)(0)-312(0)(K-1) - 312(N-1)(0)-312(N-1)(K-1) of the issued producer instruction and the corresponding M0-M N instructions in the corresponding reservation entry 304(0)(0)-304(0)(M0-1) - 304(N-1)(0)-304(N-1)(M N -1). As another example, the ready circuit 308(0)-308(N-1) can be a matrix circuit configured to compare the corresponding received wake-up signal 312(0)(0)-312(0)(K-1) - 312(N-1)(0)-312(N-1)(K-1) of the issued producer instruction and the corresponding M0-M N instructions in the corresponding reservation entry 304(0)(0)-304(0)(M0-1) - 304(N-1)(0)-304(N-1)(M N -1).

[0056] With continued reference to Figure 3A, the selection circuit 306(0)-306(N-1) in the corresponding latency-based reservation circuit 302(0)-302(N-1) includes a corresponding K selection circuits 318(0)(0)-318(0)(K-1) - 318(N-1)(0)-318(N-1)(K-1) configured to receive a corresponding M0-M N instructions ready signals 316(0)(0)-316(0)(M0-1) - 316(N-1)(0)-316(N-1)(M N -1) from the corresponding ready circuit 308(0)-308(N-1) and generate a corresponding K lane selection signals 320(0)(0)-320(0)(K-1) - 320(N-1)(0)-320(N-1)(K-1) to identify the corresponding instructions in the reservation entries 304(0)(0)-304(0)(M0-1) - 304(N-1)(0)-304(N-1)(M N -1) that are ready to be issued as indicated by the issue state of the issue ready. If K is not equal to M, then M0-M N instructions ready signals 316(0)(0)-316(0)(M0-1) - 316(N-1)(0)-316(N-1)(M N -1) to the K corresponding K issue lane selection signals 320(0)(0)-320(0)(K-1) - 320(N-1)(0)-320(N-1)(K-1) will involve multiplexing of signals in each latency-based reservation circuit 302(0)-302(N-1). The issue lane selection signals 320(0)(0)-320(0)(K-1) - 320(N-1)(0)-320(N-1)(K-1) are provided to K issue select circuits 322(0)(0)-322(0)(K-1) - 322(N-1)(0)-322(N-1)(K-1) in the corresponding reservation circuit 302(0)-302(N). The issue select circuits 322(0)(0)-322(0)(K-1) - 322(N-1)(0)-322(N-1)(K-1) are each coupled to a corresponding reservation entry 304(0)(0)-304(0)(M0-1) - 304(N-1)(0)-304(N-1)(M N -1), if K is not equal to M, such M0-M N instructions in the corresponding reservation entry 304(0)(0)-304(0)(M0-1) - 304(N-1)(0)-304(N-1)(M NThe entries are multiplexed to respective K issue select circuits 322(0)(0)-322(0)(K-1) - 322(N-1)(0)-322(N-1)(K-1). The issue select circuits 322(0)(0)-322(0)(K-1) - 322(N-1)(0)-322(N-1)(K-1) are configured to select instructions from respective reservation entries 304(0)(0)-304(0)(M0-1) - 304(N-1)(0)-304(N-1)(M N -1) in response to being identified by respective issue lane pick signals 320(0)(0)-320(0)(K-1) - 320(N-1)(0)-320(N-1)(K-1) as having an issue ready issue state. The issue select circuits 322(0)(0)-322(0)(K-1) - 322(N-1)(0)-322(N-1)(K-1) are each configured to provide instruction signals 330(0)(0)-330(0)(K-1) - 330(N-1)(0)-330(N-1)(K-1) identified by received respective issue lane issue pick signals 320(0)(0)-322(0)(K-1) - 320(N-1)(0)-322(N-1)(K-1) to be issued to respective associated issue lanes L0-L K-1 The K issue arbiter circuits 328(0)-328(K-1) are each configured to pass instructions from among the instructions selected from respective issue select circuits 322(0)(0)-322(0)(K-1) - 322(N-1)(0)-322(N-1)(K-1) to respective associated issue lanes L0-L K-1 The issue arbiter circuits 328(0)-328(K-1) are configured to decide which of the latency based reservation circuits 302(0)-302(N-1) instructions selected by respective issue select circuits 322(0)(0)-322(0)(K-1) - 322(N-1)(0)-322(N-1)(K-1) for issue lanes L0-L K-1 will actually be issued to respective issue lanes L0-L K-1 above in the current clock cycle.

[0057] Figure 3A The issue arbiter circuits 328(0)-328(K-1) in the cluster scheduler circuit 300 in the cluster 300 can be configured to decide which of the latency based reservation circuits 302(0)-302(N-1) instructions selected by respective issue select circuits 322(0)(0)-322(0)(K-1) - 322(N-1)(0)-322(N-1)(K-1) for issue lanes L0-LK-1 Which of the selected contending latency-based reservation circuits 302(0)-302(N-1) instructions will actually be issued to the respective issue lanes L0-L K-1 above in the current clock cycle will be based on an allocation policy. For example, if more than one latency-based reservation circuit 302(0)-302(N-1) is contending to issue an instruction to issue lanes L0-L K-1 , the issue arbitration circuits 328(0)-328(K-1) can be configured with an issue arbitration policy to pass the instruction selected from the respective issue selection circuits 322(0)(0)-322(0)(K-1)-322(N-1)(0)-322(N-1)(K-1) to the associated respective issue lane L0-L K-1 from the latency-based reservation circuit 302(0)-302(N-1) with the lowest latency. Alternatively, the issue arbitration circuits 328(0)-328(K-1) can be configured with an issue arbitration policy to pass the instruction selected from the respective issue selection circuits 322(0)(0)-322(0)(K-1)-322(N-1)(0)-322(N-1)(K-1) to the associated respective issue lane L0-L K-1 from the latency-based reservation circuit 302(0)-302(N-1) with the highest latency. As yet another alternative, the issue arbitration circuits 328(0)-328(K-1) can be configured with an issue arbitration policy to pass the instruction selected from the respective issue selection circuits 322(0)(0)-322(0)(K-1)-322(N-1)(0)-322(N-1)(K-1) to the associated respective issue lane L0-L K-1 based on a heuristic determination among the latency-based reservation circuits 302(0)-302(N-1). For example, as non-limiting examples, the heuristic determination can be based on available capacity of the latency-based reservation circuits 302(0)-302(N-1), frequency of conflicts among the latency-based reservation circuits 302(0)-302(N-1), random selection among the contending latency-based reservation circuits 302(0)-302(N-1), and round-robin switching among the contending latency-based reservation circuits 302(0)-302(N-1).

[0058] Further, with reference to Figure 3Acluster scheduler circuit 300 can be configured to determine whether a reservation entry 304(0)(0)-304(0)(M0-1) - 304(N-1)(0)-304(N-1)(M N -1) in the respective latency-based reservation circuit 302(0)-302(N-1) of the cycle latency assigned to the cycle latency of the consumer instruction is available. If a reservation entry 304(0)(0)-304(0)(M0-1) - 304(N-1)(0)-304(N-1)(M N -1) in the respective latency-based reservation circuit 302(0)-302(N-1) of the cycle latency assigned to the cycle latency of the consumer instruction is available, the cluster scheduler circuit 300 can assign and cause the consumer instruction to be stored in the reservation entry 304(0)(0)-304(0)(M0-1) - 304(N-1)(0)-304(N-1)(M N -1) of the respective latency-based reservation circuit 302(0)-302(N-1) having the assigned cycle latency of the consumer instruction as the preferred latency-based reservation circuit 302(0)-302(N-1). If the reservation entry 304(0)(0)-304(0)(M0-1) - 304(N-1)(0)-304(N-1)(M N -1) in the respective latency-based reservation circuit 302(0)-302(N-1) of the cycle latency assigned to the cycle latency of the consumer instruction is not available, the cluster scheduler circuit 300 can assign and cause the consumer instruction to be stored in the reservation entry 304(0)(0)-304(0)(M0-1) - 304(N-1)(0)-304(N-1)(M N -1) of the respective latency-based reservation circuit 302(0)-302(N-1) assigned from the next highest cycle latency in the cycle latency of the consumer instruction as the preferred latency-based reservation circuit 302(0)-302(N-1). Alternatively, if the reservation entry 304(0)(0)-304(0)(M0-1) - 304(N-1)(0)-304(N-1)(M N-1) If unavailable, the cluster scheduler circuit 300 can allocate and store the consumer instruction in the reservation entry 304(0)(0)-304(0)(M0-1)–304(N-1)(0)-304(N-1)(M0-1)–304(N-1)(0)-304(N-1)(M0-1) in the corresponding delay-based reservation circuit 302(0)-302(N-1) with the best average availability. N -1) in.

[0059] Figure 4A and Figure 4B It is illustrated as follows Figure 3A A flowchart of an exemplary process 400 for a cluster scheduler circuit, such as cluster scheduler circuit 300, is provided, which allocates received producer instructions to a delay-based reservation circuit based on the periodic delay of the producer instructions, and schedules the instructions to be published to a publication channel in the delay-based reservation circuit for execution in the execution circuit. This will be combined with... Figure 3A The cluster scheduler circuit 300 in the example is discussed below. Figure 4A The process 400 involves the cluster scheduler circuit 300 receiving a first instruction among a plurality of instructions, the plurality of instructions including a producer instruction containing a single-clock-cycle delay producer instruction and a first consumer instruction containing a single-clock-cycle delay producer instruction. Figure 4A (Block 402 in the middle). Process 400 further includes: the cluster scheduler circuit 300 storing the first instruction in the first reservation entry 304(0)(0)-304(0)(M0-1) in the delay-based reservation circuit 302(0). Figure 4A (Block 404 in the process). Process 400 also includes: a delay-based reservation circuit 302(0) of the cluster scheduler circuit 300 receiving single-clock-cycle delay wake-up signals 312(0)(K-1)-312(0)(K-1), each signal being associated with multiple publishing channels (L0-L). K-1 One of the publishing channels L0-L K-1 Correspondingly, multiple single-clock-cycle delay wake-up signals 312(0)(K-1)-312(0)(K-1) each indicate multiple publish channels L0-L K-1 The publishing channel L0-L K-1 The issuance status of producer instructions with single clock cycle delay (in) Figure 4A(Block 406 in the process). Process 400 further includes: in response to multiple single-clock-cycle delay wake-up signals 312(0)(K-1)-312(0)(K-1) associated with a single-clock-cycle delay producer instruction having a release-ready state, the delay-based reservation circuit 302(0) of the cluster scheduler circuit 300 determines whether the first instruction is ready to be scheduled for execution. Figure 4A (Block 408 in the process). Process 400 also includes: a delay-based reservation circuit 302(0) of the cluster scheduler circuit 300 identifying multiple first instructions with a release ready state (in the process). Figure 4A (Block 410 in the middle). Process 400 also includes: a delay-based reservation circuit 302(0) of the cluster scheduler circuit 300 selecting a first instruction (M0-1) stored among a plurality of first reservation entries 304(0)(0)-304(0)(M0-1) that is identified as having a release ready state. Figure 4A (Block 412 in the middle).

[0060] Continue to refer to Figure 4A The process 400 further includes: the cluster scheduler circuit 300 receiving a second instruction among a plurality of instructions, the plurality of instructions including a second clock cycle delay producer instruction having the same second clock cycle delay of at least two (2) clock cycles and a second consumer instruction of the second clock cycle delay producer instruction ( Figure 4A (Block 414 in the middle). Process 400 also includes: cluster scheduler circuit 300 storing second consumer instructions in multiple second reservation entries 304(N-1)(0)-304(N-1)(M). N The second reserved entry in -1) is 304(N-1)(0)-304(N-1)(M N -1) Figure 4A (Block 416 in the process). Process 400 also includes: a delay-based reservation circuit 302(N-1) in the cluster scheduler circuit 300 receiving second clock cycle delayed wake-up signals 312(N-1)(K-1)-312(N-1)(K-1), each signal associated with a publish channel L0-L0. K-1 Correspondingly, the second clock cycle delay wake-up signals 312(N-1)(K-1)-312(N-1)(K-1) each indicate a publish channel L0-L K-1 The second clock cycle delay of the producer instruction issuance status ( Figure 4B(Block 418 in the process). Process 400 further includes: in response to the second clock cycle delay wake-up signal 312(N-1)(K-1)-312(N-1)(K-1) associated with a second clock cycle delay producer instruction having a release ready state for multiple second consumer instructions, the delay-based reservation circuit 302(N-1) in the cluster scheduler circuit 300 determines whether the second consumer instruction is ready to be scheduled for execution. Figure 4B (Block 420 in the process). Process 400 also includes: a delay-based reservation circuit 302 (N-1) in the cluster scheduler circuit 300 identifying a second consumer instruction with a publish-ready state (in the process). Figure 4B (Block 422 in the middle). Process 400 also includes: the delay-based reservation circuit 302(N-1) in the cluster scheduler circuit 300 selecting the second reservation entry 304(N-1)(0)-304(N-1)(M). N The second consumer instruction (marked as having a release ready state) stored in -1) Figure 4B Block 424 in the middle.

[0061] Continue to refer to Figure 4B The process 400 further includes: the cluster scheduler circuit 300 transmitting the consumer instruction, one of the selected second instruction and the selected first consumer instruction, to its associated publish channel L0-L. K-1 ( Figure 4B (Block 426 in the middle). Process 400 further includes: cluster scheduler circuit 300 generating a single clock cycle delay wake-up signal 312(0)(0)-312(0)(K-1)(K-1)(K-1) in response to the issuance of a single clock cycle delay producer instruction. Figure 4B Block 426 in the middle.

[0062] refer to Figure 3AThe cluster scheduler circuit 300 in the middle can also latch and delay selected instruction signals 330(N-1)(0)-330(N-1)(K-1) from the delay-based reservation circuit 302(N-1) based on the allocated periodic delay of the delay-based reservation circuit 302(N-1) to isolate the selected instruction signals 330(N-1)(0)-330(N-1)(K-1) from the issuing arbitration circuit 328(0)-328(K-1) to reduce the load on the delay-based reservation circuit 302(N-1) and thus reduce or not increase its scheduling delay. For example, delaying the provision of selected instruction signals 330(N-1)(0)-330(N-1)(K-1) to the release arbitration circuits 328(0)-328(K-1) may not negatively affect the performance of the delay-based reservation circuit 302(N-1) because the data from the execution of its producer instructions will be delayed due to the multi-clock-cycle delay.

[0063] In this respect, such as Figure 3A The cluster scheduler circuit 300 in the middle, Figure 5A This is a diagram of an exemplary delay-based instruction reservation cluster scheduler circuit 500 (“cluster scheduler circuit” 500) comprising multiple (N) delay-based reservation circuits 302(0)-302(N-1). It can be seen as follows... Figure 1 The cluster scheduler circuit 500 is used, similar to the scheduler circuit 106 in the instruction processing circuit 104. Figure 5A Cluster scheduler circuit 500 and Figure 3A The common components among the cluster scheduler circuits 300 in the middle are in Figure 5A They are shown using common component numbers and will not be described again. In this example, with Figure 3A The cluster scheduler circuit 300 differs from the others; each delay-based reserved circuit 302(0)-302(N-1) is coupled to the same wake-up signal 312(0)-312(K-1), which is related to... Figure 2A Similar to the scheduler circuit 200, it is not clock cycle delayed. However, in this example, the publish channel pick signals 320(N-1)(0)-320(N-1)(K-1) are latched and the clock cycle is delayed. N channel pick latch circuits 502(N-2)-502(N-1) are provided, daisy-chained together. As an example, the channel pick latch circuits 502(N-2)-502(N-1) can be latches or flip-flops. The channel pick latch circuit 502(N-1) is connected in conjunction with the publish pick circuits 322(N-1)(0)-322(N-1)(M... N- 1) the clock cycle delayed issue lane selection signals 320(N-1)(0)- 320(N-1)(K-1) are latched within the same clock cycle that the issue is posted. The lane selection latch circuit 502(N-1) latches the clock cycle delayed versions of the issue lane selection signals 320(N-1)(0)-320(N-1)(K-1) as the clock cycle delayed issue lane selection signals 320(N-1)(0)-320(N-1)(K-1).

[0064] As discussed above and described below with respect to Figure 5A the generation of the clock cycle delayed issue lane selection signals 320(N-1)(0)-320(N-1)(K-1) by the selection circuit 306(N-1) of the latency based reservation circuit 302(N-1) does not impact performance because the data from the execution of the producer instructions corresponding to the consumer instructions for which the requests are issued that are identified by the clock cycle delayed issue lane selection signals 320(N-1)(0)-320(N-1)(K-1) will be delayed due to the multi-clock cycle latency. As an example, the clock cycle delay of the clock cycle delayed issue lane selection signals 320(N-1)(0)-320(N-1)(K-1) can be the same clock cycle delay as the cycle latency assigned to the latency based reservation circuit 302(N-1). As another example, the clock cycle delay of the clock cycle delayed issue lane selection signals 320(N-1)(0)-320(N-1)(K-1) can be a shorter clock cycle delay than the cycle latency assigned to the latency based reservation circuit 302(N-1). This would result in the selection circuit 306(N-1) for the latency based reservation circuit 302(N-1) generating the issue lane selection signals 320(N-1)(0)-320(N-1)(K-1) earlier than needed to impact performance. As another example, the clock cycle delay of the clock cycle delayed issue lane selection signals 320(N-1)(0)-320(N-1)(K-1) can be a greater clock cycle delay than the cycle latency assigned to the latency based reservation circuit 302(N-1). This would result in the selection circuit 306(N-1) for the latency based reservation circuit 302(N-1) generating the clock cycle delayed issue lane selection signals 320(N-1)(0)-320(N-1)(K-1) later than needed which can impact performance.

[0065] To further illustrate Figure 5A the issuance of instructions in the cluster scheduler circuit 500, Figure 5B-1 and Figure 5B-2 timing diagrams are provided. Figure 5B-1 is a timing diagram illustrating the issuance of instructions by Figure 5Aan exemplary clock cycle timing of the reservation, issuance, and execution of single-clock cycle latency producer instructions and consumer instructions issued by the latency-based reservation circuit 302(N-1) in the cluster scheduler circuit 300 having a latency allocation of three (3) clock cycles. Figure 5B-2 is illustrated from Figure 5A an exemplary clock cycle timing of the reservation, issuance, and execution of three-clock cycle latency producer instructions and consumer instructions issued by the latency-based reservation circuit 302(N-1) in the cluster scheduler circuit 300 having a latency allocation of three (3) clock cycles.

[0066] Referring to Figure 5B-1 , the timing diagram 524 is shown in tabular form including clock cycles 1, 2, 3, 4, and 5 along the X-axis and pipeline stages in the instruction processing circuit along the Y-axis. The illustrated pipeline stages are a reservation (RSV) for the reservation stage of the latency-based reservation circuit 302(0) in the cluster scheduler circuit 500, Figure 5A the issuance lanes L0-L K-1 the issuance (ISSUE) for the issuance stage illustrated in , and execution stages A0-A2 illustrating up to three (3) execution stages in the execution circuit 305 executed over three (3) clock cycles. As previously discussed, some producer instructions are single-clock cycle latency instructions because the data they produce is generated by an execution circuit such as the execution circuit 305 in one execution stage and thus in one (1) clock cycle. Other producer instructions are multi-clock cycle latency instructions because the data they produce is generated by an execution circuit such as the execution circuit 305 in more than one execution stage and thus in more than (1) clock cycle.

[0067] As illustrated in Figure 5B-1 , the timing diagram 524 includes a “P” in the clock cycle 1 issuance stage, representing Figure 5A the producer instruction previously issued by the selection circuit 306(0) in , the issuance lanes L0-L K-1 the clock cycle 1. Latency = 1 means that the producer instruction is a one (1) clock cycle latency instruction. The consumer instruction represented by the “C” of the producer instruction P is also in clock cycle 1, indicating that the consumer instruction C is stored in the reservation entry 304(0)(0)-304(0)(M0-1) in the reservation circuit 302(0) in Figure 5A in response to the producer instruction P in clock cycle 1 in the issuance lanes L0-L K-1In the process, a non-clock-cycle-delayed wake-up signal, represented by wake-up signal 312, is generated and transmitted to the selection circuit 306(0) in the delay-based reservation circuit 302(0) of the allocated single-clock-cycle-delay producer instructions in the cluster scheduler circuit 500 to identify the producer instruction P with an indication of the published status. As shown in the timing diagram 524 in clock cycle 2, the producer instruction P is shifted to Figure 5A The first execution stage A0 in the execution circuit 305. Consumer instruction C is generated by... Figure 5A The selection circuit 306(0) is published to the publication channel L0-L during the back-to-back clock cycle of the producer instruction P. K-1 The ability to issue consumer instructions that depend on single-clock-cycle-delay producer instructions in back-to-back clock cycles is highly efficient. Since the producer instruction P in this example is a single-clock-cycle-delay producer instruction, the data generated by the execution of producer instruction P is available to consumer instruction C in clock cycle 2. Therefore, consumer instruction C can consume the data generated by executing producer instruction P in clock cycle 3 during its execution.

[0068] Figure 5B-2 Timing diagram 526 also includes the previously published information by select circuit 306(0). Figure 5A The publishing channel L0-L K-1 The producer instruction P in clock cycle 1 of the release phase. Delay = 3 means that the producer instruction P in Figure 5B is a delay instruction of three (3) clock cycles, which means that the producer instruction P is delayed until Figure 5A The third execution stage A2 in the execution circuit 305 will be fully executed only then. The consumer instruction C of the producer instruction P is also in clock cycle 1, indicating that the consumer instruction C is stored... Figure 5A The cluster scheduler circuit 500 contains a delay-based reservation circuit 302(N-1) with reservation entries 304(N-1)(0)-304(N-1)(M). N -1). In response to the producer instruction P in clock cycle 1, in the publish channel L0-L K-1 In the middle, wake-up signal 312 is as follows Figure 2B-2 The scheduler circuit 200, as shown, generates and transmits the selection circuit 306 (N-1) in the delay-based reservation circuit 302 (N-1) of the cluster scheduler circuit 500 to identify the producer instruction P that indicates the publication status. As shown in clock cycle 2... Figure 5B-2 As shown in timing diagram 526, the producer instruction P is shifted to... Figure 5A The first execution stage A0 in the execution circuit 305. Consumer instruction C was not executed. Figure 3AThe selection circuit 306 (N-1) in the delay-based reservation circuit 302 (N-1) is published to the publication channel L0-L. K-1 This is because the producer instruction P has not yet been fully executed. Since the producer instruction P in this example is a three (3) clock cycle delayed producer instruction, the data generated by the execution of producer instruction P will only be available to consumer instruction C in clock cycle 4. Therefore, consumer instruction C can consume the data generated by executing producer instruction P in clock cycle 5 during its execution. Thus, as... Figure 5B-2 As shown, the clock cycle delayed publish channel selection signals 320(N-1)(0)-320(N-1)(K-1) are generated in clock cycle 4 so that the publication of consumer instruction C by cluster scheduler circuit 500 does not affect the performance of back-to-back publication of consumer instructions in back-to-back clock cycles, and the data from the producer instruction is available after full execution in clock cycle 5.

[0069] Alternatively, a scheduler circuit can be provided, wherein, for example... Figure 3A Like the cluster scheduler circuit 300 in the middle, a delay-based reserved circuit with an allocated clock cycle delay of more than one (1) clock cycle receives a latched wake-up signal, or as Figure 5A Like the cluster scheduler circuit 500, a latched and delayed selected instruction signal is generated from a delay-based reservation circuit with an allocated clock cycle delay of more than one (1) clock cycle. At this point, Figure 6A Is it like this? Figure 3A and Figure 5A A schematic diagram of an exemplary delay-based instruction reservation cluster scheduler circuit 600 (“cluster scheduler circuit” 600) including multiple (N) delay-based reservation circuits 302(0)-302(N-1) as in the scheduler circuits 300 and 500. Figure 1 The cluster scheduler circuit 600 is used, similar to the scheduler circuit 106 in the instruction processing circuit 104. Figure 6A Cluster scheduler circuit 600 and Figure 3A and Figure 5A The common components between the scheduler circuits 300 and 500 in the middle are Figure 5A They are indicated using common component numbers and will not be described again. Note that, although Figure 6Awake-up latch circuits 313(0)-313(N-1) corresponding to each latency-based reservation circuit 302(1)-302(N-1) are illustrated, and the release lane pick signals 320(N-1)(0)-320(N-1)(K-1) generated for each latency-based reservation circuit 302(1)-302(N-1) are also illustrated, but only one of these solutions is provided for each latency-based reservation circuit 302(1)-302(N-1) in this example to avoid unnecessarily delaying the wake-up and pick of consumer instructions.

[0070] To further illustrate Figure 6A the release of instructions in the cluster scheduler circuit 600, Figure 6B-1 and Figure 6B-2 timing diagrams are provided. Figure 6B-1 is a timing diagram 624 illustrating exemplary clock cycle timing of the reservation, release, and execution of single-clock cycle latency producer instructions and consumer instructions released by the cluster scheduler circuit 600 in Figure 6A . Figure 6B-2 is a timing diagram 626 illustrating exemplary clock cycle timing of the reservation, release, and execution of three-clock cycle latency producer instructions and consumer instructions released by the latency-based reservation circuit 302(N-1) in the cluster scheduler circuit 300 with an assigned latency of three (3) clock cycles in Figure 6A .

[0071] Referring to Figure 6B-1 , the timing diagram 624 is shown in tabular form including clock cycles 1, 2, 3, 4, and 5 along the X-axis and pipeline stages in the instruction processing circuit along the Y-axis. The illustrated pipeline stages are the reservation stage of the reservation (RSV) for the latency-based reservation circuit 302(0) in the cluster scheduler circuit 600, Figure 6A the release lane L0-L K-1 the issue stage of the issue (ISSUE) shown in , and the execution stages A0-A2 illustrating up to three (3) execution stages in the execution circuit 305 executed over three (3) clock cycles. As previously discussed, some producer instructions are single-clock cycle latency instructions in that the data they produce is generated by the execution circuit, such as the execution circuit 305, in one execution stage and thus in one (1) clock cycle. Other producer instructions are multi-clock cycle latency instructions in that the data they produce is generated by the execution circuit, such as the execution circuit 305, in more than one execution stage and thus in more than (1) clock cycle.

[0072] Figure 6B-1 AsAs shown, timing diagram 624 includes "P" in the clock cycle 1 release phase, representing Figure 6A The publishing channel L0-L K-1 The producer instruction previously issued by the selector circuit 306(0) is in the middle. Delay = 1 means that the producer instruction is a (1) clock cycle delayed instruction. The consumer instruction represented by “C” of the producer instruction P is also in clock cycle 1, which indicates that the consumer instruction C is stored in the middle. Figure 6A In the reserved circuit 302(0), the reserved entries 304(0)(0)-304(0)(M0-1) are used. In response to the producer instruction P, in clock cycle 1, in the publishing channels L0-L... K-1 In the process, a non-clock-cycle-delayed wake-up signal, represented by wake-up signal 312(0), is generated and transmitted to the selection circuit 306(0) in the delay-based reservation circuit 302(0) of the allocated single-clock-cycle-delay producer instruction in the cluster scheduler circuit 600 to identify the producer instruction P with an indication of the published status. As shown in the timing diagram 624 in clock cycle 2, the producer instruction P is shifted to Figure 6A The first execution stage A0 in the execution circuit 305. Consumer instruction C is generated by... Figure 6A The selection circuit 306(0) is published to the publication channel L0-L during the back-to-back clock cycle of the producer instruction P. K-1 The ability to issue consumer instructions that depend on single-clock-cycle-delay producer instructions in back-to-back clock cycles is highly efficient. Since the producer instruction P in this example is a single-clock-cycle-delay producer instruction, the data generated by the execution of producer instruction P is available to consumer instruction C in clock cycle 2. Therefore, consumer instruction C can consume the data generated by executing producer instruction P in clock cycle 3 during its execution.

[0073] Figure 6B-2 Timing diagram 626 also includes those previously published by select circuit 306 (N-1) Figure 6A The publishing channel L0-L K-1 The producer instruction P in clock cycle 1 of the release phase. Delay = 3 means that the producer instruction P in Figure 6B is a delay instruction of three (3) clock cycles, which means that the producer instruction P is delayed until Figure 6A The third execution stage A2 in the execution circuit 305 will be fully executed only then. The consumer instruction C of the producer instruction P is also in clock cycle 1, indicating that the consumer instruction C is stored... Figure 6A The cluster scheduler circuit 600 contains a delay-based reservation circuit 302(N-1) with reservation entries 304(N-1)(0)-304(N-1)(M). N-1). In response to the producer instruction P in clock cycle 1 in the issue lane L0-L K-1 The clock cycle delayed wake-up signal 312(N-1)(0) is not generated as in Figure 2B-2 and is not communicated to the pick circuit 306(N-1) in the latency based reservation circuit 302(N-1) in the cluster scheduler circuit 300 to identify the producer instruction P having an issue state indicating issued. As shown in the timing diagram 626 in Figure 6B-2 the producer instruction P is shifted to the first execution stage A0 in the execution circuit 305 in Figure 6A The consumer instruction C is not issued by the pick circuit 306(N-1) in the latency based reservation circuit 302(N-1) in Figure 6A the issue lane L0-L K-1 because the producer instruction P has not been fully executed. The clock cycle delayed wake-up signal 312(N-1)(0) is generated and communicated to the pick circuit 306(N-1) in the latency based reservation circuit 302(N-1) in the cluster scheduler circuit 600 in clock cycle 3 to identify the producer instruction P having an issue state indicating issued. Since the producer instruction P in this example is a three (3) clock cycle latency producer instruction, the data generated by the execution of the producer instruction P will only be available to the consumer instruction C in clock cycle 4. Thus, as shown in Figure 6B-2 the clock cycle delayed wake-up signal 312(N-1)(0) is generated in clock cycle 3 and the execution of the producer instruction in clock cycle 4 and the issue of the consumer instruction occurs in back-to-back clock cycles. Thus, as also shown in Figure 6B-2 the clock cycle delayed issue lane pick signal 320(N-1)(0)-320(N-1)(K-1) is generated in clock cycle 4 to cause the consumer instruction C to be issued by the cluster scheduler circuit 600 does not impact the performance of the back-to-back issue of the consumer instruction in back-to-back clock cycles, the data from the producer instruction is available after full execution in clock cycle 5.

[0074] Figure 7 is a block diagram of an exemplary processor-based system 700 that includes a reaching processor 702 (e.g., a microprocessor) that includes an instruction processing circuit 704 that includes a cluster scheduler circuit 706 that includes a plurality of latency based reservation circuits each configured to gather same cycle latency consumer instructions that are scheduled for issue to a common issue lane by a respective pick circuit for execution by an execution circuit. For example, the processor 702 in FIG. 11 can be Figure 1The processor 102 includes an instruction processing circuit 704, which in turn includes a cluster scheduler circuit 706. As a non-limiting example, the cluster scheduler circuit 706 may be... Figure 3A , Figure 5A , Figure 6A The cluster scheduler circuits 300, 500, and 600 in the system are used. The processor-based system 700 can be one or more circuits included in an electronic board, such as a printed circuit board (PCB), server, personal computer, desktop computer, laptop computer, personal digital assistant (PDA), computing board, mobile device, or any other device, and can represent, for example, a server or a user's computer. In this example, the processor-based system 700 includes a processor 702. Processor 702 represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, etc. More specifically, processor 702 can be an EDGE instruction set microprocessor, or other processor implementing an instruction set that supports explicit consumer naming for transmitting produced values ​​generated by the execution of producer instructions. Processor 702 is configured to execute processing logic in instructions to perform the operations and steps discussed herein. In this example, processor 702 includes an instruction cache 708, a temporary fast-access memory storage for instructions accessible to instruction processing circuitry 704. Instructions fetched or pre-fetched from memory (such as from system memory 710 via system bus 712) are stored in the instruction cache 708. The instruction processing circuit 704 is configured to process instructions fetched into the instruction cache 708 and process the instructions for execution.

[0075] Processor 702 and system memory 710 are coupled to system bus 712 and can interconnect peripheral devices included in processor-based system 700. Processor 700 is known to communicate with these other devices by exchanging address, control, and data information on system bus 712. For example, processor 702 can transmit bus transaction requests to memory controller 714 in system memory 710, which is an example of a slave device. Although... Figure 7 Not shown, but multiple system buses 712 may be provided, each forming a different architecture. In this example, the memory controller 714 is configured to provide memory access requests to the memory array 716 in the system memory 710. The memory array 716 includes an array of storage bit cells for storing data. As a non-limiting example, the system memory 710 may be read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), and static memory (e.g., flash memory, static random access memory (SRAM), etc.).

[0076] Other devices can be connected to the system bus 712. As illustrated in Figure 7 FIG. 77, these devices can include a system memory 710, one or more input devices 718, one or more output devices 720, a modem 722, and one or more display controllers 724, for example. The input device(s) 718 can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device(s) 720 can include any type of output device, including but not limited to audio, video, other visual indicators, etc. The modem 722 can be any device configured to allow exchange of data to and from a network 726. The network 726 can be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH® network, and the Internet. The modem 722 can be configured to support any type of communications protocol desired. The processor 702 can also be configured to access the display controller(s) 724 over the system bus 712 to control information sent to one or more displays 728. The display(s) 728 can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc. TM

[0077] The processor-based system 700 in FIG. 77 can include a set of instructions 730 for execution by the processor 702 for any of the applications desired for the instructions. The instructions 730 can be stored in the system memory 710, the processor 702, and / or the instruction cache 708, as examples of the non-transitory computer- readable medium 732. The instructions 730 can also reside completely, or at least partially, within the system memory 710 and / or the processor 702 during their execution. The instructions 730 can further be transmitted or received over the network 726 via the modem 722, such that the network 726 includes the computer-readable medium 732.

[0078] While the computer-readable medium 732 is illustrated in the example embodiment as a single medium, the term "computer-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store the one or more sets of instructions. The term "computer-readable medium" shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by a processing device and that causes the processing device to perform any one or more of the methodologies of embodiments disclosed herein. Therefore, the

[0079] ​Embodiments disclosed herein include various steps. The steps of embodiments disclosed herein can be formed by hardware components, or can be embodied in machine-executable instructions, which can be used to program a general-purpose or special-purpose processor to perform the steps. Alternatively, the steps can be performed by a combination of hardware and software.

[0080] Embodiments disclosed herein can be provided as a computer program product, or software, that can include a machine-readable medium (or computer-readable medium) having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes a machine-readable storage medium (e.g., ROM, RAM, magnetic disk storage media, optical storage media, flash memory devices, etc.), and the like.

[0081] Unless specifically stated otherwise and as apparent from the preceding discussion, it is appreciated that throughout the description, discussions utilizing terms such as "processing," "computing," "determining," "displaying," or the like, refer to the action and processes of a computer system, or similar electronic

[0082] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various systems can use the program in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description herein. In addition, the embodiments described herein are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the embodiments described herein.

[0083] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein can be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The components of the distributed antenna system described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein can be any type and size of memory and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such

[0084] The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein can be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. In addition, the controller can be a processor. The processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0085] The embodiments disclosed herein can be embodied in hardware and in instructions stored in hardware, and can reside, for example, in RAM, flash memory, ROM, Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The processor and the storage medium can reside in an ASIC. The ASIC can reside in a remote station. In the alternative, the processor and the storage medium can reside as discrete components in a remote station, a base station, or a server.

[0086] It is also noted that the operational steps described in any of the exemplary embodiments herein are described to provide examples and discussion. The operations can be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step can actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary embodiments can be combined. One of ordinary skill in the art will also understand that information and signals can be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0087] Unless specifically stated otherwise, and as apparent from the preceding

[0088] It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Since modifications, combinations, sub-combinations and variations of the disclosed embodiments incorporating the spirit and substance of the application can occur to persons skilled in the art, the application should not be restricted to the precisely described embodiments and drawings, and it is therefore evident that the application can be practiced otherwise than specifically set forth herein.

Claims

1. A cluster scheduler circuit in a processor, configured to receive a plurality of instructions including producer instructions and consumer instructions to be scheduled for execution, the cluster scheduler circuit comprising: A first time-delay-based reserved circuit is configured as follows: Receive a first consumer instruction that depends on a producer instruction having a single clock cycle delay from among the plurality of instructions; The first consumer instruction is stored in the first reserved entry among multiple first reserved entries; as well as Select from the plurality of first reserved entries a plurality of first consumer instructions that are identified as having a release ready state; A first selection circuit, coupled to the plurality of first reserved entries and the single-clock-cycle delay wake-up signal port, is configured to: Multiple single-clock-cycle delay wake-up signals are received on the single-clock-cycle delay wake-up signal port. Each single-clock-cycle delay wake-up signal is associated with one of the multiple publishing channels. Each of the multiple single-clock-cycle delay wake-up signals indicates the publishing status of the single-clock-cycle delay producer instruction in one of the multiple publishing channels. In response to the association of the plurality of single-clock-cycle-delay wake-up signals with the single-clock-cycle-delay producer instructions of the plurality of first consumer instructions having a publish-ready state, it is determined whether the plurality of first consumer instructions are ready to be scheduled for execution. as well as The plurality of first consumer instructions that identify the release status as release-ready; The second time-delay-based reserved circuit is configured as follows: A second consumer instruction that receives one of the plurality of instructions, which depends on the producer instruction having the same second clock cycle delay of at least two clock cycles; The second consumer instruction is stored in the second reserved entry among multiple second reserved entries; as well as Select from the plurality of second reserved entries the plurality of second consumer instructions that are identified as having a release ready state; A second selection circuit, coupled to the plurality of second reserved entries and the second clock cycle delay wake-up signal port, is configured to: Multiple second clock cycle delay wake-up signals are received on the second clock cycle delay wake-up signal port. Each second clock cycle delay wake-up signal is associated with one of the multiple publishing channels. Each of the multiple second clock cycle delay wake-up signals indicates the publishing status of the second clock cycle delay producer instruction in one of the multiple publishing channels. In response to the association of the plurality of second clock cycle delay wake-up signals with the second clock cycle delay producer instructions of the plurality of second consumer instructions having a release-ready state, it is determined whether the plurality of second consumer instructions are ready to be scheduled for execution; as well as The plurality of second consumer instructions that identify the release-ready status; Multiple publish arbitration circuits, each of which is coupled to an associated publish channel among the multiple publish channels and to a first delay-based reservation circuit and a second delay-based reservation circuit, each of the multiple publish arbitration circuits being configured to pass an instruction among a plurality of first consumer instructions and a plurality of second consumer instructions to its associated publish channel. as well as The system includes multiple publishing channel circuits, each of which is configured to: in response to a single-clock-cycle delay producer instruction published in the publishing channel circuit, generate a single-clock-cycle delay wake-up signal with a publishing ready state among the multiple single-clock-cycle delay wake-up signals on the single-clock-cycle delay wake-up signal port.

2. The cluster scheduler circuit according to claim 1, wherein: The first time-delay-based reserved circuit includes: A plurality of first release selection circuits, each of the plurality of first release selection circuits being associated with and coupled to a corresponding release channel among the plurality of release channels, and each of the plurality of first release selection circuits being configured to select the plurality of first consumer instructions stored in the plurality of first reserved entries in response to a first release channel selection signal identifying a release-ready release state in relation to a plurality of first release channel selection signals specified for the associated release channel; The first selection circuit includes: A first ready circuit coupled to the plurality of first reserved entries and the single-clock-cycle delay wake-up signal port, the first ready circuit being configured to generate a plurality of first instruction ready signals corresponding to the plurality of first consumer instructions in one of the plurality of publishing channels in response to a single-clock-cycle delay producer instruction for the plurality of first consumer instructions; and A plurality of first selection circuits, each first selection circuit being configured to receive the plurality of first instruction ready signals and, in response to the plurality of first consumer instruction ready signals having the release ready release state, generate a plurality of first release channel selection signals, each associated with one of the plurality of release channels, to identify the plurality of first consumer instructions having the release ready release state. The second time-delay-based reserved circuit includes: A plurality of second release selection circuits, each associated with and coupled to a corresponding release channel among the plurality of release channels, and each of the plurality of second release selection circuits is configured to select a plurality of second consumer instructions stored in the plurality of second reserved entries in response to a second release channel selection signal identifying a release-ready release state for the associated release channel; and The second selection circuit includes: A second ready circuit coupled to the plurality of second reserved entries and the second clock cycle delay wake-up signal port, the second ready circuit being configured to generate a plurality of second instruction ready signals corresponding to the plurality of second consumer instructions in one of the plurality of publishing channels in response to a second clock cycle delay producer instruction for the plurality of second consumer instructions; and A plurality of second selection circuits, each configured to receive the plurality of second instruction ready signals and, in response to the plurality of second consumer instruction ready signals having the release ready release state, generate a plurality of second release channel selection signals, each associated with one of the plurality of release channels, to identify the plurality of second consumer instructions having the release ready release state.

3. The cluster scheduler circuit according to claim 1 further includes: A third time-delay-based reserved circuit is configured as follows: A third consumer instruction that receives one of the plurality of instructions, which depends on the same third clock cycle delay having at least two clock cycles and a delay different from the second clock cycle delay; The third consumer instruction is stored in a third reserved entry among multiple third reserved entries; as well as Select from the plurality of third reserved entries a plurality of third consumer instructions that are identified as having a release-ready state. as well as A third selection circuit, coupled to the plurality of third reserved entries and the third clock cycle delay wake-up signal port, is configured to: Multiple third clock cycle delay wake-up signals are received on the third clock cycle delay wake-up signal port. Each third clock cycle delay wake-up signal port is associated with one of the multiple publishing channels. Each of the multiple third clock cycle delay wake-up signals indicates the publishing status of the third clock cycle delay producer instruction in one of the multiple publishing channels. In response to the association of the plurality of third clock cycle delay wake-up signals with the third clock cycle delay producer instructions of the plurality of third consumer instructions having a release-ready state, it is determined whether the plurality of third consumer instructions are ready to be scheduled for execution. as well as The plurality of third consumer instructions that identify the release-ready status; as well as Multiple third-release arbitration circuits, each of which is also coupled to the third delay-based reserved circuit, are each configured to transmit a selected third consumer instruction from among the multiple third consumer instructions to its associated release channel.

4. The cluster scheduler circuit according to claim 2 further includes a wake-up signal latching circuit, wherein the wake-up signal latching circuit is configured to receive a clock cycle delay wake-up signal based on the single clock cycle delay wake-up signal and delay the received clock cycle delay wake-up signal by at least one clock cycle as the second clock cycle delay wake-up signal based on the single clock cycle delay wake-up signal.

5. The cluster scheduler circuit according to claim 4, wherein the wake-up signal latch circuit is configured to delay the clock cycle delay wake-up signal by a second clock cycle delay based on the single clock cycle delay wake-up signal output by the latch, as the second clock cycle delay wake-up signal.

6. The cluster scheduler circuit of claim 2 further includes a publish selection latch circuit, the publish selection latch circuit being configured to receive selected plurality of second consumer instructions selected by the plurality of second publish selection circuits and delay the selected plurality of second consumer instructions by at least one clock cycle.

7. The cluster scheduler circuit of claim 6, wherein the publish selection latch circuit is configured to delay the selected plurality of second consumer instructions by the second clock cycle delay.

8. The cluster scheduler circuit according to claim 6, wherein the second clock cycle delay wake-up signal port and the single clock cycle delay wake-up signal port are the same port.

9. The cluster scheduler circuit of claim 4 further includes a publish selection latch circuit, the publish selection latch circuit being configured to receive selected plurality of second consumer instructions selected by the plurality of second publish selection circuits and delay the selected plurality of second consumer instructions by at least one clock cycle.

10. The cluster scheduler circuit according to claim 1 is further configured as follows: Determine whether the first reserved entry in the first delay-based reserved circuit is available for the received single-clock-cycle delay consumer command; and In response to the first reservation entry in the first delay-based reservation circuit being available for the received single-clock-cycle delay consumer instruction, the first delay-based reservation circuit is further configured to receive the first consumer instruction that further includes the single-clock-cycle delay consumer instruction.

11. The cluster scheduler circuit according to claim 10 is further configured to: In response to the first reservation entry in the first delay-based reservation circuit being unavailable for the received single-clock-cycle delay consumer instruction, the second delay-based reservation circuit having the highest delay compared to the first delay-based reservation circuit is further configured to receive a second consumer instruction that also includes the single-clock-cycle delay consumer instruction.

12. The cluster scheduler circuit according to claim 10 is further configured to: In response to the first reservation entry in the first delay-based reservation circuit being unavailable for the received single-clock-cycle delay consumer instruction, the second delay-based reservation circuit having a next highest delay compared to the first delay-based reservation circuit is further configured to receive a second consumer instruction that also includes the single-clock-cycle delay consumer instruction.

13. The cluster scheduler circuit according to claim 3 is further configured as follows: Determine whether the first reserved entry in the first delay-based reserved circuit can be used for the received single-clock-cycle delay consumer instruction; as well as In response to the first reservation entry in the first delay-based reservation circuit being unavailable for a received single-clock-cycle delay consumer instruction, the cluster scheduler circuit is further configured to determine the delay-based reservation circuit with the best average availability for the instruction among the second delay-based instruction circuit and the third delay-based instruction circuit. as well as In response to the third delay-based instruction having the best average availability for the instruction, the third delay-based reserved circuit is also configured to receive a second consumer instruction that further includes the single-clock-cycle delay consumer instruction.

14. The cluster scheduler circuit of claim 1, wherein if the plurality of first consumer instructions are present at the corresponding publish arbitration circuit, each of the plurality of publish arbitration circuits is configured to pass the selected plurality of first consumer instructions to its associated publish channel.

15. The cluster scheduler circuit of claim 1, wherein if the plurality of first consumer instructions are present at the corresponding publish arbitration circuit, each of the plurality of publish arbitration circuits is configured to pass the selected plurality of second consumer instructions to its associated publish channel.

16. The cluster scheduler circuit of claim 1, wherein each of the plurality of publish arbitration circuits is configured to selectively transmit the plurality of first consumer instructions and the plurality of second consumer instructions to their associated publish channels based on heuristic determination of the plurality of first consumer instructions and the plurality of second consumer instructions.

17. A method for scheduling a plurality of instructions comprising producer instructions and consumer instructions to be executed in execution circuitry in a processor, comprising: Receive a first consumer instruction that depends on the producer instruction having a single clock cycle delay from among the plurality of instructions; The first consumer instruction is stored in the first reserved entry among multiple first reserved entries; Receive multiple single-clock-cycle delay wake-up signals, each of which is associated with one of multiple publishing channels, and each of the multiple single-clock-cycle delay wake-up signals indicates the publishing status of a single-clock-cycle delay producer instruction in one of the multiple publishing channels; In response to the association of the plurality of single-clock-cycle-delay wake-up signals with single-clock-cycle-delay producer instructions of the plurality of first consumer instructions having a publish-ready state, it is determined whether the plurality of first consumer instructions are ready to be scheduled for execution; The plurality of first consumer instructions that identify the release status of being ready for release; Select from the plurality of first reserved entries a plurality of first consumer instructions that are identified as having a release ready state; Receive a second consumer instruction from among the plurality of instructions that depends on a producer instruction having the same second clock cycle delay of at least two clock cycles, the producer instruction having the same second clock cycle delay of at least two clock cycles; The second consumer instruction is stored in the second reserved entry among multiple second reserved entries; Receive multiple second clock cycle delay wake-up signals, each second clock cycle delay wake-up signal being associated with one of the multiple publishing channels, and each of the multiple second clock cycle delay wake-up signals indicating the publishing status of the second clock cycle delay producer instruction in one of the multiple publishing channels; In response to the association of the plurality of second clock cycle delay wake-up signals with the second clock cycle delay producer instructions of the plurality of second consumer instructions having a release-ready state, it is determined whether the plurality of second consumer instructions are ready to be scheduled for execution; The plurality of second consumer instructions that identify the release-ready status; Select from the plurality of second reserved entries a plurality of second consumer instructions that are identified as having a release-ready state; The selected consumer instruction from among the plurality of first consumer instructions and the selected plurality of second consumer instructions is transmitted to its associated publishing channel. as well as In response to the published single-clock-cycle delay producer instruction, a single-clock-cycle delay wake-up signal with a published ready state is generated among the plurality of single-clock-cycle delay wake-up signals.

18. The method of claim 17, further comprising: A third consumer instruction that receives one of the plurality of instructions, which depends on a producer instruction having the same third clock cycle delay of at least two clock cycles and a delay different from the second clock cycle delay. The third consumer instruction is stored in a third reserved entry among multiple third reserved entries; Receive multiple third clock cycle delay wake-up signals, each of the multiple third clock cycle delay wake-up signals being associated with one of the multiple publishing channels, and each of the multiple third clock cycle delay wake-up signals indicating the publishing status of the third clock cycle delay producer instruction in one of the multiple publishing channels; In response to the association of the plurality of third clock cycle delay wake-up signals with the third clock cycle delay producer instructions of the plurality of third consumer instructions having a release-ready state, it is determined whether the plurality of third consumer instructions are ready to be scheduled for execution. The plurality of third consumer instructions that identify the release-ready status; as well as Select from the plurality of third reserved entries a plurality of third consumer instructions that are identified as having a release-ready state. as well as The selected third consumer instruction will be transmitted to its associated publication channel.

19. The method of claim 17, further comprising delaying the clock cycle delay wake-up signal based on the single clock cycle delay wake-up signal by at least one clock cycle as the second clock cycle delay wake-up signal.

20. The method of claim 17, further comprising delaying the selected plurality of second consumer instructions by at least one clock cycle.

21. The method of claim 20, further comprising delaying the clock cycle delay wake-up signal based on the single clock cycle delay wake-up signal by at least one clock cycle as the second clock cycle delay wake-up signal.

22. A processor, comprising: The instruction processing circuit includes one or more instruction pipelines, wherein the instruction processing circuit includes a cluster scheduler circuit and an execution circuit; The instruction processing circuit is configured to fetch multiple instructions from memory into the instruction pipeline of the one or more instruction pipelines; The cluster scheduler circuit is configured to receive multiple instructions, including producer instructions and consumer instructions to be scheduled for execution, and the cluster scheduler circuit includes: The first time-delay-based reserved circuit is configured as follows: Receive a first consumer instruction that depends on the producer instruction having a single clock cycle delay from among the plurality of instructions; The first consumer instruction is stored in the first reserved entry among multiple first reserved entries; and Select from the plurality of first reserved entries a plurality of first consumer instructions that are identified as having a release ready state; A first selection circuit, coupled to the plurality of first reserved entries and the single-clock-cycle delay wake-up signal port, is configured to: Multiple single-clock-cycle delay wake-up signals are received on the single-clock-cycle delay wake-up signal port. Each single-clock-cycle delay wake-up signal is associated with one of the multiple publishing channels. Each of the multiple single-clock-cycle delay wake-up signals indicates the publishing status of the single-clock-cycle delay producer instruction in one of the multiple publishing channels. In response to the association of the plurality of single-clock-cycle-delay wake-up signals with single-clock-cycle-delay producer instructions of the plurality of first consumer instructions having a publish-ready state, it is determined whether the plurality of first consumer instructions are ready to be scheduled for execution; and The plurality of first consumer instructions that identify the release status of being ready for release; The second time-delay-based reserved circuit is configured as follows: Receive a second consumer instruction from among the plurality of instructions that depends on a producer instruction having the same second clock cycle delay of at least two clock cycles. The second consumer instruction is stored in a second reserved entry among multiple second reserved entries; and Select from the plurality of second reserved entries a plurality of second consumer instructions that are identified as having a release-ready state; A second selection circuit, coupled to the plurality of second reserved entries and the second clock cycle delay wake-up signal port, is configured to: Multiple second clock cycle delay wake-up signals are received on the second clock cycle delay wake-up signal port. Each second clock cycle delay wake-up signal is associated with one of the multiple publishing channels. Each of the multiple second clock cycle delay wake-up signals indicates the publishing status of the second clock cycle delay producer instruction in one of the multiple publishing channels. In response to the association of the plurality of second clock cycle delay wake-up signals with the second clock cycle delay producer instructions of the plurality of second consumer instructions having a publish-ready state, it is determined whether the plurality of second consumer instructions are ready to be scheduled for execution; and The plurality of second consumer instructions that identify the release-ready status; Multiple publish arbitration circuits, each coupled to an associated publish channel among the multiple publish channels and coupled to a first delay-based reservation circuit and a second delay-based reservation circuit, each of the multiple publish arbitration circuits being configured to transmit an instruction selected from a plurality of first consumer instructions and a plurality of second consumer instructions to its associated publish channel; and The system includes multiple publishing channel circuits, each of which is configured to: in response to a single-clock-cycle delay producer instruction published in the publishing channel circuit, generate a single-clock-cycle delay wake-up signal with a publishing ready state among the multiple single-clock-cycle delay wake-up signals on the single-clock-cycle delay wake-up signal port.

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