Semiconductor device and data reading method using the same

Abstract

A semiconductor device is provided. The device includes a memory storing data in a non-volatile manner and a volatile manner and a memory controller configured to control the memory. The memory includes a word line pair including a first word line and a second word line, a first bit line pair orthogonal to the first word line and the second word line and including a first bit line and a first complementary bit line, and a storage unit pair including a first storage unit and a second storage unit adjacent to the first storage unit in a word line direction. The first storage unit and the second storage unit each store data in a volatile manner.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a semiconductor device and a data reading method using the same. More particularly, the disclosure relates to a method of storing non-volatile data and volatile data by a semiconductor device. BACKGROUND

[0002] A computer system can include various types of storage systems. In a computer system, a semiconductor device can be used as a main memory. The main memory can include a random access memory (RAM) that is randomly read or written at a fast access speed. A data storage device using a semiconductor can be implemented by using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc. A semiconductor device can be largely divided into a volatile memory device and a non-volatile memory device. The volatile memory device is a memory device in which stored data is erased when a power is turned off. The non-volatile memory device is a memory device that maintains stored data even when a power is turned off.

[0003] The volatile memory device can include a static random access memory (SRAM) or a dynamic RAM (DRAM). The SRAM has lower power consumption and faster operating characteristics than the DRAM, and has been widely used in computer cache devices or portable electronic products. As methods of using data stored in a memory device have diversified, a demand for a hybrid memory device capable of storing non-volatile data and volatile data has increased.

[0004] The above information is presented as background information only to assist with an understanding of the disclosure. No determination has been made, and no assertion is made, as to whether any of the above might be applicable as prior art with regard to the disclosure. SUMMARY

[0005]

Technical Problem

[0006] Aspects of the disclosure are to address at least the above-mentioned problems and / or disadvantages, and to provide at least the advantages described below. Accordingly, an aspect of the disclosure is to provide an apparatus and method of storing non-volatile data and volatile data by a semiconductor device.

[0007] Another aspect of the disclosure is to provide a semiconductor device for storing data in a non-volatile manner and a volatile manner.

[0008]

Technical Solution

[0009] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following description and / or can be learned by practice of the presented embodiments of the disclosure.

[0010] According to an aspect of the disclosure, there is provided a semiconductor device. The device includes a memory storing data in a non-volatile manner and a volatile manner, and a memory controller configured to control the memory. Wherein the memory includes a pair of word lines including a first word line and a second word line, a pair of bit lines orthogonal to the first word line and the second word line and including a first bit line and a first complementary bit line, a pair of storage cells including a first storage cell and a second storage cell adjacent to the first storage cell in a word line direction, the first storage cell and the second storage cell each storing data in a volatile manner. A left node of the first storage cell connected to the first bit line, and a right node of the first storage cell connected to the first complementary bit line and a left node of the second storage cell are all connected to a first word line selected from among the first word line and the second word line. And a value of data stored in the pair of storage cells in a non-volatile manner is determined according to the first word line to which the left node of the first storage cell, the right node of the first storage cell, and the left node of the second storage cell are connected.

[0011] Other aspects, advantages, and salient features of the disclosure will become apparent to those skilled in the art from the following detailed description, which, taken in

[0012]

Advantageous Effects

[0013] Aspects of the disclosure provide an apparatus and method of storing non-volatile data and volatile data performed by a semiconductor device.

[0014] Another aspect of the disclosure provides a semiconductor device for storing data in a non-volatile manner and a volatile manner. BRIEF DESCRIPTION OF DRAWINGS

[0015] The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the disclosure;

[0017] Figure 2 is an equivalent circuit diagram of a static random access memory (SRAM) cell according to an embodiment of the disclosure;

[0018] Figure 3 shows a pair of storage cells according to an embodiment of the disclosure;

[0019] Figure 4A shows a pair of storage cells storing 4-bit data in a non-volatile manner according to an embodiment of the disclosure;

[0020] Figure 4B shows a pair of storage cells according to an embodiment of the disclosure;Figure 4A structure of a pair of storage units;

[0021] Figure 5 is a flowchart of a method of reading data stored in a storage unit in a volatile manner according to an embodiment of the present disclosure;

[0022] Figure 6 is a flowchart of a method of storing data in a storage unit in a volatile manner according to an embodiment of the present disclosure;

[0023] Figure 7 is a flowchart of a method of reading data stored in a pair of storage units in a non-volatile manner according to an embodiment of the present disclosure;

[0024] Figure 8 shows a pair of storage units according to an embodiment of the present disclosure;

[0025] Figure 9 shows a plurality of pairs of storage units according to an embodiment of the present disclosure;

[0026] Figure 10 shows a plurality of storage units according to an embodiment of the present disclosure;

[0027] Figure 11 is a flowchart of a method of reading data stored in a pair of storage units in a non-volatile manner according to an embodiment of the present disclosure;

[0028] Figure 12 shows a logical expression for detecting data stored in a pair of storage units in a non-volatile manner according to an embodiment of the present disclosure;

[0029] Figure 13 is a block diagram of an electronic device including a semiconductor device according to an embodiment of the present disclosure;

[0030] Figure 14 is a block diagram of an electronic device according to an embodiment of the present disclosure; and

[0031] Figure 15 shows a circuit block of an electronic device according to an embodiment of the present disclosure.

[0032] In all the drawings, the same reference numerals are used for the same elements. DETAILED DESCRIPTION

[0033] According to an aspect of the disclosure, a semiconductor device is provided. The device includes a memory storing data in a non-volatile manner and a volatile manner and a memory controller configured to control the memory. The memory includes: a word line pair including a first word line and a second word line; a first bit line pair perpendicular to the first word line and the second word line and including a first bit line and a first complementary bit line; and a storage unit pair including a first storage unit and a second storage unit adjacent to the first storage unit in a word line direction. The first storage unit and the second storage unit each store data in a volatile manner. A left node of the first storage unit connected to the first bit line, a right node of the first storage unit connected to the first complementary bit line, and a left node of the second storage unit are all connected to a first word line selected from among the first word line and the second word line, and a value of data stored in the storage unit pair in a non-volatile manner is determined according to the first word line to which the left node of the first storage unit, the right node of the first storage unit, and the left node of the second storage unit are connected.

[0034]

[0035] The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of various embodiments of the disclosure as defined by the claims and their equivalents. It includes various specific details for the purposes of explanation, but these are merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the various embodiments described herein can be made without departing from the scope and spirit of the disclosure. Also, descriptions of well-known functions and constructions can be omitted for clarity and conciseness.

[0036] The terms and words used in the following description and claims are not limited to the bibliographical meanings, but are merely used by the inventor to enable a clear and consistent understanding of the disclosure. Accordingly, it should be apparent to those skilled in the art that the following description of various embodiments of the present disclosure is provided for illustration purpose only and not for limiting the disclosure as defined by the appended claims and their equivalents.

[0037] It should be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a component surface" includes reference to one or more of such surfaces.

[0038] Throughout the disclosure, the expression "at least one of a, b, or c" means only a; only b; only c; both a and b; both a and c; both b and c; all of a, b, and c, or variations thereof.

[0039] ​The present disclosure can be described according to functional block components and various processing steps. Such functional blocks can be realized by any number of hardware and / or software components configured to perform the specified functions. For example, the functional blocks of the present disclosure can be implemented by one or more microprocessors or circuit elements for certain functions. Also, for example, the functional blocks of the present disclosure can be implemented by various programming languages or scripting languages. Aspects of the functional blocks can be implemented in algorithms that are executed on one or more processors.

[0040] In addition, the present disclosure can employ any number of conventional techniques for electronic configuration, signal processing and / or control, data processing, and the like. Also, the connecting lines or connectors shown in the various figures indicated are intended to represent functional relationships and / or physical or logical couplings between the various elements. It should be noted that many alternative or additional functional relationships, physical connections or logical connections can be present in actual devices.

[0041] In addition, the terms such as "unit" and "module" stated in the specification can represent a unit processing at least one function or operation, and the unit can be implemented by hardware, software, or a combination of hardware and software. The terms such as "unit" and "module" stated in the specification can be stored in an addressable storage medium and can be implemented by a program executable by a processor.

[0042] In addition, for ease of description, spatially relative terms such as "below", "under", "lower", "above", "upper", and the like, can be used herein for describing the relationship between one element or feature and another element or feature as shown in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. For example, if a device is turned over, elements described as "below" or "under" other elements or components would then be oriented "above" the other elements or components. Thus, the term "below" or "under" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90° about a vertical axis, for example) and the spatially relative descriptors used herein interpreted accordingly. The relevant descriptions can be interpreted in accordance with the disclosure made herein when the device is oriented in a different direction (rotated 90° about a vertical axis relative to another direction, for example).

[0043] However, the present disclosure can be implemented in many different forms and should not be construed as being limited to the embodiments of the present disclosure set forth herein; rather, these embodiments of the present disclosure are provided so that the present disclosure will be thorough and complete, and will fully convey the concept of the present disclosure to those skilled in the art. In addition, the various embodiments of the present disclosure can operate in combination with each other as needed. For example, one embodiment of the present disclosure and parts of another embodiment of the present disclosure can be combined with each other and used for the operation of a device.

[0044] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0045] Referring to Figure 1 , the semiconductor device 100 can include a memory controller 110 and a memory 120.

[0046] The semiconductor device 100 can store data in the memory 120. In an embodiment of the present disclosure, the semiconductor device 100 can store data in a non-volatile manner. In addition, the semiconductor device 100 can store data in a volatile manner. In the specification, storing data in a volatile manner can mean that the stored data is erased when power supply to the semiconductor device 100 is cut off. Storing data in a non-volatile manner can mean that the stored data is maintained even when the power supply of the semiconductor device 100 is cut off.

[0047] The memory controller 110 can control the overall operation of the semiconductor device 100. In detail, the memory controller 110 can store data in the memory 120 or read data stored in the memory 120.

[0048] The memory 120 can include a non-volatile memory 121 that stores data in a non-volatile manner and a volatile memory 122 that stores data in a volatile manner. The memory controller 110 can read data stored in the non-volatile memory 121 in a non-volatile manner. In addition, the memory controller 110 can store data in the volatile memory 122 in a volatile manner or read data stored in the volatile memory 122 in a volatile manner.

[0049] The memory controller 110 according to the embodiment of the disclosure can control the memory 120 in response to control information received from the outside. In the embodiment of the disclosure, the control information can be information indicating at least one of the nonvolatile memory 121 or the volatile memory 122. In the embodiment of the disclosure, the control information can indicate at least one of the nonvolatile memory 121 or the volatile memory 122 by using address values of the nonvolatile memory 121 and the volatile memory 122. In response to the control information, the memory controller 110 can read data stored in the memory 120 in a nonvolatile manner or a volatile manner, or store data in a volatile manner.

[0050] In the embodiment of the disclosure, data stored in the nonvolatile memory 121 can be immutable. Data immutability can mean that data is not rewritten by the memory controller 110. In this case, the memory controller 110 can read data stored in the nonvolatile memory 121, but can not perform a data write operation on the nonvolatile memory 121. However, data stored in the nonvolatile memory 121 can be rewritten by an operation of changing a physical connection of a device included in the nonvolatile memory 121.

[0051] Although Figure 1 Although the memory 120 is shown to include the nonvolatile memory 121 and the volatile memory 122, respectively, in the embodiment of the disclosure, the nonvolatile memory 121 and the volatile memory 122 can be memories logically divided on a single physical memory. In other words, the nonvolatile memory 121 and the volatile memory 122 can overlap and share the same physical space to store data. Accordingly, the semiconductor device 100 according to the embodiment of the disclosure can efficiently store data stored in a nonvolatile manner and data stored in a volatile manner within limited physical resources.

[0052] Specifically, the volatile memory 122 according to the embodiment of the disclosure can electrically store data in a storage cell by using a characteristic of a semiconductor device. In contrast, the nonvolatile memory 121 according to the embodiment of the disclosure can store data in a volatile manner based on a pattern of a physical connection between circuit elements including a storage cell in which data is electrically stored. The pattern of the physical connection between the circuit elements can be maintained regardless of a power supply, and can be independent of data electrically stored in the storage cell.

[0053] The memory 120 can include an array of storage units for storing data. The array of storage units can include a plurality of storage units. In an embodiment of the disclosure, the storage units can constitute a plurality of pairs of storage units. The pair of storage units can include two storage units. However, the array of storage units and the method of implementing the pair of storage units are not limited to the above-described example. For example, the pair of storage units can be implemented in the form of a group of storage units including N storage units.

[0054] In the following description, the storage unit included in the semiconductor device 100 is, for example, an SRAM cell. However, the technical features of the disclosure are not limited to the above-described example, and those skilled in the art will understand that the technical features of the disclosure are applicable to other forms of storage units having similar technical features.

[0055] Figure 2 is an equivalent circuit diagram of an SRAM cell according to an embodiment of the disclosure.

[0056] Referring to Figure 2 , the SRAM cell can be connected to a bit line pair including a bit line BL and a complementary bit line BLB and a word line WL through a left connection transistor TL and a right connection transistor TR. The SRAM cell can include a plurality of transistors, for example, a left load transistor PL and a right load transistor PR and a left drive transistor NL and a right drive transistor NR. However, those skilled in the art will understand that the SRAM cell implementation method can be various in addition to Figure 2 the example.

[0057] In an embodiment of the disclosure, the left load transistor PL and the right load transistor PR can include p-type metal oxide semiconductor (PMOS) transistors. In addition, the left connection transistor TL and the right connection transistor TR and the left drive transistor NL and the right drive transistor NR can include n-type metal oxide semiconductor (NMOS) transistors.

[0058] Referring to Figure 2 , the gate of each of the left connection transistor TL and the right connection transistor TR can be electrically connected to the word line WL. The drain region of each of the left connection transistor TL and the right connection transistor TR can be electrically connected to the bit line pair BL and BLB. In addition, the source region of each of the left load transistor PL and the right load transistor PR can be connected to a first power supply voltage Vdd, and the source region of each of the left drive transistor NL and the right drive transistor NR can be connected to a second power supply voltage GND. In this state, the first power supply voltage Vdd can be a power supply voltage having a high voltage level, and the second power supply voltage GND can be a ground power supply voltage.

[0059] In Figure 2In the SRAM cell, the source region of the left connection transistor TL, the drain region of the left load transistor PL, and the drain region of the left drive transistor NL can be commonly electrically connected to a first node N1. The first node N1, which is a left node of the SRAM cell, can be an output node of the first inverter. Further, the source region of the right connection transistor TR, the drain region of the right load transistor PR, and the drain region of the right drive transistor NR can be commonly electrically connected to a second node N2. The second node N2, which is a right node of the SRAM cell, can be an output node of the second inverter.

[0060] In this state, the source region of the left connection transistor TL, the drain region of the left load transistor PL, and the drain region of the left drive transistor NL can be commonly electrically connected to a first node N1. The first node N1, which is a left node of the SRAM cell, can be an output node of the first inverter. Further, the source region of the right connection transistor TR, the drain region of the right load transistor PR, and the drain region of the right drive transistor NR can be commonly electrically connected to a second node N2. The second node N2, which is a right node of the SRAM cell, can be an output node of the second inverter.

[0061] In other words, the gates of each of the left load transistor PL and the left drive transistor NL can be commonly electrically connected to the second node N2, thereby constituting a first latch circuit. The gates of each of the right load transistor PR and the right drive transistor NR can be commonly electrically connected to the first node N1, thereby constituting a second latch circuit.

[0062] Reference Figure 2 The first node N1 and the second node N2, which are output nodes of the first inverter and the second inverter, respectively, are connected to input nodes of another inverter. In other words, the output node N1 of the first inverter is connected to the input node I2 of the second inverter, and the output node N2 of the second inverter is connected to the input node I1 of the first inverter.

[0063] Based on the above connection structure, the SRAM cell can include the first inverter, the second inverter, and a circuit element CE including a wiring for connecting input / output nodes (nodes N1 and N2) thereof. The circuit element CE can be a flip-flop circuit or a latch circuit as an information accumulation unit that stores 1-bit information in a volatile manner.

[0064] In the following description, a method of storing data in the SRAM cell in a volatile manner and a method of reading data stored in the SRAM cell in a volatile manner are described.

[0065] When the first node N1 of the first inverter is in a high voltage level state, the right drive transistor NR is in an on state, and thus the second node N2 of the second inverter is in a low voltage level state. Accordingly, the left drive transistor N1 is in an off state, and the high voltage level state of the first node N1 can be maintained. In other words, the voltage level states of the first node N1 and the second node N2 can be maintained by the latch circuit that cross-connects the first and second inverters, and thus the data stored in the SRAM cell can be maintained during the application of the first power voltage Vdd.

[0066] To store data in the SRAM cell, a high level voltage can be applied to the word line WL. Also, based on a value of the data stored in a volatile manner, voltages having complementary levels to each other can be applied to the bit line BL included in the bit line pair BL and the complementary bit line BLB. For example, when a data value "1" is to be stored, a high level voltage can be applied to the bit line BL, while a low level voltage can be applied to the complementary bit line BLB. When a data value "0" is to be stored, a low level voltage can be applied to the bit line BL, while a high level voltage can be applied to the complementary bit line BLB.

[0067] Based on the voltage of the word line WL, the left connection transistor TL and the right connection transistor TR are in an on state, and thus voltage level states of the bit line pair BL and BLB can be applied to the first and second nodes N1 and N2. A data value stored in the SRAM cell in a volatile manner can be detected based on the voltage level states of the first and second nodes N1 and N2. For example, when the first node N1 is in a high voltage level state and the second node N2 is in a low voltage level state, it can be detected later that a data value "1" is stored in the SRAM cell. Alternatively, when the first node N1 is in a low voltage level state and the second node N2 is in a high voltage level state, it can be detected later that a data value "0" is stored in the SRAM cell.

[0068] To read data stored in the SRAM cell, a high level voltage (hereinafter referred to as a read voltage) can also be applied to the word line WL. Also, a pre-charge voltage can be provided to the bit line pair BL and BLB. Based on the high level voltage of the word line WL, the left connection transistor TL and the right connection transistor TR can be in an on state. Since the latch circuit and the bit line pair BL and BLB are electrically connected to each other, voltage level states of the first and second nodes N1 and N2 can occur on the bit line pair BL and BLB. The voltage level states of the bit line pair BL and BLB can be detected as data stored in the SRAM cell.

[0069] Figure 3 A storage cell pair according to an embodiment of the disclosure is illustrated. The storage cell pair can include two storage cells.

[0070] Reference Figure 3 A storage cell array including a plurality of storage cell pairs can have a cross-point structure. The cross-point structure can mean a structure in which one storage cell is formed in an area in which at least one word line and at least one bit line intersect each other.

[0071] The memory cell array can have a three-dimensional stacked structure. The three-dimensional stacked structure can mean a structure in which a plurality of memory cell layers including a plurality of memory cells are vertically stacked. When the memory cell array has the three-dimensional stacked structure, each memory cell layer can have a cross-point structure, but the present disclosure is not limited thereto.

[0072] Figure 3 The memory cell pair can store 2-bit data in a volatile manner by using the first memory cell and the second memory cell. In addition, the memory cell pair can store 2-bit data in a non-volatile manner by using the physical connection pattern of the first memory cell and the physical connection pattern of the second memory cell.

[0073] Referring to Figure 3 , the memory cell pair can be connected to a word line pair including a plurality of word lines to store data in a non-volatile manner, which will be described in detail below with reference to the accompanying drawings.

[0074] The memory cell pair can be electrically connected to a word line pair including a first word line WL1 and a second word line WL2 and a bit line pair including a bit line BL and a complementary bit line BLB. As described above, the memory cell pair can include a first memory cell and a second memory cell. In an embodiment of the present disclosure, each memory cell can be a memory cell storing 1-bit data in a volatile manner. Figure 2

[0075] Based on data to be stored in a non-volatile manner in the memory cell, the first and second left connection transistors TL1 and TL2 of each memory cell included in the memory cell pair can be connected to one selected from the word lines included in the word line pair. In this state, the gate of the left connection transistor connected to a particular word line can mean that the gate of the left connection transistor is electrically connected to the particular word line via a contact point.

[0076] In detail, each memory cell can store 1-bit data in a non-volatile manner based on the word line to which the gate of the left connection transistor is connected. For example, the left connection transistor of the memory cell connected to the first word line WL1 can mean that a data value "0" is stored in the memory cell. In addition, the left connection transistor of the memory cell connected to the second word line WL2 can mean that a data value "1" is stored in the memory cell. Referring to Figure 3 , it is exemplarily shown that the first memory cell and the second memory cell store a data value "1" and a data value "0", respectively, in a non-volatile manner. In other words, in the structure of Figure 3 , the memory cell pair can store a data value "10" in a non-volatile manner.

[0077] ​Each data stored in the storage unit in a non-volatile manner can be maintained while the word line of the left connection transistor connected to each storage unit is maintained. Since the left connection transistor of each storage unit and the word line are connected to each other via a physically formed contact point, the data stored in the storage unit in a non-volatile manner can be maintained even when the power of the semiconductor device 100 is turned off.

[0078] The pair of storage units according to the embodiments of the present disclosure can store data in a volatile manner in the storage unit and also store data in a non-volatile manner in the storage unit by using the word line connected to the storage unit. Figure 2 The pair of storage units according to the embodiments of the present disclosure can store data in a volatile manner in the storage unit and also store data in a non-volatile manner in the storage unit by using the word line connected to the storage unit. Figure 3 As shown in FIG. 1, the pair of storage units includes two storage units, and 2-bit data can be stored in a volatile manner and a non-volatile manner. Those skilled in the art will understand that the number of storage units included in the pair of storage units as shown in FIG. 1, when the pair of storage units includes N storage units, N-bit data can be stored in a volatile manner and a non-volatile manner. In other words, the pair of storage units can store 2N-bit data by using N storage units. When designing the storage unit array, since the addition of the word line has little effect on the layout of the device, the pair of storage units can effectively store additional data in a non-volatile manner by adding one word line. Figure 3

[0079] When designing the storage unit array, in order to improve the integration, the transistors, word lines, and bit lines included in the storage unit array are effectively arranged on the substrate. In this state, in order to achieve an effective layout, the left connection transistor and the right connection transistor of the storage unit adjacent in the word line direction can share the contact point connected to the word line. In other words, the left connection transistor and the right connection transistor of the storage unit adjacent in the word line direction can be connected to the same word line. In addition, the first left connection transistor TL1 and the second right connection transistor TR2 can be connected to the same word line.

[0080] Therefore, as shown in FIG. 1, the first right connection transistor TR1 of the first storage unit and the second left connection transistor TL2 of the second storage unit can be connected to the same word line, i.e., the first word line WL1. Figure 3

[0081] According to the above layout, based on the logical value of the data to be stored in the second storage unit in a non-volatile manner, the word line to which the second left connection transistor TL2 of the second storage unit is connected is detected. Therefore, based on the word line to which the second left connection transistor TL2 of the second storage unit is connected, the word line to which the first right connection transistor TR1 of the first storage unit adjacent to the second storage unit can be detected as the same word line.

[0082] Figure 4A ​​Embodiments of the present disclosure are shown that a pair of storage cells stores 4-bit data in a non-volatile manner. Figure 4A Each of the pair of storage cells of Figure 3 the pair of storage cells.

[0083] Referring to Figure 4A , for example, a first pair of storage cells including a first storage cell (Cell 1) and a second storage cell (Cell 2) stores data "01" in a non-volatile manner, and a second pair of storage cells including a third storage cell (Cell 3) and a fourth storage cell (Cell 4) stores data "10" in a non-volatile manner.

[0084] As described above, for efficient layout, the left connection transistor AXL and the right connection transistor AXR of the storage cells adjacent in the word line direction are connected to the same word line. Therefore, the right connection transistor AXR of the first storage cell Cell 1 and the left connection transistor AXL of the second storage cell Cell 2 can be connected to the same word line, that is, the second word line WL2, the right connection transistor AXR of the second storage cell Cell 2 and the left connection transistor AXL of the third storage cell Cell 3 can be connected to the same word line, that is, the second word line WL2, and the right connection transistor AXR of the third storage cell Cell 3 and the left connection transistor AXL of the fourth storage cell Cell 4 can be connected to the same word line, that is, the first word line WL1.

[0085] Figure 4B A structure of Figure 4A the pair of storage cells is shown. In detail, Figure 4B is Figure 4A a plan view of the pair of storage cells of

[0086] Referring to Figure 4B , the left connection transistor and the right connection transistor in the adjacent storage cells are arranged to share a contact via connected to a word line. By using the above-described layout, the pair of storage cells can be efficiently arranged in a limited space while being connected to one of a plurality of word lines formed in parallel via the contact via.

[0087] Figures 5 to 7 is a flowchart of a method of storing data in or reading stored data from the storage cells of Figure 3

[0088] Figure 5 is a flowchart of a method of reading data stored in a storage cell in a volatile manner according to an embodiment of the present disclosure.

[0089] Referring to Figure 5 ​In operation S510, a read voltage can be provided to the first and second word lines. In an embodiment of the disclosure, the read voltage can be a voltage high enough to put the transistors in an on state, the gate of each transistor being connected to the word line to which the read voltage is provided. In operation S510, when the read voltage is provided to all the word lines, the left connection transistor and the right connection transistor of the storage unit are in an on state regardless of which word line the left connection transistor and the right connection transistor are connected to.

[0090] In operation S520, the voltage level state of the bit line connected to the storage unit via the left connection transistor and the voltage level state of the complementary bit line connected to the storage unit via the right connection transistor are detected. In an embodiment of the disclosure, a pre-charge voltage or a pre-charge current can be previously provided to the bit line and the complementary bit line.

[0091] When the left connection transistor is in an on state, the voltage level state of the left node of the storage unit can appear on the bit line. Likewise, when the right connection transistor is in an on state, the voltage level state of the right node of the storage unit can appear on the complementary bit line. As described with reference to Figure 2 Since the left node and the right node of the storage unit are connected by the inverter and have opposite voltage level states, the voltage level state of the bit line and the voltage level state of the complementary bit line can also be opposite to each other.

[0092] In operation S530, based on the voltage level state of the bit line and the voltage level state of the complementary bit line, the logic value of the data stored in the storage unit in a volatile manner can be detected. For example, when the voltage level state of the bit line is in a high voltage level state and the voltage level state of the complementary bit line is in a low voltage level state, it can be detected that the logic value "1" is stored in the storage unit. The logic values "1" and "0" correspond to the data values "1" and "0" stored in the storage unit. Conversely, when the voltage level state of the bit line is in a low voltage level state and the voltage level state of the complementary bit line is in a high voltage level state, it can be detected that the logic value "0" is stored in the storage unit.

[0093] Figure 6 is a flowchart of a method of storing data in a storage unit in a volatile manner according to an embodiment of the disclosure.

[0094] Reference Figure 6In operation S610, a write voltage is supplied to the first and second word lines. In an embodiment of the disclosure, the write voltage can be a voltage high enough to put the transistors in an on state, the gate of each transistor being connected to the word line. The write voltage can be a voltage at the same level as the read voltage, but the technical features of the disclosure are not limited thereto. When the write voltage is supplied to all the word lines, the left and right connection transistors are in an on state regardless of which word line the left and right connection transistors are connected to.

[0095] In operation S620, a voltage corresponding to the level of the logical value of the data is supplied to the bit line, and a voltage corresponding to the level of the logical value opposite to the logical value of the data is supplied to the complementary bit line. For example, assuming that a data value of "1" is to be stored in the storage unit in a volatile manner, a high-level voltage corresponding to the data value of "1" can be supplied to the bit line, and a low-level voltage corresponding to the data value of "0" can be supplied to the complementary bit line. When the left connection transistor is in an on state, the voltage level state of the bit line can appear on the left node of the storage unit. Likewise, when the right connection transistor is in an on state, the voltage level state of the complementary bit line can appear on the right node of the storage unit.

[0096] When a prohibit voltage is later supplied to the first and second word lines, both the left and right connection transistors of the storage unit can be in an off state. In an embodiment of the disclosure, the prohibit voltage can be a voltage low enough to put the transistors in an off state, the gate of each transistor being connected to the word line. For example, the prohibit voltage can be a ground supply voltage. As described with reference to Figure 2 When both the left and right connection transistors are in an off state, the voltage level states of the left and right nodes of the storage unit can be saved as data stored in the storage unit in a volatile manner due to the latch structure of the storage unit while a supply voltage is applied to the storage unit, as described with reference to

[0097] Figure 7 is a flowchart of a method of reading data stored in a storage unit in a non-volatile manner according to an embodiment of the disclosure.

[0098] Referring to Figure 7 In operation S710, data previously stored in the storage unit in a volatile manner is stored in a buffer (not shown). In an embodiment of the disclosure, the data stored in the storage unit in a volatile manner can be read out by the method described with reference to Figure 5 and stored in the buffer.

[0099] According to Figure 7In the process of reading data stored in the storage unit in a non-volatile manner, data stored in the storage unit in a volatile manner can be destroyed in embodiments of the present disclosure. Accordingly, in order to restore data stored in the storage unit in a volatile manner, data stored in the storage unit in a volatile manner can be stored in a buffer before reading data stored in a non-volatile manner. Then, when the read operation with respect to data stored in a non-volatile manner is completed, the semiconductor device can store data stored in the buffer in the storage unit in a volatile manner again.

[0100] In operation S720, a read voltage is provided to the first word line and the second word line, and a data value "1" can be stored in the storage unit in a volatile manner. In operation S720, a method of storing a data value "1" in the storage unit can be the same as described with reference to Figure 6 In other words, a high-level voltage corresponding to a data value "1" can be provided to the bit line, and a low-level voltage corresponding to a data value "0" can be provided to the complementary bit line, thereby storing data.

[0101] In operation S730, an operation of storing a data value "0" in the storage unit in a volatile manner is performed. In this state, although a prohibit voltage can be provided to the first word line, a read voltage can be provided to the second word line.

[0102] In embodiments of the present disclosure, a low-level voltage corresponding to a data value "0" can be provided to the bit line, and a high-level voltage corresponding to a data value "1" can be provided to the complementary bit line. Based on the voltage provided to the word line, only the transistor connected to the second word line can be in an on state, and the transistor connected to the first word line can be in an off state. Accordingly, although a data value "0" is stored in the storage unit in which the left connection transistor is connected to the second word line in a volatile manner, a data value "1" stored in the storage unit in which the left connection transistor is connected to the first word line in operation S720 can be maintained.

[0103] In operation S740, data stored in the storage unit in a volatile manner is read, and a logic value of data stored in the storage unit in a non-volatile manner can be detected based on the read data. For example, when a data value "0" is read from the storage unit, the semiconductor device can detect that the left connection transistor of the storage unit is connected to the second word line. In other words, the semiconductor device can detect that a data value "1" as a second logic value is stored in the storage unit in a non-volatile manner. In contrast, when a data value "1" is read from the storage unit, the semiconductor device can detect that the left connection transistor of the storage unit is connected to the first word line. In other words, the semiconductor device can detect that a data value "0" as a first logic value is stored in the storage unit in a non-volatile manner.

[0104] According to the reference Figure 7 The data read method described above, in the process of reading data stored in the storage unit in a non-volatile manner, it can be necessary to temporarily store the data stored in the storage unit in the buffer in a volatile manner and then restore the stored data. In addition, multiple data storage operations can be requested to read data stored in a non-volatile manner. Therefore, reading data stored in a non-volatile manner can require more clock cycles than reading data stored in a volatile manner.

[0105] Figure 8 A storage unit pair according to an embodiment of the disclosure is shown.

[0106] According to the reference Figure 8 In order to store data in a non-volatile manner, the storage unit pair can be connected to a word line pair including a plurality of word lines. Although Figure 8 The word line pair is shown to include two word lines, and the number of word lines included in the word line pair can vary depending on the layout of the substrate and the configuration of the circuit.

[0107] At least one of the left connection transistor and the right connection transistor of the storage unit included in the storage unit pair (i.e., the first storage unit, for example, in Figure 8 Figure 8 The left connection transistor and the right connection transistor of at least one of the storage units included in the storage unit pair (i.e., the first storage unit, for example, in

[0108] The storage unit pair is electrically connected to a word line pair including a first word line WL1 and a second word line WL2 and a bit line pair including a bit line BL and a complementary bit line BLB. According to the reference Figure 8 The storage unit pair can include a first storage unit and a second storage unit.

[0109] Figure 8 The storage unit pair of the reference can store 2-bit data in a volatile manner by using the first storage unit and the second storage unit. In addition, the storage unit pair can store 1-bit data in a non-volatile manner by using the physical connection mode of the first storage unit.

[0110] According to the reference Figure 8 In order to store data in a non-volatile manner, the storage unit pair can be connected to a word line pair including a plurality of word lines, which will be described in detail below with reference to the accompanying drawings.

[0111] ​The left and right connection transistors of the first storage unit included in the pair of storage units can be connected to one of the word lines included in the pair of word lines, which is selected based on the data to be stored in the pair of storage units in a non-volatile manner. In this state, the gate of the left and right connection transistors being connected to the particular word line can mean that the gate of each of the left and right connection transistors is electrically connected to the particular word line via a contact point.

[0112] In detail, the pair of storage units can store 1-bit data in a non-volatile manner based on the word line to which the gates of the first left connection transistor TL1 and the first right connection transistor TR1 of the first storage unit are connected. For example, the first left connection transistor TL1 and the first right connection transistor TR1 being connected to the first word line WL1 can mean that a data value of “0” is stored in the pair of storage units. Also, the first left connection transistor TL1 and the first right connection transistor TR1 being connected to the second word line WL2 can mean that a data value of “1” is stored in the pair of storage units. In Figure 8 In the embodiment, the pair of storage units is illustrated as, for example, a pair of storage units storing a data value of “1”. However, it will be understood by those skilled in the art that the logical value corresponding to the physical connection pattern of the first storage unit is not limited to the above-described example.

[0113] As described above, in order to achieve an efficient layout, the left and right connection transistors of adjacent storage units can share a contact point connected to a word line. Accordingly, the word line connected to the second left connection transistor TL2 of the second storage unit can be selected based on the word line connected to the first right connection transistor TR1 of the first storage unit.

[0114] In other words, according to an embodiment of the disclosure of Figure 8 all of the first left connection transistor TL1 of the first storage unit, the first right connection transistor TR1 of the first storage unit, and the second left connection transistor TL2 of the second storage unit can be connected to the same word line.

[0115] In other words, since the word line to which the second left connection transistor TL2 of the second storage unit is connected is determined based on the word line connected to the first left connection transistor TL1 of the first storage unit, the pair of storage units of Figure 3 are different from the pair of storage units of Figure 8 The second storage unit of the pair of storage units of

[0116] The data stored in the pair of storage cells in a non-volatile manner can be maintained while the data word line connected to the left connection transistor and the right connection transistor of the first storage cell remains unchanged. Since the left connection transistor and the word line of the first storage cell are connected to each other via a physically formed contact point, the data stored in the pair of storage cells in a non-volatile manner can be maintained even when the power supply to the semiconductor device 100 is cut off.

[0117] Therefore, when data is stored in the first and second storage cells in a volatile manner in the method described with reference to Figure 2 , the pair of storage cells can store data in a non-volatile manner by using the word line connected to the first storage cell.

[0118] The pair of storage cells including two storage cells Figure 8 can store 2-bit data in a volatile manner. In addition, the pair of storage cells can store 1-bit data in a non-volatile manner by using the physical connection mode of the first storage cell. In other words, the pair of storage cells can store 3-bit data by using two storage cells. When designing a storage cell array, since the addition of a word line has little effect on the layout of the device, the pair of storage cells can effectively store additional data in a non-volatile manner by adding at least one word line.

[0119] In the pair of storage cells Figure 8 , since the left connection transistor and the right connection transistor of the first storage cell are connected to the same word line, a data write operation with respect to the first storage cell can not be necessary in a process of reading out data stored in the pair of storage cells Figure 8 in a non-volatile manner. Therefore, data stored in the first storage cell in a volatile manner is not destroyed in a process of reading out data stored in the pair of storage cells in a non-volatile manner. As will be described with reference to Figure 11 , the time of an operation of reading out data stored in the pair of storage cells Figure 8 in a non-volatile manner can be as short as the time of an operation of reading out data stored in a volatile manner.

[0120] In addition, in the pair of storage cells Figure 8 , since the right connection transistor of the first storage cell and the left connection transistor of the second storage cell are connected to the same word line via the same contact via, the pair of storage cells can be disposed on a substrate with high integration. Therefore, the pair of storage cells Figure 8 can be manufactured in a small area having a fast read speed for both data stored in a volatile manner and data stored in a non-volatile manner.

[0121] Figure 9 A plurality of pairs of storage cells according to an embodiment of the disclosure is illustrated. Each pair of storage cells can be the pair of storage cells 100 described with reference toFigure 8 The described pair of storage cells.

[0122] Referring to Figure 9 , in order to store data in a non-volatile manner, each pair of storage cells can be connected to a pair of word lines including a plurality of word lines. For example, in Figure 9 , a first pair of storage cells can include a first storage cell and a second storage cell, and a second pair of storage cells can include a third storage cell and a fourth storage cell.

[0123] Each storage cell can be connected to a pair of word lines including a first word line WL1 and a second word line WL2. In addition, each storage cell can be electrically connected to a pair of bit lines corresponding to each column. Referring to Figure 9 , the first storage cell can be connected to a first bit line BL1 and a first complementary bit line BLB1, the second storage cell can be connected to a second bit line BL2 and a second complementary bit line BLB2, the third storage cell can be connected to a third bit line BL3 and a third complementary bit line BLB3, and the fourth storage cell can be connected to a fourth bit line (not shown) and a fourth complementary bit line (not shown).

[0124] Figure 9 The pair of storage cells of FIG. 1 can include 4-bit data in a volatile manner by using the first to fourth storage cells. In addition, the pair of storage cells can store 2-bit data in a non-volatile manner by using a physical connection pattern of the first storage cell and the third storage cell.

[0125] As described with reference to Figure 8 , a word line to which the first left connection transistor TL1 and the first right connection transistor TR1 of the first storage cell are connected is determined to store data in the first pair of storage cells in a non-volatile manner. In addition, a word line to which the third left connection transistor TL3 and the third right connection transistor TR3 of the third storage cell are connected can be determined to store data in the second pair of storage cells in a non-volatile manner. In Figure 9 , the wiring determined to store data in the first pair of storage cells and the second pair of storage cells in a non-volatile manner is represented by a thick solid line.

[0126] In Figure 9 , for example, the first pair of storage cells is connected to the first word line WL1, and the second pair of storage cells is connected to the second word line WL2. In other words, for example, Figure 9 , the pair of storage cells of FIG. 1 is illustrated as those storing a data value "01" in a non-volatile manner.

[0127] As described above, in order to achieve an efficient layout, the left connection transistor and the right connection transistor of adjacent storage cells can share a contact point connected to a word line.

[0128] Therefore, inFigure 9 In the memory cell pair, the word line of the second left-connecting transistor TL2 connected to the second memory cell can be determined based on the word line of the first right-connecting transistor TR1 connected to the first memory cell. Furthermore, the word line of the second right-connecting transistor TR2 connected to the second memory cell can be determined based on the word line of the third left-connecting transistor TR3 connected to the third memory cell. The word line of the fourth left-connecting transistor TL4 connected to the fourth memory cell can be determined based on the word line of the third right-connecting transistor TR3 connected to the third memory cell. In other words, in Figure 9 In a pair of memory cells, the word lines connected to memory cells not used for storing data in a non-volatile manner can be determined based on the word lines connected to adjacent memory cells used for storing data in a non-volatile manner. The fourth right-connecting transistor TR4 is connected to the second word line WL2.

[0129] Data stored in the memory cell pair in a non-volatile manner can be retained, while the word lines connected to the left connecting transistor of the first memory cell and the right connecting transistor of the third memory cell remain unchanged. Therefore, even when the power supply to the semiconductor device 100 is cut off, the data stored in the memory cell pair in a non-volatile manner can be retained.

[0130] Despite Figure 9 In this embodiment, the data stored in the memory cell pair in a non-volatile manner is determined based on the word lines connected to the first and third memory cells. However, those skilled in the art will understand that the technical features of the embodiments of this disclosure are not limited to the above examples. For example, the data stored in the memory cell pair in a non-volatile manner may be determined based on the word lines connected to the second and fourth memory cells.

[0131] Figure 10 Multiple storage units according to embodiments of the present disclosure are shown.

[0132] refer to Figure 10 For example, N memory cells constitute a row of memory cells in the word line direction. In embodiments of this disclosure, Figure 10 Each storage unit can be a reference Figure 2 The described storage unit. In Figure 10 In this configuration, each memory cell in a row of memory cells can be connected to a word line pair including a first word line WL1 and a second word line WL2. Furthermore, each memory cell can be electrically connected to a bit line pair corresponding to each column. Each bit line pair can include a bit line and a complementary bit line. Although in Figure 10 As briefly shown, but those skilled in the art will understand, each memory cell can be connected to word line pairs and bit line pairs via the drain (or source) region and gate region of each connecting transistor.

[0133] refer toFigure 10 The storage cell row can store N-bit data in a volatile manner by using the N storage cells. Also, the storage cell row can store data of less than or equal to N / 2 bits in a non-volatile manner by using the N storage cells. In detail, the storage cell row can store m-bit data in a non-volatile manner by using a physical connection pattern of m storage cells that are not adjacent to each other among the N storage cells, which will be described in detail below with reference to the accompanying drawings.

[0134] In Figure 10 , for example, the first storage cell, the third storage cell, and the (N-1)th storage cell are used to store data in a non-volatile manner.

[0135] As described with reference to Figure 8 and Figure 9 , the left connection transistor and the right connection transistor of the storage cell used to store data in a non-volatile manner can be connected to the same word line selected from among the first word line and the second word line. In Figure 10 , for example, the first storage cell is connected to the second word line WL2, the third storage cell is connected to the first word line WL1, and the (N-1)th storage cell is connected to the first word line WL1. In other words, for example, Figure 10 The storage cell row of

[0136] In this state, as described above, in order to achieve an efficient layout, the left connection transistor and the right connection transistor of the adjacent storage cells in the word line direction share a contact point connected to the word line.

[0137] Therefore, in the storage cell row of Figure 10 , at least one of the word line to which the storage cell used to store data in a non-volatile manner and the adjacent storage cell are connected can be determined based on the word line to which the storage cell used to store data in a non-volatile manner is connected.

[0138] For example, the left node of the second storage cell, which is the adjacent storage cell of the first storage cell, can be connected to the second word line WL2 via the left connection transistor, the second word line WL2 being the same line as the word line to which the first storage cell is connected. In contrast, the right node of the second storage cell can be connected to the first word line WL1 via the right connection transistor, the first word line WL1 being the same word line as the word line to which the third storage cell is connected. In other words, unlike the storage cell used to store data in a non-volatile manner, the left node and the right node of the storage cell not used to store data in a non-volatile manner can be connected to different word lines based on the word line to which each adjacent storage cell is connected.

[0139] Figure 11is a flowchart of a method of reading data stored in a pair of storage cells in a non-volatile manner according to an embodiment of the disclosure. In detail, Figure 11 is a flowchart of a method of reading data stored in a pair of storage cells in a non-volatile manner according to an embodiment of the disclosure. Figure 8 is a flowchart of a method of reading data stored in a pair of storage cells in a non-volatile manner according to an embodiment of the disclosure. Figure 11 The reading method of can be equally applied to an operation of reading data stored in a row of storage cells in a non-volatile manner. Figure 10

[0140] Those skilled in the art will appreciate that the method of reading data stored in a pair of storage cells in a volatile manner and the method of storing data in a volatile manner described with reference to Figure 8 may be the same as the methods described with reference to Figure 5 and 6

[0141] With reference to Figure 11 , in operation S1110, a read voltage is supplied to the first word line and an inhibit voltage is supplied to the second word line. Accordingly, the transistor connected to the first word line is in an on state and the transistor connected to the second word line is in an off state.

[0142] In operation S1120, the voltage level state of the bit line connected to the first storage cell via the first left connection transistor and the voltage level state of the complementary bit line connected to the first storage cell via the first right connection transistor can be detected. As described with reference to Figure 8 , the first left connection transistor and the first right connection transistor of the first storage cell are both connected to the same word line. Accordingly, when the connected word line is the first word line, the first left connection transistor and the first right connection transistor are both in an on state, and when the connected word line is the second word line, the first left connection transistor and the first right connection transistor are both in an off state.

[0143] When the first left connection transistor and the first right connection transistor are both in an on state, the voltage level state of the left node of the first storage cell can appear on the bit line and the voltage level state of the right node can appear on the complementary bit line. As described with reference to Figure 2 , the left node and the right node of the storage cell are connected to the inverter and have opposite voltage level states, and thus the voltage level state of the bit line and the voltage level state of the complementary bit line can also be opposite to each other.

[0144] On the contrary, when the first left connection transistor and the first right connection transistor are both in an off state, the left node and the right node of the first storage cell are not electrically connected to the bit line and the complementary bit line, respectively, and a high voltage level state as a pre-charge voltage can appear on the bit line and the complementary bit line.

[0145] ​​In operation S1130, the value of the nonvolatile data stored in the pair of memory cells can be read based on whether the voltage level of the bit line and the voltage level of the complementary bit line are both greater than or equal to the threshold value.

[0146] In other words, when at least one of the bit line or the complementary bit line is in the low voltage level state, the semiconductor device can detect that the word line to which the first memory cell is connected is the first word line. Accordingly, the semiconductor device can detect that the logic value "0" is stored in the pair of memory cells in a nonvolatile manner.

[0147] In addition, when both the bit line and the complementary bit line are in the high voltage level state, the semiconductor device can detect that the word line to which the first memory cell is connected is the second word line. Accordingly, the semiconductor device can detect that the logic value "1" is stored in the pair of memory cells in a nonvolatile manner.

[0148] According to the method described with reference to Figure 11 In the process of reading the data stored in the pair of memory cells in a nonvolatile manner, the data stored in the pair of memory cells in a volatile manner is not destroyed. Accordingly, the process of temporarily storing the data stored in the pair of memory cells in a volatile manner in the buffer and restoring the stored data can not be necessary. Accordingly, the data stored in a nonvolatile manner can be read at an improved speed compared to the method described with reference to Figure 7

[0149] Figure 12 It is shown that in operation S1130 of Figure 11 the logic expression of the data stored in the pair of memory cells in a nonvolatile manner is detected based on the voltage level state of the bit line and the voltage level state of the complementary bit line.

[0150] With reference to Figure 12 , the semiconductor device can detect the value obtained by ANDing the logic value corresponding to the voltage level state of the bit line and the logic value corresponding to the voltage level state of the complementary bit line as the logic value of the data stored in the pair of memory cells in a nonvolatile manner. In other words, when both the voltage level state of the bit line and the voltage level state of the complementary bit line are in the high voltage level state, the semiconductor device can detect the logic value of the data stored in the pair of memory cells in a nonvolatile manner as "1". In contrast, when at least one of the voltage level state of the bit line or the voltage level state of the complementary bit line is in the low voltage level state, the semiconductor device can detect the logic value of the data stored in the pair of memory cells in a nonvolatile manner as "0".

[0151] In an embodiment of the disclosure, Figure 12 the logic expression can be implemented by an AND operation circuit. The sum operation circuit can be implemented by an analog circuit. For example, Figure 12 ​The summing operation circuit can be connected to a bit line and a complementary bit line in an input / output buffer connected to the memory cell array. In another embodiment of the disclosure, Figure 12 The logical expression can be implemented in a digital manner. For example, Figure 12 The AND gate can be implemented by using an application stored in a computer-readable storage medium.

[0152] Figure 13 is a block diagram of an electronic device including a semiconductor device according to an embodiment of the disclosure.

[0153] Referring to Figure 13 The electronic device 1300 can include a processor 1310 and a semiconductor device 1320.

[0154] The processor 1310 can control overall operations of the electronic device 1300. The processor 1310 can include a central processing unit (CPU) or a microcontroller. Also, in an embodiment of the disclosure, the processor 1310 can be a neural processing unit (NPU). In an embodiment of the disclosure, the processor 1310 can execute an operating system (OS) and an application that performs a task. The OS or the application executed by the processor 1310 can be stored in the semiconductor device 1320.

[0155] Although not shown, the processor 1310 can be connected to the semiconductor device 1320 via a bus. In an embodiment of the disclosure, the bus can include an address bus, a control bus, and / or a data bus.

[0156] The processor 1310 can detect information about a method that has been used or will be used to store data stored or to be stored in the semiconductor device 1320. In an embodiment of the disclosure, the method that has been used or will be used to store data can include a volatile manner and a non-volatile manner.

[0157] The semiconductor device 1320 can operate as a main memory of the electronic device 1300. The main memory can be a memory that directly exchanges data with the processor 1310. The semiconductor device 1320 can store data required for the processor 1310 to execute.

[0158] The semiconductor device 1320 can include a memory controller 1321 and a memory 1322. The memory 1322 can include a logically partitioned non-volatile memory and a volatile memory. In an embodiment of the disclosure, although having a smaller space than the volatile memory, the non-volatile memory can have a similar access speed and a read speed to the volatile memory.

[0159] The memory controller 1321 can receive information about a method that has been used or will be used for storing data from the processor 1310. In response to the received information, the memory controller 1321 can read out data stored in the memory 1322 or store data in the memory 1322.

[0160] Figure 14 is a block diagram of an electronic device according to an embodiment of the disclosure.

[0161] Referring to Figure 14 , the electronic device 1000, for example, a notebook computer or a portable electronic device, can include a semiconductor device 1100, a processor 1200, an interface unit 1301, a display 1400, and a solid state drive (SSD) 1500.

[0162] In an embodiment of the disclosure, the semiconductor device 1100, the processor 1200, and the SSD 1500 can be manufactured or packaged in a single chip. The semiconductor device 1100 and the SSD 1500 can be embedded in an electronic device.

[0163] In an embodiment of the disclosure, the electronic device can be a portable communication device. In this case, a modem and a transceiver performing a function of modulating / demodulating data and transmitting / receiving communication data can be connected to the interface unit 1301.

[0164] Similar to the semiconductor device 1100 of Figure 1 , the semiconductor device 1100 can store data in a non-volatile manner and a volatile manner and read the stored data. In detail, the semiconductor device 1100 can be connected to the processor 1200 and can serve as a main memory of the processor 1200 and store data in a volatile storage area in a volatile manner. Alternatively, the volatile storage area of the semiconductor device 1100 can serve as a cache memory of the electronic device 1000. Further, the semiconductor device 1100 can serve as a read-only memory (ROM) and store data in a non-volatile storage area in a non-volatile manner. As described above, in an embodiment of the disclosure, those skilled in the art will understand that the volatile memory area and the non-volatile memory area are logically divided areas sharing one physical space.

[0165] In the semiconductor device 1100 according to an embodiment of the disclosure, data stored in a volatile or non-volatile manner can be accessed through a random access method, as described with reference to Figures 3 to 8As described above, in the semiconductor device 1100, data stored in a non-volatile or volatile manner can be all stored or read out at low power and at high speed. In an embodiment of the disclosure, OS-related data (OS data), such as a stack in which a write event occurs, a heap, a read / write file, etc., can be stored in a volatile storage area of the semiconductor device 1100. Since the OS data includes a stack having a high frequency of immediate access and a high possibility of many write events, the processor 1200 can store the OS data in a volatile data area of the semiconductor device 1100 in which data can be stored and read out at high speed, thereby performing an efficient operation.

[0166] Codes of an OS and an application program, RO files, and databases can be stored in a non-volatile memory area. Since the codes of the programs and the RO files have a low frequency of data access and generally require read access, the semiconductor device 1100 can perform an efficient operation by reading out the codes of the programs and the RO files stored in the non-volatile memory area.

[0167] Specifically, the semiconductor device 1100 can store boot codes for driving the electronic device 1000 in a non-volatile manner in a non-volatile storage area. Since the semiconductor device 1100 according to an embodiment of the disclosure can read out data stored in a non-volatile manner at low power and at high speed by using an SRAM cell, the driving performance of the electronic device 1000 can be improved. Further, the semiconductor device 1100 can store data about libraries or functions permanently used in the processor 1200 of the electronic device 1000 in a non-volatile manner in a non-volatile storage area. For example, the processor 1200 can read out data stored in the non-volatile memory area and can use a volatile memory area as a cache to use the data for an application operation. Since data stored in the semiconductor device 1100 in a non-volatile manner can not be rewritten but read out at low power and at high speed, it can be appropriate to store permanent values frequently used for an operation of the processor 1200.

[0168] The processor 1200 can control the overall operation of the electronic device 1000 according to a preset program. The processor 1200 according to an embodiment of the disclosure can independently access a volatile storage area and a non-volatile storage area of the semiconductor device 1100. The semiconductor device 1100 can include a memory controller for controlling each storage area such that data stored in the volatile storage area and the non-volatile storage area, respectively, is read out without interference in response to an access of the processor 1200, and a buffer for temporarily storing data.

[0169] In an embodiment of the disclosure, the processor 1200 can be an NPU. The processor 1200 can use a volatile storage area of the semiconductor device 1100 as a cache memory for storing data generated in an artificial neural network operation process. In an electronic device such as a deep learning accelerator including an NPU as a processor, a high complexity non-linear function such as tanh or sigmoid can be used as an activation function of an artificial neural network operation. When a high-order polynomial is used to calculate the function, the operation time can be prolonged too long, and thus a method of storing a result of a previous operation as table data in a memory and loading a necessary value can be used. Since a large amount of table data needs to be quickly loaded to efficiently calculate the activation function, a non-volatile storage area of the semiconductor device 1100 can be suitable for storing table data. Not only table data of the activation function, but also non-variable data such as a library and binary code of a kernel used for artificial neural network calculation can be stored in the non-volatile storage area of the semiconductor device 1100 for NPU operation.

[0170] The processor 1200 according to an embodiment of the disclosure can perform various artificial neural network operation processes. For example, the processor 1200 can perform artificial neural network algorithm operations of various methods, such as a convolutional neural network (CNN), a recurrent neural network (RNN), a long short-term memory network (LSTM), or a gated recurrent unit (GRU).

[0171] For example, when an operation using a CNN algorithm is performed, a result of the currently performed operation can be stored in a volatile storage area of the semiconductor device 1100. However, a basic feature for the algorithm, or a result of an operation in a low-level layer can be pre-generated and stored in a non-volatile storage area of the semiconductor device 1100. The processor 1200 can simplify a logical operation of the CNN algorithm operation by using the basic feature or the operation result of the low-level layer stored in the semiconductor device 1100, thereby efficiently performing the operation. Although the CNN algorithm is used as an example, those skilled in the art will appreciate that the semiconductor device 1100 can be used in the same manner for various artificial neural network algorithm operations.

[0172] A processing operation of the processor 1200 can include an operation of verifying whether the processor 1200 normally operates. The semiconductor device 1100 can store test code for verifying whether the processor 1200 normally operates in a processing operation in a non-volatile storage area in a non-volatile manner. The processor 1200 can verify whether a defect occurs in the process operation by using the test code stored in the semiconductor device 1100.

[0173] The display 1400 can include a touch screen as a device, for example, a liquid crystal with a backlight, a liquid crystal with an LED light source, or an OLED. The display 1400 can be used as an output device to display characters, numbers, or images such as pictures in color.

[0174] The SSD 1500 can include a NOR type or a NAND type flash memory. Although Figure 11 It is shown that the SSD is used as a memory device, and the type of the memory device in the present disclosure is not limited thereto. In the present disclosure, the memory device can include various types of nonvolatile memories. The nonvolatile memory can store data information having various data forms, for example, text, graphics, or software codes.

[0175] In an embodiment of the present disclosure, the nonvolatile memory can be implemented as, for example, an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic RAM (MRAM), a spin transfer torque MRAM, a conductive bridge RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase change RAM (PRAM) called ovonic universal memory (OUM), a resistive RAM (RRAM or ReRAM), a nanotube RRAM, a polymer RAM (PoRAM), a nanofloating gate memory (NFGM), a holographic memory, a molecular electronic memory device, or an insulator resistance change memory.

[0176] In the above-described embodiment of the present disclosure, although the electronic device is mainly described as a mobile communication device, the electronic device can be used as a smart card by adding or subtracting constituent components as necessary, or can be connected to a server to be implemented as a large-capacity operation device.

[0177] In an embodiment of the present disclosure, the electronic device can be connected to an external communication device via a separate interface. The communication device can include a digital versatile disc (DVD) player, a computer, a set-top box (STB), a game console, or a digital video camera.

[0178] In an embodiment of the present disclosure, the electronic device can be further equipped with an application chip set, a camera image processor (CIS), or a mobile DRAM.

[0179] In embodiments of the disclosure, a chip for forming an electronic device can be mounted by using various types of packages. For example, the chip can be single packaged as a package such as a package on package (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic leaded chip carrier (PLCC), a plastic dual-in-line package (PDIP), a die in a wafer form, a die in a wafer form, a chip on board (COB), a ceramic dual-in-line package (CERDIP), a plastic metric quad flat package (MQFP), a thin quad flat package (TQFP), a small outline (SOIC), a shrink small outline package (SSOP), a thin small outline package (TSOP), a thin quad flat package (TQFP), a system in package (SIP), a multi-chip package (MCP), a wafer level package (WFP), or a wafer level process package (WSP).

[0180] Figure 15 A circuit block of an electronic device according to an embodiment of the disclosure is illustrated.

[0181] Reference Figure 15 The electronic device 3000 can be a portable device used as a smart phone. The electronic device 3000 can include a semiconductor device 3100, a first processor 3200, a second processor 3300, a display unit 3400, a user interface 3500, a camera unit 3600, and a modem 3700.

[0182] The semiconductor device 3100 can have m ports connected to m buses, for example, first to third buses B10, B20, and B22 in Figure 12 , and can be connected to the first processor 3200 and the second processor 3300. In detail, a first port of the semiconductor device 3100 can be connected to the first processor 3200 which can be a baseband processor via the first bus B10, and a second port of the semiconductor device 3100 can be connected to the second processor 3300 which can be an application processor via the second bus B20. Further, a third port of the semiconductor device 3100 can be connected to the second processor 3300 via the third bus B22.

[0183] The semiconductor device 3100 can store data in a non-volatile manner and a volatile manner like the semiconductor device 100 of Figure 1 , and can read the stored data.

[0184] In an embodiment of the disclosure, the interface of the first bus B10 can be a volatile memory interface, and the first port can receive first packet data generated from the first processor 3200 and transmit the data to an internal circuit block of the semiconductor device 3100. Also, the first port can provide first data stored in the semiconductor device 3100 in a volatile manner to the first processor 3200. In this case, the first data can be parallel data.

[0185] In an embodiment of the disclosure, the interface of the third bus B22 can also be a volatile memory interface, and the third port can receive third packet data generated from the second processor 3300 and transmit the data to an internal circuit block of the semiconductor device 3100. Also, the third port can provide third data stored in the semiconductor device 3100 in a volatile manner to the second processor 3300.

[0186] In an embodiment of the disclosure, the interface of the second bus B20 can be a non-volatile memory interface, and the second port can provide second data stored in the semiconductor device 3100 in a non-volatile manner to the second processor 3300. In this case, the second data can be serial or parallel data.

[0187] In an embodiment of the disclosure, the interface of the bus can include one of various interface protocols, such as a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnect express (PCIE), a serial attached SCSI (SAS), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), and an integrated drive electronics (IDE).

[0188] In an embodiment of the disclosure, the first and second processors 3200 and 3300 and the semiconductor device 3100 can be manufactured or packaged in a single chip, if necessary. Also, the semiconductor device 3100 can be embedded in an electronic device.

[0189] In an embodiment of the disclosure, when the portable device is a smart phone, a modem 3700 for performing a communication data transceiving and data modulation / demodulation function can be connected to the first processor 3200.

[0190] In order to store large-capacity information, a NOR-type or NAND-type flash memory can be additionally connected to the first processor 3200 or the second processor 3300.

[0191] The display unit 3400 can include a touch screen as a device, for example, a liquid crystal having a backlight, a liquid crystal having an LED light source, or an OLED. The display unit 3400 can be used as an output device to display characters, numbers, or images such as pictures in color.

[0192] Although in the above-described embodiments of the disclosure, the electronic device 3000 is mainly described as a smart phone device, the electronic device 3000 can operate in various forms such as a smart card by adding or omitting constituent components as necessary.

[0193] In embodiments of the disclosure, the electronic device 3000 can be connected to an external communication device through a separate interface. The communication device can include a DVD player, a computer, an STB, a game console, or a digital camera. The camera unit 3600 can include a CIS, and can be connected to the second processor 3300.

[0194] In embodiments of the disclosure, the camera unit 3600 can also be provided with an application chipset or a mobile DRAM.

[0195] Some embodiments of the disclosure can be implemented by an S / W program including instructions stored in a computer readable storage medium.

[0196] For example, a computer, which is a device capable of calling stored instructions from a storage medium and operating in response to the called instructions according to embodiments of the disclosure, can include a device according to embodiments of the disclosure or an external server connected in communication with the device.

[0197] The computer readable storage medium can be provided in the form of a non-transitory storage medium. The term "non-transitory" can mean that the storage medium does not include a signal or a current, but is tangible, and can mean that data is stored in the storage medium, regardless of whether it is semi-permanent storage or temporary storage. For example, the non-transitory storage medium can include not only a non-transitory readable storage medium such as a CD, a DVD, a hard disk, a Blu-ray disk, a USB, an embedded memory, a memory card, a ROM, or a RAM, but also a temporary storage medium such as a register, a cache, or a buffer.

[0198] In addition, the method according to the embodiments of the disclosure can be provided as a computer program product.

[0199] The computer program product can include an S / W program, a computer readable storage medium storing the S / W program, or a product traded between a seller and a buyer.

[0200] For example, the computer program product can include a product in the form of an S / W program that is electronically distributed through a device manufacturer or an electronic market (e.g., Google Play Store or App Store), such as a downloadable application. For electronic distribution, at least a portion of the S / W program can be stored on a storage medium or temporarily generated. In this case, the storage medium can be a storage medium of the manufacturer, a server of the electronic market, or a relay server.

[0201] While the present application has been shown and described with reference to various embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the application as defined by the appended claims and their equivalents.

Claims

1. A semiconductor device, comprising: Memory, storing data in both non-volatile and volatile modes; and A memory controller is configured to control the memory, wherein the memory includes: The word line pair includes the first word line and the second word line. The first line pair is orthogonal to the first and second letter lines, and includes the first line and the first complementary line. A storage cell pair includes a first storage cell and a second storage cell adjacent to the first storage cell in the word line direction, wherein the first storage cell and the second storage cell each store data in a volatile manner. The left node of the first memory cell connected to the first bit line, and the right node of the first memory cell connected to the first complementary bit line, and the left node of the second memory cell are all connected to the first word line selected from the first word line and the second word line, and The value of the data stored in the storage cell pair in a non-volatile manner is determined based on the first word line connecting the left node of the selected first storage cell, the right node of the first storage cell, and the left node of the second storage cell.

2. The semiconductor device according to claim 1, The memory controller is further configured to: Provide read voltage to the first word line. Provide a read disable voltage to the second word line. Detect the voltage level of the first bit line connected to the first memory cell and the voltage level of the first complementary bit line connected to the first memory cell, and The value of the data stored in the memory cell pair in a non-volatile manner is determined based on whether the voltage levels of the first bit line and the first complementary bit line are both greater than or equal to a threshold. The memory further includes: The left-connect transistor connects the left node of the first memory cell to the first bit line; and The right-connect transistor connects the right node of the first memory cell to the first complementary bit line, and The gate regions of the left and right connected transistors are connected together to the selected first word line, and the left and right connected transistors are turned on or off in response to the voltage applied to the selected first word line.

3. The semiconductor device of claim 2, wherein the read voltage corresponds to a power supply voltage, and the read disable voltage corresponds to a ground power supply voltage.

4. The semiconductor device according to claim 2, wherein, The memory controller is further configured to detect the value of data stored in the memory cell pair in a non-volatile manner as 1 when the voltage level of the first bit line and the voltage level of the first complementary bit line are both greater than or equal to the threshold.

5. The semiconductor device according to claim 1, wherein, Each of the first storage unit and the second storage unit includes a static random access memory (SRAM) unit.

6. The semiconductor device of claim 1, wherein each of the first memory cell and the second memory cell includes a latch circuit comprising four transistors.

7. The semiconductor device according to claim 1, in, The right node of the first memory cell is electrically connected to the first word line through the gate region of the right connection transistor of the first memory cell, and The left node of the first memory cell is electrically connected to the first word line through the gate region of the left connecting transistor of the first memory cell.

8. The semiconductor device of claim 7, wherein the right node of the first memory cell and the left node of the second memory cell are electrically connected to each other via a right connection transistor of the first memory cell and a left connection transistor of the second memory cell.

9. The semiconductor device according to claim 8, wherein, The right node of the first memory cell and the left node of the second memory cell are electrically connected to each other through a contact via formed between the gate region of the right connecting transistor of the first memory cell and the gate region of the left connecting transistor of the second memory cell.

10. The semiconductor device according to claim 1, further comprising: A summation circuit is connected to the first bit line and the first complementary bit line, and is configured to perform a summation operation on logic values ​​corresponding to the voltage levels on the first bit line and the first complementary bit line.

11. A method for reading data stored in a memory in a non-volatile manner, performed by a semiconductor device, the method comprising: Regarding the word line pair including the first word line and the second word line, a read voltage is provided to the first word line, and a read inhibit voltage is provided to the second word line; Detect the voltage level of the first bit line connected to the first memory cell included in the memory and the voltage level of the first complementary bit line connected to the first memory cell; Based on whether the voltage level of the first bit line and the voltage level of the first complementary bit line are both greater than or equal to the threshold, the value of the data stored in the first memory cell in a non-volatile manner is read out. and When the voltage levels of the first bit line and the first complementary bit line are both greater than or equal to the threshold, the value of the data stored in the memory cell pair in a non-volatile manner will be detected as 1. The left-connecting transistor connects the left node of the first memory cell to the first bit line, and the right-connecting transistor connects the right node of the first memory cell to the first complementary bit line. Wherein, the gate region of the left connecting transistor and the gate region of the right connecting transistor are together connected to a word line selected from the first word line and the second word line, and The left and right connection transistors are both turned on or off in response to a voltage applied to a selected word line, and the left and right connection transistors are connected together to the selected word line.

12. The method of claim 11, wherein the first bit line and the first complementary bit line are orthogonal to the first word line and the second word line.

13. The method of claim 11, further comprising: When the voltage level of the first bit line and the voltage level of the first complementary bit line are both less than the threshold, the value of the data stored in the memory cell pair in a non-volatile manner is detected as 0.

14. The method of claim 11, wherein detecting the value of data stored in the storage cell pair in a non-volatile manner as 1 includes performing an AND operation on the logic value of the first bit line and the logic value of the voltage level of the first complementary bit line.

Images