Interconnect structure with fully aligned vias

Abstract

An interconnect structure (100) includes an interlayer dielectric (ILD) (112) having a cavity (122) extending therethrough in a first direction. A first conductive strip (110) is formed on a substrate (102) and within the cavity (122). The first conductive strip (110) extends in the first direction and across an upper surface of the substrate (102). A second conductive strip (118) extends on an upper surface of the ILD and in a second direction opposite the first direction. A fully aligned via (FAV) (124) extends between the first and second conductive strips (110, 118) such that all sides of the FAV (124) are coplanar with opposite sides of the first conductive strip (110) and opposite sides of the second conductive strip (118), thereby providing a FAV that is fully aligned with the first conductive strip (110) and the second conductive strip (118).

Description

Technical Field

[0001] This invention generally relates to a manufacturing method and the resulting semiconductor-based integrated circuit (IC). More specifically, this invention relates to a method for manufacturing an IC with fully aligned through-holes and the resulting interconnect structure. Background Technology

[0002] ICs typically use metal interconnect structures (or "wires") to connect semiconductor devices, such as transistors, on the IC. These interconnect structures are typically formed using an add-in damascene process or a dual damascene process, in which a dielectric layer is patterned to include openings. A conductive metal, such as copper (Cu), is then deposited within the openings, and any conductive metal located outside the openings is subsequently removed by a planarization process.

[0003] For the sake of brevity, conventional techniques associated with the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Furthermore, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process with additional steps or functions not described in detail herein. In particular, the various steps involved in manufacturing semiconductor devices and semiconductor-based ICs are well-known; therefore, for the sake of brevity, many conventional steps will be mentioned only briefly herein, or omitted entirely, without providing well-known process details.

[0004] Turning now to an overview of techniques more specifically related to aspects of the present invention, interconnect structures produced by conventional dual-damascene fabrication processes are experiencing degraded performance characteristics due to the ongoing demand for smaller device profiles in modern complementary metal-oxide-semiconductor (CMOS) technology. For example, with linewidth scaling, the capability of self-aligned vias decreases. For instance, one or more sides of a self-aligned via may become misaligned and overlap with the upper and / or lower surfaces of a metal line, resulting in a reduced contact area between the via and the metal line or strip. This misalignment leads to an increase in resistivity between the metal line and the via, which ultimately degrades the performance of the interconnect structure. Therefore, there remains a need for a method of fabricating interconnect structures that can meet the requirements of reduced structural profiles while also achieving reduced line-to-via resistance.

[0005] Therefore, there is a need in this field to address the aforementioned problems. Summary of the Invention

[0006] From a first aspect, the present invention provides a method for manufacturing an interconnect structure, the method comprising: forming a first conductive strip extending along a first direction on an upper surface of a substrate; depositing an interlayer dielectric (ILD) material on the substrate to cover the first conductive strip, and etching the ILD material to expose the upper surface of the first conductive strip; forming a second conductive strip on the upper surface of the ILD material such that the second conductive strip extends along a second direction opposite to the first direction and crosses the first conductive strip; and recessing an exposed portion of the first conductive strip located on the opposite side of the second conductive strip while retaining a covered portion of the first conductive strip covered by the second conductive strip to form a fully aligned via (FAV) between the first conductive strip and the second conductive strip.

[0007] From another perspective, the present invention provides an interconnect structure comprising: an interlayer dielectric (ILD) on a substrate having a cavity extending through the ILD in a first direction; a first conductive strip formed on the substrate and within the cavity, the first conductive strip extending in the first direction and across an upper surface of the substrate; a second conductive strip on the upper surface of the ILD, the second conductive strip extending in a second direction opposite to the first direction; and a fully aligned via (FAV) extending between the first conductive strip and the second conductive strip, wherein all sides of the FAV are coplanar with opposite sides of the first conductive strip and the second conductive strip, such that the FAV is fully aligned with the first conductive strip and the second conductive strip.

[0008] In another aspect, the present invention provides a method for forming an interconnect structure, the method comprising: forming a plurality of first conductive strips extending along a first direction on an upper surface of a substrate; depositing an interlayer dielectric material on the substrate to cover the first conductive strips, and etching an ILD to expose the upper surface of the first conductive strips; forming a plurality of second conductive strips on the upper surface of the ILD such that the second conductive strips extend along a second direction opposite to the first direction and cross the first conductive strips; and recessing the exposed portions of the first conductive strips located on opposite sides of each of the second conductive strips while retaining the covered portions of the first conductive strips covered by the second conductive strips to form a plurality of perfectly aligned vias (FAVs) between the first conductive strips and the second conductive strips.

[0009] From another perspective, the present invention provides an interconnect structure comprising: an interlayer dielectric (ILD) on a substrate having a plurality of cavities extending therethrough along a first direction; a plurality of first conductive strips, each first conductive strip formed on the substrate and within a corresponding cavity of the plurality of cavities, the plurality of first conductive strips extending along the first direction and across an upper surface of the substrate; a plurality of second conductive strips on the upper surface of the ILD, the second conductive strips extending along a second direction opposite to the first direction; and a plurality of fully aligned vias (FAVs), each FAV extending between a corresponding first conductive strip and a corresponding second conductive strip, wherein all sides of a given FAV of the plurality of FAVs are coplanar with the opposite sides of the corresponding first conductive strip and the corresponding second conductive strip, such that each FAV of the plurality of FAVs is fully aligned with the first conductive strip and the second conductive strip.

[0010] From another perspective, the present invention provides an interconnect structure comprising: an interlayer dielectric (ILD) on a substrate having a plurality of cavities extending therethrough along a first direction; a plurality of first conductive strips located on the substrate, each first conductive strip being located within a corresponding cavity of the plurality of cavities and extending across an upper surface of the substrate along the first direction; a plurality of second conductive strips on an upper surface of the ILD and extending along a second direction opposite to the first direction; and a plurality of fully aligned vias (FAVs), each FAV extending between a corresponding first conductive strip and a corresponding second conductive strip, wherein the first conductive strip layer includes at least one recessed conductive strip having a stepped portion formed in the upper surface and adjacent to a given FAV contacting the upper surface of the at least one recessed conductive strip.

[0011] According to a non-limiting embodiment of the invention, the interconnect structure includes a sandwich dielectric (ILD) having a cavity extending therethrough along a first direction. A first conductive strip is formed on a substrate and within the cavity. The first conductive strip extends along the first direction and across the upper surface of the substrate. A second conductive strip is on the upper surface of the ILD and extends along a second direction opposite to the first direction. A fully aligned via (FAV) extends between the first and second conductive strips such that all sides of the FAV are coplanar with opposite sides of the first and second conductive strips, thereby providing an FAV fully aligned with the first and second conductive strips.

[0012] According to another non-limiting embodiment of the present invention, a method of manufacturing an interconnect structure includes: forming a first conductive strip extending along a first direction on an upper surface of a substrate; and depositing an interlayer dielectric (ILD) material on the substrate to cover the first conductive strip. The method further includes etching the ILD material to expose the upper surface of the first conductive strip, and forming a second conductive strip on the upper surface of the ILD material such that the second conductive strip extends along a second direction opposite to the first direction and crosses the first conductive strip. The method further includes recessing an exposed portion of the first conductive strip located on the opposite side of the second conductive strip while retaining a covered portion of the first conductive strip covered by the second conductive strip to form a fully aligned via (FAV) between the first and second conductive strips.

[0013] According to another non-limiting embodiment of the present invention, a method of forming an interconnect structure includes: forming a plurality of first conductive strips extending along a first direction on an upper surface of a substrate; and depositing an interlayer dielectric material on the substrate to cover the first conductive strips. The method further includes: etching the ILD to expose the upper surface of the first conductive strips; and forming a plurality of second conductive strips on the upper surface of the ILD such that the second conductive strips extend along a second direction opposite to the first direction and pass through the first conductive strips. The method further includes: recessing exposed portions of the first conductive strips on opposite sides of each of the second conductive strips while retaining covered portions of the first conductive strips covered by the second conductive strips to form a plurality of perfectly aligned vias (FAVs) between the first and second conductive strips.

[0014] According to another non-limiting embodiment of the invention, the interconnect structure includes an interlayer dielectric (ILD) on a substrate. The ILD has a plurality of cavities extending through the substrate along a first direction. The interconnect structure also includes a plurality of first conductive strips and a plurality of second conductive strips. Each first conductive strip is formed on the substrate and within a corresponding cavity of the plurality of cavities. The first conductive strip extends along the first direction and across the upper surface of the substrate. The second conductive strip is formed on the upper surface of the ILD and extends along a second direction opposite to the first direction. The interconnect structure also includes a plurality of fully aligned vias (FAVs). Each FAV extends between a corresponding first conductive strip and a corresponding second conductive strip. All sides of a given FAV are coplanar with the opposite sides of the corresponding first conductive strip and the opposite sides of the corresponding second conductive strip, such that each of the plurality of FAVs is fully aligned with the first and second conductive strips.

[0015] According to another non-limiting embodiment of the invention, the interconnect structure includes an interlayer dielectric (ILD) on a substrate. The ILD has a plurality of cavities extending therethrough along a first direction. A plurality of first conductive strips are formed on the substrate. Each first conductive strip is located within a corresponding cavity of the plurality of cavities and extends across an upper surface of the substrate along the first direction. A plurality of second conductive strips are formed on the upper surface of the ILD, the plurality of second conductive strips extending along a second direction opposite to the first direction. A plurality of fully aligned vias (FAVs) extend between corresponding first conductive strips and corresponding second conductive strips. The first conductive strip includes at least one recessed conductive strip having a stepped portion formed in the upper surface and adjacent to a given FAV contacting the upper surface of the at least one recessed conductive strip.

[0016] Additional technical features and advantages are achieved through the technology of this invention. Embodiments and aspects of the invention are described in detail herein and are considered part of the claimed subject matter. For a better understanding, refer to the detailed description and accompanying drawings. Attached Figure Description

[0017] The details of the proprietary rights described herein are specifically pointed out and explicitly claimed in the claims at the end of the specification. The foregoing and other features and advantages of embodiments of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1-9 A process flow for forming an interconnect structure according to an embodiment of the present invention is shown, wherein:

[0019] Figure 1 An intermediate interconnect structure following an initial set of manufacturing operations is shown according to a non-limiting embodiment of the invention;

[0020] Figure 2 An interconnect structure following the patterning of the first hard mask layer is shown according to a non-limiting embodiment of the invention;

[0021] Figure 3 An interconnect structure following the transfer of a pattern into a lower metal layer to form a lower metal strip, according to a non-limiting embodiment of the invention, is shown.

[0022] Figure 4 An interconnect structure following the deposition of an interlayer dielectric surrounding a lower metal strip is shown according to a non-limiting embodiment of the invention;

[0023] Figure 5 An interconnect structure is shown after a metal layer has been deposited on the upper surface of an interlayer dielectric according to a non-limiting embodiment of the invention;

[0024] Figure 6An interconnect structure following patterning of a second hard mask layer formed on the upper surface of an upper metal layer, according to a non-limiting embodiment of the invention, is shown.

[0025] Figure 7 An interconnect structure following the transfer of a pattern into an upper metal layer to form an upper metal strip, according to a non-limiting embodiment of the invention, is shown.

[0026] Figure 8 An interconnect structure is shown according to a non-limiting embodiment of the invention, after the exposed portion of the lower metal strip is recessed beneath the interlayer dielectric;

[0027] Figure 9 An interconnect structure with fully aligned through-holes between the lower and upper metal strips is shown according to a non-limiting embodiment of the invention.

[0028] Figure 10-21 A process flow for forming an interconnect structure according to an embodiment of the present invention is shown, wherein:

[0029] Figure 10 An intermediate interconnect structure following an initial set of manufacturing operations is shown according to a non-limiting embodiment of the invention;

[0030] Figure 11 An interconnect structure is shown according to a non-limiting embodiment of the invention after patterning a first hard mask layer and transferring the pattern to an underlying metal layer to form a plurality of underlying metal strips;

[0031] Figure 12 The interconnect structure is shown after an etching process is performed to etch a portion of the metal strip;

[0032] Figure 13 The interconnect structure after removing the remainder of the second hard mask layer is shown according to a non-limiting embodiment of the invention;

[0033] Figure 14 An interconnect structure following the deposition of an interlayer dielectric surrounding a lower metal strip is shown according to a non-limiting embodiment of the invention;

[0034] Figure 15 An interconnect structure following the deposition of an upper metal layer on the upper surface of an interlayer dielectric is shown according to a non-limiting embodiment of the invention;

[0035] Figure 16 An interconnect structure following a third hard mask layer patterned and deposited on the upper surface of an upper metal layer, according to a non-limiting embodiment of the invention, is shown.

[0036] Figure 17An interconnect structure following the transfer of a pattern into an upper metal layer to form a plurality of upper metal strips, according to a non-limiting embodiment of the invention, is shown;

[0037] Figure 18 An interconnect structure is shown according to a non-limiting embodiment of the invention, after the exposed portion of the lower metal strip is recessed beneath the interlayer dielectric;

[0038] Figure 19 An interconnect structure having a plurality of fully aligned through holes between a lower metal strip and an upper metal strip is shown according to a non-limiting embodiment of the invention;

[0039] Figure 20 An interconnect structure having a plurality of perfectly aligned through-holes between a lower metal strip and an upper metal strip, according to another non-limiting embodiment of the invention, is shown; and

[0040] Figure 21 An interconnect structure having a plurality of fully aligned through holes between a lower metal strip and an upper metal strip is shown according to another non-limiting embodiment of the invention.

[0041] The figures depicted herein are illustrative. Many variations of the figures or operations described herein may be made without departing from the scope of the invention. For example, actions may be performed in different orders, or actions may be added, deleted, or modified. Furthermore, the term "coupling" and its variations describe a communication path between two elements and do not imply a direct connection between the elements without intervening elements / connections. All such variations are considered part of the specification.

[0042] In the following detailed description of the accompanying drawings and the described embodiments, the various elements shown in the drawings are provided with two or three numerical reference numerals. With a few exceptions, the leftmost digit of each reference numeral corresponds to the figure in which its element is first shown. Detailed Implementation

[0043] Turning now to an overview of various aspects of the invention, one or more embodiments of the invention address the aforementioned disadvantages of the prior art by performing a novel subtractive patterning process that results in fully aligned vias between one or more lower metal strips and one or more upper metal strips. These aspects of the invention address the disadvantages of the prior art by improving via alignment to increase the contact area between the vias and the metal strips, thereby reducing the overall interconnect resistance. In this way, interconnect structures that meet reduced structural profile requirements (e.g., nodes below 7 nm) can be fabricated while also providing reduced line-to-via resistance.

[0044] Now we turn to a more detailed description of various aspects of the invention. Figure 1-9The process flow for forming interconnect structures according to various embodiments of the present invention is shown. Figure 1 An intermediate interconnect structure 100 according to a non-limiting embodiment of the present invention is shown. In this specification and claims, an "intermediate" interconnect structure is defined as an interconnect structure in the manufacturing stage prior to the final stage. The interconnect structure 100 includes a substrate layer 102, a first (e.g., lower) conductive layer 104 (e.g., a metal layer), and a first hard mask layer 106. The interconnect structure 100 is shown extending along a first axis (e.g., the X-axis) to define a length, along a second axis perpendicular to the X-axis (e.g., the Y-axis) to define a height, and along a third axis (e.g., the Z-axis) to define a width.

[0045] Substrate 102 may include a semiconductor material selected from, but not limited to, silicon, germanium, silicon-germanium alloys, silicon-carbon alloys, silicon-germanium-carbon alloys, gallium arsenide, indium arsenide, indium phosphide, 11I-V compound semiconductor materials, 11-VI compound semiconductor materials, organic semiconductor materials, and other compound semiconductor materials. Typically, the semiconductor material includes silicon. Substrate 102 may include a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. At least one semiconductor device may be a field-effect transistor, a bipolar transistor, a diode, a resistor, a capacitor, an inductor, an electrically programmable fuse, or any combination thereof. Optionally, substrate 102 may also include at least one dielectric material layer (not shown separately) and metal interconnect structures (not shown separately) embedded therein, such as metal lines and / or metal vias.

[0046] Metal layer 104 may comprise various metallic materials, such as copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), rhodium (Rh), platinum (Pt), molybdenum (Mo), or any combination thereof. Metal layer 104 may be deposited using various deposition processes, including but not limited to chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, chemical solution deposition, or bottom-up electroplating (e.g., bottom-to-top electroplating processes). The height of metal layer 104 may be selected based on the desired application of interconnect structure 100 and helps determine the lower metal strip (…). Figure 1 The height (not shown in the image) is as described in more detail below.

[0047] The hard mask layer 106 may include different hard mask materials, including but not limited to SiN, SiO2, SiON, SiCN, TiN, TaN, Ti, Ta, or any combination thereof. For example, a PECVD process may be performed to deposit the hard mask layer 106.

[0048] Turning Figure 2This illustrates the interconnect structure 100 following the patterning of the first hard mask layer 106. The hard mask layer 106 can be patterned using known photolithography and patterning techniques. Patterning the hard mask layer 106 results in the formation of one or more hard mask elements 108 on the upper surface of the metal layer 104. Patterning the hard mask elements 108 helps to determine the subsequently formed metal strip (…). Figure 2 The dimensions (not shown in the image) are as described in more detail below.

[0049] Reference Figure 3 The diagram illustrates the interconnect structure 100 after the hard mask pattern has been transferred into the metal layer 104. Accordingly, a first metal strip 110, such as a lower metal strip 110 (also referred to as a metal line), is formed on the upper surface of the substrate layer 102. For example, a directional reactive ion etching (RIE) process can be performed to transfer the hard mask pattern into the metal layer to form the metal strip 110. In one or more non-limiting embodiments of the invention, the metal strip 110 extends a greater distance along the Z-axis than along the X-axis and has a total height (H1).

[0050] Reference Figure 4 The diagram illustrates the deposition of an interlayer dielectric (ILD) 112 on the upper surface of a substrate 102 to form an interconnect structure 100 surrounding a metal strip 110. The ILD 112 can comprise various low-dielectric materials and can be deposited using techniques such as chemical vapor deposition (CVD) or spin-coating. Low-dielectric (low-k) materials typically have a dielectric constant (k) of less than approximately 3.9. In one or more non-limiting embodiments of the invention, the low-k material comprises silicon dioxide (SiO2). Figure 4 As further shown, the ILD 112 can be recessed by performing a chemical mechanical planarization (CMP) process, for example, until the upper surface of the metal strip 110 is exposed.

[0051] Turning Figure 5 This illustrates an interconnect structure 100 after a second (e.g., upper) metal layer 114 is deposited on the upper surface of the interlayer dielectric 112. The upper metal layer 114 may comprise various metallic materials, such as copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), rhodium (Rh), platinum (Pt), or any combination thereof. The upper metal layer 114 can be deposited using various deposition processes, including but not limited to chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, chemical solution deposition, or bottom-up electroplating (e.g., bottom-up electroplating processes). The height of the upper metal layer 114 can be selected based on the desired application of the interconnect structure 100 and helps determine the upper metal strip (…). Figure 5 The height (not shown in the image) is as described in more detail below.

[0052] Turn now Figure 6 This illustrates a second hard mask layer formed on the upper surface of the patterned upper metal layer 114. Figure 6 (Not shown in the image) to form an interconnect structure 100 after forming one or more second hard mask elements 116. Alternatively, the formation of the first hard mask element 108 (see image) can also be performed. Figure 2 Similar photolithography and patterning techniques are used to form the second hard mask element 116. The second hard mask element 116 helps to determine the subsequently formed upper metal strip ( Figure 6 (Dimensions not shown). In one or more embodiments of the invention, the second hard mask element 116 extends in the opposite direction (e.g., vertical direction) to the lower metal strip 110.

[0053] Reference Figure 7 The diagram illustrates the interconnect structure 100 after the hard mask pattern has been transferred into the upper metal layer 114. Accordingly, a second conductive strip (e.g., a metal strip) 118 (e.g., the upper metal strip 118) is formed on the upper surface of the ILD 112. For example, a reactive ion etching (RIE) process can be performed to transfer the hard mask pattern into the metal layer to form the upper metal strip 118. The upper metal strip 118 has a total height (H2). However, the patterning of the second hard mask element 108 results in the upper metal strip 118 extending a greater distance along the X-axis than along the Z-axis. Consequently, the upper metal strip 118 extends fully across the upper surface of the metal strip 110, thereby establishing a physical contact between the two metal strips 110 and 118 at the contact region 120.

[0054] Turn now Figure 8 The diagram illustrates an interconnect structure 100 after recessing the exposed portion of the lower metal strip 110 below the ILD 112 to form a cavity 122 on the opposite side of the upper metal strip 118. In one or more non-limiting embodiments of the invention, the cavity can be formed by performing a selective orientation RIE process on the ILD material 112. In this way, the lower metal strip 110 can be recessed without substantially eroding or etching the ILD 112. The process of subsequently recessing the lower metal strip 110 relative to the upper metal strip 118 is also referred to herein as a “subtractive patterning process.” In one or more embodiments of the invention, the recessed lower metal strip 110 has a reduced height (H3) that is less than the height (H2) of the upper metal strip 118. Furthermore, since the exposed portion of the lower metal strip 110 is recessed relative to the upper metal strip 118 and the ILD 112, the length of the resulting cavity 122 (i.e., extending along the Z-axis) matches the length of the recessed portion of the lower metal strip 110 (i.e., extending along the Z-axis).

[0055] The non-recessed portion of the lower metal strip 110, protected by the overlying upper metal strip 118, defines a fully aligned through-hole (FAV) 124 between the remaining portion of the lower metal strip 110 and the upper metal strip 118. Figure 9 ILD 112 is shown transparently to illustrate FAV 124 in more detail. More specifically, FAV 124 extends from the lower metal strip 110 and contacts the upper metal strip 118 at contact area 120. Because the lower metal strip 110 is subsequently recessed relative to the upper metal strip 118, all sides 126 of FAV 124 are perfectly aligned with the upper surface of the lower metal strip 110 and the lower surface of the upper metal strip 118, without any overlap. In other words, the recess of the lower metal strip 110 relative to the upper metal strip 118 makes all sides 126 of FAV 124 flush (i.e., coplanar) with the sides 128 of the lower metal strip 110 and the sides 130 of the upper metal strip 118. Therefore, a more precise strip-to-via contact area can be achieved.

[0056] Turn now Figure 10-21 This illustrates another process flow for forming an interconnect structure according to an embodiment of the present invention. Figure 10 An intermediate interconnect structure 200 according to a non-limiting embodiment of the invention is illustrated. In this specification and claims, an "intermediate" interconnect structure is defined as an interconnect structure in the manufacturing stage prior to the final stage. The interconnect structure 200 includes a substrate layer 202, a first (e.g., lower) metal layer 204, and a first hard mask layer 206. The interconnect structure 200 is shown extending along a first axis (e.g., the X-axis) to define a length, along a second axis perpendicular to the X-axis (e.g., the Y-axis) to define a height, and along a third axis (e.g., the Z-axis) to define a width.

[0057] Metal layer 204 may comprise various metallic materials, such as copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), rhodium (Rh), platinum (Pt), molybdenum (Mo), or any combination thereof. Metal layer 204 may be deposited using various deposition processes, including but not limited to chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, chemical solution deposition, or bottom-up electroplating (e.g., bottom-up electroplating processes). The height of metal layer 204 may be selected based on the desired application of interconnect structure 200 and helps determine the height of the lower metal strip, as described in more detail below.

[0058] The hard mask layer 206 may include different hard mask materials, including but not limited to SiN, SiO2, SiON, SiCN, TiN, TaN, Ti, Ta, or any combination thereof. For example, a PECVD process may be performed to deposit the hard mask layer 106.

[0059] Turning Figure 11 The diagram illustrates an interconnect structure 200 following the patterning of a first hard mask layer 206 and the transfer of the pattern to a metal layer 204 to form a plurality of first conductive strips (e.g., metal strips) 208a, 208b, 208c (e.g., lower metal strips). The hard mask layer 206 can be patterned using known photolithography and patterning techniques, and a directional RIE process can be performed to transfer the pattern to the metal layer 204. In one or more non-limiting embodiments of the invention, the lower metal strips 208a, 208b, 208c extend a greater distance along the Z-axis than along the X-axis and have an initial total height (H1).

[0060] Reference Figure 12 The hard mask layer 206 is patterned, and each pattern is transferred to the corresponding metal strips 208a, 208b, and 208c. Various known photolithography and patterning techniques can be used to pattern the hard mask layer 206. Accordingly, the uncovered portions of the metal strips 208a, 208b, and 208c are recessed, while the portions of the metal strips 208a, 208b, and 208c covered by the remaining hard mask layer 206 are retained.

[0061] Reference Figure 13 The figure shows the interconnect structure 200 after the remaining hard mask layer 206 has been removed. As shown, the retained portions 218a, 218b, 218c (i.e., non-recessed portions) of the lower metal strips 208a, 208b, 208c previously covered by the hard mask layer 206 are retained according to their initial height (H1), while the remaining portions 220a, 220b, 220c (i.e., recessed portions) of the lower metal strips 208a, 208b, 208c are recessed below the non-recessed portions 218a, 218b, 218c, thereby defining a second height (H2) less than the initial height (H1). Therefore, the non-recessed portions 218a, 218b, 218c can be used as vias for fully aligned ( Figure 13 (not shown) connected to the upper metal strip ( Figure 13 The contact area (not shown in the diagram) is formed at a later stage of the process flow described in more detail below.

[0062] Turn now Figure 14 The diagram illustrates an interconnect structure 200 after depositing an ILD 222 around lower metal strips 208a, 208b, and 208c. The ILD 222 can comprise various low-dielectric materials and can be deposited using techniques such as chemical vapor deposition (CVD) or spin-coating. The low-dielectric (low-k) materials described herein typically have a dielectric constant (k) of less than approximately 3.9. In one or more non-limiting embodiments of the invention, the low-k material comprises silicon dioxide (SiO2). Figure 14As further illustrated, the ILD 222 can be recessed by performing a chemical mechanical planarization (CMP) process, for example, until the upper surfaces of the non-recessed metal strip portions 218a, 218b, 218c are exposed.

[0063] refer to Figure 15 The diagram illustrates an interconnect structure 200 after a second metal layer 224 (e.g., an upper metal layer) has been deposited on the upper surface of the ILD 222. The upper metal layer 224 may comprise various metallic materials, such as copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), rhodium (Rh), platinum (Pt), molybdenum (Mo), or any combination thereof. The upper metal layer 224 can be deposited using various deposition processes, including but not limited to chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, chemical solution deposition, or bottom-up electroplating (e.g., bottom-up electroplating processes). The height of the upper metal layer 224 can be selected based on the desired application of the interconnect structure 200 and helps determine the upper metal strip to be formed at a later stage of the process flow (in...). Figure 15 The height (not shown in the image) is as described in more detail below.

[0064] Turn now Figure 16 This illustrates a third hard mask layer formed on the upper surface of the patterned upper metal layer 224. Figure 16 (Not shown in the image) to form an interconnect structure 200 after forming multiple hard mask elements 226a, 226b. Patterning of the first hard mask layer 206 (see image) can also be performed. Figure 11 Similar photolithography and patterning techniques are used to pattern the third hard mask layer and form hard mask elements 226a and 226b. Hard mask elements 226a and 226b help determine the upper metal strip to be formed in a later stage of the processing flow. Figure 16 (Dimensions not shown). In one or more non-limiting embodiments of the invention, the hard mask elements 226a, 226b extend in the opposite direction (e.g., vertical direction) to the lower metal strips 208a, 208b, 208c.

[0065] Reference Figure 17 This illustrates the interconnect structure 200 after the hard mask pattern is transferred into the upper metal layer 224 (see...). Figure 16Therefore, a plurality of second-layer metal strips 228a, 228b (e.g., upper metal strips) are formed on the upper surface of ILD 222. For example, a reactive ion etching (RIE) process can be performed to transfer the hard mask pattern into the metal layer to form the upper metal strips 228a, 228b. Similar to the lower metal strips 208a, 208b, 208c, the upper metal strips 228a, 228b have a total height (H3). However, the patterning of the hard mask elements 226a, 226b results in the upper metal strips 228a, 228b extending a greater distance along the X-axis than along the Z-axis. Therefore, the upper metal strips 228a, 228b extend completely across the upper surface of the lower metal strips 208a, 208b, 208c, thereby establishing physical contact between the upper metal strips 228a, 228b and contact areas 230 of one or more corresponding lower metal strips 208a, 208b, 208c.

[0066] Turn now Figure 18 The diagram illustrates an interconnect structure 200 after the exposed portions of the lower metal strips 208b, 208c are recessed below the ILD 222 to form corresponding cavities 232a, 232b on opposite sides of the upper metal strips 228a, 228b. In one or more non-limiting embodiments of the invention, the cavities 232a, 232b can be formed by performing a selectively oriented RIE process on the ILD 222. In this way, the exposed lower metal strips 208b, 208c can be recessed without substantially etching or corroding the ILD 222. As described above, the process of subsequently recessing the metal lines and / or vias is referred to herein as a "subtractive patterning process" and differs from conventional damascene processes that etch the dielectric during the formation of metal lines and / or vias. The formed recessed lower metal strips 208b, 208c have a second height (H2). In one or more non-limiting embodiments of the invention, the exposed portions 218a, 218b, 218c may be recessed to have a recess height (H2) matching the portion of the lower metal strips 208a, 208b, 208c covered by the ILD 222. Furthermore, although the recessed lower metal strips 208b, 208c are shown to have the same height (H2) as the non-recessed metal strip 208a, the invention is not limited thereto. In other embodiments of the invention, the lower metal strips 208a, 208b, and 208c may have different heights, as described in more detail below.

[0067] Reference Figure 19 The non-recessed portions of the lower metal strips 208b and 208c, covered by the upper metal strips 228a and 228b, define fully aligned through-holes (FAVs) 234a, 234b and 234c between the remaining portions of the lower metal strips 208a, 208b and 208c and the upper metal strips 228a and 228b. Figure 19ILD 222 is described transparently to show FAVs 234a, 234b, and 234c in more detail. More specifically, FAVs 234a, 234b, and 234c extend from the corresponding lower metal strips 208a, 208b, and 208c and contact the upper metal strips 228a and 228b at the corresponding contact areas 130. Since the lower metal strips 208a, 208b, and 208c are subsequently recessed relative to the upper metal strips 228a and 228b, all sides 236 of FAVs 234a, 234b, and 234c are perfectly aligned with the upper surfaces of the lower metal strips 208a, 208b, and 208c and the lower surfaces of the upper metal strips 228a and 228b, without any overlap. In other words, the lower metal strips 208a, 208b, and 208c are recessed relative to the upper metal strips 228a and 228b, making all sides 126 of FAV 234a, 234b, and 234c flush with (i.e. coplanar) the sides 238 of the lower metal strips 208a, 208b, and 208c and the sides 240 of the upper metal strips 228a and 228b. Therefore, a more precise strip-to-via contact area can be achieved.

[0068] In one or more non-limiting embodiments of the invention, the depths of cavities 232a, 232b can be varied. Variations in cavity depth allow for different heights to be formed between one or more metal strips (e.g., lower metal strips 208a, 208b, 208c). (Steering) Figure 20 For example, cavities 232a and 232b have a higher... Figure 18 The cavity shown is at a greater depth. This is because portions of the lower metal strips 208a, 208b, and 208c, 218a, 218b, and 218c, are exposed while the remainder is covered by ILD 222 (see [link]). Figure 14 Therefore, the first recessed portions 242 of the lower metal strips 208a, 208b, and 208c maintain their initial recessed height (H2), while the second recessed portions 244 of the lower metal strips 208a, 208b, and 208c have a reduced height (H4) relative to the initial recessed height (H2). Thus, a stepped portion 246 is formed at the boundary between the first recess 242 and the second recess 244.

[0069] Figure 21 Another non-limiting embodiment of the invention is shown, wherein cavities 232a and 232b have the same... Figure 20The cavity shown is shallower than the previous one. The first recessed portions 242 of the lower metal strips 208a, 208b, and 208c maintain their initial recessed height (H2) because they are covered by the ILD 222. However, the second recessed portion 244 has a higher height (H5) relative to the initial recessed height (H2) of the first recessed portion 242. The height difference still forms a stepped portion 246 at the boundary between the first recessed portion 242 and the second recessed portion 244.

[0070] As described herein, various non-limiting embodiments of the invention provide a novel subtractive patterning process that produces fully aligned vias between one or more lower metal strips and one or more upper metal strips. The resulting interconnect structure has an increased contact area between the fully aligned vias and the metal strips, thereby reducing the overall interconnect resistance. In this way, interconnect structures fabricated according to the teachings described herein can meet reduced structure profile requirements (e.g., below 7nm nodes) while also providing reduced line-to-via resistance.

[0071] Various embodiments of the invention have been described herein with reference to the accompanying drawings. Alternative embodiments may be designed without departing from the scope of the invention. While different connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are illustrated in the description and drawings, those skilled in the art will recognize that many of the positional relationships described herein are orientation-independent while the described function is maintained (even if the orientation changes). Unless otherwise specified, these connections and / or positional relationships may be direct or indirect, and the invention is not intended to limit in this respect. Thus, the connection of entities may refer to direct or indirect connections, and the positional relationship between entities may be direct or indirect positional relationship. As an example of an indirect positional relationship, the reference in this specification to forming layer "A" on layer "B" includes the case where one or more intermediate layers (e.g., layer "C") are located between layer "A" and layer "B," provided that the intermediate layers substantially do not alter the relevant features and functions of layer "A" and layer "B."

[0072] The following definitions and abbreviations are used to interpret the claims and description. As used herein, the terms “comprising,” “including,” “having,” “containing,” or any other variations thereof are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or other elements inherent to such composition, mixture, process, method, article, or apparatus.

[0073] Furthermore, the term "exemplary" is used herein to mean "serving as an example, illustration, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as superior to or better than other embodiments or designs. The terms "at least one" and "one or more" should be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "multiple" should be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" can include both indirect "connection" and direct "connection."

[0074] References to "an embodiment," "embodiment," "exemplary embodiment," etc., in the specification indicate that the described embodiment may include a particular feature, structure, or characteristic; however, each embodiment may or may not include a particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, if a particular feature, structure, or characteristic is described in connection with an embodiment, the effect of such feature, structure, or characteristic in connection with other embodiments (whether explicitly described or not) is within the knowledge of those skilled in the art.

[0075] For the purposes described below, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives will refer to the structures and methods described in the orientation shown in the figures. The terms “cover,” “top,” “on top,” “positioned on,” or “positioned on top of” mean that a first element (such as a first structure) is present on a second element (such as a second structure), wherein an insert element (such as an interface structure) may be present between the first and second elements. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface of the two elements without any intermediate conductive, insulating, or semiconductor layer.

[0076] The phrase “selective”, such as “selective first element for second element”, means that the first element can be etched and the second element can be used as an etch stop.

[0077] The terms “about,” “substantially,” “roughly,” and their variations are intended to include the degree of error associated with a measurement based on a specific quantity of equipment available at the time of application submission. For example, “about” could include a range of ±8%, 5%, or 2% of a given value.

[0078] As previously stated, for the sake of brevity, conventional techniques associated with the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. However, by way of background, a more general description of semiconductor device manufacturing processes that can be used to implement one or more embodiments of the present invention is now provided. Although specific manufacturing operations used to implement one or more embodiments of the present invention may be individually known, the combinations of operations described herein and / or the resulting structures are unique. Thus, the unique combinations of operations described in conjunction with the manufacture of semiconductor devices according to the present invention utilize a variety of individually known physical and chemical processes performed on semiconductor (e.g., silicon) substrates, some of which are described in the various paragraphs.

[0079] Generally, the various processes used to form microchips that will be packaged into ICs fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / photolithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry) and chemical mechanical planarization (CMP). Semiconductor doping modifies electrical properties by doping (e.g., transistor source and drain), typically through diffusion and / or ion implantation. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing is used to activate the implanted dopant. Films of conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of different regions on a semiconductor substrate allows the substrate's conductivity to change with the application of voltage. By creating structures of these different components, millions of transistors can be built and connected together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate so that the pattern can be subsequently transferred onto the substrate. In semiconductor lithography, the pattern is formed from a photosensitive polymer called photoresist. To build the many wires that make up the complex structure of transistors and the interconnecting circuits of millions of transistors, the photolithography and etching pattern transfer steps are repeated multiple times. Each pattern printed on the wafer is aligned with the previously formed pattern, and conductors, insulators, and selectively doped regions are slowly built up to form the final device.

[0080] The flowcharts and block diagrams in the accompanying drawings illustrate possible implementations of manufacturing and / or operating methods according to different embodiments of the present invention. Different functions / operations of the method are represented by blocks in the flowcharts. In some alternative implementations, the functions marked in the blocks may occur in a different order than indicated in the figures. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order.

[0081] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the described embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements over those found in the market, or to enable those skilled in the art to understand the embodiments described herein.

Claims

1. A method for manufacturing an interconnect structure, the method comprising: A first conductive band extending in a first direction is formed on the upper surface of the substrate; This causes a first portion of the first conductive band to be recessed. After recessing a first portion of the first conductive strip, an interlayer dielectric (ILD) material is deposited on the substrate to cover the first conductive strip, and the ILD material is etched to expose the upper surface of the first conductive strip. A second conductive strip is formed on the upper surface of the ILD material, such that the second conductive strip extends in a second direction opposite to the first direction and crosses the first conductive strip. as well as The exposed portion of the first conductive strip on the opposite side of the second conductive strip is recessed below the interlayer dielectric to form a corresponding cavity exposing the upper surface of the first conductive strip, while the covered portion of the first conductive strip covered by the second conductive strip is retained, so as to form a fully aligned through-hole (FAV) between the first conductive strip and the second conductive strip.

2. The method according to claim 1, wherein, The FAV includes a first end that directly contacts the upper surface of the first conductive strip and a opposite second end that directly contacts the lower part of the second conductive strip.

3. The method according to any one of the preceding claims, wherein, All sides of the FAV are coplanar with the opposite sides of the first conductive strip and the second conductive strip, such that the FAV is perfectly aligned with the first and second conductive strips.

4. The method according to claim 1 or 2, wherein, The first and second conductive strips comprise metallic materials selected from the group consisting of copper, tungsten, cobalt, rhodium, platinum, molybdenum, and combinations thereof.

5. The method according to claim 1 or 2, wherein, After the first conductive strip is recessed, the second conductive strip has a first height extending from the second end of the FAV to the upper surface of the second conductive strip, and the first conductive strip has a second height extending from the substrate to the first end of the FAV, the second height being less than the first height.

6. The method according to claim 1 or 2, wherein, Forming the first conductive strip includes: forming a plurality of first conductive strips extending along a first direction on the upper surface of the substrate; Depositing an interlayer dielectric (ILD) material on a substrate includes: depositing an ILD material to cover a first conductive strip and etching the ILD to expose the upper surface of the first conductive strip; Forming the second conductive strip includes: forming a plurality of second conductive strips on the upper surface of the ILD, such that the second conductive strips extend along a second direction opposite to the first direction and cross the first conductive strip; and The process of recessing the exposed portion of the first conductive strip includes: recessing the exposed portion of the first conductive strip on the opposite side of each of the second conductive strips, while retaining the covered portion of the first conductive strip that is covered by the second conductive strip, so as to form a plurality of fully aligned vias (FAVs) between the first conductive strip and the second conductive strip.

7. The method according to claim 6, wherein, Each of the multiple FAVs includes a first end that directly contacts the upper surface of the corresponding first conductive strip and an opposing second end that directly contacts the lower part of the corresponding second conductive strip.

8. The method according to claim 7, wherein, All sides of the FAV are coplanar with the opposite sides of the corresponding first conductive strip and the corresponding second conductive strip, such that the FAV is perfectly aligned with the corresponding first conductive strip and the corresponding second conductive strip.

9. The method according to claim 6, wherein, The first and second conductive strips comprise metallic materials selected from copper, tungsten, cobalt, rhodium, molybdenum, or combinations thereof.

10. The method according to claim 6, wherein, After the first conductive strip is recessed, the second conductive strip has a first height extending from the second end of the FAV to the upper surface of the corresponding second conductive strip, and the first conductive strip has a second height extending from the substrate to the first end of the corresponding FAV, the second height being less than the first height.

11. An interconnection structure, comprising: An interlayer dielectric (ILD) on a substrate, wherein the ILD has a cavity extending through the ILD along a first direction; A first conductive strip is formed on a substrate and within a cavity. The first conductive strip extends along a first direction and crosses the upper surface of the substrate. The first conductive strip includes a first recessed portion having a first etched upper surface and a second recessed portion having a second etched upper surface covered by an ILD, different from the first recessed portion. The first etched upper surface is exposed within the cavity. A second conductive strip on the upper surface of the ILD, the second conductive strip extending in a second direction opposite to the first direction; as well as A fully aligned through-hole (FAV) extending between a first conductive strip and a second conductive strip, wherein all sides of the FAV are coplanar with the opposite sides of the first conductive strip and the opposite sides of the second conductive strip, such that the FAV is fully aligned with the first conductive strip and the second conductive strip.

12. The interconnection structure according to claim 11, wherein, The FAV includes a first end that directly contacts the upper surface of the first conductive strip and a opposite second end that directly contacts the lower part of the second conductive strip.

13. The interconnection structure according to claim 11 or 12, wherein, The first length of the cavity extending from the ILD to the FAV matches the second length of the first conductive strip extending from the ILD to the FAV.

14. The interconnection structure according to claim 11 or 12, wherein, The first and second conductive strips comprise metallic materials selected from the group consisting of copper, tungsten, cobalt, rhodium, platinum, molybdenum, and combinations thereof.

15. The interconnection structure according to claim 11 or 12, wherein, The second conductive strip has a first height extending from the second end of the FAV to the upper surface of the second conductive strip, and the first conductive strip has a second height extending from the substrate to the first end of the FAV, the second height being smaller than the first height.

16. The interconnection structure according to claim 11 or 12, wherein, ILD includes: Multiple cavities extending through the ILD along the first direction; A plurality of first conductive strips are formed on the substrate and in a corresponding cavity of a plurality of cavities, the plurality of first conductive strips extending along a first direction and across the upper surface of the substrate; Multiple second conductive strips on the upper surface of the ILD, the second conductive strips extending along a second direction opposite to the first direction; and Multiple fully aligned vias (FAVs), each FAV extending between a corresponding first conductive strip and a corresponding second conductive strip, wherein all sides of a given FAV are coplanar with the opposite sides of the corresponding first conductive strip and the corresponding second conductive strip, such that each FAV is fully aligned with the first and second conductive strips.

17. The interconnection structure according to claim 16, wherein, Each FAV includes a first end that directly contacts the upper surface of the corresponding first conductive strip and a corresponding second end that directly contacts the lower part of the corresponding second conductive strip.

18. The interconnection structure according to claim 17, wherein, The first length of a given cavity extending from the ILD to one side of the corresponding FAV matches the second length of a first conductive strip disposed in the given cavity and extending from the ILD to that side of the corresponding FAV.

19. The interconnection structure according to claim 16, wherein, The plurality of first conductive strips and the plurality of second conductive strips comprise metallic materials selected from the group consisting of copper, tungsten, cobalt, rhodium, platinum, and combinations thereof.

20. The interconnection structure according to claim 16, wherein, At least one of the plurality of first conductive strips has a first height extending from the substrate to a first end of a first FAV among the plurality of FAVs, and at least one of the plurality of first conductive strips has a second height extending from the substrate to a first end of a second FAV among the plurality of FAVs, the second height being different from the first height.

21. An interconnection structure, comprising: An interlayer dielectric (ILD) on a substrate, wherein the ILD has a plurality of cavities extending through it along a first direction; A plurality of first conductive strips on a substrate, each first conductive strip being located within a corresponding cavity in the plurality of cavities and extending across the upper surface of the substrate along a first direction; Multiple second-layer conductive strips are located on the upper surface of the ILD and extend along a second direction opposite to the first direction; as well as Multiple fully aligned vias (FAVs) extend between a corresponding first conductive layer and a corresponding second conductive layer, wherein the first conductive layer includes at least one recessed conductive layer having a stepped portion formed in an upper surface and adjacent to a given FAV that contacts the upper surface of the at least one recessed conductive layer, the recessed conductive layer having a second upper surface exposed within the cavity.

22. The interconnection structure according to claim 21, wherein, The recessed conductive strip includes a first upper surface adjacent to a first side of a given FAV and a second upper surface on a second side of a given FAV opposite to the first side, the first upper surface having a first height greater than the second height of the second upper surface.

23. The interconnection structure according to claim 22, wherein, The stepped portion is located between the given FAV and the first upper surface.

24. The interconnection structure according to claim 22, wherein, The stepped portion is located between the given FAV and the second upper surface.

25. The interconnection structure according to claim 21, wherein, All sides of each of the plurality of FAVs are coplanar with the opposite sides of the corresponding first conductive strip and the corresponding second conductive strip, such that each of the plurality of FAVs is perfectly aligned with the plurality of first conductive strips and the plurality of second conductive strips.

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