Three-dimensional memory devices with staircase structures and methods of forming the same

Abstract

A three-dimensional (3D) memory device includes interleaved conductive layers and dielectric layers. Edges of the conductive layers and the dielectric layers define a plurality of terraces. The 3D memory device can also include a plurality of landing structures, each landing structure disposed on a respective conductive layer at a respective terrace. Each of the landing structures includes a first layer of a first material and a second layer of a second material. The first layer is over the second layer. The second material is different than the first material.

Description

Background Technology

[0001] This disclosure relates to memory devices and methods for forming memory devices, and more particularly, to three-dimensional (3D) memory devices and methods for forming 3D memory devices.

[0002] Planar semiconductor devices (e.g., memory cells) have been shrunk to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of semiconductor devices approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. 3D semiconductor device architectures can address some of the density limitations in planar semiconductor devices (e.g., flash memory devices). Summary of the Invention

[0003] In one aspect, a 3D memory device includes staggered conductive and dielectric layers. The edges of the conductive and dielectric layers define multiple steps. The 3D memory device may also include multiple landing structures, each landing structure disposed on a corresponding conductive layer at a corresponding step. Each landing structure includes a first layer of a first material and a second layer of a second material. The first layer is on top of the second layer. The second material is different from the first material.

[0004] In another aspect, a memory system includes a 3D memory device comprising interleaved conductive and dielectric layers. The edges of the conductive and dielectric layers define multiple steps. The 3D memory device also includes multiple landing structures, each disposed on a corresponding conductive layer at a corresponding step. Each landing structure includes a first layer of a first material and a second layer of a second material. The first layer is on top of the second layer. The second material is different from the first material. The memory system may further include a memory controller coupled to the 3D memory device and configured to control the operation of the 3D memory device.

[0005] In another aspect, a method for forming a 3D memory device includes the following operations: forming a stacked structure having interleaved sacrificial layers and dielectric layers. The edges of the sacrificial layers and dielectric layers define multiple steps. Forming sacrificial portions, each in contact with a corresponding sacrificial layer. Removing the sacrificial portions and sacrificial layers to form lateral recesses, each lateral recess having a first recess portion and a second recess portion above and in contact with the first recess portion. Depositing a first material into each lateral recess to fill the first recess portion and forming a first layer in the second recess portion. Depositing a second material into the second recess portion to form a second layer above the first layer in the second recess portion. Attached Figure Description

[0006] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate aspects of this disclosure and, together with the specification, further serve to explain this disclosure and enable those skilled in the art to make and use it.

[0007] Figure 1 A cross-section of a 3D memory device is shown.

[0008] Figure 2A A top view of an exemplary 3D memory device according to some aspects of this disclosure is shown.

[0009] Figure 2B and Figure 2C Each shows some aspects according to this disclosure. Figure 2A A cross-sectional view of an example of a 3D memory device.

[0010] Figure 2D and Figure 2E Each shows some aspects according to this disclosure. Figure 2A A cross-sectional view of another example of a 3D memory device.

[0011] Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A and Figure 12B Cross-sectional views of exemplary 3D memory devices at different stages of the manufacturing process according to some aspects of this disclosure are shown.

[0012] Figure 13 A flowchart illustrating an exemplary method for forming a 3D memory device according to some aspects of this disclosure is shown.

[0013] Figure 14 A block diagram of an exemplary system having a memory device according to some aspects of this disclosure is shown.

[0014] Figure 15A A diagram of an exemplary memory card having a memory device according to some aspects of this disclosure is shown.

[0015] Figure 15BA diagram of an exemplary solid-state drive (SSD) having a memory device is shown according to some aspects of this disclosure.

[0016] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0017] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Thus, other configurations and arrangements can be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other, and in a manner not specifically depicted in the accompanying drawings, such combinations, adjustments, and modifications are within the scope of this disclosure.

[0018] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a” or “described” can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0019] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on something” but also includes “on something” with an intermediate feature or layer therebetween, and that “above” or “on top of” means not only “above something” but also includes “above something” or “on top of something” without an intermediate feature or layer therebetween (i.e., directly on something).

[0020] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for ease of description to describe the relationship between one element or feature and (one or more) another element or feature as shown in the figures. Spatial relative terms are intended to cover different orientations in the use or operation of the device other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0021] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0022] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0023] As used herein, the term "3D memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," e.g., NAND memory strings) on a laterally oriented substrate such that the memory strings extend in a direction perpendicular to the substrate. As used herein, the term "vertically / perpendicularly" means nominally perpendicular to the lateral surface of the substrate.

[0024] In a 3D memory device (e.g., a 3D NAND memory device), a stack of interleaved conductive and dielectric layers (e.g., a memory stack) can be disposed on a substrate, and multiple channel structures extend through and intersect the conductive layers. The memory stack can be formed by replacing the sacrificial layers in the dielectric stack of the interleaved and dielectric layers with conductive layers in a gate replacement process. Memory cells are formed by the intersections between the conductive layers and the channel structures. Some of the conductive layers serve as word lines in the 3D NAND memory device and are arranged in multiple steps. Each step includes a top conductive layer with a landing region on which word line contacts land. The word line contacts apply a voltage to the top conductive layer for operation of the 3D NAND memory device.

[0025] As the demand for higher capacities continues to increase, the number of conductive layers (e.g., word lines) in 3D NAND memory devices is also increasing. This increase in the number of conductive layers leads to an increase in the height of the stack, and makes the fabrication process for forming word line contacts more challenging. For example, word line contacts are formed by creating openings in the dielectric structure above a step and filling the openings with conductive material. Openings that contact the top conductive layer of the corresponding step are typically formed in the same patterning process. Due to the different heights of the steps, etching may result in the top conductive layer in higher steps being overetched more, and the top conductive layer in lower steps being underetched or even etched less. Overetching of the top conductive layer can cause the opening to contact the underlying conductive layer, for example, resulting in a "punch-through" phenomenon. During word line contact formation, the conductive material of the word line contact may leak into the damaged underlying conductive layer, leading to short circuits and / or leaks.

[0026] To reduce the likelihood of damage to the top conductive layer, the landing region of the top conductive layer is thickened by forming additional conductive portions. To form a top conductive layer with conductive portions, sacrificial portions that contact the corresponding sacrificial layers are formed in the landing region of the corresponding steps. In the gate replacement process, gate line slots are formed in the stack, and then both the sacrificial portions and the sacrificial layers are removed through the gate line slots to form lateral recesses. Conductive material is then deposited through the gate line slots to fill the lateral recesses. Therefore, the portion of the lateral recess at the landing region is thicker than the rest of the lateral recess. To completely fill the lateral recess at the landing region, a large amount of conductive material, such as tungsten, needs to be deposited. This large amount of conductive material can form a thick conductive material layer on the sidewalls of the gate line slot. When forming source contact structures in the gate line slots, it may be difficult to completely remove the thick conductive material layer during recess etching (used to remove excess conductive material). Conductive residues may remain on the sidewalls of the gate line slots, leading to short circuits between adjacent conductive layers. On the other hand, if less conductive material is deposited to avoid a thick layer, the lateral recesses in the landing region may not be fully filled, and insufficient conductive material may not be deposited to sustain subsequent recess etching (for removing excess conductive material) during the formation of the source contact structure. Therefore, the lateral recesses in the landing region may be partially or completely hollow. This increases the likelihood of break-through when forming word line contacts, and 3D NAND memory devices are more susceptible to short circuits / leakage.

[0027] Figure 1A cross-sectional view of a 3D memory device 100 is shown, in which the top conductive layer is at least partially hollow at the landing region for reasons described above. The 3D memory device 100 includes a stacked structure 102 on a substrate (not shown) having a plurality of interleaved conductive layers 104 and dielectric layers 106. The edges of the conductive layers 104 and dielectric layers 106 may define a plurality of steps. Each step includes one of the conductive layers 104 as a top conductive layer and includes a lower dielectric layer 106. The 3D memory device 100 also includes a dielectric structure 108 above the steps and a plurality of word line contacts 110 in the dielectric structure 108. Each word line contact 110 contacts a landing region of a corresponding conductive layer 104 of a corresponding step. For illustrative purposes, one word line contact 110 is shown.

[0028] like Figure 1 As shown, the conductive layer 104 may include a first portion 104-1 and a second portion 104-2 in contact with each other. The second portion 104-2 includes a conductive material, such as tungsten. The first portion 104-1 includes any conductive material in the recessed portion, which is formed by removing portions of the underlying sacrificial layer and the sacrificial portion. The conductive material filling the conductive layer 104 is deposited through the gate line gap. In the gate replacement process, the recessed portion may not be completely filled. In the fabrication process that forms the source contact structure, a recess etching is performed to remove excess conductive material from the sidewalls of the gate line gap, and the recess etching may remove portions of all conductive material in the recessed portion. Therefore, the first portion 104-1 may be partially or completely hollow. During the formation of the opening in which the word line contact 110 is formed, the dielectric structure 108 is etched. The etching may cause the opening to extend into or through the partially or completely hollow first portion 104-1. The deposited conductive material used to fill the opening is then more likely to contact the underlying conductive layer 104. On the other hand, if the recessed area is completely filled by a conductive material layer (not formed), the conductive layer material deposited on the gate line gap may be too thick to be removed. Conductive residue may cause short circuits between conductive layers.

[0029] This disclosure provides a 3D memory device and a method of manufacturing a 3D memory device. The 3D memory device includes a memory stack having multiple steps extending on at least one side of a stack of interleaved conductive and dielectric layers (e.g., a memory stack). The 3D memory device includes a landing structure deposited on a corresponding conductive layer at the top surface of a corresponding step. The landing structure has a first layer and a second layer below the first layer. The first layer includes a conductive material, such as tungsten. The second layer includes a material different from the first layer. In some embodiments, the second layer includes silicon oxide, silicon nitride, silicon oxynitride, polysilicon, or any combination thereof. The first layer surrounds the second layer and is in contact with the underlying conductive material. In some embodiments, the first layer extends on a side surface of the landing structure, and the second layer fills the remainder of the landing structure. In some other embodiments, the 3D memory device also includes a third layer surrounded by the second layer. The third layer fills the remainder of the landing structure. The third layer also includes a conductive material, such as the same material as the first layer or a different material.

[0030] A landing structure with a conductive first layer allows word line contacts to become electrically connected to the corresponding conductive layer upon contact with the landing structure. The word line contacts can stop at any depth within the landing structure and remain electrically connected to the corresponding conductive layer. Simultaneously, the first material only partially fills the landing structure and does not form an undesirable thick monolayer on the sidewalls of the slot structure through which the first material deposition passes. The second material formed on top of the first material on the sidewalls of the slot structure can be easily removed. Therefore, the removal of the first material can be easier. Even if a third layer of a third material (e.g., a conductive material) is formed on the sidewalls of the slot structure to fill the landing structure, the layer of the third material is separated from the layer of the first material by the layer of the second material. The thickness of each of the first, second, and third layers can be as thin as desired to facilitate the complete removal of one or more excess conductive materials on the sidewalls of the slot structure. On the other hand, the thickness of the first layer is sufficient to provide high conductivity between the word line contacts and the corresponding conductive layer. Short circuits between adjacent conductive layers caused by conductive residues on the sidewalls of the slot structure can be reduced or prevented.

[0031] Figures 2A-2E Parts of 3D memory devices 200 and 201 according to some aspects of this disclosure are shown. 3D memory devices 200 and 201 may each be 3D NAND memory devices. Figure 2A A top view of portions of 3D memory devices 200 and 201 is shown. Figure 2B A cross-sectional view of a portion of the 3D memory device 200 in the A-A' direction is shown. Figure 2C A cross-sectional view of a portion of the 3D memory device 200 in the B-B' direction is shown. Figure 2DA cross-sectional view of a portion of the 3D memory device 201 in the A-A' direction is shown. Figure 2E A cross-sectional view of a portion of the 3D memory device 201 in the B-B' direction is shown.

[0032] 3D memory device 200 may include a stacked structure 202 on a substrate (not shown). The substrate may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In some embodiments, the substrate is a thinned substrate (e.g., a semiconductor layer) thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. It should be noted that the accompanying drawings of this disclosure include x-axis and y-axis to further illustrate the spatial relationships of the components in 3D memory device 200. The substrate of 3D memory device 200 includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction and y-direction (i.e., the lateral direction) orthogonal to the z-direction (i.e., the vertical direction). As used herein, when a substrate is positioned in the lowest plane of a 3D memory device (e.g., 3D memory device 200) in the z-direction (i.e., the vertical direction), the location of one component (e.g., layer or device) of the 3D memory device relative to the substrate of the 3D memory device in the z-direction is determined to be “on,” “above,” or “below” another component (e.g., layer or device). The same concepts used to describe spatial relationships apply throughout this disclosure.

[0033] 3D memory device 200 may be part of a monolithic 3D memory device. The term "monolithic" means that the components of the 3D memory device (e.g., peripheral devices and memory array devices) are formed on a single substrate. For monolithic 3D memory devices, manufacturing faces additional constraints due to the convolution involved in processing the peripheral devices and the memory array devices. For example, the manufacturing of memory array devices (e.g., NAND memory strings) is limited by the thermal budget associated with the peripheral devices that have been formed or will be formed on the same substrate.

[0034] Alternatively, the 3D memory device 200 may be part of a non-monolithic 3D memory device, in which components (e.g., peripheral devices and memory array devices) may be formed separately on different substrates and then bonded, for example, face-to-face. In some embodiments, the memory array device substrate (e.g., the substrate of the 3D memory device 200) remains the substrate of the bonded non-monolithic 3D memory device, and the peripheral devices (e.g., including any digital, analog, and / or mixed-signal peripheral circuitry for facilitating the operation of the 3D memory device 200, such as page buffers, decoders, and latches; not shown) are flipped and face down toward the memory array device (e.g., a NAND memory string) for hybrid bonding. It should be understood that in some embodiments, the memory array device substrate is flipped and face down toward the peripheral devices (not shown) for hybrid bonding, such that in the bonded non-monolithic 3D memory device, the memory array device is above the peripheral devices. The substrate of the memory array device can be a thinned substrate (the thinned substrate is not the substrate of the bonded non-monolithic 3D memory device), and back-end-of-line (BEOL) interconnects of the non-monolithic 3D memory device can be formed on the back side of the thinned memory array device substrate.

[0035] In some embodiments, the 3D memory device 200 is a NAND flash memory device, wherein the memory cells are provided in the form of an array of NAND memory strings (not shown), each NAND memory string extending vertically above a substrate. Figure 1 As shown, the 3D memory device 200 may include a stacked body structure 202 formed on a substrate, and the NAND memory string may include a channel structure (not shown) extending vertically through the stacked body structure in the z-direction. The stacked body structure 202 includes a plurality of staggered conductive layers 204 and a plurality of dielectric layers 206. The conductive layers 204 may include at least one source-select gate line, a plurality of word lines, and at least one drain-select gate line.

[0036] The stacked structure 202 may include a plurality of interleaved conductive layers 204 and dielectric layers 206 stacked in the z-direction. For example... Figures 2A-2C As shown, the edges of the conductive layer 204 and the dielectric layer 206 form multiple steps extending in the x-direction. Figure 2AThe steps are shown in dashed lines. In some embodiments, a pair of conductive layers 204 and an underlying dielectric layer 206 are arranged in the steps. In some embodiments, more than one pair of conductive layers 204 and dielectric layers 206 are arranged in the steps. Each conductive layer 204 may comprise a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicide, or any combination thereof. Each dielectric layer 206 may comprise a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0037] The 3D memory device 200 may include a dielectric structure 208 disposed on a step. A plurality of word line contacts 210 may extend within the dielectric structure 208. Each word line contact 210 may land on a corresponding step. A word line voltage may be applied to the word line contacts 210 on the conductive layer 204 for operation of the 3D memory device 200. Each word line contact 210 may each include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. The dielectric structure 208 may each include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0038] like Figure 2B and Figure 2C As shown, the 3D memory device 200 may further include a plurality of landing structures 212, each disposed on a corresponding step. Specifically, the landing structure 212 may contact and be electrically connected to a corresponding (e.g., top) conductive layer 204 on the top surface of the corresponding step. The landing structure 212 may include a first layer 212-1 and a second layer 212-2 below the first layer 212-1. The first layer 212-1 may include a first material, such as a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicide, or any combination thereof. For example, the first material includes tungsten. The second layer 212-2 may include a second material different from the first material. For example, the second material may include silicon oxide, silicon nitride, silicon oxynitride, polycrystalline silicon, or any combination thereof. In this example, the second material includes silicon oxide.

[0039] like Figure 2BAs shown, the first layer 212-1 can extend laterally (e.g., in the xy plane) and vertically (e.g., in the z direction). For example, the first layer 212-1 may include a lateral portion and a pair of vertical portions. The lateral portion may contact the vertical portion. The first layer 212-1 may contact the corresponding lower conductive layer 204 through at least one vertical portion (e.g., two vertical portions). When the word line contact 210 contacts the landing structure 212, the word line contact 210 contacts the lateral portion of the landing structure 212 and is therefore electrically connected to the corresponding lower conductive layer 204.

[0040] The second layer 212-2 may contact and be surrounded by the first layer 212-1 (e.g., surrounded by the horizontal and vertical portions of the first layer 212-1). Figure 2B As shown, the second layer 212-2 is surrounded by and in contact with the first layer 212-1 and the corresponding lower conductive layer 204. In some embodiments, although not shown, the second layer 212-2 completely fills the space formed / surrounded by the first layer 212-1 and the corresponding lower conductive layer 204. In other words, the second layer 212-2 fills the remainder of the landing structure 212, except for the first layer 212-1. When the word line contact 210 contacts the landing structure 212, the word line contact 210 may or may not contact the second layer 212-2. However, since the word line contact 210 contacts the lateral portion of the first layer 212-1, the word line contact 210 is electrically connected to the corresponding lower conductive layer 204.

[0041] In some implementations, such as Figure 2B and Figure 2CAs shown, the second layer 212-2 may not fill the space formed by the first layer 212-1 and the corresponding lower conductive layer 204, and the landing structure 212 may include a third layer 212-3 surrounded by and in contact with the second layer 212-2. The second layer 212-2 may be disposed on the first layer 212-1, and the third layer 212-3 may be disposed on the second layer 212-2 and fill the space formed / surrounded by the second layer 212-2. The third layer 212-3 may fill the remaining portion of the space formed by the second layer 212-2 and provide sufficient support for the landing of the word line contact 210. The third layer 212-3 may include a third material, such as a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the third layer 212-3 includes the same material as the first material, such as tungsten. In some embodiments, the third layer 212-3 differs from the first and second materials and can be conductive or non-conductive. For example, the third layer 212-3 may include W, Co, Al, Cu, silicide, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, carbon, or any combination thereof. When the word line contact 210 contacts the landing structure 212, the word line contact 210 may or may not contact the third layer 212-3. However, since the word line contact 210 contacts the lateral portion of the landing structure 212, the word line contact 210 is electrically connected to the corresponding lower conductive layer 204.

[0042] In some embodiments, the first material comprises tungsten, the second material comprises silicon oxide, and the third material and the lower conductive layer 204 each comprise tungsten. In some embodiments, the first material comprises tungsten, the second material comprises silicon nitride, and the third material and the lower conductive layer 204 each comprise tungsten. In some embodiments, the first material comprises tungsten, the second material comprises polycrystalline silicon, and the third material and the lower conductive layer 204 each comprise tungsten.

[0043] like Figure 2B and Figure 2CAs shown, although the landing structure 212 is not completely filled with a conductive material (e.g., tungsten), the first layer 212-1 can facilitate electrical connection between the word line contact 210 and the corresponding lower conductive layer 204 when the word line contact 210 contacts the landing structure 212. When both the first layer 212-1 and the third layer 212-3 are formed, they are separated by a second layer 212-2, which comprises a material different from that of the first layer 212-1 and the third layer 212-3. The formation of the second layer 212-2 allows the thickness of each of the first layer 212-1 and the third layer 212-3 to be less than the thickness of the landing structure 212. Even if the first layer 212-1 and the third layer 212-3 comprise the same material (e.g., tungsten), the thickness of each of the first layer 212-1 and the third layer 212-3 on the sidewalls of the slot structure will not be undesirably thick. Therefore, during the formation of the source contact structure (described below), the conductive material on the sidewalls of the slot structure (deposited by the formation of the first layer 212-1 and / or the third layer 212-3) can be completely removed during recess etching. The conductive layer 204 is less susceptible to short circuits caused by conductive residues on the side surfaces of the slot structure.

[0044] Figure 2D and Figure 2E A 3D memory device 201 is illustrated, wherein a second layer completely fills the space formed / surrounded by a first layer and a corresponding conductive layer. Unlike 3D memory device 200, 3D memory device 201 includes a landing structure 211 comprising a first layer 211-1 of a first material and a second layer 211-2 of a second material. The second layer 211-2 may completely fill the space surrounded / formed by the first layer 211-1 and a corresponding lower conductive layer 204. In some embodiments, the second layer 211-2 is on top of and in contact with the first layer 211-1 and the corresponding lower conductive layer 204. The structure or material of the first layer 211-1 may be similar to that of the first layer 212-1, and will not be described again here. The second material may differ from the first material and may include polysilicon, silicon oxide, silicon nitride, silicon oxynitride, carbon, or any combination thereof. In one example, the second material includes silicon nitride. In another example, the second material comprises polysilicon (e.g., doped polysilicon and / or undoped polysilicon). Word line contacts 210 may contact the first layer 211-1 and may or may not contact the second layer 211-2 and the underlying conductive layer 204. In some embodiments, the first material comprises tungsten, the second material comprises silicon nitride, and the underlying conductive layer 204 comprises tungsten. In some embodiments, the first material comprises tungsten, the second material comprises polysilicon, and the underlying conductive layer 204 comprises tungsten.

[0045] The 3D memory device 200 / 201 may also include one or more slot structures 214 extending (e.g., in the x and z directions) within the stacked body structure 202. In some embodiments, the slot structure 214 may also be referred to as a gate line slot. Source contact structures may be formed in the slot structures 214. The source contact structures may be portions of the source of the 3D memory device 200 / 201, and a source voltage may be applied to the 3D memory device 200 / 201. Figure 2C As shown, the source contact structure may include a dielectric spacer 218 and source contacts 216 within the dielectric spacer 218. The source contacts 216 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. The dielectric spacer 218 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0046] In some embodiments, conductive layer 204 serves as the gate conductor for memory cells in a NAND memory string (not shown). Conductive layer 204 may extend laterally to couple multiple memory cells. In some embodiments, the memory cell transistors in the NAND memory string include a channel structure having semiconductor channels and storage films (including tunneling layers, storage layers, and barrier layers). The NAND memory string may be located within the core array region of the 3D memory device 200 / 201.

[0047] The channel structure may include channel vias filled with a semiconductor material (e.g., as a semiconductor channel) and a dielectric material (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some embodiments, the memory film is a composite layer including a tunneling layer, a memory layer (also referred to as a "charge trapping layer"), and a barrier layer. In some embodiments, the remaining space of the channel structure may be partially or completely filled with a fill layer including a dielectric material (e.g., silicon oxide). The channel structure may have a cylindrical shape (e.g., a columnar shape). According to some embodiments, the fill layer, semiconductor channel, tunneling layer, memory layer, and barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the storage film may include a silicon oxide / silicon oxynitride (or silicon nitride) / silicon oxide (ONO) composite layer.

[0048] In some embodiments, the NAND memory string may also include channel contacts (or semiconductor plugs) in the lower portion of the NAND memory string below the channel structure (e.g., at the lower end). As used herein, when the substrate is positioned in the lowest plane of the 3D memory device 200 / 201, the “upper end” of the component (e.g., the NAND memory string) is the end away from the substrate in the z-direction, and the “lower end” of the component (e.g., the NAND memory string) is the end closer to the substrate in the z-direction. The channel contacts may include a semiconductor material, such as silicon, epitaxially grown from the substrate in any suitable direction. It should be understood that in some embodiments, the channel contacts include monocrystalline silicon, i.e., the same material as the substrate. In other words, the channel contacts may include an epitaxially grown or deposited semiconductor layer of the same material as the substrate. In some embodiments, a portion of the channel contacts is above the top surface of the substrate and contacts the semiconductor channel. The channel contacts can serve as a channel controlled by the source-select gate of the NAND memory string. It should be understood that in some implementations, the 3D memory device 200 / 201 does not include channel contacts.

[0049] In some embodiments, the NAND memory string further includes a channel plug in the upper portion of the NAND memory string (e.g., at the upper end). The channel plug may contact the upper end of the semiconductor channel. The channel plug may include a semiconductor material (e.g., polysilicon). By covering the upper end of the channel structure during the fabrication of the 3D memory device 200 / 201, the channel plug can serve as an etch stop layer to prevent etching of the dielectric, such as silicon oxide and silicon nitride, filling the channel structure. In some embodiments, the channel plug also serves as the drain of the NAND memory string. It should be understood that in some embodiments, the 3D memory device 200 / 201 does not include a channel plug.

[0050] Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A and Figure 12BCross-sections of a 3D memory device at different stages of the manufacturing process according to some aspects of this disclosure are shown. The 3D memory device may be an example of 3D memory device 200 or 201. Figure 13 A flowchart of an exemplary method 1300 for forming a 3D memory device according to some aspects of this disclosure is shown. For the purpose of better describing this disclosure, it will be discussed together. Figure 3A-12B The structure and Figure 13 Method 1300. It should be understood that the operations shown in Method 1300 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figures 3A-12B and Figure 13 The different execution sequences are shown.

[0051] like Figure 13 As shown, method 1300 begins with operation 1302, in which a stacked body structure is formed on a substrate and a channel structure is formed in the stacked body structure. Figure 3A and Figure 3B The corresponding structure is shown.

[0052] like Figure 3A and Figure 3B As shown, the stack structure 301 can be formed on a substrate (not shown). The stack structure 301 can include a dielectric stack having a plurality of staggered sacrificial layers 305 and dielectric layers 306 extending in the x-direction, thereby forming a plurality of sacrificial layer / dielectric layer pairs. The edges of the sacrificial layer / dielectric layer pairs can define a plurality of steps. In some embodiments, the sacrificial layer 305 can be located at the top surface of a corresponding step. The dielectric stack (e.g., steps) can be formed by repeatedly trimming the staggered sacrificial material layers and dielectric material layers of the dielectric material stack. In some embodiments, each dielectric layer 306 can include a silicon oxide layer, and each sacrificial layer 305 can include a silicon nitride layer. The dielectric material stack can be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some embodiments, a pad oxide layer (not shown) is formed between the substrate and the dielectric material stack by depositing a dielectric material (e.g., silicon oxide) on the substrate. Trimming of the dielectric material stack may include photolithography and etching (e.g., dry and / or wet etching) processes.

[0053] A channel structure (not shown) is formed extending vertically through the stack structure 301 in the z-direction. In some embodiments, an etching process is performed to form a channel via in the stack structure 301. The channel via may extend vertically through interleaved sacrificial and dielectric layers. In some embodiments, the fabrication process for forming the channel via may include wet etching and / or dry etching, such as deep reactive ion etching (DRIE). In some embodiments, the channel via may further extend into the top portion of the substrate. The etching process through the stack structure 301 may not stop at the top surface of the substrate and may continue etching portions of the substrate. After forming the channel via, an epitaxial operation (e.g., selective epitaxial growth operation) may be performed to form a channel contact at the bottom of the channel via. The channel contact (or semiconductor plug) may include a semiconductor material, such as silicon, epitaxially grown from the substrate in any suitable direction. The semiconductor channel and a memory film including a tunneling layer, a storage layer, and a barrier layer may then be formed. Optionally, a fill layer may be formed in the channel via. In some embodiments, the channel structure may not include a semiconductor plug. The deposition of the storage film, semiconductor channel, and filling layer can include any suitable thin-film deposition process, such as CVD, PVD, ALD, or any combination thereof. The deposition of the channel plug can include CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof.

[0054] Method 1300 proceeds to operation 1304, in which multiple sacrificial parts are formed on their respective sacrificial layers. Figure 3A , Figure 3B , Figure 4A and Figure 4B The corresponding structure is shown.

[0055] Return to reference Figure 3A and Figure 3B A sacrificial material layer 303 can be deposited on top of the steps. Layer 303 can at least cover the landing area of ​​each step. Layer 303 can contact the exposed sacrificial layer 305 and has the same material as the sacrificial layer 305, such as silicon nitride. In some embodiments, layer 303 can be thick enough that the subsequently formed landing structure (e.g., return reference landing structure 212) can maintain over-etching during word line contact fabrication. In some embodiments, the thickness of layer 303 is equal to or greater than 10 nm. The sacrificial material of layer 303 can also include other suitable materials such that the sacrificial material of layer 303 and sacrificial layer 305 can be removed in the same etching process during a subsequent gate replacement process. The deposition of layer 303 can include any suitable thin film deposition process, such as CVD, PVD, ALD, or any combination thereof.

[0056] Return to reference Figure 4A and Figure 4B Layer 303 can be patterned to form a plurality of sacrificial portions 403, each sacrificial portion disposed on a corresponding sacrificial layer 305 of a corresponding step. The sacrificial portions 403 can be disposed at the landing region of the corresponding step. To form the sacrificial portions 403, layer 303 can be patterned to remove portions of sacrificial material deposited on the side surfaces of the step. Therefore, each sacrificial portion 403 can be disconnected from each other. Patterning of layer 303 can include photolithography and etching (e.g., dry and / or wet etching) processes.

[0057] A dielectric material structure is deposited on the step to cover the sacrificial portion 403. The dielectric material structure is then planarized to form a dielectric structure 408 covering the step. The deposition of the dielectric material structure can include any suitable thin-film deposition process, such as CVD, PVD, ALD, or any combination thereof. Planarization of the dielectric material structure can include CMP and / or recess etching processes.

[0058] Method 1300 proceeds to operation 1306, in which the sacrificial layer and sacrificial portion are removed to form a plurality of lateral recesses, each lateral recess having a first recess portion and a second recess portion above and in contact with the first recess portion. Figure 5A and Figure 5B The corresponding structure is shown.

[0059] like Figure 5A and Figure 5B As shown, the sacrificial layer 305 and sacrificial portion 403 are removed from the stacked structure 301. A plurality of lateral recesses 502 extending laterally in the xy-plane are formed in the stacked structure 301. To form the lateral recesses 502, one or more slot structures 504 (e.g., gate line slots) extending through the stacked structure 301 in the z-direction may be formed. (Return to Reference) Figure 2A The slot structure 504 may extend laterally in the x-direction. The slot structure 504 may contact or extend into the top portion of the substrate. In some embodiments, the fabrication process for forming the slot structure 504 may include wet etching and / or dry etching, such as deep ion reactive etching (DRIE). An isotropic etching process (e.g., wet etching) may be performed on the slot structure 504 to remove the sacrificial layer 305 and the sacrificial portion 403, thereby forming a plurality of lateral recesses 502.

[0060] The lateral recess 502 may include a first recessed portion 502-1 and a second recessed portion 502-2 that is above and contacts the first recessed portion 502-1. The first recessed portion 502-1 can be formed by removing the corresponding sacrificial layer 305. In the x-direction, the length of the first recessed portion 502-1 is greater than the length of the second recessed portion 502-2. In some embodiments, the first recessed portion 502-1 extends laterally to the edge of the corresponding step and also intersects with the channel structure in the stack structure 301. The second recessed portion 502-2 can be formed by removing the corresponding sacrificial portion 403, and the second recessed portion 502-2 is disposed in the landing area of ​​the corresponding step. In other words, the first recessed portion 502-1 and the second recessed portion 502-2 form a hollow space at the landing area of ​​the corresponding step.

[0061] Return to reference Figure 13 Method 1300 proceeds to operation 1308, in which a first material is deposited into each of the transverse recesses to fill the first recess portion and form a first layer in the second recess portion, and a second material is deposited into each of the second recess portions to form a second layer on top of the first layer in the second recess portion. Figure 6A and Figure 6B The corresponding structure is shown.

[0062] like Figure 6A and Figure 6B As shown, a first material can be deposited into the lateral recess 502 via the slot structure 504 to fill the first recess portion 502-1, and a first layer 612-1 can be formed in each of the second recess portions 502-2. A second material can be deposited into the second recess portion 502-2 via the slot structure 504 to form a second layer 612-2 on top of the first layer 612-1. A first material (e.g., a conductive material) can be deposited via the slot structure 504 to fill each of the first recess portions 502-1. In some embodiments, the first material at least fills the portion of the first recess portion 502-1 located in the core array region of the 3D memory structure (e.g., intersecting with the channel structure). In some embodiments, the first material fills the entire first recess portion 502-1, extending from the edge of the step to the core array region, and forms a conductive layer 604 (e.g., word lines). The first layer 612-1 can be on the side surfaces (e.g., the upper lateral surface and the vertical surface) of the second recess portion 502-2. Therefore, the first layer 612-1 may include a lateral portion and a pair of vertical portions. The first layer 612-1 may contact the conductive layer 604 at the vertical portions. The first layer 612-1 partially fills the second recessed portion 502-2.

[0063] The second layer 612-2 can be deposited on top of the first layer 612-1 and the lower conductive layer 604 in the second recessed portion 502-2. As an example, Figure 6A and Figure 6B The illustration shows a scenario where the second layer 612-2 partially fills the space formed / surrounded by the first layer 612-1 and the lower conductive layer 604, referring back to reference 3D memory device 200. In some embodiments, although not shown, the second layer 612-2 may completely fill the space formed / surrounded by the first layer 612-1 and the lower conductive layer 604, referring back to reference 3D memory device 201. In some embodiments, such as Figure 6A and Figure 6B As shown, when the second layer 612-2 partially fills the space formed by the first layer 612-1 and the lower conductive layer 604, a space (e.g., a hollow portion) can be formed in the second recessed portion 502-2.

[0064] The first material may include a conductive material, such as tungsten, and may be formed by any suitable thin-film deposition process, such as CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The second material may include a material different from the first material. For example, the second material may include silicon oxide, silicon nitride, silicon oxynitride, polycrystalline silicon, carbon, or any combination thereof. In some embodiments, the second material includes silicon oxide. The deposition of the second material may include any suitable thin-film deposition process, such as CVD, PVD, ALD, or any combination thereof.

[0065] like Figure 6B As shown, the first material and the second material can also be deposited on the sidewalls of the slot structure 504. For example, the first material can be located on the dielectric structure 408 and the conductive layer 604 exposed on the sidewalls of the slot structure 504, and the second material can be disposed on the first material. In some embodiments, the second material can protect the first material on the sidewalls of the slot structure 504.

[0066] Return to reference Figure 13 Method 1300 proceeds to operation 1310, in which a third layer is deposited to fill the second depression. Figure 7A and Figure 7B The corresponding structure is shown.

[0067] like Figure 7A and Figure 7B As shown, in some embodiments, when the second material partially fills the space formed / surrounded by the first layer 612-1 and the lower conductive layer 604 (e.g.) Figure 6A and Figure 6BAs shown in the example, a third material can be deposited into the second recessed portion 502-2 via the slit structure 504 to fill the space formed by the enclosure / surrounding of the second layer 612-2. When the second layer 612-2 does not completely fill the space in the second recessed portion 502-2 formed by the first layer 612-1 and the lower conductive layer 604, a third layer 612-3 is deposited. The third layer 612-3 can be formed on top of, surrounded by, and in contact with the second layer 612-2. The third material can include a conductive material, for example, the same as the first material. In some embodiments, the third material is different from the first and second materials and can be conductive or non-conductive. For example, the third material can be W, Co, Al, Cu, silicide, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, carbon, or any combination thereof. The third material can be formed by any suitable thin-film deposition process, such as CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. Figure 7B As shown, a third material may also be deposited on the sidewalls of the slot structure 504. For example, the third material may be deposited on top of the second material. In some embodiments, the third material is not deposited when the second material completely fills the space formed / surrounded by the first layer 612-1 and the lower conductive layer 604.

[0068] Return to reference Figure 13 Method 1300 proceeds to operation 1312, in which a source contact structure is formed in the slot structure. Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A and Figure 11B The corresponding structure is shown.

[0069] One or more recess etching processes can be performed to remove excess material deposited on the sidewalls of the slot structure 504. For example... Figure 8A and Figure 8B As shown, if a third material is deposited, the third material on the sidewalls of the slot structure 504 can be removed, leaving the third layer 612-3 in the second recessed portion 502-2 intact. The second material on the sidewalls of the slot structure 504 can be exposed. In some embodiments, the third material comprises tungsten. A suitable etching process (e.g., dry and / or wet etching processes) can be performed to remove the third material.

[0070] like Figure 9A and Figure 9BAs shown, the second material on the sidewalls of the slot structure 504 can be removed, while the second layer 612-2 in the second recessed portion 502-2 remains. The first material on the sidewalls of the slot structure 504 can be exposed. A suitable etching process (e.g., dry and / or wet etching process) can be performed to remove the second material.

[0071] like Figure 10A and Figure 10B As shown, the first material on the sidewall of the slot structure 504 can be removed, leaving the first layer 612-1 in the second recessed portion 502-2 intact. The dielectric structure 408 and the conductive layer 604 on the sidewall of the slot structure 504 can be exposed. The etching process for removing the first material can also be used as a recess etching process to form a recess in each conductive layer 604 in the x-direction from the sidewall of the slot structure 504 (or from the dielectric layer 306). Simultaneously, the first layer 612-1 and the third layer 612-3 exposed on the sidewall of the slot structure 504 are also etched to form a recess in the x-direction from the second layer 612-2. That is, the dielectric layer 306 and the second layer 612-2 can form protrusions on the sidewall of the slot structure 504. The conductive layers 604 can be disconnected from each other. The etching process can include dry and / or wet etching processes.

[0072] Then, a source contact structure can be formed in the slot structure 504. The source contact structure may include a dielectric spacer 1118 (e.g., silicon oxide) and source contacts 1116 (e.g., W) within the dielectric spacer 1118. The formation of the dielectric spacer 1118 may include one or more thin-film deposition processes, such as CVD, PVD, and / or ALD. The formation of the source contacts 1116 may include CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof.

[0073] Return to reference Figure 13 Method 1300 proceeds to operation 1314, in which word line contacts are formed on the corresponding landing structure. Figure 12A and Figure 12B The corresponding structure is shown.

[0074] like Figure 12A and Figure 12BAs shown, multiple word line contacts 1210 may each be formed on a corresponding landing structure 612 of a corresponding step. The word line contacts 1210 may contact at least the first layer 612-1 of the landing structure 612. In some embodiments, depending on the manufacturing process, the word line contacts 1210 may contact the second layer 612-2 and / or the third layer 612-3 of the landing structure 612. To form the word line contacts 1210, the dielectric structure 408 may be patterned to form a plurality of openings extending in the z-direction within the dielectric structure 408. Each opening may contact a corresponding landing structure 612. A conductive material is then deposited to fill the openings. In some embodiments, a planarization process is performed on the dielectric structure 408 to remove any excess material on the dielectric structure 408. The etching forming the openings may include suitable etching processes, such as dry and / or wet etching processes. The deposition of the conductive material may include CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. Planarization of dielectric structures can include CMP and / or recess etching processes.

[0075] Figure 14 A block diagram of an exemplary system 1400 having a memory device according to some aspects of this disclosure is shown. System 1400 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 14 As shown, system 1400 may include a host 1408 and a memory system 1402, the memory system 1402 having one or more memory devices 1404 and a memory controller 1406. The host 1408 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 1408 may be configured to send data to or receive data from the memory device 1404.

[0076] Memory device 1404 can be any memory device disclosed herein. As detailed above, memory device 1404 (e.g., a NAND flash memory device) can have a landing structure on a respective conductive layer. The landing structure has a top layer made of conductive material that is as thin as desired to be removed in a recess etching process, and as thick as desired to provide high conductivity. According to some embodiments, memory controller 1406 is coupled to memory device 1404 and host 1408 and is configured to control memory device 1404. Memory controller 1406 can manage data stored in memory device 1404 and communicate with host 1408. For example, memory controller 1406 can be coupled to memory device 1404 (e.g., 3D memory devices 200 and / or 201 described above), and memory controller 1406 can be configured to control the operation of the channel structure in 3D memory devices 200 / 201, e.g., the application of word line voltages on the landing structure and conductive material.

[0077] In some embodiments, the memory controller 1406 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 1406 is designed to operate in high duty cycle environments, such as SSDs or embedded multi-media cards (eMMCs), which serve as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. The memory controller 1406 can be configured to control the operation of the memory device 1404, such as read, erase, and program operations. The memory controller 1406 can also be configured to manage various functions related to data stored or to be stored in the memory device 1404, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller 1406 is also configured to process error correction codes (ECCs) regarding data read from or written to the memory device 1404. The memory controller 1406 may also perform any other suitable functions, such as formatting the memory device 1404. The memory controller 1406 may communicate with external devices (e.g., host 1408) according to specific communication protocols. For example, the memory controller 1406 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnection (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0078] The memory controller 1406 and one or more memory devices 1404 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 1402 can be implemented and packaged into different types of end electronic products. Figure 15A In one example shown, the memory controller 1406 and a single memory device 1404 can be integrated into a memory card 1502. The memory card 1502 may include a PC card (PCMCIA (Personal Computer Memory Card International Association), CF card, smart media (SM) card, memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1502 may also include a connection between the memory card 1502 and a host computer (e.g., Figure 14 The memory card connector 1504 is coupled to the host 1408. In such a... Figure 15B In another example shown, the memory controller 1406 and multiple memory devices 1404 can be integrated into the SSD 1506. The SSD 1506 may also include a connection between the SSD 1506 and a host (e.g., ...). Figure 14 The SSD connector 1508 is coupled to the host 1408. In some embodiments, the storage capacity and / or operating speed of the SSD 1506 is greater than the storage capacity and / or operating speed of the memory card 1502.

[0079] According to one aspect of this disclosure, a 3D memory device includes staggered conductive layers and dielectric layers. The edges of the conductive and dielectric layers define multiple steps. The 3D memory device may further include multiple landing structures, each landing structure disposed on a corresponding conductive layer at a corresponding step. Each landing structure includes a first layer of a first material and a second layer of a second material. The first layer is on top of the second layer. The second material is different from the first material.

[0080] In some embodiments, the first material includes a conductive material.

[0081] In some implementations, the first material includes tungsten.

[0082] In some embodiments, the second material includes silicon oxide, silicon nitride, silicon oxynitride, polycrystalline silicon, or combinations thereof.

[0083] In some implementations, the first layer contacts a corresponding conductive layer and surrounds the second layer laterally and vertically.

[0084] In some embodiments, each landing structure further includes a third layer surrounded by the second layer. The third layer comprises a third material.

[0085] In some implementations, the third material is a conductive material.

[0086] In some implementations, the third material is the same as the first material.

[0087] In some implementations, the first layer is on the side surface of the corresponding landing structure, and the second layer fills the rest of the corresponding landing structure.

[0088] In some embodiments, the first layer comprises tungsten, the second layer comprises silicon nitride, and the corresponding conductive layer comprises tungsten.

[0089] In some embodiments, the first layer comprises tungsten, the second layer comprises polycrystalline silicon, and the corresponding conductive layer comprises tungsten.

[0090] In some embodiments, the first layer is on the side surface of the corresponding landing structure, the second layer is on the side surface of the first layer and the corresponding conductive layer, and the third layer fills the remainder of the corresponding landing structure.

[0091] In some embodiments, the first layer comprises tungsten, the second layer comprises silicon oxide, the third layer comprises tungsten, and the corresponding conductive layer comprises tungsten.

[0092] In some embodiments, each conductive layer comprises a first material.

[0093] According to another aspect of this disclosure, a memory system includes a 3D memory device comprising interleaved conductive and dielectric layers. The edges of the conductive and dielectric layers define multiple steps. The 3D memory device also includes multiple landing structures, each landing structure disposed on a corresponding conductive layer at a corresponding step. Each landing structure includes a first layer of a first material and a second layer of a second material. The first layer is on top of the second layer. The second material is different from the first material. The memory system may further include a memory controller coupled to the 3D memory device and configured to control the operation of the 3D memory device.

[0094] In some embodiments, the first material includes a conductive material, and the second material is different from the first material.

[0095] In some implementations, the first layer contacts a corresponding conductive layer and surrounds the second layer laterally and vertically.

[0096] In some implementations, the first layer is on the side surface of the corresponding landing structure; and the second layer fills the rest of the corresponding landing structure.

[0097] In some embodiments, the first layer comprises tungsten, the second layer comprises silicon nitride, and the corresponding conductive layer comprises tungsten.

[0098] In some embodiments, the first layer comprises tungsten, the second layer comprises polycrystalline silicon, and the corresponding conductive layer comprises tungsten.

[0099] In some other embodiments, each landing structure further includes a third layer surrounded by the second layer. The third layer comprises the material that served as the first layer.

[0100] In some implementations, the third layer fills the remainder of the corresponding landing structure.

[0101] In some embodiments, the first layer comprises tungsten, the second layer comprises silicon oxide, the third layer comprises tungsten, and the corresponding conductive layer comprises tungsten.

[0102] According to another aspect of this disclosure, a method for forming a 3D memory device includes the following operations: forming a stacked structure having interleaved sacrificial layers and dielectric layers. The edges of the sacrificial layers and dielectric layers define a plurality of steps. Forming sacrificial portions, each in contact with a corresponding sacrificial layer. Removing the sacrificial portions and sacrificial layers to form lateral recesses, each lateral recess having a first recess portion and a second recess portion above and in contact with the first recess portion. Depositing a first material into each lateral recess to fill the first recess portion and forming a first layer in the second recess portion. Depositing a second material into the second recess portion to form a second layer above the first layer in the second recess portion.

[0103] In some embodiments, depositing the first material includes depositing a conductive material to form a first layer on the side surface of the second recessed portion.

[0104] In some implementations, the deposition of the first material includes the deposition of tungsten.

[0105] In some embodiments, depositing a second material includes depositing a material different from the first material.

[0106] In some embodiments, the deposition of a second material includes the deposition of silicon oxide, silicon nitride, silicon oxynitride, polysilicon, or a combination thereof.

[0107] In some embodiments, the second material is deposited on top of and in contact with the first layer in the second recessed portion.

[0108] In some embodiments, a second material is deposited on top of the first layer and fills the second recessed portion.

[0109] In some embodiments, the method further includes depositing a third material into the second recessed portion to form a third layer on top of the second layer in the second recessed portion.

[0110] In some implementations, depositing a third material includes depositing a first material.

[0111] In some embodiments, a third material is deposited on top of the second layer and fills the second recessed portion.

[0112] In some embodiments, the method further includes: forming a gap structure in an interleaved sacrificial layer and dielectric layer; and performing an isotropic etching process to remove the sacrificial layer and sacrificial portion to form a lateral recess.

[0113] The foregoing description of the specific embodiments can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalent variations of the disclosed embodiments.

[0114] The breadth and scope of this disclosure should not be limited to any of the exemplary embodiments described above, but should be defined only by the appended claims and their equivalents.

Claims

1. A three-dimensional (3D) memory device, comprising: Interlaced conductive and dielectric layers, wherein the edges of the conductive and dielectric layers define multiple steps; and Multiple landing structures are provided, each disposed on a corresponding conductive layer at a corresponding step. Each landing structure includes a first layer of a first material and a second layer of a second material, wherein the first layer is on top of the second layer, and the second material is different from the first material. Wherein, the first material includes a conductive material, and The first layer is in contact with the corresponding conductive layer and surrounds the second layer laterally and vertically.

2. The three-dimensional memory device according to claim 1, wherein, The first material includes tungsten.

3. The three-dimensional memory device according to claim 1 or 2, wherein, The second material includes silicon oxide, silicon nitride, silicon oxynitride, polycrystalline silicon, or a combination thereof.

4. The three-dimensional memory device according to claim 1 or 2, wherein, Each landing structure also includes a third layer surrounded by the second layer, the third layer comprising a third material.

5. The three-dimensional memory device according to claim 4, wherein, The third material is a conductive material.

6. The three-dimensional memory device according to claim 4, wherein, The third material is the same as the first material.

7. The three-dimensional memory device according to claim 1, wherein... The first layer is on the side surface of the corresponding landing structure; and The second layer fills the remainder of the corresponding landing structure.

8. The three-dimensional memory device according to claim 7, wherein, The first layer comprises tungsten, the second layer comprises silicon nitride, and the respective conductive layer comprises tungsten.

9. The three-dimensional memory device according to claim 7, wherein, The first layer comprises tungsten, the second layer comprises polycrystalline silicon, and the respective conductive layer comprises tungsten.

10. The three-dimensional memory device according to claim 4, wherein The first layer is on the side surface of the corresponding landing structure; The second layer is on the side surface of the first layer and the corresponding conductive layer; and The third layer fills the remainder of the corresponding landing structure.

11. The three-dimensional memory device according to claim 10, wherein, The first layer comprises tungsten, the second layer comprises silicon oxide, the third layer comprises tungsten, and the respective conductive layer comprises tungsten.

12. The three-dimensional memory device according to claim 1 or 2, wherein, Each of the conductive layers comprises the first material.

13. A memory system, comprising: Three-dimensional (3D) memory devices, including: Interlaced conductive and dielectric layers, wherein the edges of the conductive and dielectric layers define multiple steps; and Multiple landing structures are provided, each disposed on a corresponding conductive layer at a corresponding step. Each landing structure includes a first layer of a first material and a second layer of a second material, the first layer being on top of the second layer. The second material is different from the first material. The first material includes a conductive material. The first layer is in contact with the corresponding conductive layer and surrounds the second layer laterally and vertically. A memory controller coupled to the three-dimensional memory device and configured to control the operation of the three-dimensional memory device.

14. The memory system of claim 13, wherein The first layer is on the side surface of the corresponding landing structure; and The second layer fills the remainder of the corresponding landing structure.

15. The memory system according to claim 14, wherein, The first layer comprises tungsten, the second layer comprises silicon nitride, and the respective conductive layer comprises tungsten.

16. The memory system of claim 14, wherein, The first layer comprises tungsten, the second layer comprises polycrystalline silicon, and the respective conductive layer comprises tungsten.

17. The memory system according to claim 13, wherein, Each landing structure also includes a third layer surrounded by the second layer, the third layer comprising the material that forms part of the first layer.

18. The memory system according to claim 17, wherein, The third layer fills the remaining portion of the corresponding landing structure.

19. The memory system according to claim 17 or 18, wherein, The first layer comprises tungsten, the second layer comprises silicon oxide, the third layer comprises tungsten, and the respective conductive layer comprises tungsten.

20. A method for forming a three-dimensional (3D) memory device, comprising: A stacked structure comprising staggered sacrificial layers and dielectric layers is formed, wherein the edges of the sacrificial layers and the dielectric layers define multiple steps; Each part forms a sacrificial portion that comes into contact with its corresponding sacrificial layer; Remove the sacrificial portion and the sacrificial layer to form a lateral recess, each lateral recess including a first recess portion and a second recess portion above and in contact with the first recess portion; A first material is deposited into each of the lateral recesses to fill the first recess portion, and a first layer is formed in the second recess portion; and A second material is deposited into the second recessed portion to form a second layer on top of the first layer in the second recessed portion. The deposition of the first material includes depositing a conductive material to form the first layer on the side surface of the second recessed portion, and The deposition of the second material includes the deposition of a material different from the first material.

21. The method according to claim 20, wherein, The deposition of the first material includes the deposition of tungsten.

22. The method according to claim 20 or 21, wherein, Depositing the second material includes depositing silicon oxide, silicon nitride, silicon oxynitride, polycrystalline silicon, or a combination thereof.

23. The method according to claim 20 or 21, wherein, The second material is deposited on top of and in contact with the first layer in the second recessed portion.

24. The method according to claim 20 or 21, wherein, The second material is deposited on top of the first layer and fills the second recessed portion.

25. The method of claim 20 or 21, further comprising depositing a third material into the second recessed portion to form a third layer over the second layer in the second recessed portion.

26. The method of claim 25, wherein, Depositing the third material includes depositing the same material as the first material.

27. The method according to claim 25 or 26, wherein, The third material is deposited on the second layer and fills the second recessed portion.

28. The method of claim 20 or 21, further comprising: A gap structure is formed in the interlaced sacrificial layer and the dielectric layer; and An isotropic etching process is performed to remove the sacrificial layer and the sacrificial portion to form the lateral recess.

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