A PCIE interface correctness testing method

Abstract

The present invention discloses a PCIE interface correctness test method, comprising the following steps: S1, before sending data, Party A fills the sending buffer and fills the message descriptor; S2, Party A starts to send data to Party B; S3, Party B waits to receive data; S4, Party A waits to receive data sent by Party B, and after receiving the data sent by Party B, performs data correctness verification; S7, returns to S1, until all the cloth number modes, operation types, message lengths and message offset tests are traversed and completed. The present invention improves the coverage and test intensity of the PCIE interface correctness test.

Description

Technical Field

[0001] The invention relates to a PCIE interface correctness testing method, belonging to the technical field of high-speed interconnection networks. Background Art

[0002] The PCIE interface is a system interface that connects peripherals to the processor, providing a unified data transmission interface for the host and peripherals. Its link stability and data transmission correctness are related to the stability of the entire system. Due to its protocol complexity and high transmission rate, comprehensive verification of the PCIE interface faces great difficulties.

[0003] The PCIE interface can only be verified at the message layer by sending and receiving messages and performing data verification on the received messages. The PCIE interface uses DMA to access memory. The Max_Payload_Size is defined in the device control register of its PCIE capability structure, which indicates the maximum TLP packet size of the PCIE interface. The large data packet sent from the upper layer will be split into small data packets of the Max_Payload_Size length. At the same time, the PCIE interface allows the DMA operation start address to be out of bounds within the cache line. Therefore, in order to fully verify DMA reading and writing, it is necessary to traverse and test various message lengths and offsets within various cache lines to ensure the correctness of the PCIE interface. The existing mainstream processor manufacturers' test technology for PCIE interface correctness verification is not comprehensive enough, and the pertinence and functional coverage are not strong. Summary of the invention

[0004] The object of the present invention is to provide a PCIE interface correctness test method, which improves the PCIE interface correctness test coverage and test intensity.

[0005] To achieve the above object, the technical solution adopted by the present invention is: to provide a PCIE interface correctness testing method, comprising the following steps:

[0006] S1. Party A performs the following operations before sending data:

[0007] The sending buffer is filled by using the following methods: sequential filling circular right shift, fixed value, and jump filling circular right shift;

[0008] Fill in the message descriptor and assign the message operation type field to Send / Recv, Rdma Write, and Rdma Read operation types respectively;

[0009] Fill the message descriptor with different byte sizes for the message length field and different offsets from the cache line for the data start address field. The offset within the cache line ranges from 0 to (cache line size – 1) bytes.

[0010] S2. Party A starts sending data to Party B:

[0011] For the Send / Recv operation type, Party A posts a Send / Recv request to send data;

[0012] For Rdma Write and Rdma Read operation types, Party A submits an RDMA Write or Rdma Read request to start sending data;

[0013] When the data is sent, Party A sends a notification message to Party B to notify that the sending is complete;

[0014] S3, Party B waits to receive data:

[0015] For the Send / Recv operation type, after receiving the data sent by Party A, Party B performs a data correctness check. After the check is completed, Party B fills the send buffer according to the distribution method described in S1 and sends a send request to Party A to send the data;

[0016] For the Rdma Write and Rdma Read operation types, after receiving the notification message from Party A, Party B performs a data correctness check, then allocates the send buffer according to the allocation method described in S1, and delivers an RDMAWrite or Rdma Read request to start sending data to Party A. When the sending is completed, a notification is also sent to Party A.

[0017] S4, Party A waits to receive data sent by Party B, and after receiving the data sent by Party B, performs data correctness verification;

[0018] S7. Return to S1 until all the numbering modes, operation types, message lengths, and message offset tests are traversed.

[0019] The further improved scheme in the above technical scheme is as follows:

[0020] 1. In the above scheme, in the numbering stage in S1, the following three methods are used to count:

[0021] When the sending data buffer is numbered, the method of filling in order and shifting right cyclically is adopted. The specific process is as follows: fill the numbers 0, 1, 2, ..., 255 into the sending buffer in order, and shift the data position right by one position each time iterates;

[0022] When the send data buffer is numbered, a fixed value numbering method is used. The specific process is as follows: In any iteration, a fixed value is filled for each buffer position;

[0023] When the sending data buffer is numbered, the jump filling and circular right shifting method is adopted. The specific process is as follows: the numbers 0, 1, 2, ..., 255 are filled into the sending buffer at a certain step interval. Each time it is iterated, the data position is shifted right by one place.

[0024] 2. In the above scheme, during the filling phase of the message length field in S1, the message length is selected in the following manner:

[0025] When the message length ranges from 1 byte to 1K bytes, each message length is traversed;

[0026] When the message length is greater than 1KB, the message length is increased by a fixed value each time it is tested, such as 9999 bytes each time.

[0027] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art:

[0028] The present invention discloses a method for verifying the correctness of a PCIE interface. The method comprises the following steps: transmitting messages of various types and lengths between a processor and a peripheral device, and performing data verification on the received messages during the data transmission and reception process to determine the correctness of a PCIE DMA operation. In addition, in each test, the address offset and the number distribution method of the message are different to improve the coverage and strength of the PCIE interface correctness test. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Attached Figure 1 It is a schematic diagram of the cloth number method of filling in sequence and shifting right cyclically;

[0030] Attached Figure 2 It is a schematic diagram of the cloth number method of jump filling and circular right shift;

[0031] Attached Figure 3 It is a flow chart of verification using Send / Recv operation in the present invention;

[0032] Attached Figure 4 It is a schematic diagram of the process of using RDMA Write operation for verification in the present invention;

[0033] Attached Figure 5 The figure is a flow chart of verification using RDMA Read operation in the present invention. DETAILED DESCRIPTION

[0034] Embodiment: The present invention provides a PCIE interface correctness testing method, which specifically includes the following steps:

[0035] S1. Party A performs the following operations before sending data:

[0036] The sending buffer is filled by using the following methods: sequential filling circular right shift, fixed value, and jump filling circular right shift;

[0037] Fill in the message descriptor and assign the message operation type field to Send / Recv, Rdma Write, and Rdma Read operation types respectively;

[0038] Fill the message descriptor with different byte sizes for the message length field and different offsets from the cache line for the data start address field. The offset within the cache line ranges from 0 to (cache line size – 1) bytes.

[0039] S2. Party A starts sending data to Party B:

[0040] For the Send / Recv operation type, Party A posts a Send / Recv request to send data;

[0041] For Rdma Write and Rdma Read operation types, Party A submits an RDMA Write or Rdma Read request to start sending data;

[0042] When the data is sent, Party A sends a notification message to Party B to notify that the sending is complete;

[0043] S3, Party B waits to receive data:

[0044] For the Send / Recv operation type, after receiving the data sent by Party A, Party B performs a data correctness check. After the check is completed, Party B fills the send buffer according to the distribution method described in S1 and sends a send request to Party A to send the data;

[0045] For the Rdma Write and Rdma Read operation types, after receiving the notification message from Party A, it means that the data has been sent. Party B checks the data correctness, and then counts the sending buffer according to the counting method described in S1, and sends an RDMA Write or Rdma Read request to start sending data to Party A. When the sending is completed, a notification is also sent to Party A.

[0046] S4, Party A waits to receive data sent by Party B, and after receiving the data sent by Party B, performs data correctness verification;

[0047] S7, return to S1, and the process continues until all the layout modes, operation types, message lengths and message offset tests are traversed.

[0048] In the cloth counting stage in S1, the cloth counting is performed in the following three ways:

[0049] When the sending data buffer is numbered, you can choose to use the method of filling in sequence and circular right shifting. The specific process is as follows: fill the numbers 0, 1, 2, ..., 255 into the sending buffer in sequence, and each time iterates, the data position is shifted right by one position;

[0050] When counting the send data buffer, you can choose to use a fixed value counting method. The specific process is as follows: in any iteration, fill each buffer position with a fixed value;

[0051] When counting the send data buffer, you can choose to use the jump fill and circular right shift counting method. The specific process is as follows: fill the numbers 0, 1, 2,..., 255 into the send buffer at a certain step interval. Each time iterates, the data position is shifted right by one place.

[0052] During the message length field filling phase in S1, the message length is selected in the following manner:

[0053] When the message length ranges from 1 byte to 1K bytes, each message length is traversed;

[0054] When the message length is greater than 1KB, the message length is increased by a fixed value each time it is tested, such as 9999 bytes each time.

[0055] The above embodiment is further explained as follows:

[0056] 1. Traverse and test various message lengths and offsets within cache lines

[0057] Test message lengths range from 1 byte to 1K bytes, and offsets within cache lines range from 0 to (cache line size – 1) bytes, with every combination tested thoroughly.

[0058] In order to increase the randomness of the test, the transmission of large messages on the PCIE interface was tested. In one test, the message length was selected in the following way:

[0059] (1) When the message length ranges from 1 byte to 1K bytes, each message length is traversed;

[0060] (2) When the message length is greater than 1KB, the message length is increased by a fixed value each time the test is performed, such as 9999 bytes each time.

[0061] 2. Use multiple distribution methods to fully cover DMA operations

[0062] Before sending data, the sending buffer must be counted first; after receiving the data, the correctness of the data must be verified.

[0063] The following cloth counting methods were used in turn:

[0064] (1) The method of filling in order and shifting right in a loop: fill the numbers 0, 1, 2, ..., 255 into the sending buffer in order. Each time iterates, the data position is shifted right by one position. When the test message length is 14B and the starting address offset is 4B, the data filling in the first 4 iterations is as follows: Figure 1 shown.

[0065] (2) Fixed value distribution method: In any iteration, each buffer position is filled with a fixed value, such as 0xf, 0xff, etc.

[0066] (3) Jump filling and circular right shift algorithm: Fill the numbers 0, 1, 2, ..., 255 into the send buffer at a certain step interval. Each time iterates, the data position is shifted right by one position. When the test message length is 14B and the starting address offset is 4B, the data filling in the first 4 iterations is as follows: Figure 2 shown.

[0067] 3. Use multiple operation types to improve test intensity

[0068] A method to comprehensively verify the PCIE interface and improve the test intensity by using various operations such as Send / Recv, Rdma Write, and Rdma Read.

[0069] (1) Use Send / Recv operation for verification, as follows Figure 3 As shown, a "ping-pong" method is used to send and receive data.

[0070] Party A first fills the send buffer according to the cloth number algorithm, and then delivers the send request to send data;

[0071] After receiving the data from Party A, Party B verifies the correctness of the data;

[0072] Then, Party B fills the send buffer according to the cloth number algorithm and delivers the send request to send the data;

[0073] After receiving the data sent by Party B, Party A also performs data verification;

[0074] The process continues.

[0075] (2) Use RDMA Write operation for verification, as follows Figure 4 As shown in the figure, there is an obvious difference in semantics between the RDMA Write operation and the Send / Recv operation, that is, the data receiver does not need to participate in the data transmission process, so it cannot know when the data transmission ends. For this reason, a notification message is added during the test process.

[0076] First, Party A fills the send buffer with data according to the cloth number algorithm, and then sends an RDMA Write request to start data transmission;

[0077] When the data transmission is completed, Party A sends a notification to Party B;

[0078] When Party B receives the notification, it means that the data has been transmitted;

[0079] Party B first verifies the data, then counts the send buffer according to the count algorithm, and submits an RDMA Write request to start sending data.

[0080] When the sending is completed, a notification is also sent;

[0081] This process continues.

[0082] (3) Use RDMA Read operation for verification, as follows Figure 5 As shown in the figure, the semantic difference between the RDMA Read operation and the Send / Recv operation is that the RDMA Read operation does not require the participation of the data sender during the data transmission process. For this reason, a notification message is also added during the test process.

[0083] First, Party A fills the sending buffer with data according to the cloth number algorithm, and then sends a notification to Party B;

[0084] After receiving the notification, Party B can transmit data through the RDMA Read operation and verify the received data;

[0085] Then, Party B counts the sending buffer according to the counting algorithm and sends a notification to Party A;

[0086] After receiving the notification, party A also starts sending data and performing data verification through the RDMA Read operation;

[0087] This process continues.

[0088] When the above-mentioned PCIE interface correctness test method is adopted, it transmits messages of various types and lengths between the processor and the peripherals, and performs data verification on the received messages during the data transmission and reception process to determine the correctness of the PCIE DMA operation. In addition, in each test, the address offset and the number distribution method of the message are different to improve the coverage and test intensity of the PCIE interface correctness test.

[0089] In order to facilitate a better understanding of the present invention, the terms used in this article are briefly explained below:

[0090] PCIE (PCI Express): A high-speed serial computer expansion bus standard that connects peripherals to the processor, allowing high-bandwidth communication between devices and the motherboard.

[0091] DMA (Direct Memory Access): Direct memory access enables batch data exchange between high-speed peripherals and main memory, reducing input / output operations involving CPU intervention.

[0092] Cache Line: Cache is a high-speed cache memory located between the CPU and the main memory. Cache is composed of many cache lines. Cache line is the smallest unit for exchanging data between cache and RAM.

[0093] DC (Direct Current) balance: DC balance of signals during communication.

[0094] Remote Direct Memory Access (RDMA): A method of directly accessing the memory of a remote system without the involvement of the remote CPU.

[0095] RDMA Write: A type of operation in RDMA technology where the sender can directly write data to the main memory of the remote system.

[0096] RDMA Read: A type of operation in RDMA technology where the sender can read data directly from the remote party's main memory.

[0097] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A PCIE interface correctness testing method, characterized in that: The following steps are involved: S1. Party A performs the following operations before sending data: The sending buffer is filled by using the following methods: sequential filling circular right shift, fixed value, and jump filling circular right shift; Fill in the message descriptor and assign the message operation type field to the Send / Recv, Rdma Write, and RdmaRead operation types respectively; Fill the message descriptor with different byte sizes for the message length field and different offsets from the cache line for the data start address field. The offset within the cache line ranges from 0 to (cache line size – 1) bytes. S2. Party A starts sending data to Party B: For the Send / Recv operation type, Party A posts a Send / Recv request to send data; For Rdma Write and Rdma Read operation types, Party A submits an RDMA Write or Rdma Read request to start sending data; When the data is sent, Party A sends a notification message to Party B to notify that the sending is complete; S3, Party B waits to receive data: For the Send / Recv operation type, after receiving the data sent by Party A, Party B performs a data correctness check. After the check is completed, Party B fills the send buffer according to the distribution method described in S1 and sends a send request to Party A to send the data; For the Rdma Write and Rdma Read operation types, after receiving the notification message from Party A, Party B performs a data correctness check, then allocates the send buffer according to the allocation method described in S1, and delivers an RDMA Write or Rdma Read request to start sending data to Party A. When the sending is completed, a notification is also sent to Party A. S4, Party A waits to receive data sent by Party B, and after receiving the data sent by Party B, performs data correctness verification; S7, return to S1, until all the numbering modes, operation types, message lengths and message offset tests are completed; In the cloth counting stage in S1, the cloth counting is performed in the following three ways: When the sending data buffer is numbered, the method of filling in order and shifting right cyclically is adopted. The specific process is as follows: fill the numbers 0, 1, 2, ..., 255 into the sending buffer in order, and shift the data position right by one position each time iterates; When the send data buffer is numbered, a fixed value numbering method is used. The specific process is as follows: In any iteration, a fixed value is filled for each buffer position; When the sending data buffer is numbered, the jump filling and circular right shifting method is adopted. The specific process is as follows: the numbers 0, 1, 2, ..., 255 are filled into the sending buffer at a certain step interval. Each time it is iterated, the data position is shifted right by one place.

2. A PCIE interface correctness testing method according to claim 1, characterized in that: During the message length field filling phase in S1, the message length is selected in the following manner: When the message length ranges from 1 byte to 1K bytes, each message length is traversed; When the message length is greater than 1KB, the message length is increased by a fixed value each time it is tested, such as 9999 bytes each time.

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