Lightweight Parallel Test Case Generation Method for Heterogeneous Many-Core Processors

Abstract

The present invention discloses a lightweight parallel test case generation method for a heterogeneous multi-core processor, which includes the following steps: constructing a configuration file; using a configuration analyzer module to analyze the constructed configuration file, converting the configuration information in the configuration file into a format (which is a dictionary) recognizable by a code generator module, and adding the configuration file name and the test case name; the code generator module generates a heterogeneous parallel test case project; inputting multiple groups of configuration information into the code generator module, obtaining multiple groups of heterogeneous parallel test case projects, and performing mixed compilation to obtain a parallel test case program. The heterogeneous parallel test cases generated by the present invention have the advantages of high speed and high efficiency in the pre-silicon verification of domestic heterogeneous multi-core processors.

Description

Technical Field

[0001] The present invention relates to a lightweight parallel test case generation method for heterogeneous multi-core processors, and belongs to the field of functional correctness verification of heterogeneous multi-core processors. Background Art

[0002] Parallel patterns can provide programmers with a series of parallel programming solutions, and their patterns are usually organized into a hierarchical structure so that users can design complex systems through a set of patterns. Parallel patterns have been applied in many fields, including synthetic benchmark generation, dynamic task mapping and compiler optimization, parallel application development, and selection of the best architecture. The commonly used parallel patterns are three patterns based on tasks, data, and data flow. With the development of multi-core and heterogeneous multi-core processors, parallel test case generation technology has led to the rise of related research in the field of processor verification.

[0003] Due to the complexity of their algorithms, the programs in application topics and Benchmarks generally take a long time to test in the pre-silicon simulation environment, and it is very difficult to locate errors. However, in order to cover the application scenarios of the chip as early as possible, lightweight test cases need to be written for correctness verification.

[0004] MINIME-Validator is a generator that generates comprehensive parallel test cases through a parallel pattern markup language (PPML). Its advantage is that it uses a custom language (PPML) to generate parallel test cases and can specify the methods executed by different threads. Write a ppml file according to the test needs to generate parallel test cases; its disadvantages are also very obvious. It can only generate parallel test cases suitable for multi-core processors and does not consider mapping the workload to heterogeneous multi-core processors.

[0005] In the operating environment of heterogeneous multi-core processors, processes or threads within the same processor can build a parent-child relationship. However, when the program runs in an environment of two or more heterogeneous multi-core processors, a direct parent-child relationship cannot be built between different processors, making the test cases generated by MINIME-Validator unable to run in an environment of two or more heterogeneous multi-core processors. Moreover, communication between different processors or different processes can only use communication interfaces, such as MPI, etc. MINIME-Validator does not support message interfaces and cannot add common interfaces or common algorithms to the thread execution methods. Summary of the Invention

[0006] The purpose of the present invention is to provide a lightweight parallel test case generation method for heterogeneous multi-core processors, and the generated heterogeneous parallel test cases have the advantages of fast speed and high efficiency in the pre-silicon verification of domestic heterogeneous multi-core processors.

[0007] To achieve the above object, the technical solution adopted by the present invention is: to provide a lightweight parallel test case generation method for a heterogeneous multi-core processor, based on the following configurations:

[0008] A configuration analyzer module for analyzing a configuration file and converting the configuration file into a format directly usable by a code generator;

[0009] The configurations that can be read from the configuration file include: the process parallel mode, the computing array parallel mode, the data type, the data block size, the storage space size used, the process execution method, and the computing array execution method of the parallel test case; wherein, the execution method is a classical algorithm or a common function interface;

[0010] A code generator module for generating a parallel test case program, specifically:

[0011] Generate a heterogeneous parallel test case project file, including a test case control core common library, a computing core array common library, a makefile file, control core source code, computing core source code, and common header files;

[0012] According to the configuration information in a certain format read by the configuration analyzer module from the configuration file, generate corresponding control core source code and computing core source code for the test case, and add them to the test case project to generate a heterogeneous parallel test case program;

[0013] The method includes the following steps:

[0014] S1. Construct a configuration file to configure the process parallel mode, the computing array parallel mode, the data type, the data block size, the storage space size used, the process execution method, and the computing array execution method of the parallel test case;

[0015] S2. Use the configuration analyzer module to analyze the configuration file constructed in S1, convert the configuration information in the configuration file into a format recognizable by the code generator module, and add the configuration file name and the test case name;

[0016] S3. The code generator module generates a heterogeneous parallel test case project, including a test case control core common library, a computing core common library, and a makefile file, wherein the common library part includes a control core synchronization interface, a computing core array synchronization interface, a full core synchronization interface, a computing core communication interface, and a computing core access memory interface;

[0017] S4. Input the configuration information obtained in S2 into the code generator module, generate control core source code according to the control core parallel mode and the control core execution method, and add it to the test case project;

[0018] S5. Input the configuration information obtained in S2 into the code generator module, generate the source code of the computing core according to the parallel mode of the computing core and the execution method of the computing core, and add it to the test case project;

[0019] S6. Input the configuration information obtained in S2 into the code generator module, generate a common header file containing data information, and add it to the test case project;

[0020] S7. Input multiple groups of configuration information into the code generator module, obtain multiple groups of heterogeneous parallel test case projects according to the steps from S3 to S6, and perform hybrid compilation to obtain a heterogeneous parallel test case program.

[0021] The further improved solutions in the above technical solutions are as follows:

[0022] 1. In the above solution, according to one or more groups of configuration information specified in the configuration file, generate one or more parallel mode test cases, where the configuration information consists of process parallel mode, computing array parallel mode, data type, data block size, storage space size used, process execution method, and computing array execution method.

[0023] Due to the application of the above technical solutions, the present invention has the following advantages compared with the prior art:

[0024] The present invention discloses a method for generating parallel test cases capable of mapping workloads to heterogeneous many-core processors, which can specify different parallel modes at the control core (process level) and the computing core array, generate rich heterogeneous parallel test cases through combination, and the generated heterogeneous parallel test cases have the advantages of high speed and high efficiency in the pre-silicon verification of domestic heterogeneous many-core processors. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Attached Figure 1 is a schematic flow chart of the method for generating parallel test cases of the present invention;

[0026] Attached Figure 2 is a supplementary description of the configuration information of the present invention;

[0027] Attached Figure 3 is a schematic diagram of the mapping relationship between the configuration information of the present invention and the code blocks in the source code of the test case project. DETAILED DESCRIPTION OF THE INVENTION

[0028] Embodiment: The present invention provides a lightweight method for generating parallel test cases for heterogeneous many-core processors, based on the following configuration:

[0029] A configuration analyzer module for analyzing the configuration file and converting the configuration file into a format that can be directly used by the code generator;

[0030] Configurations that can be read from the configuration file include: the process parallel mode of parallel test cases, the computing array parallel mode, data types, data block sizes, the amount of storage space used, the process execution method, and the computing array execution method; among them, the execution method is a classical algorithm or a common function interface;

[0031] The code generator module is used to generate a parallel test case program, specifically:

[0032] Generate a heterogeneous parallel test case project file, including a test case control core common library, a computing core array common library, a makefile, control core source code, computing core source code, and common header files;

[0033] According to the configuration information in a certain format read by the configuration analyzer module from the configuration file, generate the corresponding control core source code and computing core source code for the test case, and add them to the test case project to generate a heterogeneous parallel test case program;

[0034] The method includes the following steps:

[0035] S1. Construct a configuration file, configure the process parallel mode of parallel test cases, the computing array parallel mode, data types, data block sizes, the amount of storage space used, the process execution method, and the computing array execution method. Multiple configurations can be written in the configuration file;

[0036] S2. Use the configuration analyzer module to analyze the configuration file constructed in S1, convert the configuration information in the configuration file into a format (this format is a dictionary) that the code generator module can recognize, and add the configuration file name and the test case name;

[0037] S3. The code generator module generates a heterogeneous parallel test case project, including a test case control core common library, a computing core common library, and a makefile. Among them, the common library part includes a control core synchronization interface, a computing core array synchronization interface, a full core synchronization interface, a computing core communication interface, and a computing core access memory interface. These common library interfaces play a basic supporting role in the test case;

[0038] S4. Input the configuration information obtained in S2 into the code generator module, generate the control core source code according to the control core parallel mode and the control core execution method, and add it to the test case project;

[0039] S5. Input the configuration information obtained in S2 into the code generator module, generate the computing core source code according to the computing core parallel mode and the computing core execution method, and add it to the test case project;

[0040] S6. Input the configuration information obtained in S2 into the code generator module to generate a common header file containing data information and add it to the test case project;

[0041] S7. Input multiple groups of configuration information into the code generator module, obtain multiple heterogeneous parallel test case projects according to the steps from S3 to S6, and perform hybrid compilation to obtain a heterogeneous parallel test case program.

[0042] Generate one or more parallel mode test cases according to one or more groups of configuration information specified in the configuration file, where the configuration information consists of process parallel mode, computing array parallel mode, data type, data block size, storage space size used, process execution method, and computing array execution method.

[0043] The further explanation of the above embodiments is as follows:

[0044] The full name of the present invention is Parallel Mode Generation (hereinafter referred to as PMGen);

[0045] PMGen uses the JSON format as the configuration file and can generate multiple different test cases using a single configuration file;

[0046] PMGen uses MPI as the method for inter-process communication, and at the same time applies the communication method between computing cores and the method for computing cores to access the memory, and different parallel modes and execution methods can be configured at the process level and the computing core array level; the execution method can be various classic algorithms or transplanted interfaces, etc.

[0047] PMGen can not only generate parallel mode test cases running in a heterogeneous many-core processor environment, but also support running in an environment with any number of processes when the storage space permits.

[0048] The present invention customizes a heterogeneous parallel mode markup language to represent the characteristics of heterogeneous parallel applications, and uses a configuration analyzer and a code generator to generate heterogeneous parallel test cases. The parallel modes at the process level (control core level) used are divided into four modes: task parallel, recursive data, pipeline, and process independent, and the parallel modes of the computing core array used are divided into three modes: divide and conquer, recursive data, and pipeline independent.

[0049] The information that can also be configured in the configuration file includes: data type, data block size, storage space size used, process execution method, and computing array execution method; among them, the execution method can be various classic algorithms or common function interfaces.

[0050] According to the architecture of heterogeneous many-core processors, the parallel mode markup language needs to mark the levels of parallelism: the first-level parallelism is mapped to the control core, and the second-level parallelism is mapped to the computing core; the parallel mode markup language also needs to mark the parallel mode, thread number, task size, private data size, shared data size, and core function; in addition, in the pipeline parallel mode, it is also necessary to specify the pipeline stage and the number of times the thread reads data from the previous stage.

[0051] The present invention is mainly divided into three parts, and the specific details are as follows:

[0052] 1. Construct a configuration file and configure one or more groups of configuration information, where one group of configuration information includes process parallel mode, computing array parallel mode, data type, data block size, storage space size used, process execution method, and computing array execution method;

[0053] 2. Use the configuration analyzer module to analyze the configuration file, read out one or more groups of configuration information in the configuration file, and convert it into a format that can be used by the code generator;

[0054] 3. Use the code generator module, take one or more groups of configuration information obtained in step 2 as input, and generate heterogeneous parallel test cases that are the same as the configuration information in the configuration file.

[0055] When adopting the above lightweight parallel test case generation method for heterogeneous many-core processors, it can set a certain parallel mode, including task parallelism and data parallelism, etc., for the process level (control core level) and the computing core array level respectively according to different configuration files, so as to generate heterogeneous parallel test cases with multiple parallel modes, which has the advantages of high speed and high efficiency in the pre-silicon verification of domestic many-core processors.

[0056] To facilitate a better understanding of the present invention, the terms used in this article will be briefly explained below:

[0057] Heterogeneous many-core processor: A processor composed of a control core and a computing core array.

[0058] Control core: The core responsible for communication, starting the computing core array, and computing tasks.

[0059] Computing core array: An array composed of multiple computing cores, and each computing core can execute computing tasks.

[0060] Benchmark: That is, benchmark testing, which refers to realizing quantitative and comparable testing of a certain performance index of a class of test objects by designing scientific testing methods, testing tools, and testing systems.

[0061] Multi-threading: Refers to the technology of realizing concurrent execution of multiple threads from software or hardware.

[0062] Task parallelism: In the case of the process level, the model distributes tasks to all processes.

[0063] Pipeline: In the case of the process level and the computing core array level, each set of data passes through each process, and each set of data passes through each core and executes the method.

[0064] Recursive data: In the present invention, the model adopts the method of a complete binary tree. In the case of the process level and the computing core array level, it is regarded as a binary tree, decomposes the data to the leaf nodes for calculation, and performs reduction calculation when returning to the root node.

[0065] Divide-and-conquer method: In the present invention, the model divides the data into multiple sub-data and sends them to other processes or computing cores, that is, divides a complex algorithm problem into many parallel sub-problems according to a certain "decomposition" method, each sub-problem is solved separately, and the solutions of each sub-problem are combined into the solution of the whole problem.

[0066] The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose is to enable those who are familiar with this technology to understand the content of the present invention and implement it accordingly, and cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit and essence of the present invention should be covered within the protection scope of the present invention.

Claims

1. A lightweight parallel test case generation method for heterogeneous multi-core processors, characterized in that, based on the following configurations: A configuration analyzer module for analyzing a configuration file and converting the configuration file into a format directly usable by a code generator; The configurations read from the configuration file include: the process parallel mode, the computing array parallel mode, the data type, the data block size, the storage space size used, the process execution method, and the computing array execution method of the parallel test case; wherein, the execution method is a classical algorithm or a common function interface; A code generator module for generating a parallel test case program, specifically: Generating a heterogeneous parallel test case project file, including a test case control core common library, a computing core array common library, a makefile file, control core source code, computing core source code, and common header files; According to the configuration information read from the configuration file by the configuration analyzer module, generating corresponding control core source code and computing core source code for the test case, and adding them to the test case project to generate a heterogeneous parallel test case program; The method includes the following steps: S1. Construct a configuration file to configure the process parallel mode, the computing array parallel mode, the data type, the data block size, the storage space size used, the process execution method, and the computing array execution method of the parallel test case; S2. Use the configuration analyzer module to analyze the configuration file constructed in S1, convert the configuration information in the configuration file into a format recognizable by the code generator module, and add the configuration file name and the test case name; S3. The code generator module generates a heterogeneous parallel test case project, including a test case control core common library, a computing core common library, and a makefile file, wherein the common library part includes a control core synchronization interface, a computing core array synchronization interface, a full-core synchronization interface, a computing core communication interface, and a computing core access memory interface; S4. Input the configuration information obtained in S2 into the code generator module, generate control core source code according to the control core parallel mode and the control core execution method, and add it to the test case project; S5. Input the configuration information obtained in S2 into the code generator module, generate computing core source code according to the computing core parallel mode and the computing core execution method, and add it to the test case project; S6. Input the configuration information obtained in S2 into the code generator module, generate a common header file containing data information, and add it to the test case project; S7. Input multiple groups of configuration information into the code generator module, obtain multiple groups of heterogeneous parallel test case projects according to the steps from S3 to S6, and perform mixed compilation to obtain a heterogeneous parallel test case program.

2. The lightweight parallel test case generation method for heterogeneous multi-core processors according to claim 1, characterized in that: According to one or more groups of configuration information specified in the configuration file, generate one or more parallel mode test cases, wherein the configuration information consists of a process parallel mode, a computing array parallel mode, a data type, a data block size, a storage space size used, a process execution method, and a computing array execution method.

Images