On-chip storage space dynamic configuration method

Abstract

The present invention discloses a method for dynamically configuring on-chip storage space, comprising the following steps: S1, reading input parameters; S2, reading hardware LDM configuration registers; S3, obtaining the size of computing core stack space and the stack pointer of the computing core; S4, comparing new_cache_size and old_cache_size; S5, transferring the computing core stack space to the newly allocated local storage space; S6, confirming that all DMA operations related to the computing core have been completed; S7, refreshing the computing core Cache; S8, comparing new_cache_size and old_cache_size; S9, releasing mem_a space, and transferring to S11 for execution. The present invention can avoid performance loss caused by insufficient LDM or Cache capacity under fixed configuration, and maximize its performance advantage.

Description

Technical Field

[0001] The invention relates to an on-chip storage space dynamic configuration method, belonging to the technical field of Cache space configuration. Background Art

[0002] In the many-core processor architecture, the control core is mainly responsible for control and task distribution and scheduling, while the computing core is mainly responsible for computing acceleration tasks. A small number of control cores and a large number of computing cores are a classic structure in the many-core processor architecture. The performance overhead of computing cores directly accessing the main memory is too high, so they are generally equipped with multiple levels of storage hierarchy. The use of main memory and on-chip memory is one of the typical configurations. Under this configuration, each computing core has a high-speed local data storage space, which can be configured as a conventional on-chip local data memory (LDM) completely managed by software, or partially configured as a data cache automatically managed by hardware. The capacity allocation of the two management methods is adjustable in stages. For different application scenarios, the functions of cache and LDM have their own advantages and disadvantages. The traditional method is to configure the capacity of cache and LDM when the program starts.

[0003] When the local local data storage space of the computing core in the many-core processor architecture is configured as a software-managed LDM, the computing core can access it by accessing the load / store method of the LDM space, or by initiating asynchronous DMA to realize batch data exchange between the LDM and the outside world (main memory or LDM of other computing cores). Under this usage mode, it is generally required that the amount of data accessed by DMA is relatively large, the continuity is good, and the memory access operation performance of the LDM space is relatively high; when part of the space is configured as data cache, the computing core can access the space by accessing the load / store method of the main memory space. This access method has no requirements for the continuity and amount of accessed data, and is more flexible in usage, but the performance of the memory access operation of the main memory is relatively poor. At the same time, because the many-core processor has a large number of computing cores, it is difficult to ensure cache consistency through hardware, and software is required to ensure cache consistency between the control core and the computing core, and between the computing cores.

[0004] With the development of many-core processors, the use of software-managed local data storage space has become more mature, but there is no unified specification for the use of cache in many computing cores. For the LDM / Cache configuration method, the traditional method is to configure the cache and LDM capacity when the program starts. However, because LDM and Cache are used differently, their application scenarios and requirements for program features are also different. The total capacity of the local local data storage space of the computing core is unchanged. The fixed LDM / Cache configuration makes it impossible to effectively use the space of the other item to improve the performance of the program when the space of one item is insufficient. Summary of the invention

[0005] The purpose of the present invention is to provide a method for dynamically configuring on-chip storage space, which can avoid performance loss caused by insufficient LDM or Cache capacity under fixed configuration and maximize its performance advantage.

[0006] To achieve the above object, the technical solution adopted by the present invention is: to provide a method for dynamically configuring on-chip storage space, comprising the following steps:

[0007] S1. Read the input parameter and determine whether the input parameter is a capacity size supported by the hardware according to the supported cache capacity configuration size provided by the hardware. If so, proceed to the next step and record the input parameter as new_cache_size. Otherwise, exit with an error and remind that the input parameter is wrong.

[0008] S2, read the LDM configuration register of the hardware to obtain the cache capacity size under the current configuration, recorded as old_cache_size;

[0009] S3, obtaining the computing core stack space size and the computing core stack pointer;

[0010] S4, compare new_cache_size and old_cache_size. If new_cache_size is larger than old_cache_size, go to S5 for execution; otherwise, go to S6 for execution.

[0011] S5. Allocate a local memory space mem_a in the LDM space that is equal to the size of the computing core stack space, and transfer the computing core stack space to the newly allocated local memory space;

[0012] S6. Confirm that all DMA operations related to the computing core have been completed by judging the answer word, and confirm that all memory access operations previously issued by the computing core have been completed by hardware MEMB instructions;

[0013] S7, refresh the computing core cache to ensure cache consistency, set the value of the LDM configuration register to new_cache_size to reconfigure the cache capacity, and ensure that subsequent memory access operations use the new configuration through the hardware MEMB instruction;

[0014] S8, compare new_cache_size and old_cache_size, if new_cache_size is greater than old_cache_size, go to S9 for execution, otherwise go to S10 for execution;

[0015] S9, transfer the computing core stack space in mem_a to the LDM space next to the new cache space, release the mem_a space, and go to S11 for execution;

[0016] S10, transferring the computing core stack space to the LDM space next to the new cache space;

[0017] S11. Point the computing core stack pointer to the end of the new computing core stack space, and the configuration is completed.

[0018] The further improved scheme in the above technical scheme is as follows:

[0019] 1. In the above scheme, the configuration method is encapsulated as a function interface for users to use, and the input parameter is the cache capacity that the user wants to configure.

[0020] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art:

[0021] The present invention provides a method for dynamically configuring Cache and LDM at runtime, which can flexibly configure the capacity of Cache and LDM according to the characteristics of different stages of the program, avoid performance loss caused by insufficient LDM or Cache capacity under fixed configuration, and maximize its performance advantage. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Attached Figure 1 This is a diagram of the computing core LDM / Cache configuration structure proposed by the present invention;

[0023] Attached Figure 2 This is a schematic diagram of the computing core stack space allocation proposed by the present invention;

[0024] Attached Figure 3 The figure is a flow chart of the method of the present invention. DETAILED DESCRIPTION

[0025] Embodiment: The present invention provides a method for dynamically configuring on-chip storage space, which specifically includes the following steps:

[0026] S1. Read the input parameter and determine whether the input parameter is a capacity size supported by the hardware according to the supported cache capacity configuration size provided by the hardware. If so, proceed to the next step and record the input parameter as new_cache_size. Otherwise, exit with an error and remind that the input parameter is wrong.

[0027] S2, read the LDM configuration register of the hardware to obtain the cache capacity size under the current configuration, recorded as old_cache_size;

[0028] S3, obtaining the computing core stack space size and the computing core stack pointer;

[0029] S4, compare new_cache_size and old_cache_size. If new_cache_size is larger than old_cache_size, go to S5 for execution; otherwise, go to S6 for execution.

[0030] S5. Allocate a local memory space mem_a in the LDM space that is equal to the size of the computing core stack space, and transfer the computing core stack space to the newly allocated local memory space;

[0031] S6. Confirm that all DMA operations related to the computing core have been completed by judging the answer word, and confirm that all memory access operations previously issued by the computing core have been completed by hardware MEMB instructions;

[0032] S7, refresh the computing core cache to ensure cache consistency, set the value of the LDM configuration register to new_cache_size to reconfigure the cache capacity, and ensure that subsequent memory access operations use the new configuration through the hardware MEMB instruction;

[0033] S8, compare new_cache_size and old_cache_size, if new_cache_size is greater than old_cache_size, go to S9 for execution, otherwise go to S10 for execution;

[0034] S9, transfer the computing core stack space in mem_a to the LDM space next to the new cache space, release the mem_a space, and go to S11 for execution;

[0035] S10, transferring the computing core stack space to the LDM space next to the new cache space;

[0036] S11. Point the computing core stack pointer to the end of the new computing core stack space, and the configuration is completed.

[0037] The configuration method is encapsulated as a function interface for user use, and the input parameter is the cache capacity that the user wishes to configure.

[0038] The above embodiment is further explained as follows:

[0039] The local local data storage space in the computing core is as follows Figure 1 As shown: Its total size is 256KB, and the hardware supports configuration in three forms:

[0040] (a) All are configured as regular on-chip local data memory LDM; (b) Part is configured as hardware-automatically managed cache (size is 32KB), and the rest is LDM; (c) Part is configured as hardware-automatically managed data cache (size is 128KB), and the rest is LDM; When configured as cache, the hardware cache adopts a 4-way set associative strategy and supports hardware elimination and filling.

[0041] Since there are a large number of computing cores in a many-core processor, the cost of implementing the computing core cache consistency in hardware is very huge and difficult to achieve. Therefore, the consistency of the computing core cache needs to be guaranteed by software.

[0042] The configuration structure of the local local data storage space is controlled by the hardware's LDM configuration register. Assigning different values ​​to the LDM configuration register represents the implementation of different local memory space configurations. In addition, since the hardware does not support the consistency of the computing core cache, dynamic configuration of the local memory space also needs to ensure the consistency of the data in the cache.

[0043] In addition, in order to improve performance, the stack space of the computing core is generally stored in the local memory space. In this process, the correctness of the stack space data must also be ensured. The storage location of the computing core stack space in the local memory is as follows: Figure 2 As shown (taking Cache size of 32KB as an example): The computing core stack space is stored in LDM, but in order to distinguish it from other computing core data and avoid space overlap conflicts as much as possible, the computing core stack space is stored next to the allocated Cache space.

[0044] This patent is based on the different usage methods of Cache and LDM in the local local data storage space of the computing core and their different impacts on program performance. By providing a packaged function interface, the user can dynamically configure the capacity of the computing core LDM / Cache according to different application scenarios and program characteristics for different capacity requirements of LDM or Cache during program operation, avoiding performance loss caused by insufficient LDM or Cache capacity under fixed configuration, improving program performance, and the configuration process is transparent to the user, making it convenient for users to use.

[0045] Based on the configurable characteristics of local memory space, a packaged function interface is provided for programmers to use to dynamically configure LDM and cache capacity. The configuration process is transparent to users, avoiding performance loss caused by insufficient LDM or cache capacity.

[0046] Based on the comparison of cache capacity before and after configuration, different methods are selected for transferring the computing core stack space, which not only ensures that the computing core stack space is not destroyed but also increases the configuration speed as much as possible;

[0047] Before and after configuring the computing core cache capacity, ensure that the computing core is in a stable and consistent state by judging the DMA response word, judging whether the memory access operation is completed, inserting MEMB instructions, refreshing the computing core cache, etc., to ensure the consistency of the cache and the correctness of the program.

[0048] The present invention proposes a method for dynamically configuring on-chip storage space, which is provided to users in the form of a packaged function interface. The input parameter is the cache capacity that the user wishes to configure. The specific flow chart is as follows: Figure 3 As shown, the brief description is as follows:

[0049] 1) Read the input parameter and determine whether the parameter is the configurable cache capacity supported by the hardware. If yes, proceed to the next step. We record the parameter as new_cache_size. Otherwise, exit with an error and remind the user that the input parameter is wrong.

[0050] 2) Read the hardware LDM configuration register to obtain the cache capacity under the current configuration, recorded as old_cache_size;

[0051] 3) Get the size of the computing core stack space and the stack pointer of the computing core;

[0052] 4) Compare new_cache_size and old_cache_size. If new_cache_size is greater than old_cache_size, go to step 5, otherwise go to step 6.

[0053] 5) Allocate a local memory space mem_a in the LDM space that is equal to the size of the computing core stack space, and transfer the computing core stack space to the newly allocated local memory space;

[0054] 6) Confirm that all DMA operations related to this computing core have been completed through the judgment of the answer word, and confirm that all memory access operations previously issued by this computing core have been completed through the hardware MEMB instruction;

[0055] 7) Refresh the compute core cache to ensure cache consistency; set the value of the LDM configuration register to new_cache_size to reconfigure the cache capacity, and use the hardware MEMB instruction to ensure that subsequent memory access operations use the new configuration;

[0056] 8) If new_cache_size is greater than old_cache_size, go to step 9, otherwise go to step 10;

[0057] 9) Move the computing core stack space in mem_a back to the LDM space next to the new cache space; release the mem_a space; go to step 11;

[0058] 10) Move the computing core stack space to the LDM space next to the new cache space;

[0059] 11) Set the computing core stack pointer to the end of the new computing core stack space, and the configuration is complete.

[0060] Assume that the current configuration of the computing core cache capacity is 32KB, and the user reconfigures the cache input parameter to 128KB. The brief process is as follows:

[0061] 1) Read the input parameters and the value of the hardware LDM configuration register, new_cache_size = 128KB, old_cache_size = 32KB, and obtain the computing core space size and stack pointer value. Assuming that the current computing core stack space size is 8KB, the computing core stack pointer value is 40 (32 + 8) KB;

[0062] 2) Because new_cache_size> old_cache_size, we apply for a new 8KB space mem_a in the regular LDM space and transfer all 8KB data in the computing core stack space to mem_a;

[0063] 3) After confirming that the DMA operations and memory access operations related to the computing core are completed, refresh the computing core cache, set the value of the LDM configuration register to 128KB to reconfigure the cache capacity, and insert the MEMB instruction to ensure that subsequent operations use the new configuration;

[0064] 4) The 8KB data in mem_a (computing core stack space) is transferred back to the regular LDM space adjacent to the cache space in the new configuration, freeing up the mem_a space; the computing core stack pointer is updated. At this time, the value of the computing core stack pointer is 136 (128 + 8) KB.

[0065] When the above-mentioned on-chip storage space dynamic configuration method is adopted, the capacity of Cache and LDM can be flexibly configured according to the characteristics of different stages of the program, avoiding performance loss caused by insufficient LDM or Cache capacity under fixed configuration, and maximizing its performance advantage.

[0066] In order to facilitate a better understanding of the present invention, the terms used in this article are briefly explained below:

[0067] Cache: Cache memory is a special memory subsystem, a high-speed, small-capacity memory between the central processing unit (CPU) and the main memory.

[0068] LDM: local data memory, local / local data memory.

[0069] DMA: direct memory access, direct memory access, is a data exchange mode that accesses data directly from memory without going through the CPU.

[0070] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for dynamically configuring on-chip storage space, It is characterized in that The following steps are involved: S1. Read the input parameter and determine whether the input parameter is a capacity size supported by the hardware according to the supported cache capacity configuration size provided by the hardware. If so, proceed to the next step and record the input parameter as new_cache_size. Otherwise, exit with an error and remind that the input parameter is wrong. S2, read the LDM configuration register of the hardware to obtain the cache capacity size under the current configuration, recorded as old_cache_size; S3, obtaining the computing core stack space size and the computing core stack pointer; S4, compare new_cache_size and old_cache_size. If new_cache_size is larger than old_cache_size, go to S5 for execution; otherwise, go to S6 for execution. S5. Allocate a local memory space mem_a in the LDM space that is equal to the size of the computing core stack space, and transfer the computing core stack space to the newly allocated local memory space; S6. Confirm that all DMA operations related to the computing core have been completed by judging the answer word, and confirm that all memory access operations previously issued by the computing core have been completed by hardware MEMB instructions; S7, refresh the computing core cache to ensure cache consistency, set the value of the LDM configuration register to new_cache_size to reconfigure the cache capacity, and ensure that subsequent memory access operations use the new configuration through the hardware MEMB instruction; S8, compare new_cache_size and old_cache_size, if new_cache_size is greater than old_cache_size, go to S9 for execution, otherwise go to S10 for execution; S9, transfer the computing core stack space in mem_a to the LDM space next to the new cache space, release the mem_a space, and go to S11 for execution; S10, transferring the computing core stack space to the LDM space next to the new cache space; S11. Point the computing core stack pointer to the end of the new computing core stack space, and the configuration is completed.

2. The on-chip storage space dynamic configuration method according to claim 1, Features: The configuration method is encapsulated as a function interface for user use, and the input parameter is the cache capacity that the user wishes to configure.

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