Register randomization methods, systems, devices, and storage media for authentication

Abstract

The present disclosure provides a register random method, system, device and storage medium for verification, the method comprising: establishing a plurality of register modules according to a device to be verified, each of the plurality of register modules comprising one or more registers; setting a configuration stage of each of the plurality of register modules; obtaining the configuration stage of each of the plurality of register modules to obtain a configuration stage set; selecting the configuration stage of at least part of the configuration stage set in series, and randomly selecting the registers of the register module corresponding to each currently selected configuration stage in the at least part of the configuration stage. The register random method of the present disclosure introduces a mechanism related to the configuration stage of the register, thereby realizing serial randomization, improving randomization efficiency, saving hardware resources, solving the problem of random difficulty, making debugging easier, and having good portability.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a register random method, system, device and storage medium for verification. BACKGROUND

[0002] With the rapid development of the integrated circuit industry, the complexity of chips has greatly increased, and the number of corresponding registers has become increasingly large. The properties of the registers are also becoming more and more complex. It is an urgent problem for verification personnel to verify the completeness and efficiency of the registers. The increase of the registers also puts higher requirements on constraint algorithms and iteration speed. The traditional verification method cannot meet the requirements of iteration period and chip verification difficulty. At the same time, the constraints implemented by using the traditional verification method are becoming more and more complex, and more and more algorithm resources are required. However, due to limited resources, it is easy to cause a situation that the random answer cannot be solved for a long time. SUMMARY

[0003] At least one embodiment of the present disclosure provides a register random method for verification, comprising: establishing a plurality of register modules according to a device to be verified, wherein each of the plurality of register modules comprises one or more registers; setting a configuration stage of each of the plurality of register modules; obtaining the configuration stage of each of the plurality of register modules to obtain a configuration stage set; selecting the configuration stage of at least a part of the configuration stage set in series, and randomly selecting the registers of the register module corresponding to each currently selected configuration stage in the at least a part of the configuration stage.

[0004] For example, in the register random method provided by at least one embodiment of the present disclosure, the setting of the configuration stage of each of the plurality of register modules comprises: recording the configuration stage of each current register in each register module in the plurality of register modules by setting a configuration stage variable at the establishment stage of the current register, and respectively making each register in the same register module have the same configuration stage.

[0005] For example, in the register random method provided by at least one embodiment of the present disclosure, the obtaining of the configuration stage of each of the plurality of register modules to obtain the configuration stage set comprises: recording the configuration stage of each of the plurality of register modules by setting a static association array; and obtaining a plurality of configuration stages set in the static association array to obtain the configuration stage set.

[0006] For example, in the register randomization method provided in at least one embodiment of the present disclosure, the at least one part of the configuration stages includes all configuration stages in the configuration stage set; or, the at least one part of the configuration stages includes a second part of configuration stages remaining after a first part of configuration stages is removed from all configuration stages in the configuration stage set, the first part of configuration stages including configuration stages corresponding to at least one first register module configured as a command line input mode or a performance test mode.

[0007] For example, in the register randomization method provided in at least one embodiment of the present disclosure, the configuration stage set is an array queue generated according to the plurality of configuration stages.

[0008] For example, in the register randomization method provided in at least one embodiment of the present disclosure, in response to the at least one part of the configuration stages including all configuration stages in the configuration stage set, the selecting at least one part of the configuration stages in the configuration stage set in series and the randomizing registers of register modules corresponding to each currently selected configuration stage in the at least one part of the configuration stages respectively includes: sequentially and in series selecting each configuration stage in the array queue according to the length of the array queue, and respectively randomizing each register of register modules corresponding to each currently selected configuration stage in the array queue.

[0009] For example, in the register randomization method provided in at least one embodiment of the present disclosure, in response to the configuration stage set including the first part of configuration stages, the register randomization method further includes: directly configuring registers of each first register module in the at least one first register module to fixed values respectively before the selecting the second part of configuration stages in series and the randomizing registers of register modules corresponding to each currently selected configuration stage in the second part of configuration stages respectively.

[0010] For example, in the register randomization method provided in at least one embodiment of the present disclosure, in response to the current target register module including a plurality of registers, performing randomization on the current target register module to randomly configure each register in the current target register module includes: randomly configuring each register in the plurality of registers in the current target register module in parallel.

[0011] For example, in the register randomization method provided in at least one embodiment of the present disclosure, in response to the current target register module including a plurality of registers, performing randomization on the current target register module to randomly configure each register in the current target register module includes: randomly configuring each register in the plurality of registers in the current target register module in parallel.

[0012] For example, in the register randomization method provided in at least one embodiment of the present disclosure, at least one register module in the plurality of register modules includes a plurality of sub-register modules, and each of the sub-register modules includes a plurality of registers.

[0013] For example, in the register randomization method provided in at least one embodiment of the present disclosure, in response to the current target register module including a plurality of sub-register modules, performing randomization on the current target register module to randomly configure each register in the current target register module includes: performing randomization on the plurality of sub-register modules in the current target register module in parallel to randomly configure each register in each of the plurality of sub-register modules.

[0014] For example, in the register randomization method provided in at least one embodiment of the present disclosure, in response to the current target register module including a plurality of registers with cross constraints, performing randomization on the current target register module to randomly configure each register in the current target register module includes: by adding an additional constraint, controlling the plurality of registers with cross constraints in the current target register module to be randomly configured according to the additional constraint.

[0015] The verification method provided in at least one embodiment of the present disclosure includes the register randomization method described in any of the above embodiments.

[0016] The register randomization system for verification provided in some embodiments of the present disclosure includes: a establishing module configured to establish a plurality of register modules according to a device to be verified, wherein each of the plurality of register modules includes one or more registers; a setting module configured to set a configuration stage of each of the plurality of register modules; an obtaining module configured to obtain the configuration stage of each of the plurality of register modules to obtain a configuration stage set; and a serial randomization module configured to serially select at least part of the configuration stages in the configuration stage set and respectively randomize the registers of the register module corresponding to each currently selected configuration stage in the at least part of the configuration stages.

[0017] The electronic device provided in some embodiments of the present disclosure includes a processor and a memory, wherein the memory has stored thereon a computer program, and the computer program, when executed by the processor, implements the register randomization method according to any one of the above.

[0018] The computer readable storage medium provided in some embodiments of the present disclosure has stored therein a computer program, and the computer program, when executed by a processor, implements the register randomization method according to any one of the above. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0020] Figure 1 The flowchart of the register randomization method for verification provided in some embodiments of the present disclosure is shown in FIG. 1;

[0021] Figure 2 The flowchart of the register randomization method provided in some embodiments of the present disclosure is shown in FIG. 2; Figure 1 The flowchart of step S3 in the method for verification provided in some embodiments of the present disclosure is shown in FIG. 3;

[0022] Figure 3 The flowchart of step S4 in the method for verification provided in some embodiments of the present disclosure is shown in FIG. 4; Figure 1 The flowchart of step S4 in the method for verification provided in some embodiments of the present disclosure is shown in FIG. 4;

[0023] Figure 4 The flowchart of the register randomization method provided in some embodiments of the present disclosure is shown in FIG. 2;

[0024] Figure 5 The block diagram of the register randomization system provided in some embodiments of the present disclosure is shown in FIG. 5; and

[0025] Figure 6 A block diagram of an electronic device provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present disclosure.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined in the embodiments of the present disclosure.

[0028] The terms "first", "second", and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different constituent parts. The terms "one", "a", or "the" and similar terms do not denote a quantity of particular mentioned items, but denote the existence of at least one of those items. Similarly, the terms "include", "comprise", and the like are intended to mean that the elements or objects listed after the terms encompass the elements or objects listed and equivalents thereof, and do not exclude other elements or objects. The terms "connected" or "coupled" and the like are not limited to physical or mechanical connections or couplings, but can include electrical connections or couplings, whether direct or indirect. Flowcharts are used in the embodiments of the present disclosure to illustrate the steps of the methods according to the embodiments of the present disclosure. It should be understood that the preceding or subsequent steps do not necessarily proceed in order. Instead, various steps can be processed in reverse order or simultaneously. In addition, other operations can be added to these processes, or one or more steps can be removed from these processes.

[0029] SystemVerilog, short for SV, is built on the basis of Verilog language and becomes the next generation of hardware design and verification language. SystemVerilog combines the concepts from Verilog, VHDL, C++, verification platform language and assertion language, that is, it combines hardware description language (HDL) and modern high-level verification language (HVL). At present, SystemVerilog is mainly positioned in the implementation and verification process of chips. SystemVerilog has all the structures required by chip design and verification engineers, and it integrates object-oriented programming, dynamic threads and inter-thread communication. As an industry standard language, SV comprehensively integrates RTL design, test platform, assertion and coverage, and provides strong support for system-level design and verification.

[0030] In addition to being applied as a high-level language for abstract modeling, another significant feature of SystemVerilog is that it can be combined with chip verification methodology, that is, it is a language tool for implementation methodology. Using verification methodology can greatly enhance module reusability, improve chip development efficiency and shorten development cycle. It can be seen that SystemVerilog language contains many features of design, verification, assertion and other aspects.

[0031] The inventors of the present disclosure found that according to the register definition in hardware design, the register constraints can be added according to the actual hardware design and the properties of the registers, and then a random function (for example, the randomize function of SystemVerilog) is called before the registers are configured, so that all the constraints are randomly configured (also called random solving) at the same time and the same stage of simulation, thereby realizing the parallel random of the registers. However, this method has the following problems: (1) in the case of a large number of registers, the solving efficiency will be reduced, and it is not suitable for random of a large number of registers and complex projects; (2) parallel random will consume a large amount of hardware resources and high-configuration servers for running; (3) parallel random will put higher requirements on the algorithm of the tool, and with the linear increase of the registers, the difficulty of random configuration will increase exponentially, which can easily lead to random failure; (4) parallel random has poor readability, and all the related and unrelated registers are mixed together; (5) due to the simultaneous random of a large number of registers, if random failure occurs, it increases the difficulty of error correction, and due to the simultaneous random of a large number of registers, it is difficult to quickly locate the registers that cause the error; (6) poor portability.

[0032] To this end, at least one embodiment of the present disclosure provides a register randomization method for verification, comprising: establishing a plurality of register modules according to a device to be verified, wherein each of the plurality of register modules comprises one or more registers; setting a configuration stage of each of the plurality of register modules; obtaining the configuration stage of each of the plurality of register modules to obtain a configuration stage set; selecting, in series, configuration stages of at least a part of the configuration stage set, and randomly selecting registers of a register module corresponding to each currently selected configuration stage in the at least a part of the configuration stages.

[0033] The register randomization method of the above-mentioned embodiments of the present disclosure realizes serial randomization by introducing a mechanism related to the configuration stage of the register, thereby improving the randomization efficiency, saving hardware resources, solving the problem of randomization difficulty, and avoiding the problem of hardware limitation in the randomization process. The register randomization method can more conveniently distinguish the difference between registers, is easier to debug, has good portability, can be applied to all register randomization application scenarios, and has strong realizability and operability.

[0034] Figure 1 A flowchart of the register randomization method for verification provided by some embodiments of the present disclosure is shown in FIG. 1.

[0035] For example, as shown in FIG. 2, the register randomization method for verification provided by at least one embodiment of the present disclosure comprises steps S1 to S4. Figure 1

[0036] Step S1, establishing a plurality of register modules according to a device to be verified, wherein each of the plurality of register modules comprises one or more registers.

[0037] Step S2, setting a configuration stage of each of the plurality of register modules.

[0038] Step S3, obtaining the configuration stage of each of the plurality of register modules to obtain a configuration stage set.

[0039] Step S4, selecting, in series, configuration stages of at least a part of the configuration stage set, and randomly selecting registers of a register module corresponding to each currently selected configuration stage in the at least a part of the configuration stages.

[0040] ​Embodiments of the present disclosure realize a serial random register random method by introducing a mechanism related to a configuration phase of a register, greatly improve random efficiency, save hardware resources, solve random difficulty problems, can avoid the problem of hardware limitation in the random process, and are suitable for random of a large number of registers. The register random method can more conveniently distinguish the difference between registers, is easier to debug, has good portability, can be applied to all register random application scenarios, and has strong realizability and operability.

[0041] For example, in step S1, the register random method of the present disclosure can be a step of a device under test (DUT) before starting verification. Since other contents of the verification method are not the focus of the embodiments of the present disclosure, they are not described here.

[0042] In some examples, in step S1, for a plurality of register modules (blocks), for example, a part of the plurality of register modules each include one register, and another part of the plurality of register modules each include a plurality of registers; for another example, each of the plurality of register modules includes one register; for still another example, each of the plurality of register modules includes a plurality of registers. Embodiments of the present disclosure do not limit this, and can reasonably divide according to the number and constraints of registers of an actual device under test. This is not described here, and thus the flexibility of the register random method is increased.

[0043] In some examples, a register has many attributes, such as a mapping relationship, an offset, an access mode, a bit width, whether it can be randomized, and a power-on reset value. Embodiments of the present disclosure also add an attribute of a configuration phase (Solve_phase) to the register. In some examples, in step S2, the configuration phase refers to randomizing a value in a constraint range as a configuration of a product. For example, a register can randomize all values, and a register can be limited by a register constraint to perform constraint randomization. Thus, the configuration phase of the embodiments of the present disclosure can specify a phase in which a register or a constraint is located.

[0044] In some examples, all registers of a device under test have a configuration phase attribute. For example, for a register module and the register module including a plurality of registers, the configuration phases of all registers in the register module are the same, and the configuration phase of the register module is consistent with the configuration phase of the registers in the register module, that is, all registers in the register module perform randomization in a phase (Active_phase, see below) in which the register module currently performs randomization to complete random configuration.

[0045] For example, for step S2, in some examples, the configuration phase setting of each register module in the plurality of register modules includes the following step S21: in the establishment phase of each current register of each register module in the plurality of register modules, recording the configuration phase of the current register by setting a configuration phase variable, and respectively making each register in the same register module have the same configuration phase.

[0046] Thus, the embodiment of the present disclosure sets the configuration phase of the plurality of register modules by adding the attribute of the configuration phase to the register, which can more conveniently distinguish the registers, and can be implemented by using the algorithm of a more conventional tool, simple and efficient.

[0047] For example, for step S21, in some examples, all attributes of the register are recorded in the establishment phase of the register, for example, the configuration phase of the current register can be recorded in real time by setting a solve_phase variable (for example, a configuration phase variable).

[0048] For example, in some examples, if each register module includes one register, i.e., step S2 of the embodiment of the present disclosure is mainly to set the configuration phase in units of registers. For the convenience of description, this case is recorded as case one. Thus, the register random method operation of case one is simpler, which is very convenient to distinguish the registers, can avoid the problem of mixing unrelated registers together, and can quickly and accurately locate the register causing the error, but the number of times of serially performing individual randomization is relatively large in this case.

[0049] In some examples, for case one, in step S21, the configuration phase of the current register is recorded in real time by setting a configuration phase variable in the establishment phase of each register, i.e., the configuration phase of the current register module is recorded in real time, thereby completing the setting of the configuration phase of all registers of the device to be verified.

[0050] For example, in other examples, when each register module in the plurality of register modules includes a plurality of registers, i.e., step S2 of the embodiment of the present disclosure is mainly to set the configuration phase in units of register combinations, which can be reasonably divided into modules according to the actual situation of the number of registers and constraints. For the convenience of description, this case is recorded as case two. Thus, the efficiency of the register random method of case two is higher, the operation is relatively simple, and the hardware resources can be saved.

[0051] In some examples, for case two, in step S21, the configuration phase of the current register is recorded in real time by setting the configuration phase variable in the establishment phase of each register, and the plurality of registers with the same configuration phase are divided into a register module, so as to complete the setting of the configuration phase of each register module in the plurality of register modules, that is, the setting of the configuration phase of all registers of the device to be verified. Of course, this is only exemplary and is not a limitation of the present disclosure. For example, in other embodiments, after being reasonably divided into a plurality of register modules, the configuration phase of the current register module can be recorded in real time by the set configuration phase variable, so that each register in the current register module has the same configuration phase. The present disclosure does not limit this as long as each register module and / or each register is labeled with a configuration phase so that the registers are configured in series in a phase at random. Details are not repeated here.

[0052] For example, in some other examples, when some register modules in the plurality of register modules each include one register, and some other register modules each include a plurality of registers, that is, the setting of the attribute of the configuration phase in step S2 of the embodiments of the present disclosure is performed in a combined manner according to case one and case two. This can be referred to case one and case two described above, and details are not repeated here.

[0053] Figure 2 For some embodiments of the present disclosure Figure 1 The flowchart of step S3 in the method.

[0054] For example, as shown in Figure 2 Step S3 includes step S31 and step S32.

[0055] Step S31, the configuration phase of each register module in the plurality of register modules is recorded by setting a static association array.

[0056] Step S32, the plurality of configuration phases set in the static association array are obtained to obtain a configuration phase set.

[0057] Therefore, the embodiments of the present disclosure record the attribute of the configuration phase of all register modules by the static association array to obtain the configuration phase set, so that the calling speed is faster, and the reliability and maintainability are better.

[0058] For example, for step S31, in some examples, the static association array obtains the configuration phase of the current register module in real time and records it after the configuration phase variable records the configuration phase of each current register module, so as to complete the recording of the configuration phase of all register modules.

[0059] For example, embodiments of the present disclosure set the above-mentioned variable solve phase and the above-mentioned static associated array solve phase [int] by Set_solve_phase to complete the setting of the configuration phase. This is merely exemplary and is not a limitation of the present disclosure.

[0060] For example, for step S32, in some examples, the configuration phase set is an array queue generated according to a plurality of configuration phases. In this way, it is beneficial to index and select subsequent configuration phases, improving efficiency. This is merely exemplary and is not a limitation of the present disclosure, which will not be described here.

[0061] For example, the total number of registers to be randomized of one CPU module is P, and the P registers can be divided into Q groups, i.e., divided into P register modules, each of the P register modules includes a plurality of registers, and thus the array queue records a total of P configuration phases.

[0062] In some examples, the at least a part of the configuration phases includes all configuration phases in the configuration phase set. In other examples, the at least a part of the configuration phases includes a second part of the configuration phases remaining after removing a first part of the configuration phases from all configuration phases in the configuration phase set, and the first part of the configuration phases includes configuration phases corresponding to at least one register module configured as a command line input mode or a performance test mode, i.e., the at least a part of the configuration phases does not include all configuration phases in the configuration phase set, but only includes a part of the configuration phases in the configuration phase set. For the convenience of description, embodiments of the present disclosure refer to the register configured as the command line input mode or the performance test mode as the first register. In this way, embodiments of the present disclosure have good portability and can be applied to any register randomization application scenario.

[0063] For example, for step S4, in some examples, in the case where the at least a part of the configuration phases in the configuration phase set includes all configuration phases in the configuration phase set, the step of serially selecting and respectively randomizing the registers of the register module corresponding to each currently selected configuration phase in the at least a part of the configuration phases in the configuration phase set in step S4 includes the following steps or processes: sequentially and serially selecting each configuration phase in the array queue according to the length of the array queue, and respectively randomizing each register of the register module corresponding to each currently selected configuration phase in the array queue. In this way, embodiments of the present disclosure can serially randomize the registers in an orderly manner, one configuration phase after another, greatly shortening the randomization time of a large number of registers and accelerating the iteration speed of the product.

[0064] For example, for step S4, in some examples, the serially selecting and randomly selecting the registers of the register modules corresponding to each currently selected configuration phase of the at least part of the configuration phases of the configuration phase set comprises the following steps or procedures: before the serially selecting and randomly selecting the registers of the register modules corresponding to each currently selected configuration phase of the second part of the configuration phases, directly constraining the registers of each first register module of the at least one first register module to be a fixed value respectively. In this way, the embodiments of the present disclosure can be applied to more complex register randomization cases, have good portability, and can be applied to any register randomization application scenario.

[0065] In some examples, the first register can be a register configured as a command line input mode or a performance test mode. In the command line input mode or the performance test mode, the first register does not need complex randomization (for example, does not need to call the randomize function), can be directly generated, that is, can be directly constrained to a fixed value, and the direct generation of the first register is only called in the first loop, that is, the process is completed before the registers corresponding to the configuration phases of the second part start to perform serial randomization.

[0066] Figure 3 For some embodiments of the present disclosure Figure 1 the flowchart of step S4.

[0067] For example, for step S4, in some examples, the serially selecting and randomly selecting the registers of the register modules corresponding to each currently selected configuration phase of the at least part of the configuration phases of the configuration phase set comprises the following steps or procedures: serially selecting the at least part of the configuration phases of the configuration phase set and sequentially performing randomization on the register modules corresponding to the selected configuration phases respectively. For example, for each currently selected configuration phase of the at least part of the configuration phases of the configuration phase set, step S4 comprises steps S41 to S43, as shown in Figure 3 .

[0068] Step S41, passing the currently selected configuration phase to each register module of the plurality of register modules in a recursive manner.

[0069] Step S42, comparing the currently selected configuration phase with the configuration phase corresponding to each register module of the plurality of register modules.

[0070] Step S43, performing randomization on the current target register module among the plurality of register modules having the configuration phase consistent with the currently selected configuration phase, to randomly configure each register in the current target register module.

[0071] Embodiments of the present disclosure find the registers of the target register module corresponding to the current configuration phase by recursively climbing to the registers of all register modules at one stage, to complete the random configuration of the registers of the target register module at the current stage, the algorithm is more concise and clear, and better readability.

[0072] For example, in step S41, passing the currently selected configuration phase to each register module in the plurality of register modules by recursion refers to passing the currently selected configuration phase to the registers corresponding to the plurality of register modules respectively by top-down propagation, and the currently selected configuration phase can be denoted as Active phase, i.e. the phase in which the current randomization is performed. For example, the level of the top-down propagation here is consistent with the structure level of the device to be verified, and since this is not the focus of the present disclosure, it will not be described here.

[0073] For example, in step S42, comparing the currently selected configuration phase with the configuration phase corresponding to each register module in the plurality of register modules, i.e. comparing the currently selected configuration phase with the configuration phase of the registers in each register module in the plurality of register modules, to determine the random opening (i.e. the registers currently perform random configuration to complete randomization) or closing (i.e. the registers are not currently randomized) of each register.

[0074] For example, in step S42, since the configuration phase of each register in the same register module is the same, i.e. the configuration phase of the register module is consistent with the configuration phase of any register in the register module, therefore, comparing the currently selected configuration phase with the configuration phase corresponding to each register module in the plurality of register modules can be achieved by comparing the currently selected configuration phase with the configuration phase corresponding to at least one register (e.g. one or two or all registers) in each register module. For example, if it is determined by comparison that the configuration phase of at least one register of a certain register module is consistent with the currently selected configuration phase, it is determined that the register module is the current target register module that needs to perform random configuration, i.e. all registers in the current target register module perform random configuration at the currently selected stage to complete randomization. Of course, this is only exemplary and is not a limitation of the present disclosure, as long as it can be compared to determine which register modules and / or registers are to be opened and which register modules and / or registers are to be closed, for example, it is freely adjusted according to the configuration phase setting in step S21 described above, which will not be described here.

[0075] For example, in step S43, randomization is performed on the current target register module among multiple register modules that has a configuration stage consistent with the currently selected configuration stage. That is, if the configuration stage of a certain register module is consistent with the currently selected configuration stage, random configuration is performed on the registers of that register module to complete randomization, i.e., randomization of the registers of that register module is enabled. As another example, if the configuration stage of a certain register module is inconsistent with the currently selected configuration stage, then the registers of that register module are not currently randomized, i.e., randomization of the registers of that register module is disabled.

[0076] In some examples, where the current target register module includes multiple registers, step S43, which performs randomization on the current target register module to randomly configure each register in the current target register module, includes the following steps or processes: randomly configuring each of the multiple registers in the current target register module in parallel. Thus, embodiments of this disclosure can implement a register randomization method combining serial and parallel processing, which not only reduces the difficulty of randomization and saves hardware resources but also improves randomization efficiency, making it suitable for randomizing a large number of registers.

[0077] Figure 4 A flowchart illustrating a register randomization method provided for other embodiments of this disclosure. For ease of description, Figure 4 The illustration mainly takes the case where at least a portion of the configuration stages in the configuration stage set includes all the configuration stages in the configuration stage set as an example. However, the process of the register randomization method in the embodiments of this disclosure is not limited to this. That is, the process and flowchart of other cases will not be exhaustively described here.

[0078] For example, such as Figure 4 As shown, the register randomization method provided in some embodiments of this disclosure includes steps T1 to T5.

[0079] Step T1: Establish N register modules based on the device to be verified. Each of the N register modules includes one or more registers, where N is an integer greater than 1.

[0080] Step T2: Set the configuration phase for each of the N register modules.

[0081] Step T3: Obtain the configuration stage of each of the N register modules to obtain the configuration stage set.

[0082] Step T41: Select N configuration stages from the set of configuration stages sequentially.

[0083] Step T42, pass the currently selected configuration stage to the register of each register module in the N register modules by recursion to pass to all registers.

[0084] Step T43, compare the currently selected configuration stage with the configuration stage corresponding to each register module in the N register modules.

[0085] Step T44, determine whether the currently selected configuration stage is consistent with the configuration stage corresponding to the register module: if yes, open the random of the register of the register module; if no, close the random of the register of the register module.

[0086] Step T45, determine whether the N configuration stages in the configuration stage set are selected: if no, jump to step T41, and cyclically execute steps T41-T45 until the N configuration stages are all selected, and go to step T5; if yes, go to step T5.

[0087] Step T5, the register randomization ends and the result of the register randomization is obtained.

[0088] Thus, the embodiments of the present disclosure can reasonably group according to the number of registers and the constraint situation, introduce the mechanism of the configuration stage, let the registers be labeled with the configuration stage, make at least part of the parallel randomization become serial randomization, improve the randomization efficiency, save the resources, solve the problem of randomization difficulty, and can realize the verification dimension that the traditional scheme cannot complete, enhance the product reliability, and have good portability, for example, the platform can be ported by modifying the register code of the corresponding design.

[0089] In some examples, the register module (Block) can include one or more sub-register modules, and each sub-register module includes a plurality of registers. In this way, the embodiments of the present disclosure merge and split according to the complexity of the register related module, and increase the flexibility.

[0090] In some examples, in the case that the current target register module includes a plurality of sub-register modules, the step of performing randomization on the current target register module to randomly configure each register in the current target register module in step S43 includes the following steps or processes: performing randomization on the plurality of sub-register modules in the current target register module in parallel to randomly configure each register of each sub-register module in the plurality of sub-register modules. In this way, embodiments of the present disclosure can be combined according to the complexity of the register-related module, which can increase flexibility, depending on the number of registers and the difficulty of randomization, etc. For example, the above-mentioned register module can be composed of more than two groups of registers. This is merely exemplary and is not a limitation of the present disclosure. For example, embodiments of the present disclosure can also be split according to the complexity of the register-related module, which can also increase flexibility, depending on the number of registers and the difficulty of randomization, etc. For example, embodiments of the present disclosure can split a register group that is more complex or has a larger number of registers into a plurality of the above-mentioned register modules and perform serial randomization according to the configuration stage, which can be performed according to the above description and will not be described here. It should be noted that the register group described here refers to any combination of register groups with multiple registers according to design division, and is not limited to one or some specific modules.

[0091] For example, one register group includes 50 registers, and another register group includes 50 registers, i.e., the two register groups together include 100 registers. If the randomization of the 100 registers can be satisfied in one stage, the two register groups can be combined into one register module, i.e., the configuration stages of the two register groups are set to be the same. In this way, when the register module is the current target register module, the 100 registers of the two register groups can be randomly configured in parallel. In this way, embodiments of the present disclosure can implement a register randomization method combining serial and parallel, which not only reduces the difficulty of randomization and saves hardware resources, but also improves the efficiency of randomization and is suitable for randomization of a large number of registers.

[0092] In some examples, in the case that the current target register module includes a plurality of registers with cross constraints, the step of performing randomization on the current target register module to randomly configure each register in the current target register module in step S43 includes the following steps or processes: by adding an additional constraint, the plurality of registers with cross constraints in the current target register module are controlled to be randomly configured according to the additional constraint. In this way, the randomization of the plurality of registers with cross constraints in the current target register module not only satisfies the constraints of the registers themselves, but also satisfies the additional constraint. In this way, embodiments of the present disclosure can be suitable for randomization of registers with correlation and other more complex randomization, which is more universal and suitable for randomization of a large number of registers.

[0093] In some examples, the multiple registers with cross constraints refer to the relationship that the registers cross, for example, register A = 5 and register B = 6, register A = 3 and register B = 4. This is merely exemplary and not a limitation of the present disclosure.

[0094] In some examples, embodiments of the present disclosure can call the randomize function of SystemVerilog to perform randomization, for example, sequentially performing the pre_randomize, randomize and post_randomize functions of SystemVerilog. This is merely exemplary and not a limitation of the present disclosure. In some examples, additional constraints can be added using SystemVerilog, for example, SystemVerilog allows the use of randomize() with {} to add additional constraints. Of course, this is merely exemplary and not a limitation of the present disclosure.

[0095] In some examples, in the case that the register module includes multiple registers with cross constraints, embodiments of the present disclosure call the callback function pre_randomize function of SystemVerilog, so that the constraint_mode of each register related constraint can be changed in the pre_randomize stage, wherein the constraint_mode function opens or closes the constraint, which is a built-in class of SystemVerilog, and the constraint in the inactive state will be disabled when the randomize function is called.

[0096] In some examples, embodiments of the present disclosure open and close the constraint_mode according to the currently selected configuration stage and the configuration stage where the constraint is located. For example, if the configuration stage where the constraint is located is inconsistent with the currently selected configuration stage, the constraint is closed by the constraint_mode function; if the configuration stage where the constraint is located is consistent with the currently selected configuration stage, the constraint is opened by the constraint_mode function and the function value is randomized to return, completing the random configuration.

[0097] For example, when the constraint of the multiple registers with cross constraints is consistent with the currently selected configuration stage, the constraint is opened by the constraint_mode function and the function value is randomized to return, completing the random configuration.

[0098] In some examples, the obtaining the random result of the registers in step T5 includes the following steps or processes: printing a text file about the registers, for example, printing the names and values of the corresponding registers of all the register modules. In some examples, the printing of the text file about the registers can be used in the verification process, that is, the register random method of the embodiments of the present disclosure can be applied to the verification process.

[0099] The verification method provided by at least one embodiment of the present disclosure also includes the register random method described in any of the above embodiments. It should be noted that the specific functions and technical effects of the verification method in the embodiments of the present disclosure can be referred to the description of the register random method for verification above. Since other related contents of the verification method are not the focus of the description of the present disclosure, they will not be described here.

[0100] Figure 5 A block diagram of a register random system provided by some embodiments of the present disclosure.

[0101] For example, as shown in Figure 5 The register random system for verification 100 provided by at least one embodiment of the present disclosure includes a establishing module 101, a setting module 102, an obtaining module 103 and a serial random module 104. The establishing module 101 is configured to establish a plurality of register modules according to a device to be verified, wherein each of the plurality of register modules includes one or more registers. The setting module 102 is configured to set a configuration stage of each of the plurality of register modules. The obtaining module 103 is configured to obtain the configuration stage of each of the plurality of register modules to obtain a configuration stage set. The serial random module 104 is configured to serially select at least part of the configuration stages in the configuration stage set and respectively randomize the registers of the register module corresponding to each currently selected configuration stage in the at least part of the configuration stages.

[0102] It should be noted that in the embodiments of the present disclosure, the register random system for verification 100 can include more or fewer modules, and the connection relationship between the modules is not limited and can be determined according to actual needs. The specific constituting manner of each module is not limited. The specific implementation and technical effects of the register random system for verification 100 can be referred to the technical effects of the register random method for verification provided by the above embodiments of the present disclosure, which will not be described here.

[0103] Each module in the above embodiments can be respectively configured as software, hardware, firmware or any combination of the above, which performs a specific function. For example, these modules can correspond to a dedicated integrated circuit, a pure software code, or a combination of software and hardware modules.

[0104] It should be noted that although the register random system used for verification is divided into modules for performing corresponding processes in the above description, it is clear to those skilled in the art that the processes performed by each module can also be performed in the random system without any specific module division or without clear boundaries between the modules.

[0105] Figure 6 This is a schematic diagram of the structure of an electronic device provided in at least one embodiment of the present disclosure. The terminal device in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle terminals (e.g., vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 6 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0106] For example, such as Figure 6 As shown, in some examples, electronic device 200 includes a processing unit (e.g., central processing unit, graphics processor, etc.) 201, which can execute the register randomization method described above based on a program stored in read-only memory (ROM) 202 or a program loaded from storage device 208 into random access memory (RAM) 203. The RAM 203 also stores various programs and data required for the operation of the computer system. The processing unit 201, ROM 202, and RAM 203 are connected via bus 204. Input / output (I / O) interface 205 is also connected to bus 204.

[0107] For example, the following components can be connected to I / O interface 205: input devices 206 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 207 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 208 including, for example, magnetic tapes, hard disks, etc.; and communication devices 209 including, for example, network interface cards such as LAN cards, modems, etc. Communication device 209 allows electronic device 200 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 310 is also connected to I / O interface 205 as needed. Removable media 311, such as disks, optical discs, magneto-optical discs, semiconductor memories, etc., are installed on drive 310 as needed so that computer programs read from them can be installed into storage device 209 as needed. Although Figure 6 An electronic device 200 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively.

[0108] For example, the electronic device 200 can further include a peripheral interface (not shown in the figure) and the like. The peripheral interface can be various types of interfaces, such as a USB interface, a lighting interface, and the like. The communication device 209 can communicate with networks and other devices through wireless communication, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). The wireless communication can use any of a plurality of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0109] For example, the electronic device can be any device such as a mobile phone, a tablet computer, a notebook computer, an e-book, a game console, a television, a digital photo frame, a navigator, and the like, or any combination of electronic devices and hardware, and embodiments of the present disclosure are not limited thereto.

[0110] For example, according to embodiments of the present disclosure, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product including a computer program carried on a non-transitory computer readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network through the communication device 209, or installed from the storage device 208, or installed from the ROM 202. When the computer program is executed by the processing device 201, the above-mentioned derived register random function defined in the methods of embodiments of the present disclosure is executed.

[0111] It should be noted that the computer readable medium in the embodiments of the present disclosure can be a computer readable signal medium or a computer readable storage medium or any combination of the two. The computer readable storage medium may, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination thereof. More specific examples of the computer readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the embodiments of the present disclosure, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or apparatus. In the embodiments of the present disclosure, the computer readable signal medium can include a data signal carried in a baseband or as a part of a carrier wave, which carries computer readable program code. Such a propagated data signal can take various forms, including but not limited to an electromagnetic signal, an optical signal or any suitable combination thereof. The computer readable signal medium can also be any computer readable medium other than the computer readable storage medium, which can send, propagate or transmit a program for use by or in conjunction with an instruction execution system, device or apparatus. The program code contained in the computer readable medium can be transmitted by any suitable medium, including but not limited to a wire, a cable, an RF (radio frequency) or the like, or any suitable combination thereof.

[0112] In some embodiments, the client, server can communicate using any currently known or future developed network protocol, such as HTTP (HyperText Transfer Protocol), and can be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include local area networks ("LAN"), wide area networks ("WAN"), the Internet, and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future developed networks.

[0113] The above computer readable medium can be contained in the above electronic device; or can exist separately without being assembled into the electronic device.

[0114] It should be noted that in the embodiments of the present disclosure, the specific functions and technical effects of the electronic device 200 can refer to the description of the above-mentioned register randomization method for verification, which will not be described here.

[0115] The following points need to be explained:

[0116] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0117] (2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0118] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A register randomization method for verification, comprising: Multiple register modules are established based on the device to be verified, wherein each of the multiple register modules includes one or more registers; Configure the configuration phase for each of the plurality of register modules; Obtain the configuration stage of each of the plurality of register modules to obtain a set of configuration stages; At least a portion of the configuration stages in the set of configuration stages are selected sequentially, and the registers of the register module corresponding to each currently selected configuration stage in the set of at least a portion of the configuration stages are randomly selected. The configuration phase for each of the plurality of register modules includes: In the setup phase of each current register in each of the plurality of register modules, the configuration phase of the current register is recorded by setting a configuration phase variable, and each register in the same register module has the same configuration phase.

2. The register randomization method as described in claim 1, wherein, The configuration stage of each of the plurality of register modules is obtained to obtain a set of configuration stages, including: The configuration phase of each of the multiple register modules is recorded by setting a static associative array; The set of configuration stages is obtained by retrieving multiple configuration stages that have been set in the static associated array.

3. The register randomization method as described in claim 1, wherein, The at least part of the configuration phases includes all configuration phases in the set of configuration phases; or, The configuration phase of at least one part includes: the configuration phase of the second part remaining after removing the configuration phase of the first part from all the configuration phases in the configuration phase set, wherein the configuration phase of the first part includes the configuration phase corresponding to at least one first register module configured as command line input mode or performance test mode.

4. The register randomization method as described in claim 3, wherein, The configuration phase set is an array queue generated based on the multiple configuration phases.

5. The register randomization method as described in claim 4, wherein, The configuration phases in response to at least a portion of the configuration phases include all configuration phases in the set of configuration phases. Serially selecting at least a portion of the configuration stages in the set of configuration stages, and randomly accessing the registers of the register module corresponding to each currently selected configuration stage in the set of at least a portion of the configuration stages, including: Based on the length of the array queue, each configuration stage in the array queue is selected sequentially and serially, and each register of the register module corresponding to each currently selected configuration stage in the array queue is randomly selected.

6. The register randomization method as described in claim 3, wherein, In response to the configuration phase set including the first portion of the configuration phase, the register randomization method further includes: Before sequentially selecting the configuration phases of the second part and randomly selecting the registers of the register module corresponding to each currently selected configuration phase in the second part, the registers of each of the at least one first register modules are directly constrained to fixed values.

7. The register randomization method as described in any one of claims 1 to 6, wherein, Serially selecting at least a portion of the configuration stages in the set of configuration stages, and randomly accessing the registers of the register module corresponding to each currently selected configuration stage in the set of at least a portion of the configuration stages, including: The configuration phases of at least some of the components are selected sequentially; For each currently selected configuration stage in at least one of the configuration stages: The currently selected configuration phase is passed recursively to each of the plurality of register modules; Compare the currently selected configuration phase with the configuration phase corresponding to each of the plurality of register modules; Randomization is performed on the current target register module among the plurality of register modules that has a configuration stage consistent with the currently selected configuration stage, so as to randomly configure each register in the current target register module.

8. The register randomization method as described in claim 7, wherein, In response to the current target register module including multiple registers, performing randomization on the current target register module to randomly configure each register in the current target register module includes: Each of the multiple registers in the current target register module is randomly configured in parallel.

9. The register randomization method as described in claim 7, wherein, At least one of the plurality of register modules includes a plurality of sub-register modules, and each sub-register module includes a plurality of registers.

10. The register randomization method as described in claim 9, wherein, In response to the current target register module comprising multiple sub-register modules, performing randomization on the current target register module to randomly configure each register in the current target register module includes: The multiple sub-register modules in the current target register module are randomly configured in parallel to randomly configure each register of each sub-register module.

11. The register randomization method as described in claim 7, wherein, In response to the current target register module comprising multiple registers with cross constraints, performing randomization on the current target register module to randomly configure each register in the current target register module includes: By adding additional constraints, the multiple registers with cross constraints in the current target register module are controlled to be randomly configured according to the additional constraints.

12. A verification method comprising the register randomization method as described in any one of claims 1 to 11.

13. A register random system for verification, comprising: A module is configured to establish multiple register modules based on the device to be verified, wherein each of the multiple register modules includes one or more registers; The configuration module is configured to set the configuration phase for each of the plurality of register modules; The acquisition module is configured to acquire the configuration phase of each of the plurality of register modules to obtain a set of configuration phases; A serial random module is configured to serially select at least a portion of the configuration stages in the set of configuration stages and randomly select the registers of the register module corresponding to each currently selected configuration stage in the set of at least a portion of the configuration stages. The configuration phase for each of the plurality of register modules includes: In the setup phase of each current register in each of the plurality of register modules, the configuration phase of the current register is recorded by setting a configuration phase variable, and each register in the same register module has the same configuration phase.

14. An electronic device comprising: Processor and memory, The memory stores a computer program, which, when executed by the processor, implements the register randomization method according to any one of claims 1 to 11.

15. A computer-readable storage medium, wherein, The storage medium stores a computer program, which, when executed by a processor, implements the register randomization method according to any one of claims 1 to 11.

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