A method, apparatus and related equipment for SoC chip testing
By building a hardware test layer for the SoC chip and deploying a pre-defined storage space, the accuracy problem of SoC chip system-level verification is solved, and system-level performance verification and a simplified testing environment are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
- Filing Date
- 2021-11-30
- Publication Date
- 2026-05-26
AI Technical Summary
In existing technologies, system-level verification of SoC chips is easily overlooked, leading to inaccurate chip verification results.
By building a hardware test layer for the SoC chip and deploying a preset storage space within it to store register configuration instructions, register configuration and device startup are achieved, and the chip test results are determined based on the running results.
It achieves system-level verification of SoC chips, ensuring the accuracy of chip verification results, and simplifies the construction of the test environment, making the test scenario closer to the real working scenario.
Smart Images
Figure CN114218882B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of hardware testing technology, and in particular to a method for testing SoC chips, as well as a device, equipment and computer-readable storage medium for testing SoC chips. Background Technology
[0002] SoC (System on Chip) technology integrates a CPU (Central Processing Unit / Processor), input / output peripherals, memory, and other functional peripherals onto a single chip. SoC technology can effectively reduce product area, improve product performance, reduce power consumption, and increase reliability, thus gaining widespread application. However, due to the high cost of chips, extensive and thorough verification is required before SoC chip fabrication to ensure functionality and performance.
[0003] Currently, SoC verification technology is divided into three parts: module-level, subsystem-level, and system-level verification. Among these three levels of verification technology, system-level verification is often overlooked, with people assuming that once module-level and subsystem-level verification is complete, there are few problems. However, system-level hardware and software simulation more realistically simulates real-world scenarios.
[0004] Therefore, how to achieve system-level SoC chip performance verification and ensure the accuracy of chip verification results is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0005] The purpose of this application is to provide a SoC chip testing method that can realize system-level SoC chip performance verification and ensure the accuracy of chip verification results. Another purpose of this application is to provide an SoC chip testing apparatus, device, and computer-readable storage medium, all of which have the above-mentioned beneficial effects.
[0006] Firstly, this application provides a method for testing a SoC chip, including:
[0007] When a verification command is received, a register configuration command is read from a preset storage space according to the verification command; wherein, the SoC chip is connected to the hardware test layer, and the preset storage space is deployed in the hardware test layer;
[0008] The registers are configured according to the register configuration instructions, and the various components and devices in the SoC chip are started after the registers are configured.
[0009] Obtain the operating results of each of the aforementioned components and devices, and determine the SoC chip inspection results based on the operating results.
[0010] Preferably, receiving the verification instruction includes:
[0011] When a reset signal is received, the verification instruction is responded to; wherein the reset signal is generated by the hardware test layer based on a test simulation script.
[0012] Preferably, the step of reading the register configuration instruction from the preset storage space according to the verification instruction includes:
[0013] According to the verification instruction, the register configuration instructions are read starting from the first address of the preset storage space until all the register configuration instructions have been read.
[0014] Preferably, configuring the registers according to the register configuration instructions includes:
[0015] The target register is determined according to the register configuration instructions;
[0016] The target register is configured via the BUS bus.
[0017] Preferably, determining the SoC chip inspection result based on each of the aforementioned operating results includes:
[0018] Generate corresponding waveform data based on the running results;
[0019] Determine whether the waveform data meets the preset waveform requirements;
[0020] If so, the SoC chip inspection result is determined to be a pass.
[0021] If not, then the SoC chip inspection result is determined to be an inspection failure.
[0022] Preferably, the SoC chip testing method further includes:
[0023] When the SoC chip fails the inspection, an alarm message is output.
[0024] Preferably, the register configuration instructions are binary instructions generated by the IDE compiler.
[0025] Secondly, this application also discloses a SoC chip testing device, comprising:
[0026] The instruction reading module is used to read register configuration instructions from a preset storage space according to the verification instruction when a verification instruction is received; wherein, the SoC chip is connected to the hardware test layer, and the preset storage space is deployed in the hardware test layer;
[0027] The register configuration module is used to configure registers according to the register configuration instructions, and to start the various components and devices in the SoC chip after the register configuration is completed.
[0028] The chip verification module is used to obtain the operating results of each of the aforementioned components and devices, and to determine the SoC chip inspection result based on the operating results.
[0029] Thirdly, this application also discloses a SoC chip testing device, comprising:
[0030] Memory, used to store computer programs;
[0031] A processor, used to execute the computer program to implement the steps of any of the SoC chip inspection methods described above.
[0032] Fourthly, this application also discloses a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the SoC chip testing methods described above.
[0033] The present application provides a SoC chip inspection method, which includes reading register configuration instructions from a preset storage space according to a verification instruction when a verification instruction is received; wherein the SoC chip is connected to a hardware test layer and the preset storage space is deployed in the hardware test layer; configuring registers according to the register configuration instructions, and starting each component device in the SoC chip after the register configuration is completed; obtaining the running results of each component device, and determining the SoC chip inspection result based on each running result.
[0034] By applying the technical solution provided in this application, a hardware test layer is pre-built for the SoC chip, and a preset storage space is deployed within it to store register configuration instructions. Therefore, when entering the SoC chip verification stage, the register configuration instructions can be directly read from the preset storage space, and register configuration can be completed, thereby starting the various components and devices in the SoC chip. Based on this, the performance test results of each component and device can be used to determine whether the SoC chip has passed. It is evident that this implementation method achieves system-level verification of the SoC chip through hardware and software co-verification. Furthermore, the test environment built based on this method is simple, easy to understand and construct, and makes the test scenario closely resemble the real working scenario of the SoC chip, effectively ensuring the accuracy of the chip verification results.
[0035] The SoC chip testing device, equipment, and computer-readable storage medium provided in this application all have the aforementioned beneficial effects, which will not be elaborated further here. Attached Figure Description
[0036] To more clearly illustrate the technical solutions in the prior art and the embodiments of this application, the accompanying drawings used in the description of the prior art and the embodiments of this application will be briefly introduced below. Of course, the accompanying drawings described below with respect to the embodiments of this application are only a part of the embodiments in this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort, and such other drawings also fall within the protection scope of this application.
[0037] Figure 1 A flowchart illustrating a SoC chip inspection method provided in this application;
[0038] Figure 2 This application provides a schematic diagram of the structure of a SoC chip.
[0039] Figure 3 This is a schematic diagram of a SoC chip simulation and verification architecture provided in this application.
[0040] Figure 4 This is a schematic diagram of a SoC chip testing device provided in this application;
[0041] Figure 5 This is a schematic diagram of the structure of a SoC chip testing device provided in this application. Detailed Implementation
[0042] The core of this application is to provide a SoC chip testing method, which can realize system-level performance verification of SoC chips and ensure the accuracy of chip verification results; another core aspect of this application is to provide an SoC chip testing device, a multi-controller server, and a computer-readable storage medium, which also have the above-mentioned beneficial effects.
[0043] To provide a clearer and more complete description of the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0044] This application provides a method for testing SoC chips.
[0045] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating a SoC chip inspection method provided in this application. The SoC chip inspection method may include:
[0046] S101: When a verification instruction is received, the register configuration instruction is read from the preset storage space according to the verification instruction; wherein, the SoC chip is connected to the hardware test layer, and the preset storage space is deployed in the hardware test layer;
[0047] This step aims to obtain register configuration instructions, which are used to configure corresponding registers in the SoC chip to enable the various components and devices within the SoC. Specifically, technicians can pre-write register configuration instructions based on the actual structure of the SoC chip and store them in a preset storage space. When a verification instruction is received, the register configuration instructions can be retrieved from this preset storage space. This preset storage space is deployed in a hardware test layer, which is connected to the SoC chip and provides a hardware testing environment for the SoC chip.
[0048] It is understood that the specific type of the preset storage space does not affect the implementation of this technical solution; as long as it can store register configuration instructions, this application does not impose any limitations on it. Furthermore, the number and type of register configuration instructions stored in the preset storage space are determined by the structure of the SoC chip itself, and this application also does not impose any limitations on them.
[0049] S102: Configure the registers according to the register configuration instructions, and start the various components and devices in the SoC chip after the registers are configured;
[0050] This step aims to configure the registers, thereby enabling the various components and devices within the SoC chip to start. Specifically, after reading the register configuration instructions from the preset storage space, the corresponding registers in the SoC chip can be configured according to these instructions. Furthermore, after the register configuration is complete, the various components and devices within the SoC chip can be started directly, allowing each component and device to enter normal operating mode.
[0051] S103: Obtain the operating results of each component device, and determine the SoC chip inspection result based on the operating results.
[0052] This step aims to determine the SoC chip's test result based on the operational results of each component within the SoC chip, i.e., whether the SoC chip's performance test has passed. Specifically, after starting each component within the SoC chip, the operational results of each component can be collected in real time. Furthermore, the SoC chip's test result is determined based on these results. In other words, when the operational results of each component meet their respective requirements, the SoC chip's test result is considered passed, indicating that the SoC chip's performance test is qualified. If the operational results of one or more components do not meet the corresponding requirements, the SoC chip's test result is considered failed, indicating that the SoC chip's performance test is unqualified.
[0053] As can be seen, the SoC chip verification method provided in this application pre-constructs a hardware test layer for the SoC chip and deploys a preset storage space within it for storing register configuration instructions. Therefore, when entering the SoC chip verification stage, the register configuration instructions can be directly read from the preset storage space, and register configuration can be completed, thereby starting the various components and devices within the SoC chip. Based on this, the performance test results of each component and device can be used to determine whether the SoC chip has passed. This implementation method achieves system-level verification of the SoC chip through hardware and software co-verification. Furthermore, the test environment built based on this method is simple, easy to understand and construct, and makes the test scenario closely resemble the real working scenario of the SoC chip, effectively ensuring the accuracy of the chip verification results.
[0054] In one embodiment of this application, receiving a verification instruction may include: responding to a verification instruction when a reset signal is received; wherein the reset signal is generated by the hardware test layer based on a test simulation script.
[0055] This application provides a method for responding to verification commands. Specifically, when a reset signal is received, the verification command can be automatically responded to. The reset signal is generated by the hardware test layer based on a test simulation script. That is, when the test simulation script starts running, the hardware test layer will automatically generate a reset signal, which will be received by the controller in the SoC chip, thereby automatically responding to the verification command and entering the verification stage of the SoC chip.
[0056] In one embodiment of this application, reading register configuration instructions from a preset storage space according to a verification instruction may include: reading register configuration instructions starting from the first address of the preset storage space according to the verification instruction until all register configuration instructions have been read.
[0057] This application provides a method for reading register configuration instructions from a preset storage space. Specifically, in the preset storage space, the register configuration instructions corresponding to each register can be stored sequentially according to their storage addresses. Thus, after obtaining a verification instruction, the first register configuration instruction can be obtained by reading from the first address of the preset storage space, and so on, until all the register configuration instructions stored in the preset storage space have been read.
[0058] In one embodiment of this application, register configuration according to register configuration instructions may include: determining a target register according to register configuration instructions; and configuring the target register via a BUS bus.
[0059] This application provides a register configuration method. It is understood that the preset storage space typically stores multiple register configuration instructions. To configure a corresponding register, after reading the register configuration instruction from the preset storage space, the target register can be determined according to the instruction. This target register is the register that needs to be configured, as indicated by the instruction, because the register configuration instruction necessarily contains relevant information about the register to be configured. Furthermore, after determining the target register, it can be configured according to the configuration information in the register configuration instruction.
[0060] In one embodiment of this application, determining the SoC chip inspection result based on each running result may include: generating corresponding waveform data based on the running result; determining whether the waveform data meets the preset waveform requirements; if yes, then determining that the SoC chip inspection result is a pass; if no, then determining that the SoC chip inspection result is a fail.
[0061] This application provides a method for determining the inspection result of a SoC chip. Specifically, the operating results produced by each component device can be output to a waveform device (such as an oscilloscope) through relevant interfaces in the SoC chip, such as the I2C interface (Inter-Integrated Circuit). The waveform data can then be checked for correctness, thereby determining whether the SoC chip inspection has passed. Clearly, the SoC chip inspection passes when the waveform data meets preset waveform requirements; otherwise, it fails.
[0062] Of course, the above implementation is only one implementation provided by the embodiments of this application, and is not the only one. For example, for the SPI (Serial Peripheral Interface) controller and DMA (Direct Memory Access) in the SoC chip, the determination can be made by data transfer and then data result comparison. Specifically, the UART (Universal Asynchronous Receiver / Transmitter) interface is connected to a UART module in the hardware test layer, and then the data in the SPI FLASH (FlashEEPROM Memory) is transferred to the UART interface output through DMA. Finally, the printed data in the UART module is compared with the actual data in the SPI FLASH. When the two are consistent, the SoC chip can be confirmed to have passed the test.
[0063] In one embodiment of this application, the SoC chip inspection method may further include: outputting an alarm prompt when the SoC chip inspection result is that the inspection fails.
[0064] The SoC chip testing method provided in this application can also implement an alarm function. Specifically, when the SoC chip fails the test, an alarm can be directly output to promptly inform the technicians that the SoC chip being tested is unqualified and needs to be returned to the factory for repair. The method of outputting the alarm is not unique; for example, it can be a voice prompt or an indicator light prompt. The technicians can set it according to the actual situation, and this application does not limit this.
[0065] In one embodiment of this application, the register configuration instruction can specifically be a binary instruction generated based on an IDE compiler (a type of compiler).
[0066] As mentioned above, technicians can pre-write register configuration instructions based on the actual structure of the SoC chip. Specifically, an IDE compiler can be used to compile these register configuration instructions, thereby obtaining the corresponding binary instructions and storing them in a preset memory space. The IDE compiler integrates low-level language functionality to translate C language into assembly language.
[0067] Based on the above implementation examples:
[0068] Please refer to Figure 2 , Figure 2This application provides a schematic diagram of the structure of a SoC chip. The SoC chip is a small SoC chip with a CPU microcore structure based on the AMBA bus architecture (Advanced Microcontroller Bus Architecture). The microcore is connected to the AHB bus (Advanced High performance Bus) via the ACE (Adaptive Communication Environment) bus. The AHB bus connects to high-speed devices such as DMA, SRAM (Static Random-Access Memory), and SPI flash controller. The high-speed bus is connected to the APB bus (Advanced Peripheral Bus) via a conversion bridge AHB2APB. The APB bus connects to some low-speed interface devices, such as UART interface and I2C interface.
[0069] Further, refer to Figure 3 , Figure 3 This is a schematic diagram of a SoC chip simulation and verification architecture provided in this application. Figure 3 The SoC chip simulation verification architecture shown is in Figure 2 Based on the SoC chip shown, a TOP layer for simulation verification, namely the hardware test layer, is added. This hardware test layer mainly integrates clock reset signals, a memory module (flash model), and some peripheral interface modules. The memory module is connected to the SPI flash controller in the SoC chip, providing the CPU with test stimulus command codes. Thus, a basic verification circuit environment is built.
[0070] (1) Configuration phase:
[0071] First, configure the IDE compiler environment. Then, write the configuration logic for the SoC chip's relevant registers in the C language's main function. Next, use the IDE compiler to compile the code to generate a binary .bin file for use by the SoC system. Finally, store the generated .bin file in the storage module.
[0072] (2) Testing phase:
[0073] First, the Makefile simulation script is started to run the simulation. Once running, the hardware test layer generates clock and reset signals and sends them to the SoC chip. Next, after the CPU in the SoC chip resets, it reads the binary instructions from the zero-address memory module by default, performs the calculations, and then sends register configuration information via the BUS bus to complete the register configuration, enabling the relevant devices in the SoC chip to function and achieve the desired scenario. Finally, the verification results of the SoC chip are determined based on the data generated by each device during operation. Clearly, because this verification process matches the actual operating scenario of the SoC chip, this simulation verification can better identify errors in the actual system scenario of the SoC chip.
[0074] As can be seen, the SoC chip verification method provided in this application pre-constructs a hardware test layer for the SoC chip and deploys a preset storage space within it for storing register configuration instructions. Therefore, when entering the SoC chip verification stage, the register configuration instructions can be directly read from the preset storage space, and register configuration can be completed, thereby starting each component device in the SoC chip. Based on this, the performance test of the SoC chip can be determined according to the operating results of each component device. It is evident that this implementation method achieves system-level verification of the SoC chip through hardware and software co-verification. Furthermore, the test environment constructed based on this implementation method is simple, easy to understand and construct, making the test scenario close to the real working scenario of the SoC chip, effectively ensuring the accuracy of the chip verification results.
[0075] This application provides a SoC chip testing device.
[0076] Please refer to Figure 4 , Figure 4 This is a schematic diagram of a SoC chip testing device provided in this application. The SoC chip testing device may include:
[0077] Instruction reading module 1 is used to read register configuration instructions from preset storage space according to the verification instructions when a verification instruction is received; wherein, the SoC chip is connected to the hardware test layer, and the preset storage space is deployed in the hardware test layer;
[0078] Register configuration module 2 is used to configure registers according to register configuration instructions and start the various components and devices in the SoC chip after the registers are configured.
[0079] Chip verification module 3 is used to obtain the operating results of each component device and determine the SoC chip inspection result based on the operating results.
[0080] As can be seen, the SoC chip verification device provided in this application pre-constructs a hardware test layer for the SoC chip and deploys a preset storage space within it for storing register configuration instructions. Therefore, when entering the SoC chip verification stage, the register configuration instructions can be directly read from the preset storage space, and register configuration can be completed, thereby starting the various components and devices in the SoC chip. Based on this, the performance test of the SoC chip can be determined according to the operating results of each component and device. It is evident that this implementation method achieves system-level verification of the SoC chip through hardware and software co-verification. Furthermore, the test environment constructed based on this implementation method is simple, easy to understand and construct, making the test scenario close to the real working scenario of the SoC chip, effectively ensuring the accuracy of the chip verification results.
[0081] In one embodiment of this application, the SoC chip testing device may further include a verification instruction receiving module, used to respond to a verification instruction when a reset signal is received; wherein the reset signal is generated by the hardware test layer based on a test simulation script.
[0082] In one embodiment of this application, the instruction reading module 1 described above can be specifically used to read register configuration instructions from the starting address of a preset storage space according to the verification instructions, until all register configuration instructions have been read.
[0083] In one embodiment of this application, the register configuration module 2 described above can be specifically used to determine the target register according to the register configuration instruction; and to configure the target register via the BUS bus.
[0084] In one embodiment of this application, the chip verification module 3 described above can be specifically used to generate corresponding waveform data based on the running results; determine whether the waveform data meets the preset waveform requirements; if yes, then determine that the SoC chip inspection result is that the inspection passed; if no, then determine that the SoC chip inspection result is that the inspection failed.
[0085] In one embodiment of this application, the SoC chip testing device may further include an alarm module for outputting an alarm prompt when the SoC chip testing result is that the testing fails.
[0086] In one embodiment of this application, the above-mentioned register configuration instructions may specifically be binary instructions generated based on the IDE compiler.
[0087] For a description of the device provided in this application, please refer to the above method embodiments; further details will not be provided here.
[0088] This application provides a SoC chip testing device.
[0089] Please refer to Figure 5 , Figure 5 This is a schematic diagram of a SoC chip testing device provided in this application. The SoC chip testing device may include:
[0090] Memory, used to store computer programs;
[0091] The processor, when executing a computer program, can implement the steps of any of the SoC chip testing methods described above.
[0092] like Figure 5 The diagram shows the structural composition of a SoC chip testing device. The SoC chip testing device may include: a processor 10, a memory 11, a communication interface 12, and a communication bus 13. The processor 10, memory 11, and communication interface 12 all communicate with each other through the communication bus 13.
[0093] In this embodiment, the processor 10 may be a central processing unit (CPU), an application-specific integrated circuit, a digital signal processor, a field-programmable gate array, or other programmable logic devices.
[0094] The processor 10 can call the program stored in the memory 11. Specifically, the processor 10 can execute the operations in the embodiments of the SoC chip inspection method.
[0095] The memory 11 is used to store one or more programs. The programs may include program code, which includes computer operation instructions. In this embodiment, the memory 11 stores at least a program for implementing the following functions:
[0096] When a verification command is received, the register configuration command is read from the preset storage space according to the verification command; wherein, the SoC chip is connected to the hardware test layer, and the preset storage space is deployed in the hardware test layer;
[0097] Configure the registers according to the register configuration instructions, and start the various components and devices in the SoC chip after the register configuration is completed;
[0098] Obtain the operating results of each component and device, and determine the SoC chip inspection results based on the operating results.
[0099] In one possible implementation, the memory 11 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; and the data storage area may store data created during use.
[0100] In addition, memory 11 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device or other volatile solid-state storage device.
[0101] Communication interface 12 can be an interface for the communication module, used to connect with other devices or systems.
[0102] Of course, it should be noted that, Figure 5 The structure shown does not constitute a limitation on the SoC chip testing equipment in the embodiments of this application. In practical applications, the SoC chip testing equipment may include more than Figure 5 More or fewer components as shown, or combinations of certain components.
[0103] This application provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement the steps of any of the SoC chip testing methods described above.
[0104] The computer-readable storage medium may include various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0105] For a description of the computer-readable storage medium provided in this application, please refer to the above method embodiments; further details will not be repeated here.
[0106] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.
[0107] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0108] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0109] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.
Claims
1. A method for testing SoC chips, characterized in that, The CPU microcore deployed in the SoC chip includes: When a verification command is received, a register configuration command is read from a preset storage space according to the verification command; wherein, the SoC chip is connected to the hardware test layer, and the preset storage space is deployed in the hardware test layer; Registers are configured according to the register configuration instructions, and after the registers are configured, each component device in the SoC chip is started so that all the component devices in the SoC chip enter the running state, and the SoC chip enters the working state. Obtain the operating results of each of the aforementioned components and devices, and determine the SoC chip inspection result based on the operating results. Receiving the verification instruction includes: responding to the verification instruction when a reset signal is received; wherein the reset signal is generated by the hardware test layer based on a test simulation script; The step of reading register configuration instructions from a preset storage space according to the verification instructions includes: reading the register configuration instructions starting from the first address of the preset storage space according to the verification instructions, until all the register configuration instructions have been read; The step of configuring the register according to the register configuration instruction includes: determining the target register according to the register configuration instruction; and configuring the target register via the BUS bus. The step of determining the SoC chip inspection result based on the operation results includes: generating corresponding waveform data based on the operation results; determining whether the waveform data meets the preset waveform requirements; if yes, then determining that the SoC chip inspection result is a pass; if no, then determining that the SoC chip inspection result is a fail.
2. The SoC chip inspection method according to claim 1, characterized in that, Also includes: When the SoC chip fails the inspection, an alarm message is output.
3. The SoC chip inspection method according to claim 1, characterized in that, The register configuration instructions are specifically binary instructions generated by the IDE compiler.
4. A SoC chip testing device, characterized in that, The CPU microcore deployed in the SoC chip includes: The instruction reading module is used to read register configuration instructions from a preset storage space according to the verification instruction when a verification instruction is received; wherein, the SoC chip is connected to the hardware test layer, and the preset storage space is deployed in the hardware test layer; The register configuration module is used to configure registers according to the register configuration instructions, and after the register configuration is completed, start each component device in the SoC chip so that all the component devices in the SoC chip enter the running state, and the SoC chip enters the working state. The chip verification module is used to obtain the operating results of each of the aforementioned components and devices, and to determine the SoC chip inspection result based on the operating results. It also includes a verification instruction receiving module, used to respond to the verification instruction when a reset signal is received; wherein the reset signal is generated by the hardware test layer based on a test simulation script; Specifically, the instruction reading module is used to read the register configuration instructions starting from the first address of the preset storage space according to the verification instructions, until all the register configuration instructions have been read. The register configuration module is specifically used to determine the target register according to the register configuration instruction; and to configure the target register via the BUS bus; The chip verification module is specifically used to generate corresponding waveform data based on the running results; determine whether the waveform data meets the preset waveform requirements; if yes, then determine that the SoC chip inspection result is a pass; if no, then determine that the SoC chip inspection result is a fail.
5. A SoC chip testing device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the SoC chip inspection method as described in any one of claims 1 to 3.
6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the SoC chip inspection method as described in any one of claims 1 to 3.