A Nand Flash testing method based on a general test platform for SOC

Abstract

The present invention relates to a Nand Flash testing method based on a general SOC testing platform, which includes: plugging a Nand Flash chip onto a test board through a socket; starting a chip power supply module to supply power to the Nand Flash chip; defining a test file and an auxiliary test file; a signal driving unit providing an enable signal for starting the Nand Flash chip to perform read, write, and erase operations and the data to be written; the Nand Flash chip performing erase, write, and read tests; and a signal measuring unit obtaining the waveforms output by the Nand Flash chip for calculation to determine whether the number of bad blocks exceeds a threshold. Through this method, read, write, and erase tests can be performed on various packages and various models of Nand Flash without an additional Nand Flash controller, reducing the intermediate testing links and greatly improving the testing reliability; this method can not only perform fixed characteristic verification tests, but also customize the test process according to requirements and provide test results, increasing the flexibility of Nand Flash testing, improving the testing efficiency, and reducing the testing cost.

Description

Technical Field

[0001] The present invention relates to the field of chip testing, and in particular to a method for testing Nand Flash based on a general-purpose SOC testing platform. Background Art

[0002] Nand Flash chips have rapidly emerged with their absolute advantages such as large capacity, fast read / write speed, and low price, and are widely used in mobile storage and big data storage services. In order to ensure that Nand Flash chips can work reliably for a long time, it is necessary to test Nand Flash chips. Traditional testing methods rely on evaluation boards provided by Nand Flash controller manufacturers or dedicated Nand Flash testing platforms. The software and hardware compatibility of evaluation boards or dedicated testing platforms developed by different controller manufacturers is poor, the development efficiency is low, the cost is high, and reliable testing of Nand Flash cannot be satisfied. Facing various controller manufacturers and their incompatible evaluation boards or dedicated testing platforms, it is difficult to test Nand Flash chips quickly, efficiently, and reliably. Secondly, due to the different processes of Nand Flash from different manufacturers, the characteristics of Nand Flash are also very different. Traditional methods only support testing of some fixed characteristics. For some special tests, traditional testing cannot be satisfied, and the development cycle is long, the software compatibility is poor, and the cost is high. Therefore, it is necessary to develop a method for testing Nand Flash based on a general-purpose testing platform to be able to complete the testing of Nand Flash quickly, efficiently, and reliably. Summary of the Invention

[0003] The task of the present invention is to provide a method for testing Nand Flash based on a general-purpose SOC testing platform. Through this method, read, write, and erase tests can be performed on Nand Flash of various packages and models without an additional Nand Flash controller, reducing the intermediate links of testing and greatly improving the testing reliability; this method can not only perform verification tests on fixed characteristics, but also customize the test process and provide test results, increasing the flexibility of Nand Flash testing, improving the testing efficiency, and reducing the testing cost.

[0004] In a first aspect of the present invention, in view of the problems existing in the prior art, the present invention provides a method for testing Nand Flash based on a general-purpose SOC testing platform, including:

[0005] Plug the Nand Flash chip onto the test board through a socket;

[0006] Start the chip power supply module to supply power to the Nand Flash chip;

[0007] Define test files and auxiliary test files;

[0008] The signal driving unit provides an enable signal for starting the read, write, and erase operations of the Nand Flash chip and the data to be written;

[0009] The Nand Flash chip performs erase, write, and read tests; and

[0010] The signal measurement unit acquires the waveforms output by the Nand Flash chip for calculation to determine whether the number of bad blocks exceeds a threshold.

[0011] In a preferred embodiment of the present invention, it is stipulated that the starting addresses of erase, write, and read are also included.

[0012] In another preferred embodiment of the present invention, it is stipulated that test interfaces are provided on the socket;

[0013] The pins of the chip are electrically connected to the test interfaces on the socket.

[0014] In still another preferred embodiment of the present invention, it is stipulated that the defined test files include:

[0015] Define a read test file, which is used for the block read operation of the Nand Flash chip;

[0016] Define a write test file, which is used for the block write operation of the Nand Flash chip;

[0017] Define an erase file, which is used for the block erase operation of the Nand Flash chip;

[0018] Define a test flow file, which stipulates the process of Nand Flash testing;

[0019] Define a configer file, which stipulates the connection order of the pins of the Nand Flash chip to the test interfaces;

[0020] Define a level file, which defines the logical relationship between the test signals output by the chip and the signals collected by the signal measurement unit;

[0021] Define a Timing file, which defines the relationship on the time axis; and

[0022] Define a limit file, which defines the threshold of the number of bad blocks.

[0023] In another preferred embodiment of the present invention, it is stipulated that the test files are stored in the test file library of the signal driving unit.

[0024] In yet another preferred embodiment of the present invention, it is stipulated that the NandFlash operation commands encapsulated in the interface encapsulation library in the signal driving unit include read, write, and erase.

[0025] In another preferred embodiment of the present invention, it is stipulated that the parameters of the operation commands include:

[0026] read(Block_Number, Read_Pattern),

[0027] write(Block_Number, Write_Pattern),

[0028] erase(Block_Number, Erase_Pattern),

[0029] wherein, Block_Number represents the block range for read, write, and erase operations;

[0030] Read_Pattern, Write_Pattern, Erase_Pattern represent the chip select signal CE, address signal ALE, command signal CLE, write enable signal WE, read enable signal RE, and data input / output signal I / O;

[0031] Read_Pattern, Write_Pattern, and Erase_Pattern define the test waveforms of different types of signals in different cycles and the waveforms output by the Nand Flash chip.

[0032] In yet another preferred embodiment of the present invention, it is stipulated that according to the test process defined in the flow file, erase, write, and read tests of the NandFlash chip are performed, including:

[0033] Calling the erase test file from the test file library to perform the block erase operation on the Nand Flash chip;

[0034] Calling the write test file from the test file library to perform the block write operation on the Nand Flash chip;

[0035] Calling the read test file from the test file library to perform the block read operation on the Nand Flash chip; and

[0036] Calling the DC class test file from the test file library to perform the working current and voltage tests on the Nand Flash chip.

[0037] In another preferred embodiment of the present invention, it is stipulated that if the number of bad blocks exceeds a specified threshold, the Nand Flash chip is determined to be unqualified;

[0038] If the number of bad blocks does not exceed the specified threshold, the Nand Flash chip is determined to be qualified.

[0039] In a second aspect of the present invention, in view of the problems existing in the prior art, the present invention provides a general-purpose SOC test platform for NandFlash testing, including:

[0040] A test board for testing the performance of the Nand Flash chip; a socket is provided on the test board for fixing the NandFlash chip on the test board;

[0041] A test channel, which is a circuit for connecting the host computer and the test board;

[0042] A host computer, which includes:

[0043] A chip power supply module for supplying power to the Nand Flash chip;

[0044] A signal measurement unit for receiving the waveform output by the Nand Flash chip, then performing calculations, and judging the measurement result of the NandFlash chip; and

[0045] A signal driving unit for providing an enable signal for the Nand Flash chip to start reading, writing, and erasing, and providing data written to the Nand Flash chip.

[0046] The present invention has at least the following beneficial effects: The present invention discloses a NandFlash testing method based on a general test platform. Through this method, read, write, and erase tests can be performed on various packages and various models of Nand Flash without an additional Nand Flash controller, reducing the intermediate links in testing and greatly improving the testing reliability; this method can not only perform fixed characteristic verification tests, but also customize the test process according to requirements and provide test results, increasing the flexibility of Nand Flash testing, improving the testing efficiency, and reducing the testing cost; the general test platform has a visual interface, clear parameters, and clear test items, is convenient to operate, and reduces the threshold of testing. Description of the Drawings

[0047] To further clarify the above and other advantages and features of the embodiments of the present invention, a more specific description of the embodiments of the present invention will be presented with reference to the accompanying drawings. It can be understood that these drawings only depict typical embodiments of the present invention and thus will not be considered as limiting its scope. In the drawings, for clarity, the same or corresponding components will be denoted by the same or similar reference numerals.

[0048] Figure 1 FIG. shows a schematic diagram of a Nand Flash test method according to the prior art.

[0049] Figure 2 FIG. shows a schematic diagram of a SOC general test platform for Nand Flash test according to an embodiment of the present invention.

[0050] Figure 3 FIG. shows a flowchart of a Nand Flash test method based on a SOC general test platform according to an embodiment of the present invention. Detailed Embodiments

[0051] It should be noted that the components in the drawings may be exaggerated for illustration purposes and are not necessarily drawn to scale.

[0052] In the present invention, the embodiments are only intended to illustrate the solutions of the present invention and should not be construed as restrictive.

[0053] In the present invention, unless otherwise specified, the quantifiers "a" and "one" do not exclude the scenario of multiple elements.

[0054] It should also be noted here that in the embodiments of the present invention, for clarity and simplicity, only a part of the components or assemblies may be shown. However, those of ordinary skill in the art can understand that, under the teaching of the present invention, the required components or assemblies can be added according to the specific scenario requirements.

[0055] It should also be noted here that within the scope of the present invention, the terms "the same", "equal", "equivalent", etc. do not mean that the two values are absolutely equal, but allow for a certain reasonable error. That is to say, the said terms also cover "substantially the same", "substantially equal", "substantially equivalent".

[0056] It should also be noted here that in the description of the present invention, the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than explicitly or implicitly indicating that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as explicitly or implicitly indicating relative importance.

[0057] In addition, the embodiments of the present invention describe the process steps in a specific order. However, this is only for the convenience of distinguishing each step and does not limit the order of the steps. In different embodiments of the present invention, the order of each step can be adjusted according to the adjustment of the process.

[0058] Figure 1 A schematic diagram of a Nand Flash test method according to the prior art is shown.

[0059] As Figure 1 shown, the mainstream Nand Flash test method at the present stage is as follows: First, the host computer controls the Nand Flash controller to output commands, and the host computer controller in the host computer controls the command execution module in the Nand Flash controller to execute the commands and output the signals required for Nand Flash read, write, erase and other commands. Secondly, after receiving the signals, Nand Flash performs read, write and erase tests. Finally, the data feedback module of the Nand Flash controller captures the test signals output by Nand Flash and uploads them to the host computer, and the data processing module of the host computer analyzes the data and visually displays the test operations.

[0060] Figure 2 A schematic diagram of a SOC general test platform for Nand Flash testing according to an embodiment of the present invention is shown.

[0061] As Figure 2 shown, the general test platform for testing Nand Flash includes:

[0062] A test board for testing the performance of the Nand Flash chip; a socket is provided on the test board for fixing the Nand Flash chip on the test board; a test interface is provided on the socket;

[0063] A test channel, which is a line for connecting the host computer and the test board;

[0064] A host computer, where the host computer includes:

[0065] A chip power supply module (DPS module) for supplying power to the Nand Flash chip;

[0066] A signal measurement unit for receiving the waveform output by the Nand Flash chip, then performing operations to judge the measurement result of the Nand Flash chip;

[0067] A signal driving unit for providing an enable signal for the Nand Flash chip to start chip read, write, and erase operations, and can also provide data to be written into the Nand Flash chip.

[0068] Figure 3 The flowchart of the Nand Flash test method based on the SOC general test platform according to an embodiment of the present invention is shown.

[0069] The Nand Flash test method based on the general test platform includes the following steps:

[0070] In step 1, the Nand Flash chip is plugged onto the test board through a socket. In an embodiment of the present invention, the pins of the chip are electrically connected to the test interfaces on the socket.

[0071] In step 2, start the chip power supply module to supply power to the Nand Flash chip.

[0072] In step 3, define the test file and the auxiliary test file. Defining the test file includes: defining the read test file, which is used for the block read operation of the Nand Flash chip; defining the write test file, which is used for the block write operation of the Nand Flash chip; defining the erase file, which is used for the block erase operation of the Nand Flash chip;

[0073] Define a test flow file, which stipulates the test process and operation command parameters of Nand Flash; define a configer file, which stipulates the connection sequence between the pins of the Nand Flash chip and the test interface. For example, the first pin is connected to the first test channel; define a level file, which defines the logical relationship between the test signals output by the chip and the signals collected by the signal measurement unit. For example, the range of high voltage and the range of low voltage; define a Timing file, which defines the relationship on the time axis. For example, the Timing file defines the operating frequencies of the chip for reading, writing, and erasing, that is, the cycle for reading, writing, and erasing a piece of data. The Timing file can also define the rising edge time and the falling edge time; define a limit file, which defines the threshold of the number of bad blocks. If the number of bad blocks exceeds the threshold, the NandFlash chip is determined to be unqualified.

[0074] In one embodiment of the present invention, the test files are stored in the test file library of the signal driving unit.

[0075] In step 4, the signal driving unit provides an enable signal for starting the Nand Flash chip to perform read, write, and erase operations, as well as the data to be written. The Nand Flash operation commands encapsulated in the interface encapsulation library in the signal driving unit include read, write, and erase. The operation command parameters include:

[0076] read(Block_Number, Read_Pattern),

[0077] write(Block_Number, Write_Pattern),

[0078] erase(Block_Number, Erase_Pattern),

[0079] Among them, Block_Number represents the block range for performing erase, write, and read operations; Read_Pattern, Write_Pattern, Erase_Pattern represent the chip select signal CE, address signal ALE, command signal CLE, write enable signal WE, and read enable signal RE, as well as the data input / output signal I / O; Read_Pattern, Write_Pattern, and Erase_Pattern define the test waveforms of the above different types of signals in different cycles and the waveforms output by the Nand Flash chip.

[0080] In step 5, determine the starting addresses for erasing, writing, and reading. The method for determining the addresses is as follows: Start addressing from the first address and traverse all the addresses until the last address.

[0081] In step 6, the Nand Flash chip performs erasing, writing, and reading tests. According to the test procedures defined in the flow file, perform the erasing, writing, and reading tests on the Nand Flash chip, including: calling the erasing test file from the test file library to perform the block erasing operation on the Nand Flash chip; calling the writing test file from the test file library to perform the block writing operation on the Nand Flash chip; calling the reading test file from the test file library to perform the block reading operation on the Nand Flash chip; calling the DC class test file to perform the working current and voltage tests on the Nand Flash chip.

[0082] In step 7, the signal measurement unit acquires the waveforms output by the Nand Flash chip for calculation to determine whether the number of bad blocks exceeds the threshold. If the number of bad blocks exceeds the specified threshold, the Nand Flash chip is determined to be unqualified; if the number of bad blocks is within the specified range of manual inspection of the chip, the Nand Flash chip is determined to be qualified.

[0083] The present invention has at least the following beneficial effects: The present invention discloses a method for testing Nand Flash based on a SOC general test platform. Through this method, read, write, and erase tests can be performed on various packages and various models of Nand Flash without an additional Nand Flash controller, reducing the intermediate links in the test and greatly improving the test reliability; this method can not only perform verification tests on fixed characteristics, but also customize the test procedures according to requirements and provide test results, increasing the flexibility of Nand Flash testing, improving the test efficiency, and reducing the test cost; the general test platform has a visual interface, clear parameters, and clear test items, which is convenient to operate and reduces the threshold of the test.

[0084] Although some embodiments of the present invention have been described in this application document, those skilled in the art can understand that these embodiments are merely shown as examples. Those skilled in the art can conceive of numerous variant schemes, alternative schemes, and improvement schemes under the teaching of the present invention without departing from the scope of the present invention. The appended claims are intended to define the scope of the present invention and thereby cover the methods and structures within the scope of these claims themselves and their equivalent transformations.

Claims

1. A Nand Flash testing method based on a general SOC testing platform, characterized in that, The SOC general test platform includes: A test board for testing the performance of Nand Flash chips; a socket is provided on the test board for fixing the Nand Flash chip on the test board; A test channel, which is a circuit for connecting the host computer and the test board; A host computer, which includes: A chip power supply module for supplying power to the Nand Flash chip; A signal measurement unit for receiving the waveform output by the Nand Flash chip, then performing calculations, and judging the measurement result of the Nand Flash chip; and A signal driving unit for providing an enable signal for the Nand Flash chip to start chip read, write, and erase operations, and providing data written to the Nand Flash chip; The Nand Flash test method includes: Plugging the Nand Flash chip onto the test board through the socket; Starting the chip power supply module to supply power to the Nand Flash chip; Defining test files and auxiliary test files; The signal driving unit provides an enable signal for starting the Nand Flash chip to perform read, write, and erase operations and the written data; The Nand Flash chip performs erase, write, and read tests; and The signal measurement unit obtains the waveform output by the Nand Flash chip for calculation to judge whether the number of bad blocks exceeds the threshold; No additional Nand Flash controller is required.

2. The Nand Flash testing method based on the SOC general testing platform according to claim 1, wherein, It also includes determining the start addresses of erase, write, and read.

3. The Nand Flash test method based on a general test platform according to claim 1, characterized in that, A test interface is provided on the socket; The pins of the chip are electrically connected to the test interface on the socket.

4. The Nand Flash testing method based on the SOC general testing platform according to claim 1, characterized in that The definition of the test files includes: Defining a read test file for block read operations of the Nand Flash chip; Defining a write test file for block write operations of the Nand Flash chip; Defining an erase file for block erase operations of the Nand Flash chip; Defining a test flow file, and the flow file specifies the process of Nand Flash testing; Defining a configer file, and the configer file specifies the connection order of the pins of the Nand Flash chip and the test interface; Defining a level file, and the level file defines the logical relationship between the test signals output by the chip and the signals collected by the signal measurement unit; Defining a Timing file, and the Timing file defines the relationship on the time axis; and Defining a limit file, and the limit file defines the threshold of the number of bad blocks.

5. The Nand Flash test method based on the SOC general test platform according to claim 4, characterized in that, The test files are stored in the test file library of the signal driving unit.

6. The Nand Flash test method based on the SOC general test platform according to claim 1, wherein The Nand Flash operation commands encapsulated in the interface encapsulation library in the signal driving unit include read, write, and erase.

7. The Nand Flash testing method based on the SOC general testing platform according to claim 6, characterized in that The parameters of the operation commands include: read(Block_Number, Read_Pattern), write(Block_Number, Write_Pattern), erase(Block_Number, Erase_Pattern), where Block_Number represents the block range for read, write, and erase operations; Read_Pattern, Write_Pattern, Erase_Pattern represent the chip select signal CE, address signal ALE, command signal CLE, write enable signal WE, read enable signal RE, and data input / output signal I / O; Read_Pattern, Write_Pattern, and Erase_Pattern define the test waveforms of different types of signals in different cycles and the waveforms output by the Nand Flash chip.

8. The Nand Flash testing method based on the SOC general testing platform according to claim 1, characterized in that According to the test process defined in the flow file, perform erase, write, and read tests on the Nand Flash chip, including: Call the erase test file from the test file library to perform the block erase operation on the Nand Flash chip; Call the write test file from the test file library to perform the block write operation on the Nand Flash chip; Call the read test file from the test file library to perform the block read operation on the Nand Flash chip; and Call the DC class test file from the test file library to perform the working current and voltage tests on the Nand Flash chip.

9. The Nand Flash testing method based on the SOC general testing platform according to claim 1, characterized in that If the number of bad blocks exceeds the specified threshold, the Nand Flash chip is determined to be unqualified; If the number of bad blocks does not exceed the specified threshold, the Nand Flash chip is determined to be qualified.

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