Power semiconductor devices

Abstract

This application provides a power semiconductor device comprising a silicon carbide substrate of a first conductivity type and a drift layer of the first conductivity type located above the substrate, and an active region, a termination region, and a main junction region located between the active region and the termination region disposed on the drift layer; the active region includes a plurality of first doped regions of a second conductivity type disposed at intervals within the surface of the drift layer, and a first metal layer and a second metal layer located above the drift layer; the main junction region includes a second doped region of the second conductivity type disposed within the surface of the drift layer, and a resistive layer covering a portion of the upper surface of the second doped region; the resistive layer has a positive temperature coefficient; the first metal layer, the second metal layer, and the resistive layer are electrically connected to each other. By providing a resistive layer with a positive temperature coefficient in the main junction region, surge current on the main junction of the chip is suppressed, reducing the risk of the main junction metal melting.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a power semiconductor device. Background Technology

[0002] Power semiconductor devices are the most basic building blocks of power electronic circuits. Among them, power diodes are frequently used in power electronic circuits. To improve the robustness of the circuit system, it is necessary to further enhance the robustness of power diodes. To withstand circuit anomalies, power diodes need to withstand very high surge currents. For example, in power factor correction (PFC) applications, there may be undetectable circuit faults in the system, and the charging current of the capacitor may reach more than seven times the forward current at a high frequency.

[0003] Among them, the silicon carbide junction barrier controlled Schottky (JBS) diode utilizes the space charge region expansion of the PN junction to protect the Schottky junction, thereby reducing leakage current at the Schottky contact on the SiC surface. However, in the design of power devices such as JBS diodes, due to process tolerance considerations, to ensure that the PN junction barrier region completely covers the Schottky electrode metal, the outermost PN junction is wider than the active PN junction, called the main junction region. However, this structure may cause the main junction region to turn on before the active PN junction when subjected to multiple surge currents. When the main junction region PN junction turns on, the current carried on the main junction increases rapidly due to the conductivity modulation effect, and the temperature of the main junction region rises further. Since the PN junction current has a negative temperature coefficient, thermal runaway occurs in the main junction region of the chip, causing the metal to melt and the chip to fail. Summary of the Invention

[0004] To address the aforementioned problems, this application provides a power semiconductor device that solves the technical problem that the main junction region of power devices is prone to failure under surge current in the prior art.

[0005] In a first aspect, this application provides a power semiconductor device, comprising: a first conductivity type substrate and a first conductivity type drift layer located above the substrate, and an active region, a terminal region, and a main junction region located between the active region and the terminal region disposed on the drift layer;

[0006] The active region includes a plurality of first doped regions of a second conductivity type spaced apart within the surface of the drift layer, and a first metal layer and a second metal layer located above the drift layer.

[0007] The first metal layer covers a portion of the upper surface of the first doped region and forms an ohmic contact with the first doped region; the second metal layer covers the portion of the upper surface of the drift layer not covered by the first doped region and forms a Schottky contact with that portion of the drift layer.

[0008] The main junction region includes a second doped region of a second conductivity type disposed within the surface of the drift layer, and a resistive layer covering a portion of the upper surface of the second doped region; the resistive layer has a positive temperature coefficient.

[0009] The first metal layer, the second metal layer, and the resistive layer are electrically connected to each other.

[0010] According to an embodiment of this application, optionally, in the above-described power semiconductor device, the main junction region further includes: a third metal layer that covers the upper surface of the resistive layer portion and forms an ohmic contact with the resistive layer.

[0011] According to an embodiment of this application, optionally, the power semiconductor device further includes: an anode metal layer located above the first metal layer, the second metal layer, and the third metal layer;

[0012] The anode metal layer is electrically connected to the first metal layer, the second metal layer, and the third metal layer.

[0013] According to an embodiment of this application, optionally, in the above-described power semiconductor device, the main junction region further includes a first passivation layer covering the resistive layer;

[0014] The first passivation layer has a contact hole that penetrates the first passivation layer, and the third metal layer fills the contact hole and forms an ohmic contact with the resistive layer portion at the bottom of the contact hole.

[0015] According to an embodiment of this application, optionally, in the power semiconductor device described above, the second metal layer further covers the portion of the upper surface of the resistive layer not covered by the third metal layer, and forms an ohmic contact with that portion of the resistive layer.

[0016] According to an embodiment of this application, optionally, in the power semiconductor device described above, the second metal layer further covers the portion of the upper surface of the first doped region not covered by the first metal layer, and forms an ohmic contact with that portion of the first doped region.

[0017] Optionally, in an embodiment of this application, the second metal layer is in contact with the first metal layer in the power semiconductor device described above.

[0018] According to an embodiment of this application, optionally, in the power semiconductor device described above, the second metal layer extends over the first metal layer.

[0019] Optionally, according to an embodiment of this application, in the power semiconductor device described above, the material of the resistive layer includes polycrystalline silicon.

[0020] According to an embodiment of this application, optionally, in the above-described power semiconductor device, the orthographic projection of the first doped region on the substrate is a strip, a square, or a hexagon.

[0021] Optionally, in an embodiment of this application, the width of the first doped region in the power semiconductor device is smaller than the width of the second doped region.

[0022] Optionally, according to an embodiment of this application, in the power semiconductor device described above, the doping concentration of the first doped region and the second doped region is the same.

[0023] Optionally, according to an embodiment of this application, in the power semiconductor device described above, the first doped region and the second doped region have the same depth.

[0024] According to an embodiment of this application, optionally, in the power semiconductor device described above, the terminal region includes a third doped region of a second conductivity type disposed within the surface of the drift layer, and a second passivation layer covering the upper surface of the third doped region.

[0025] According to an embodiment of this application, optionally, in the above-described power semiconductor device, the doping concentration of the third doped region is less than the doping concentration of the first doped region and the second doped region.

[0026] According to an embodiment of this application, optionally, in the power semiconductor device described above, the side of the third doped region closest to the second doped region is in contact with the second doped region.

[0027] Optionally, according to an embodiment of this application, the power semiconductor device further includes a cathode metal layer located below the substrate and electrically connected to the substrate.

[0028] By adopting the above technical solution, at least the following technical effects can be achieved:

[0029] This application provides a power semiconductor device comprising a silicon carbide substrate of a first conductivity type and a drift layer of the first conductivity type located above the substrate, and an active region, a termination region, and a main junction region located between the active region and the termination region disposed on the drift layer. The active region includes a plurality of first doped regions of a second conductivity type disposed at intervals within the surface of the drift layer, and a first metal layer and a second metal layer located above the drift layer. The main junction region includes a second doped region of the second conductivity type disposed within the surface of the drift layer, and a resistive layer covering a portion of the upper surface of the second doped region. The resistive layer has a positive temperature coefficient. The first metal layer, the second metal layer, and the resistive layer are electrically connected to each other. By providing a resistive layer with a positive temperature coefficient in the main junction region, surge current on the main junction of the chip is suppressed, the risk of the main junction metal melting is reduced, and the chip's ability to withstand multiple surge currents and the reliability of the chip in long-term application are improved. The resistance value of the resistive layer can be set as needed, thereby flexibly adjusting the magnitude of the surge current shared by the main junction. Furthermore, the resistive layer forms an electrical connection with the first metal layer and the second metal layer of the active region, which will not impair the reverse blocking capability of the chip. Attached Figure Description

[0030] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:

[0031] Figure 1 This is a schematic diagram of a cross-sectional structure of a power semiconductor device;

[0032] Figure 2 This is a front top view schematic diagram of a power semiconductor device illustrated in an exemplary embodiment of this application;

[0033] Figure 3 yes Figure 2 A schematic diagram of the cross-sectional structure along the tangent line A-A';

[0034] Figure 4 This is another front top view of a power semiconductor device shown in an exemplary embodiment of this application;

[0035] Figure 5 This is a front top view schematic diagram illustrating another power semiconductor device according to an exemplary embodiment of this application;

[0036] Figure 6 This is a front top view schematic diagram illustrating another power semiconductor device according to an exemplary embodiment of this application;

[0037] Figure 7 yes Figure 3 A schematic diagram of the potential connection of power semiconductor devices in the diagram;

[0038] Figure 8 This is a front top view schematic diagram illustrating another power semiconductor device according to an exemplary embodiment of this application;

[0039] Figure 9 yes Figure 8 A schematic diagram of the cross-sectional structure of a power semiconductor device in China;

[0040] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0041] The following detailed description of the embodiments of this application, in conjunction with the accompanying drawings, will provide a thorough understanding of how this application uses technical means to solve technical problems and achieve corresponding technical effects, enabling its implementation. The embodiments of this application and the various features within them can be combined with each other without conflict, and the resulting technical solutions are all within the protection scope of this application. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0042] It should be understood that although the terms "first," "second," "third," etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0043] It should be understood that spatial relation terms such as "above," "located above," "below," "located below," etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as "below other elements" will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0045] Embodiments of this application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, fabrication techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, fabrication. For example, implanted regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implanted to non-implanted regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of regions of the device and are not intended to limit the scope of this application.

[0046] To fully understand this application, a detailed structure will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0047] A power semiconductor device, such as Figure 1 As shown, it includes: substrate 11, drift layer 12, active region 13, main junction region 14, terminal region 15, anode metal layer 16, protective adhesive layer 17, and cathode metal layer 18.

[0048] The substrate 11 is a substrate of the first conductivity type and has a relatively thick thickness. The substrate 11 can be a silicon carbide substrate.

[0049] The drift layer 12 is a drift layer of the first conductivity type and is located above the substrate 11. The doping concentration and thickness of the drift layer 12 are adjusted according to the different voltage withstand capabilities of the chip. The doping concentration of the drift layer 12 can be less than the doping concentration of the substrate 11, and the thickness of the drift layer 12 can be less than the thickness of the substrate 11.

[0050] The active region 13, the main junction region 14 and the terminal region 15 are all located on the drift layer 12, with the main junction region 14 located between the active region 13 and the terminal region 15.

[0051] The active region 13 includes a plurality of active regions 131 of the second conductivity type first doped regions 131 spaced apart within the surface of the drift layer 12, and a first metal layer 132 and a second metal layer 133 located above the drift layer 12.

[0052] The first metal layer 132 covers part of the upper surface of the first doped region 131 and forms an ohmic contact with the first doped region 131.

[0053] The second metal layer 133 covers the portion of the upper surface of the drift layer 12 that is not covered by the first doped region 131, and forms a Schottky contact with that portion of the drift layer 12.

[0054] The main junction region 14 includes a second doped region 141 of a second conductivity type disposed within the surface of the drift layer 12, and a third metal layer 142 located above the second doped region 141. The width of the second doped region 141 is greater than the width of the first doped region 131.

[0055] The first metal layer 132, the second metal layer 133, and the third metal layer 142 are electrically connected through the anode metal layer 16 above them.

[0056] The terminal region 15 includes a third doped region 151 of a second conductivity type disposed within the surface of the drift layer 12, and a passivation layer 152 located above the third doped region 151.

[0057] The protective adhesive layer 17 covers the passivation layer 152 and part of the anodic metal layer 16.

[0058] The cathode metal layer 18 is located below the substrate 11 and forms an electrical connection with the substrate 11.

[0059] In this power semiconductor device, because the width of the second doped region 141 is greater than the width of the first doped region 131, the PN junction of the main junction region 14 is wider than the PN junction of the active region 13, ensuring that the PN junction barrier region is completely covered by the Schottky electrode metal (second metal layer 133). However, this structure can lead to the main junction region 14 turning on before the PN junction of the active region 13 when the chip is subjected to a forward surge current under multiple surge currents. When the PN junction of the main junction region 14 turns on, the current carried on the main junction increases rapidly due to the conductivity modulation effect, and the temperature of the main junction region 14 further rises. Since the PN junction current has a negative temperature coefficient, thermal runaway occurs in the main junction region of the chip, causing the metal to melt and the chip to fail.

[0060] Therefore, this application provides another power semiconductor device that can significantly improve the current distribution of the main junction under surge conditions and enhance the chip's ability to withstand surge current.

[0061] Example 1

[0062] Figure 2 This is a front top view schematic diagram of a power semiconductor device illustrated in an exemplary embodiment of this application.

[0063] Figure 3 This is a schematic cross-sectional view of a power semiconductor device illustrated in an exemplary embodiment of this application. Figure 2 and 3 As shown, this application provides a power semiconductor device, including a substrate 21, a drift layer 22, an active region 23, a main junction region 24, a terminal region 25, an anode metal layer 26, a protective adhesive layer 27, and a cathode metal layer 28.

[0064] The substrate 21 is a substrate of the first conductivity type and has a relatively thick thickness. The substrate 21 can be a silicon carbide substrate.

[0065] The drift layer 22 is a drift layer of the first conductivity type and is located above the substrate 21. The doping concentration and thickness of the drift layer 22 are adjusted according to the different voltage withstand capabilities of the chip. The doping concentration of the drift layer 22 can be less than the doping concentration of the substrate 21, and the thickness of the drift layer 22 can be less than the thickness of the substrate 21.

[0066] The active region 23, the main junction region 24 and the terminal region 25 are all located on the drift layer 22, with the main junction region 24 located between the active region 23 and the terminal region 25.

[0067] The active region 23 includes a plurality of first doped regions 231 of the second conductivity type spaced apart within the surface of the drift layer 22, and a first metal layer 232 and a second metal layer 233 located above the drift layer 22.

[0068] The first metal layer 232 covers a portion of the upper surface of the first doped region 231 and forms an ohmic contact with the first doped region 231. Furthermore, the first metal layer 232 does not contact the portion of the drift layer 22 not covered by the first doped region 231.

[0069] The material of the first metal layer 232 includes metals with low contact resistivity such as aluminum and nickel.

[0070] The second metal layer 233 covers the portion of the upper surface of the drift layer 22 that is not covered by the first doped region 231, and forms a Schottky contact with that portion of the drift layer 22.

[0071] Furthermore, the second metal layer 233 also covers the portion of the upper surface of the resistor layer 242 that is not covered by the third metal layer 243, and forms an ohmic contact with that portion of the resistor layer 242.

[0072] Furthermore, the second metal layer 233 is in contact with the first metal layer 232, and the second metal layer 233 may even extend above the first metal layer 232.

[0073] The material of the second metal layer 233 includes metals such as titanium, nickel, and molybdenum.

[0074] The main junction region 24 includes a second doped region 241 of a second conductivity type disposed within the surface of the drift layer 22, and a resistive layer 242 covering a portion of the upper surface of the second doped region 241; the resistive layer 242 has a positive temperature coefficient.

[0075] The first metal layer 232, the second metal layer 233, and the resistor layer 242 are electrically connected to each other.

[0076] In this embodiment, a resistive layer 242 with a positive temperature coefficient is provided in the main junction region 24. This resistive layer 242 has both conductivity and a positive temperature coefficient. During reverse blocking of the chip, the main junction region 24 is connected to the first metal layer 232 and the second metal layer 233 through the resistive layer 242, without changing the potential distribution of the main junction. Therefore, the reverse blocking capability of the chip is unaffected. When the chip is subjected to high surge current, the resistive layer 242, with its positive temperature coefficient, can suppress the current shared on the main junction to a certain extent, thereby reducing the risk of the metal (third metal layer 243) on the main junction melting, thus improving the chip's ability to withstand multiple surge currents and the reliability of the chip in long-term applications.

[0077] Furthermore, the material of the resistive layer 242 includes polycrystalline silicon. The thickness of the resistive layer 242 is set to be 50 nm or more, preferably N-type polycrystalline silicon, and its doping concentration can be adjusted according to the actual device requirements, up to 1E12 cm. -3 above.

[0078] The resistance value of the resistive layer 242 can be adjusted by the doping concentration, thereby flexibly adjusting the magnitude of the surge current shared by the main junction.

[0079] Furthermore, the main junction region 24 also includes a third metal layer 243 that covers part of the upper surface of the resistor layer 242 and forms an ohmic contact with the resistor layer 242.

[0080] Furthermore, the second metal layer 233 also covers the portion of the upper surface of the resistor layer 242 that is not covered by the third metal layer 243, and forms an ohmic contact with that portion of the resistor layer 242.

[0081] Moreover, the width of the second doped region 241 is greater than the width of the first doped region 231, so even with process errors, the PN junction of the active region 23 is completely covered by the Schottky electrode metal (second metal layer 233).

[0082] In this application, the setting of the resistive layer 242 in the main junction region 24 not only ensures that the PN junction of the active region 23 is completely covered by the Schottky electrode metal (second metal layer 233), but also suppresses the surge current on the chip main junction and reduces the risk of the main junction metal being melted.

[0083] The anode metal layer 26 is located above the first metal layer 232, the second metal layer 233 and the third metal layer 243, and simultaneously forms an electrical connection with the first metal layer 232, the second metal layer 233 and the third metal layer 243.

[0084] The aforementioned anode metal layer 26 has a relatively thick thickness, which can be 2 to 6 μm.

[0085] It can be understood that the first metal layer 232, the second metal layer 233 and the third metal layer 243 are electrically connected to each other through the anode metal layer 26.

[0086] In some cases, the first doped region 231 and the second doped region 241 have the same doping concentration and the same depth.

[0087] The first doped region 231 and the second doped region 241 can be prepared by the same ion implantation process.

[0088] In this embodiment, as Figure 4 As shown, the orthographic projection of the first doped region 231 on the substrate 21 is a stripe shape, wherein the stripe shape means that the plurality of first doped regions 231 extend along the first direction and are arranged along the second direction perpendicular to the first direction.

[0089] Or, such as Figure 5 As shown, the orthographic projection of the first doped region 231 onto the substrate 21 is square, where the square can be either a square or a rectangle, which can be understood as... Figure 4 The first doped region 231 in the middle strip is truncated into multiple square doped regions.

[0090] Or, such as Figure 6 As shown, the orthographic projection of the first doped region 231 onto the substrate 21 is hexagonal.

[0091] In this embodiment, the terminal region 25 includes a third doped region 251 of a second conductivity type disposed in the surface of the drift layer 22, and a second passivation layer 252 covering the upper surface of the third doped region 251.

[0092] The doping concentration of the third doped region 251 is less than that of the first doped region 231 and the second doped region 241.

[0093] Furthermore, the side of the third doped region 251 closest to the second doped region 241 is in contact with the second doped region 241.

[0094] Furthermore, the second passivation layer 252 can extend toward the main junction region 24, extending above the resistor layer 242 and covering part of the upper surface of the resistor layer 242.

[0095] The material of the second passivation layer 252 can be insulating materials such as SiO2, SIPOS, and SiON.

[0096] The cathode metal layer 28 is located below the substrate 21 and forms an electrical connection with the substrate 21. The material of the cathode metal layer 28 can be a metal with low contact resistivity, such as aluminum.

[0097] The electrical connections between the aforementioned metal layers are as follows: Figure 7 As shown, the first metal layer 232, the second metal layer 233 and the third metal layer 243 are connected to the same electrical signal through the anode metal layer 26.

[0098] The protective adhesive layer 27 covers the passivation layer and part of the anodic metal layer 26.

[0099] In this embodiment, the power semiconductor device can be a silicon carbide junction barrier Schottky (JBS) diode.

[0100] In this embodiment, the first conductivity type and the second conductivity type are opposite. For example, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P-type, the second conductivity type is N-type. Specifically, the appropriate type can be selected based on the actual device type to be fabricated.

[0101] This application provides a power semiconductor device, which includes a silicon carbide substrate 21 of a first conductivity type and a drift layer 22 of a first conductivity type located above the substrate 21, as well as an active region 23, a terminal region 25, and a main junction region 24 located between the active region 23 and the terminal region 25 disposed on the drift layer 22; the active region 23 includes a plurality of first doped regions 231 of a second conductivity type disposed at intervals within the surface of the drift layer 22, and a first metal layer 232 and a second metal layer 233 located above the drift layer 22; the main junction region 24 includes a second doped region 241 of a second conductivity type disposed within the surface of the drift layer 22, and a resistive layer 242 covering a portion of the upper surface of the second doped region 241; the resistive layer 242 has a positive temperature coefficient; the first metal layer 232, the second metal layer 233, and the resistive layer 242 are electrically connected to each other. By providing a resistive layer 242 with a positive temperature coefficient in the main junction region 24, surge current on the chip's main junction is suppressed, reducing the risk of the main junction metal (third metal layer 243) melting, and improving the chip's ability to withstand multiple surge currents and its long-term reliability. The resistance value of this resistive layer 242 can be set as needed, thereby flexibly adjusting the magnitude of the surge current shared by the main junction. Moreover, the resistive layer 242 forms an electrical connection with the first metal layer 232 and the second metal layer 233 of the active region 23, without compromising the chip's reverse blocking capability.

[0102] Example 2

[0103] Figure 8 This is a front top view schematic diagram illustrating another power semiconductor device according to an exemplary embodiment of this application.

[0104] Figure 9 This is a schematic cross-sectional view of another power semiconductor device illustrated in an exemplary embodiment of this application. Figure 8 and 9 As shown, this application provides a power semiconductor device, including a substrate 21, a drift layer 22, an active region 23, a main junction region 24, a terminal region 25, an anode metal layer 26, a protective adhesive layer 27, and a cathode metal layer 28.

[0105] The substrate 21 is of the first conductivity type and has a relatively thick thickness. The substrate 21 can be a silicon carbide substrate.

[0106] The drift layer 22 is a drift layer of the first conductivity type and is located above the substrate 21. The doping concentration and thickness of the drift layer 22 are adjusted according to the different voltage withstand capabilities of the chip. The doping concentration of the drift layer 22 can be less than the doping concentration of the substrate 21, and the thickness of the drift layer 22 can be less than the thickness of the substrate 21.

[0107] The active region 23, the main junction region 24 and the terminal region 25 are all located on the drift layer 22, with the main junction region 24 located between the active region 23 and the terminal region 25.

[0108] The active region 23 includes a plurality of first doped regions 231 of the second conductivity type spaced apart within the surface of the drift layer 22, and a first metal layer 232 and a second metal layer 233 located above the drift layer 22.

[0109] The first metal layer 232 covers a portion of the upper surface of the first doped region 231 and forms an ohmic contact with the first doped region 231. Furthermore, the first metal layer 232 does not contact the portion of the drift layer 22 not covered by the first doped region 231.

[0110] The material of the first metal layer 232 includes metals with low contact resistivity such as aluminum and nickel.

[0111] The second metal layer 233 covers the portion of the upper surface of the drift layer 22 that is not covered by the first doped region 231, and forms a Schottky contact with that portion of the drift layer 22.

[0112] Furthermore, the second metal layer 233 also covers the portion of the upper surface of the resistor layer 242 that is not covered by the third metal layer 243, and forms an ohmic contact with that portion of the resistor layer 242.

[0113] Furthermore, the second metal layer 233 is in contact with the first metal layer 232, and the second metal layer 233 may even extend above the first metal layer 232.

[0114] The material of the second metal layer 233 includes metals such as titanium, nickel, and molybdenum.

[0115] The main junction region 24 includes a second doped region 241 of a second conductivity type disposed within the surface of the drift layer 22, and a resistive layer 242 covering a portion of the upper surface of the second doped region 241; the resistive layer 242 has a positive temperature coefficient.

[0116] The first metal layer 232, the second metal layer 233, and the resistor layer 242 are electrically connected to each other.

[0117] In this embodiment, a resistive layer 242 with a positive temperature coefficient is provided in the main junction region 24. This resistive layer 242 has both conductivity and a positive temperature coefficient. During reverse blocking of the chip, the main junction region 24 is connected to the first metal layer 232 and the second metal layer 233 through the resistive layer 242, without changing the potential distribution of the main junction. Therefore, the reverse blocking capability of the chip is unaffected. When the chip is subjected to high surge current, the resistive layer 242, with its positive temperature coefficient, can suppress the current shared on the main junction to a certain extent, thereby reducing the risk of the metal (third metal layer 243) on the main junction melting, thus improving the chip's ability to withstand multiple surge currents and the reliability of the chip in long-term applications.

[0118] Furthermore, the material of the resistive layer 242 includes polycrystalline silicon. The thickness of the resistive layer 242 is set to be 50 nm or more, preferably N-type polycrystalline silicon, and its doping concentration can be adjusted according to the actual device requirements, up to 1E12 cm. -3 above.

[0119] The resistance value of the resistive layer 242 can be adjusted by the doping concentration, thereby flexibly adjusting the magnitude of the surge current shared by the main junction.

[0120] In this embodiment, the main junction region 24 further includes a first passivation layer 244 covering the resistive layer 242; wherein, a contact hole 245 penetrating the first passivation layer 244 is provided on the first passivation layer 244.

[0121] The main junction region 24 further includes a third metal layer 243 that covers a portion of the upper surface of the resistive layer 242 and forms an ohmic contact with the resistive layer 242. The third metal layer 243 fills the contact hole 245 and forms an ohmic contact with a portion of the resistive layer 242 at the bottom of the contact hole 245.

[0122] The number of contact holes 245 can be multiple, such as... Figure 8 As shown.

[0123] Correspondingly, in this embodiment, the contact resistance between the resistive layer 242 and the second doped region 241 can be adjusted by designing the size and number of contact holes 245.

[0124] Furthermore, the second metal layer 233 also covers the portion of the upper surface of the resistor layer 242 that is not covered by the third metal layer 243, and forms an ohmic contact with that portion of the resistor layer 242.

[0125] Moreover, the width of the second doped region 241 is greater than the width of the first doped region 231, so even with process errors, the PN junction of the active region 23 is completely covered by the Schottky electrode metal (second metal layer 233).

[0126] In this application, the setting of the resistive layer 242 in the main junction region 24 not only ensures that the PN junction of the active region 23 is completely covered by the Schottky electrode metal (second metal layer 233), but also suppresses the surge current on the chip main junction and reduces the risk of the main junction metal (third metal layer 243) melting.

[0127] The anode metal layer 26 is located above the first metal layer 232, the second metal layer 233 and the third metal layer 243, and simultaneously forms an electrical connection with the first metal layer 232, the second metal layer 233 and the third metal layer 243.

[0128] The aforementioned anode metal layer 26 has a relatively thick thickness, which can be 2 to 6 μm.

[0129] It can be understood that the first metal layer 232, the second metal layer 233 and the third metal layer 243 are electrically connected to each other through the anode metal layer 26.

[0130] In some cases, the first doped region 231 and the second doped region 241 have the same doping concentration and the same depth.

[0131] The first doped region 231 and the second doped region 241 can be prepared by the same ion implantation process.

[0132] In this embodiment, the orthogonal projection of the first doped region 231 on the substrate 21 is a stripe shape, wherein the stripe shape means that the plurality of first doped regions 231 extend along the first direction and are arranged along the second direction perpendicular to the first direction.

[0133] Alternatively, the orthographic projection of the first doped region 231 onto the substrate 21 is square, where the square can be a square or a rectangle, which can be understood as cutting the above-mentioned strip-shaped first doped region 231 into multiple square doped regions.

[0134] Alternatively, the orthographic projection of the first doped region 231 onto the substrate 21 is hexagonal.

[0135] In this embodiment, the terminal region 25 includes a third doped region 251 of a second conductivity type disposed in the surface of the drift layer 22, and a second passivation layer 252 covering the upper surface of the third doped region 251.

[0136] The doping concentration of the third doped region 251 is less than that of the first doped region 231 and the second doped region 241.

[0137] Furthermore, the side of the third doped region 251 closest to the second doped region 241 is in contact with the second doped region 241.

[0138] Furthermore, the second passivation layer 252 can extend toward the main junction region 24, extending above the resistor layer 242 and covering part of the upper surface of the resistor layer 242.

[0139] The material of the second passivation layer 252 can be insulating materials such as SiO2, SIPOS, and SiON.

[0140] The cathode metal layer 28 is located below the substrate 21 and forms an electrical connection with the substrate 21. The material of the cathode metal layer 28 can be a metal with low contact resistivity, such as aluminum.

[0141] The protective adhesive layer 27 covers the passivation layer and part of the anodic metal layer 26.

[0142] In this embodiment, the power semiconductor device can be a silicon carbide junction barrier Schottky (JBS) diode.

[0143] In this embodiment, the first conductivity type and the second conductivity type are opposite. For example, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P-type, the second conductivity type is N-type. Specifically, the appropriate type can be selected based on the actual device type to be fabricated.

[0144] This application provides a power semiconductor device, which includes a silicon carbide substrate 21 of a first conductivity type and a drift layer 22 of a first conductivity type located above the substrate 21, as well as an active region 23, a terminal region 25, and a main junction region 24 located between the active region 23 and the terminal region 25 disposed on the drift layer 22; the active region 23 includes a plurality of first doped regions 231 of a second conductivity type disposed at intervals within the surface of the drift layer 22, and a first metal layer 232 and a second metal layer 233 located above the drift layer 22; the main junction region 24 includes a second doped region 241 of a second conductivity type disposed within the surface of the drift layer 22, and a resistive layer 242 covering a portion of the upper surface of the second doped region 241; the resistive layer 242 has a positive temperature coefficient; the first metal layer 232, the second metal layer 233, and the resistive layer 242 are electrically connected to each other. By setting a resistive layer 242 with a positive temperature coefficient in the main junction region 24, surge current on the chip's main junction is suppressed, reducing the risk of the main junction metal melting and improving the chip's ability to withstand multiple surge currents and its long-term reliability. The resistance value of this resistive layer 242 can be set as needed, thereby flexibly adjusting the magnitude of the surge current shared by the main junction. Moreover, the resistive layer 242 forms an electrical connection with the first metal layer 232 and the second metal layer 233 of the active region 23, without compromising the chip's reverse blocking capability.

[0145] Example 3

[0146] Based on Embodiment 1 or 2, this embodiment provides another power semiconductor device, including a substrate 21, a drift layer 22, an active region 23, a main junction region 24, a terminal region 25, an anode metal layer 26, a protective adhesive layer 27, and a cathode metal layer 28.

[0147] In this embodiment, the first base region is an N+ substrate 21 with a doping concentration of 1E18 to 1E19 cm⁻¹. -3 The doping concentration of the N+ substrate is optimized based on the chip's blocking voltage.

[0148] Drift layer 22 is an N-drift layer with a doping concentration of 1E14 to 5E16 cm⁻¹. -3 .

[0149] The active region 23 includes a plurality of first doped regions 231 of the second conductivity type spaced apart within the surface of the drift layer 22, and a first metal layer 232 and a second metal layer 233 located above the drift layer 22.

[0150] The main junction region 24 includes a second doped region 241 of a second conductivity type disposed within the surface of the drift layer 22, and a resistive layer 242 covering a portion of the upper surface of the second doped region 241; the resistive layer 242 has a positive temperature coefficient.

[0151] Both the first doped region 231 and the second doped region 241 are P+ doped regions with a doping concentration greater than or equal to 1E18cm. -3 The depth is 0.5–2 μm.

[0152] In some cases, the first doped region 231 and the second doped region 241 are formed by the same ion implantation and have the same concentration and depth.

[0153] The resistive layer 242 can be made of N-type polysilicon, and its doping concentration can be adjusted according to the actual device requirements, up to 1E12cm. -3 The thickness is above 50nm.

[0154] The terminal region 25 includes a third doped region 251 of a second conductivity type disposed within the surface of the drift layer 22, and a second passivation layer 252 covering the upper surface of the third doped region 251.

[0155] The third doped region 251 is entirely P-doped, with a doping concentration of 5E16 to 1E18 cm⁻¹. -3 .

[0156] The positional relationships of the above-mentioned components are the same as in Embodiment 1 or 2, and will not be repeated in this embodiment.

[0157] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the scope of protection of this application. Although the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and variations in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A power semiconductor device, characterized in that, include: A first conductivity type substrate and a first conductivity type drift layer located above the substrate, and an active region, a terminal region and a main junction region located between the active region and the terminal region disposed on the drift layer; The active region includes a plurality of first doped regions of a second conductivity type spaced apart within the surface of the drift layer, and a first metal layer and a second metal layer located above the drift layer. The first metal layer covers a portion of the upper surface of the first doped region and forms an ohmic contact with the first doped region; the second metal layer covers the portion of the upper surface of the drift layer not covered by the first doped region and forms a Schottky contact with that portion of the drift layer. The main junction region includes a second doped region of a second conductivity type disposed within the surface of the drift layer, and a resistive layer covering a portion of the upper surface of the second doped region; the resistive layer has a positive temperature coefficient. The first metal layer, the second metal layer, and the resistive layer are electrically connected to each other; The main junction region further includes: a third metal layer that covers the upper surface of the resistive layer portion and forms an ohmic contact with the resistive layer; The second metal layer also covers the portion of the upper surface of the resistive layer not covered by the third metal layer, and forms an ohmic contact with that portion of the resistive layer.

2. The power semiconductor device according to claim 1, characterized in that, It also includes: an anode metal layer located above the first metal layer, the second metal layer and the third metal layer; The anode metal layer is electrically connected to the first metal layer, the second metal layer, and the third metal layer.

3. The power semiconductor device according to claim 1, characterized in that, The main junction region also includes a first passivation layer covering the resistive layer; The first passivation layer has a contact hole that penetrates the first passivation layer, and the third metal layer fills the contact hole and forms an ohmic contact with the resistive layer portion at the bottom of the contact hole.

4. The power semiconductor device according to claim 1, characterized in that, The second metal layer also covers the portion of the upper surface of the first doped region not covered by the first metal layer, and forms an ohmic contact with that portion of the first doped region.

5. The power semiconductor device according to claim 4, characterized in that, The second metal layer is in contact with the first metal layer.

6. The power semiconductor device according to claim 5, characterized in that, The second metal layer extends over the first metal layer.

7. The power semiconductor device according to claim 1, characterized in that, The resistive layer is made of polycrystalline silicon.

8. The power semiconductor device according to claim 1, characterized in that, The orthographic projection of the first doped region onto the substrate is in the shape of a bar, a square, or a hexagon.

9. The power semiconductor device according to claim 1, characterized in that, The width of the first doped region is smaller than the width of the second doped region.

10. The power semiconductor device according to claim 1, characterized in that, The first doped region and the second doped region have the same doping concentration.

11. The power semiconductor device according to claim 1, characterized in that, The first doped region and the second doped region have the same depth.

12. The power semiconductor device according to claim 1, characterized in that, The terminal region includes a third doped region of a second conductivity type disposed within the surface of the drift layer, and a second passivation layer covering the upper surface of the third doped region.

13. The power semiconductor device according to claim 12, characterized in that, The doping concentration of the third doped region is less than that of the first doped region and the second doped region.

14. The power semiconductor device according to claim 12, characterized in that, The third doped region is in contact with the second doped region on the side closest to the second doped region.

15. The power semiconductor device according to claim 1, characterized in that, It also includes a cathode metal layer located below the substrate and electrically connected to the substrate.

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