A gate bus structure and trench gate chip

Abstract

The present invention provides a gate bus structure and a trench gate chip, wherein the gate bus structure comprises: a well region with a second conductivity type formed above a drift region of a first conductivity type, the well region intersecting with a cell region trench extending from a cell region, and a plurality of gate bus trenches at a set angle to the cell region trench direction formed in the well region to alleviate the warping of the trench gate chip; an insulating layer formed above the well region; and a gate signal conduction layer formed above the insulating layer. By introducing a plurality of gate bus trenches at a certain angle to the cell region trench in the well region, the warping caused by the trench gate chip during the processing can be effectively alleviated, and the preparation process is fully compatible with the original process, has no impact on the original process, and is easy to implement.

Description

Technical Field

[0001] The present invention belongs to the technical field of trench gate chips, and in particular relates to a gate bus structure and a trench gate chip. Background Art

[0002] Chips such as IGBT have two common structures: planar gate and trench gate. IGBT (Insulated Gate Bipolar Transistor) combines the advantages of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and BJT (Bipolar Junction Transistor), and has the characteristics of low on-state voltage drop, high breakdown voltage, strong short-circuit tolerance, high switching frequency and low driving power. Therefore, it is widely used in almost all fields involving power conversion and transmission. Compared with the planar gate structure, the trench gate structure has a higher current density and stronger anti-latch capability, so it has become the mainstream structure of chips such as IGBT. However, while the trench gate chip brings performance advantages, it also puts forward higher requirements on the manufacturing process. The stress problem in the chip wafer manufacturing process is one of the difficulties faced by the trench gate chip.

[0003] The gate electrode material of trench gate chips (such as trench gate IGBT) is usually polysilicon. The polysilicon filled in the trench becomes more crystallized during the thermal process of the subsequent process, and the thermal expansion coefficient does not match that of the underlying material, which will generate large stress in the direction perpendicular to the trench on the wafer, causing the wafer to warp, affecting the transmission and processing of the wafer, and even causing fragments. With the development trend of chip trench refinement, the trench density will become larger and larger, and the above-mentioned warping problem will become more and more serious.

[0004] Although some related technologies can improve the stress and warping problems in the trench gate IGBT wafer manufacturing process to a certain extent, they also face great limitations, that is, the IGBT chip can only be square, because the non-square chip structure will bring great inconvenience to wafer dicing or groove arrangement. In actual applications, due to the different current densities required in different application fields and the limitations of the liner and module structure layout, the IGBT chip is not necessarily square in appearance, but may appear as a rectangular appearance of different sizes. Although the grooves of the folding line structure in other related technologies are not restricted by the shape of the chip appearance, there will be certain difficulties in the layout of the grooves at the edge of the chip.

[0005] Therefore, how to effectively solve the warpage in the manufacturing process of trench gate chip wafers without being restricted by the chip appearance shape is a problem that needs to be solved urgently in this field. Summary of the invention

[0006] In order to solve the warping problem in the manufacturing process of trench gate chip wafers without being restricted by the chip appearance shape, the present invention provides a gate bus structure and a trench gate chip.

[0007] In a first aspect, an embodiment of the present invention provides a gate bus structure, including:

[0008] A well region of second conductivity type is formed above a drift region of first conductivity type, the well region intersects with a cell region trench extending from the cell region, and a plurality of gate bus trenches are formed in the well region at a set angle to the cell region trench direction to alleviate the warping of the trench gate chip;

[0009] an insulating layer formed above the well region; and

[0010] A gate signal conducting layer is formed on the insulating layer.

[0011] In some embodiments, the depth and / or width of the gate bus trench is consistent with that of the cell region trench, or is smaller than the depth and / or width of the cell region trench.

[0012] In some embodiments, the width of the gate bus groove ranges from 0.3 micrometers to 2 micrometers, and the depth of the gate bus groove ranges from 2 micrometers to 7 micrometers.

[0013] In some embodiments, a pitch of the gate bus grooves is consistent with a pitch of the cell region grooves, or is smaller than a pitch of the cell region grooves.

[0014] In some embodiments, the pitch of the gate bus grooves ranges from 0.3 microns to 6 microns.

[0015] In some embodiments, the set angle comprises 90°.

[0016] In some embodiments, the insulating layer is formed with a contact hole penetrating the insulating layer, so that when the gate signal conducting layer is formed above the insulating layer, it covers the contact hole and realizes potential connection with the conductive material in the cell region trench.

[0017] In some embodiments, the material of the insulating layer includes one or more of silicon dioxide, silicon nitride, and silicon oxynitride.

[0018] In some embodiments, the material of the gate signal conducting layer includes one or more of polysilicon, metal silicide, and metal.

[0019] In a second aspect, an embodiment of the present invention provides a trench gate chip, comprising the gate bus structure described in the first aspect.

[0020] In some embodiments, the trench gate chip includes a trench gate IGBT chip or a trench gate MOSFET chip.

[0021] Compared with the prior art, one or more embodiments of the present invention can at least bring the following beneficial effects:

[0022] The gate bus structure provided by the present invention comprises: a well region with a second conductivity type formed above a drift region of a first conductivity type, the well region intersects with a cell region groove extending from a cell region, and a plurality of gate bus grooves are formed in the well region at a set angle to the cell region groove direction to alleviate the warping of the trench gate chip; an insulating layer formed above the well region; and a gate signal conduction layer formed above the insulating layer. By introducing a plurality of gate bus grooves at a certain angle to the cell region groove in the well region, the warping caused by the trench gate chip during the processing can be effectively alleviated, and the preparation process is fully compatible with the original process, has no impact on the original process, and is easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 This is a schematic diagram of the gate bus structure of a conventional IGBT chip;

[0025] Figure 2 is a schematic diagram of a gate bus structure provided by an embodiment of the present invention;

[0026] Figure 3 yes Figure 1 A partial enlarged schematic diagram of the dotted line box area;

[0027] Figure 4 yes Figure 2 A partial enlarged schematic diagram of the dotted line box area;

[0028] Figure 5 yes Figure 3 A-A' cross section;

[0029] Figure 6 yes Figure 4 Middle B-B' cross section;

[0030] The meanings of the reference numerals in the figures are as follows:

[0031] 101-Terminal Area

[0032] 102-Gate pad

[0033] 103-Gate bus

[0034] 104-Emitter pad

[0035] 105-cell region groove

[0036] 106 Cell Area

[0037] 107-gate bus groove

[0038] 108-gate signal transmission layer

[0039] 109-Insulation layer

[0040] 110-well region

[0041] 111-Drift Zone

[0042] 112-Contact hole. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present invention.

[0044] A related technology provides a semiconductor wafer chip layout, which keeps the strip grooves in adjacent chips perpendicular to each other, and the wafer warping caused by the groove and gate filling offsets each other, thereby improving the warping problem of the entire wafer.

[0045] Another related technology provides a trench-type IGBT layout structure, which divides the chip cell area into four areas. The trench directions of adjacent areas are perpendicular to each other, so that the wafer warping caused by the trench and gate filling offset each other, thereby improving the warping problem of the entire wafer.

[0046] Although the above-mentioned related technologies can improve the stress and warpage problems in the trench gate IGBT wafer manufacturing process to a certain extent, they also face a great limitation, that is, the IGBT chip can only be square, because the non-square chip structure will bring great inconvenience to wafer dicing or trench arrangement. In actual applications, due to the different current densities required in different application fields and the limitations of the liner and module structure layout, the IGBT chip may not be a square appearance, but may be a rectangular appearance of different sizes.

[0047] Another related technology provides a groove chip layout structure for improving wafer stress, specifically, the grooves in the chip are set as a broken line structure, and the vertical bend in the middle of the groove is conducive to improving wafer stress. Although this solution is not limited by the appearance of the chip, it will be difficult to layout the grooves at the edge of the chip.

[0048] Therefore, in order to solve the warping problem in the trench gate chip wafer manufacturing process without being restricted by the chip appearance shape, an embodiment of the present invention provides a gate bus structure and a trench gate chip.

[0049] Embodiment 1

[0050] The gate bus structure provided in this embodiment is applicable to a trench gate chip, such as a trench gate IGBT chip. The gate bus structure of a conventional IGBT chip is as follows: Figure 1 As shown, the gate bus structure provided in this embodiment is as follows Figure 2 As shown, by setting a gate bus groove below the gate pad in the gate bus area and / or in the area outside the gate pad, the warping of the trench gate IGBT chip caused by the processing process can be effectively alleviated, and the preparation process is fully compatible with the original process, has no impact on the original process, and is easy to implement. A plurality of gate bus grooves 107 are set in the gate bus 103 area located above the terminal area 101, and the cell area groove 105 extends around the emitter pad 104 on the cell area 106 along the X direction, forming a certain angle with the gate bus groove 107, for example, the gate bus groove 107 is along the Y direction, and the directions of the two grooves are perpendicular to each other. Figure 1 , Figure 2 The dotted box area in the structure shown is enlarged to obtain Figure 3 , Figure 4 The enlarged partial view shown, Figure 5 yes Figure 3 A-A' cross section, Figure 6 yes Figure 4 B-B' cross section.

[0051] like Figure 2 , Figure 4 , Figure 6As shown, the gate bus structure provided in this embodiment includes:

[0052] Drift zone 111;

[0053] A well region 110 of the second conductivity type is formed above a drift region 111 of the first conductivity type, the well region 110 intersects with a cell region trench 105 extending from the cell region 106, and a plurality of gate bus trenches 107 are formed in the well region 110 at a set angle to the direction of the cell region trench 105 to alleviate the warping of the trench gate chip;

[0054] an insulating layer 109 formed over the well region 110; and

[0055] A gate signal conducting layer 108 is formed on the insulating layer 109 .

[0056] The first conductivity type may be N type, and the second conductivity type may be P type. The setting angle includes but is not limited to 90°. When the setting angle is 90°, the multiple gate bus grooves 107 formed in the well region 110 are perpendicular to the cell region grooves 105 extending from the cell region 106, so that the warping of the trench gate IGBT chip during the processing can be effectively alleviated without requiring the shape and size of the trench gate chip, thereby improving the stress problem in the trench gate chip wafer manufacturing process and reducing the stress generated by the wafer during the processing.

[0057] This embodiment introduces multiple gate bus grooves in the well region that form a certain angle (for example, 90°) with the cell region grooves in the X direction of the cell region, which can effectively alleviate the warping caused by the trench gate chip during the processing process. The preparation process is fully compatible with the original process, has no impact on the original process, and is easy to implement.

[0058] In some embodiments, the insulating layer 109 is formed with a contact hole 112 penetrating the insulating layer, so that when the gate signal conducting layer 108 is formed on the insulating layer 109 , it covers the contact hole 112 and realizes potential connection with the conductive material in the cell region trench 105 .

[0059] In this embodiment, the conductive material in the cell region trench 105 includes polysilicon, and the gate signal conduction layer 108 is connected to the polysilicon in the cell region trench 105 in the X direction extending from the cell region 106 through a contact hole penetrating the insulating layer 109 to achieve potential connection, thereby achieving the conduction of the gate signal from the gate pad 102 to the gate bus 103 and then to the cell gate.

[0060] In some embodiments, the depth and / or width of the gate bus groove 107 is consistent with the cell region groove 105, or is smaller than the depth and / or width of the cell region groove. In some cases, the depth of the gate bus groove 107 or the cell region groove 105 ranges from 2 microns to 7 microns, and the groove width ranges from 0.3 microns to 2 microns. Under such a range of values, the depth and / or width of the gate bus groove 107 and the cell region groove 105 take the same value or are smaller than the value of the cell region groove 105.

[0061] In some embodiments, the pitch of the gate bus trenches 107 is consistent with the pitch of the cell region trenches 105, or is smaller than the pitch of the cell region trenches 105. In some cases, the pitch of the gate bus trenches 107 ranges from 0.3 microns to 6 microns. Within this range, the pitch of the gate bus trenches 107 can be the same as or smaller than the pitch of the cell region trenches 105.

[0062] In practical applications, the greater the density of the gate bus grooves 107 in the well region (the smaller the spacing), the more obvious the effect of suppressing the warping of the cell region 106 is. The spacing size of the gate bus grooves 107 can be determined according to the actual required warping suppression effect.

[0063] In some embodiments, the material of the insulating layer 109 includes one or more of silicon dioxide, silicon nitride, and silicon oxynitride. Among them, silicon nitride and silicon oxynitride have stronger mechanical strength, and the use of materials with stronger mechanical strength is conducive to further alleviating the warping of the cell area. In practical applications, a combination of one or more materials of silicon dioxide, silicon nitride, and silicon oxynitride can be selected, for example, a combination of silicon nitride and silicon oxynitride, a combination of silicon dioxide and silicon nitride, and a combination of silicon dioxide and silicon oxynitride can be used to prepare the insulating layer to enhance the mechanical strength and improve the effect of suppressing the warping.

[0064] In some embodiments, the material of the gate signal conducting layer 108 includes one or more of polysilicon, metal silicide, and metal. In practical applications, when the material of the gate signal conducting layer 108 includes at least one layer of metal or metal silicide material with low resistivity, the gate signal conduction speed can be effectively improved, and the current sharing characteristics between the cell regions can be improved. For example, the gate signal conducting layer 108 is prepared using a combination of polysilicon and metal silicide, or a combination of metal silicide and metal, so as to effectively improve the gate signal conduction speed and improve the current sharing characteristics between the cell regions.

[0065] In one embodiment, the process of preparing the gate bus structure is as follows:

[0066] A well region intersecting the cell region trench extending from the cell region is formed above the drift region by an implantation and well-driving process;

[0067] Etching a cell region groove in the cell region and etching a gate bus groove in the well region;

[0068] Forming a sacrificial oxide layer;

[0069] removing the sacrificial oxide layer, forming a gate oxide layer and depositing polysilicon over the gate oxide layer;

[0070] Etch away the polysilicon on the surface, leaving only the polysilicon in the cell area trench and the gate bus trench;

[0071] Depositing an insulating layer;

[0072] etching the insulating layer to form a contact hole;

[0073] Metal is deposited on the front side and etched to form an emitter pad, a gate pad and a gate signal conducting layer.

[0074] Embodiment 2

[0075] This embodiment provides a trench gate chip, including the gate bus structure of the first embodiment.

[0076] The trench gate chip of this embodiment is realized based on a gate bus structure formed by introducing multiple gate bus grooves in the well region that form a certain angle (for example, 90°) with the cell region grooves. This can effectively alleviate the warping of the trench gate chip caused by the processing process, and the preparation process is fully compatible with the original process, has no impact on the original process, and is easy to implement.

[0077] In some embodiments, the trench gate chip includes but is not limited to a trench gate IGBT chip or a trench gate MOSFET chip.

[0078] The gate bus structure and trench gate chip provided by the embodiments of the present invention can effectively improve the stress problem in the trench gate IGBT chip or trench gate MOSFET chip wafer manufacturing process, and the appearance shape of the trench gate IGBT chip or trench gate MOSFET chip is not restricted; the preparation process is fully compatible with the original process, has no impact on the original process, and is easy to implement.

[0079] In the several embodiments provided in the embodiments of the present invention, it should be understood that the disclosed system and method can also be implemented in other ways. The system and method embodiments described above are merely illustrative.

[0080] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0081] Although the embodiments disclosed in the present invention are as above, the above contents are only embodiments adopted for facilitating the understanding of the present invention and are not intended to limit the present invention. Any technician in the technical field to which the present invention belongs can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A gate bus structure, characterized in that: A cell region trench extends around the emitter pad on the cell region, and the gate bus structure includes: A well region of the second conductivity type is formed above the drift region of the first conductivity type, the well region intersects with the cell region trench extending from around the emitter pad on the cell region, and a plurality of gate bus trenches are formed in the well region at a set angle to the direction of the cell region trench to alleviate the warping of the trench gate chip; an insulating layer formed above the well region; and A gate signal conducting layer is formed on the insulating layer.

2. The gate bus structure according to claim 1, characterized in that: The depth and / or width of the gate bus groove is consistent with that of the cell region groove, or is smaller than the depth and / or width of the cell region groove.

3. The gate bus structure according to claim 2, characterized in that: The width of the gate bus groove ranges from 0.3 micrometers to 2 micrometers, and the depth of the gate bus groove ranges from 2 micrometers to 7 micrometers.

4. The gate bus structure according to claim 1, characterized in that: The spacing of the gate bus grooves is consistent with the spacing of the cell region grooves, or is smaller than the spacing of the cell region grooves.

5. The gate bus structure according to claim 4, characterized in that: The spacing between the gate bus grooves ranges from 0.3 microns to 6 microns.

6. The gate bus structure according to claim 1, characterized in that: The set angle includes 90°.

7. The gate bus structure according to claim 1, characterized in that: The insulating layer is formed with a contact hole penetrating the insulating layer, so that when the gate signal conducting layer is formed on the insulating layer, it covers the contact hole and realizes potential connection with the conductive material in the cell region trench.

8. The gate bus structure according to claim 1, characterized in that: The material of the insulating layer includes one or more of silicon dioxide, silicon nitride, and silicon oxynitride.

9. The gate bus structure according to claim 1, characterized in that: The material of the gate signal conducting layer includes one or more of polysilicon, metal silicide and metal.

10. A trench gate chip, characterized in that: The gate bus structure comprises the gate bus structure as claimed in any one of claims 1 to 9.

11. The trench gate chip according to claim 10, characterized in that: The trench gate chip includes a trench gate IGBT chip or a trench gate MOSFET chip.

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