Power device

Abstract

The invention discloses a power device comprising a substrate, the substrate is provided with a first surface and a second surface, and the first surface is provided with an interlayer medium; the substrate comprises a terminal area and a cellular area, an interlayer medium of the cellular area is provided with source electrode metal, grid electrode metal and a grid electrode bonding pad, the source electrode metal is provided with a source electrode protruding part, and the grid electrode metal is provided with a grid electrode protruding part; the first surface of the cellular region is provided with a cellular region groove, the first surface of the terminal region is provided with a terminal groove, polycrystalline silicon is arranged in the terminal groove and the cellular region groove respectively, and the end face of a polycrystalline silicon notch in the terminal groove and the first surface of the terminal region jointly form a connecting surface; the connecting surface penetrates through the interlayer dielectric and is respectively connected with the source electrode protruding part and the grid electrode protruding part; and the first surface between the adjacent cell region grooves is led out, penetrates through the interlayer dielectric and is connected with the source electrode metal. According to the invention, the gate metal and the source metal are led out, and the pull-down resistor is integrated in the terminal region, so that the gate self-starting is inhibited, and the self-protection effect of the device gate is realized.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a power device. Background Art

[0002] Power devices, also known as power electronic devices or power semiconductor devices, are vital components in electronic devices. They have the ability to carry high voltage and high current and are the core of power conversion and control circuits.

[0003] When existing power devices are used in switching circuits, the required resistance is usually directly connected in parallel between the gate electrode and the source electrode outside the power device. This technology requires additional circuit space and increases the complexity of circuit design. Summary of the invention

[0004] In order to solve the problem that a power MOSFET device needs an external resistor between the gate and the source when in use, the present application provides a power device that integrates the resistor in the terminal area by leading the gate metal and the source metal to the terminal area, thereby simplifying the circuit design.

[0005] The embodiment of the present application provides a power device, including a substrate, the substrate having a first surface and a second surface, an interlayer dielectric is provided on the first surface; the substrate includes a terminal region and a cell region, a source metal, a gate metal and a gate pad are provided on the interlayer dielectric of the cell region, the gate pad is connected to the gate metal, the source metal is provided with a source protrusion, the gate metal is provided with a gate protrusion, and the source protrusion and the gate protrusion are respectively provided on the interlayer dielectric of the terminal region;

[0006] A cell region groove is formed on the first surface of the cell region, a terminal groove is formed on the first surface of the terminal region, polysilicon is respectively formed in the terminal groove and the cell region groove, and a notch end surface of the polysilicon in the terminal groove and the first surface of the terminal region jointly form a connection surface;

[0007] The connection surface penetrates the interlayer dielectric and is respectively connected to the source protrusion and the gate protrusion; the first surface between the adjacent cell region grooves is led out, penetrates the interlayer dielectric, and is connected to the source metal.

[0008] Preferably, the gate protrusion is symmetrically arranged on both sides of the source protrusion.

[0009] Preferably, the distance between the source protrusion and the gate protrusion is adjustable, and the distance between the source protrusion and the gate protrusion is used to adjust the resistance value of the pull-down resistor.

[0010] Preferably, the first surface between adjacent terminal trenches is led out, penetrates the interlayer dielectric, and is respectively connected to the source protrusion and the gate protrusion.

[0011] Preferably, a first impurity layer is provided between the first surface between adjacent terminal grooves and the interlayer dielectric, the first impurity layer is led out, penetrates the interlayer dielectric, and is respectively connected to the source protrusion and the gate protrusion, wherein the first impurity layer has a first impurity concentration.

[0012] Preferably, the polysilicon in the terminal trench is led out, penetrates the interlayer dielectric, and is respectively connected to the source protrusion and the gate protrusion.

[0013] Preferably, a first impurity layer is provided between the interlayer dielectric of the cell region and the first surface, the first impurity layer is led out, penetrates the interlayer dielectric, and is connected to the source metal, wherein the first impurity layer has a first impurity concentration.

[0014] Preferably, a source contact layer is provided between the interlayer dielectric of the cell region and the first impurity layer, and the first impurity layer is led out, passes through the source contact layer and the interlayer dielectric, and is connected to the source metal.

[0015] Preferably, a first contact hole is provided on the interlayer dielectric between the source protrusion and the connection surface, and the connection surface is connected to the source protrusion through the first contact hole;

[0016] A second contact hole is provided on the interlayer dielectric between the gate protrusion and the connection surface, and the connection surface is connected to the gate protrusion through the second contact hole;

[0017] A third contact hole is provided on the interlayer dielectric between the source metal and the first surface of the cell region, and the first surface is connected to the source metal through the third contact hole.

[0018] Preferably, the substrate includes a body region, an epitaxial layer, a substrate and a substrate contact layer, the epitaxial layer is arranged between the body region and the substrate contact layer, the substrate is arranged between the epitaxial layer and the substrate contact layer, the surface of the body region in contact with the interlayer dielectric is the first surface, and the surface of the substrate contact layer facing away from the substrate is the second surface; the bottom of the terminal groove and the bottom of the cell region groove are respectively connected to the epitaxial layer.

[0019] The beneficial effects of the present application are as follows: the present application provides a power device, by means of a source protrusion and a gate protrusion separately arranged on the interlayer dielectric of the terminal region, the gate-source resistor is integrated in the terminal region of the power device, the complexity of circuit design is reduced, the external components of the power device are reduced, and thus the chip area is saved;

[0020] The resistance value of the gate-source resistor is flexibly adjustable; the resistance value of the required resistor can be flexibly selected by adjusting the distance between the source protrusion and the gate protrusion. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 A top view of a power device in the first embodiment of the present application;

[0023] Figure 2 For this application Figure 1 The cross-sectional view along the AA′ plane;

[0024] Figure 3 For this application Figure 1 The cross-section along the BB′ plane;

[0025] Figure 4 A top view of a power device in a second embodiment of the present application;

[0026] Figure 5 For this application Figure 4 The cross-sectional view along the AA′ plane;

[0027] Figure 6 A top view of a power device in the third embodiment of the present application;

[0028] Figure 7 For this application Figure 6 Cross-sectional view along plane AA′.

[0029] Figure numerals: 1-cell region, 2-terminal region, 3-cell region trench, 4-terminal trench, 5-first contact hole, 6-second contact hole, 7-third contact hole, 8-source metal, 9-gate metal, 10-body region, 11-highly doped P+ layer, 12-source contact layer, 13-interlayer dielectric, 14-polysilicon, 15-epitaxial layer, 16-substrate, 17-substrate contact layer, 18-first surface, 19-second surface, 20-source protrusion, 21-gate pad, 22-connection surface, 23-gate protrusion. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, in the description of the present application, the term "including" means "including but not limited to". The terms first, second, third, etc. are used only as labels, and no numerical requirements are imposed or order is established. Various embodiments of the present application may exist in the form of a range; it should be understood that the description in the form of a range is only for convenience and simplicity, and should not be understood as a hard limit to the scope of the present application; therefore, it should be considered that the range description has specifically disclosed all possible sub-ranges and single values ​​within the range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the numbered range, such as 1, 2, 3, 4, 5 and 6, which are applicable regardless of the range. Additionally, whenever a numerical range is indicated herein, it is meant to include any cited numeral (fractional or integral) within the indicated range.

[0031] In response to the problem that power MOSFET devices require external resistors between the gate and the source when in use, the present application provides a power device that integrates the resistor in the terminal area by leading the gate metal and the source metal to the terminal area, thereby simplifying the circuit design.

[0032] In some embodiments, a power device includes a substrate, the substrate having a first surface and a second surface, an interlayer dielectric is disposed on the first surface; the substrate includes a terminal region and a cell region, a source metal, a gate metal and a gate pad are disposed on the interlayer dielectric of the cell region, the gate pad is connected to the gate metal, the source metal is provided with a source protrusion, the gate metal is provided with a gate protrusion, and the source protrusion and the gate protrusion are respectively disposed on the interlayer dielectric of the terminal region;

[0033] A cell region groove is formed on the first surface of the cell region, a terminal groove is formed on the first surface of the terminal region, polysilicon is respectively formed in the terminal groove and the cell region groove, and a notch end surface of the polysilicon in the terminal groove and the first surface of the terminal region jointly form a connection surface;

[0034] The connection surface penetrates the interlayer dielectric and is respectively connected to the source protrusion and the gate protrusion; the first surface between the adjacent cell region grooves is led out, penetrates the interlayer dielectric, and is connected to the source metal.

[0035] Preferably, the gate protrusion is symmetrically arranged on both sides of the source protrusion.

[0036] Preferably, the distance between the source protrusion and the gate protrusion is adjustable, and the distance between the source protrusion and the gate protrusion is used to adjust the resistance value of the pull-down resistor.

[0037] Preferably, the first surface between adjacent terminal trenches is led out, penetrates the interlayer dielectric, and is respectively connected to the source protrusion and the gate protrusion.

[0038] Preferably, a first impurity layer is provided between the first surface between adjacent terminal grooves and the interlayer dielectric, the first impurity layer is led out, penetrates the interlayer dielectric, and is respectively connected to the source protrusion and the gate protrusion, wherein the first impurity layer has a first impurity concentration.

[0039] Preferably, the polysilicon in the terminal trench is led out, penetrates the interlayer dielectric, and is respectively connected to the source protrusion and the gate protrusion.

[0040] Preferably, a first impurity layer is provided between the interlayer dielectric of the cell region and the first surface, the first impurity layer is led out, penetrates the interlayer dielectric, and is connected to the source metal, wherein the first impurity layer has a first impurity concentration.

[0041] Preferably, a source contact layer is provided between the interlayer dielectric of the cell region and the first impurity layer, and the first impurity layer is led out, passes through the source contact layer and the interlayer dielectric, and is connected to the source metal.

[0042] Preferably, a first contact hole is provided on the interlayer dielectric between the source protrusion and the connection surface, and the connection surface is connected to the source protrusion through the first contact hole;

[0043] A second contact hole is provided on the interlayer dielectric between the gate protrusion and the connection surface, and the connection surface is connected to the gate protrusion through the second contact hole;

[0044] A third contact hole is provided on the interlayer dielectric between the source metal and the first surface of the cell region, and the first surface is connected to the source metal through the third contact hole.

[0045] Preferably, the substrate includes a body region, an epitaxial layer, a substrate and a substrate contact layer, the epitaxial layer is arranged between the body region and the substrate contact layer, the substrate is arranged between the epitaxial layer and the substrate contact layer, the surface of the body region in contact with the interlayer dielectric is the first surface, and the surface of the substrate contact layer facing away from the substrate is the second surface; the bottom of the terminal groove and the bottom of the cell region groove are respectively connected to the epitaxial layer.

[0046] In the above embodiment, the first impurity layer and the body region have a first type of majority carriers, and the majority carriers of the first impurity layer have a first concentration. The majority carriers of the first concentration can form an ohmic contact with the conductor connected thereto when the power device is working.

[0047] The source contact layer, the epitaxial layer, the substrate, and the substrate contact layer have a second type of majority carrier concentration, wherein the source contact layer and the substrate contact layer have a second type of majority carrier concentration, which can form an ohmic contact with a conductor connected thereto when the power device is working.

[0048] Illustratively, the majority carriers of the first type are holes, and the majority carriers of the second type are electrons.

[0049] The source metal has a source protrusion, and the gate metal has at least one gate protrusion.

[0050] Optionally, the source protrusion is disposed at a corner of the terminal trench.

[0051] Optionally, the source protrusion is arranged perpendicular to a side of the terminal trench.

[0052] Optionally, the gate metal has a gate protrusion, which is spaced apart from the source protrusion and arranged on the top layer of the terminal region.

[0053] Preferably, the gate metal has at least one gate protrusion. In the case where the number of gate protrusions is greater than one, the gate protrusions are arranged on both sides of the source protrusion.

[0054] Preferably, the number of the gate protrusions is two, and the two gate protrusions are at least partially symmetrically arranged on both sides of the source protrusion and spaced apart from the source protrusion.

[0055] Preferably, the gate metal has two gate protrusions of the same shape. The two gate protrusions of the same shape are symmetrically arranged on both sides of the source protrusion and are spaced apart from the source protrusion.

[0056] The technical solution of the present invention is described below by taking N-channel MOSFET as an example.

[0057] Embodiment 1

[0058] like Figures 1 to 3 As shown, an embodiment of the present application provides a power device, Figure 1 The top view of the power device is shown, and the power device is arranged on a substrate. The substrate includes a cell region 1 and a terminal region 2 , and the terminal region 2 is arranged on the periphery of the cell region 1 .

[0059] The cell region 1 is provided with a cell region groove 3, which is in a grid shape; the terminal region 2 is provided with at least one terminal groove 4, and any terminal groove 4 is a closed strip-shaped figure. The closed figure surrounded by any terminal groove 4 is a rounded rectangle. Any terminal groove 4 surrounds the inner terminal groove 4 adjacent to it, wherein the innermost terminal groove 3 surrounds the cell region 1. Polysilicon is respectively arranged in the cell groove 3 and the terminal groove 4.

[0060] The top layer of the cell region 1 is provided with a source metal 8, a gate metal 9 and a gate pad 21. The gate metal 9 is provided at the periphery of the source metal 8, the gate pad 21 is provided between the source metal 8 and the gate metal 9, and the gate pad 21 is electrically connected to the gate metal 9. The source metal 8 has a source protrusion 20, and the gate metal 9 has two gate protrusions 23.

[0061] The source protrusion 20 is disposed at a corner of the terminal trench 4 .

[0062] The gate metal 9 has two gate protrusions 23 . The two gate protrusions 23 are symmetrically disposed on both sides of the source protrusion 20 and are spaced apart from the source protrusion 20 .

[0063] The gate metal 9 has two gate protrusions 23 of the same shape. The two gate protrusions 23 of the same shape are symmetrically arranged on both sides of the source protrusion 20 and are spaced apart from the source protrusion 20 .

[0064] along Figure 1 The cross-sectional view of the power device obtained by cutting the AA′ line is as follows: Figure 2 As shown. Among them, Figure 2 The left side is the A side. Figure 2 The right side is the A′ side. Figure 3 Shows Figure 1 The substrate of the power device includes: a body region 10 , an epitaxial layer 15 , a substrate 16 and a substrate contact layer 17 .

[0065] The body region 10 is a P-type body region, the epitaxial layer 15 is an N-type epitaxial layer, the substrate 16 is an N-type substrate, and the substrate contact layer 17 is a highly doped N+ layer.

[0066] The epitaxial layer 15 is connected to the body region 10 and the substrate 16 respectively, and the substrate 16 is connected to the epitaxial layer 15 and the substrate contact layer 17 respectively. The substrate is provided with a first surface 18 and a second surface 19, wherein the body region 10 is provided on one side of the first surface 18, the substrate contact layer 17 is provided on one side of the second surface 19, and an interlayer dielectric 13 is provided on the first surface 18. The substrate includes a terminal region 2 and a cell region 1, the terminal region 2 is provided at the periphery of the cell region 1, a source metal 8, a gate metal 9 and a gate pad 21 are provided on the interlayer dielectric of the cell region 1, the gate metal 9 is provided at the periphery of the source metal 8, the gate pad 21 is provided between the source metal 8 and the gate metal 9, the gate pad 21 is connected to the gate metal 9, the source metal 8 is provided with a source protrusion 20, the gate metal 9 is provided with a gate protrusion 23, and the source protrusion 20 and the gate protrusion 23 are respectively provided on the interlayer dielectric 13 of the terminal region 2.

[0067] A cell region groove 3 is provided on the front surface 18 of the cell region 1, and the cell region groove 3 is in a grid-like shape. A terminal groove 4 is provided on the front surface 18 of the terminal region 2, and the terminal groove 4 is in a square shape and is surrounded layer by layer in sequence. Polysilicon 14 is provided in the terminal groove 4 and the cell region groove 3 respectively, and the notch end surface of the polysilicon 14 in the terminal groove 4 and the front surface 18 of the terminal region 2 jointly form a connection surface 22. The source protrusion 20 is provided at the corner of the terminal groove 4, and the gate protrusions 23 are symmetrically provided on both sides of the source protrusion 20.

[0068] A highly doped P+ layer 11 is provided between the body region 10 and the interlayer dielectric 13 between adjacent terminal trenches 4, and the highly doped P+ layer 11 is provided below the gate protrusion 23 and the source protrusion 20, respectively, and the highly doped P+ layer 11 is provided inside the first surface 18, and a first contact hole 5 is provided on the interlayer dielectric 13 between the source protrusion 20 and the highly doped P+ layer 11, and the polysilicon 14 is led out. The source protrusion 20 forms an ohmic contact with the highly doped P+ layer 11 through the first contact hole 5.

[0069] A second contact hole 6 is provided on the interlayer dielectric 13 between the gate protrusion 23 and the highly doped P+ layer 11, and the polysilicon 14 is led out. The gate protrusion 23 forms an ohmic contact with the highly doped P+ layer 11 through the second contact hole 6.

[0070] A highly doped P+ layer 11 is provided between the P-type body region 10 of the cell region 1 and the interlayer dielectric 13, and a source contact layer 12 is provided between the interlayer dielectric 13 of the cell region 1 and the highly doped P+ layer 11. The source contact layer 12 and the highly doped P+ layer 11 are sequentially arranged on the inner side of the first surface 18 along the direction from the first surface 18 to the second surface 19. A third contact hole 7 is provided between the source metal 8 and the highly doped P+ layer 11 thereunder, and the third contact hole 7 penetrates the interlayer dielectric 13 and the source contact layer 12, and the highly doped P+ layer 11 is connected to the source metal 8 through the third contact hole 7, and the source metal 8 is grounded.

[0071] The source contact layer 12 is a highly doped N+ layer.

[0072] The gate-source resistance of the power device is formed by the polysilicon resistor in the terminal groove 4 connected to the gate protrusion 23 and the source protrusion 20. A pull-down resistor integrated in the device terminal region is formed between the gate protrusion 23 and the source protrusion 20, and the resistance of the pull-down resistor is adjusted by the distance between the source protrusion 20 and the gate protrusion 23.

[0073] Embodiment 2

[0074] like Figure 4 and Figure 5As shown, an embodiment of the present application provides a power device, including a substrate, which includes a body region 10, an epitaxial layer 15, a substrate 16 and a substrate contact layer 17 in sequence, wherein the body region 10 is a P-type body region, the epitaxial layer 15 is an N-type epitaxial layer, the substrate 16 is an N-type substrate, and the substrate contact layer 17 is a highly doped N+ layer.

[0075] The epitaxial layer 15 is respectively connected to the body region 10 and the substrate 16, and the substrate 16 is respectively connected to the epitaxial layer 15 and the substrate contact layer 17. The substrate is provided with a first surface 18 and a second surface 19, wherein the body region 10 is arranged on one side of the first surface 18, the substrate contact layer 17 is arranged on one side of the second surface 19, and an interlayer dielectric 13 is arranged on the first surface 18; the substrate includes a terminal region 2 and a cell region 1, the terminal region 2 is arranged at the periphery of the cell region 1, and a source metal 8, a gate metal 9 and a gate pad 21 are arranged on the interlayer dielectric of the cell region 1, the gate metal 9 is arranged at the periphery of the source metal 8, the gate pad 21 is arranged between the source metal 8 and the gate metal 9, the gate pad 21 is connected to the gate metal 9, the source metal 8 is provided with a source protrusion 20, the gate metal 9 is provided with a gate protrusion 23, and the source protrusion 20 and the gate protrusion 23 are respectively arranged on the interlayer dielectric 13 of the terminal region 2.

[0076] A cell region groove 3 is provided on the first surface 18 of the cell region 1, and the cell region groove 3 is in a grid-like shape. A terminal groove 4 is provided on the first surface 18 of the terminal region 2, and the terminal groove 4 is in a square shape and is surrounded layer by layer in sequence. Polysilicon 14 is provided in the terminal groove 4 and the cell region groove 3 respectively, and the notch end surface of the polysilicon 14 in the terminal groove 4 and the first surface 18 of the terminal region 2 jointly form a connection surface 22. The source protrusion 20 is provided at the corner of the terminal groove 4, and the gate protrusions 23 are symmetrically provided on both sides of the source protrusion 20.

[0077] A first contact hole 5 is provided on the interlayer dielectric 13 between the source protrusion 20 and the polysilicon 14, and the polysilicon 14 is led out and connected to the source protrusion 20 through the first contact hole 5; a second contact hole 6 is provided on the interlayer dielectric 13 between the gate protrusion 23 and the polysilicon 14, and the polysilicon 14 is led out and connected to the gate protrusion 23 through the second contact hole 6; a highly doped P+ layer 11 is provided between the interlayer dielectric 13 of the cell area 1 and the first surface 18, a source contact layer 12 is provided between the interlayer dielectric 13 of the cell area 1 and the highly doped P+ layer 11, both the highly doped P+ layer 11 and the source contact layer 12 are arranged on the inner side of the first surface 18, a third contact hole 7 is provided between the source metal 8 and the highly doped P+ layer 11 thereunder, the third contact hole 7 penetrates the interlayer dielectric 13 and the source contact layer 12, the highly doped P+ layer 11 is connected to the source metal 8 through the third contact hole 7, and the source metal 8 is grounded.

[0078] The source contact layer 12 is a highly doped N+ layer.

[0079] The gate-source resistance of the power device is formed by the polysilicon resistor in the terminal groove 4 connected to the gate protrusion 23 and the source protrusion 20. A pull-down resistor integrated in the device terminal region is formed between the gate protrusion 23 and the source protrusion 20, and the resistance of the pull-down resistor is adjusted by the distance between the source protrusion 20 and the gate protrusion 23.

[0080] Embodiment 3

[0081] like Figure 6 and Figure 7 As shown, an embodiment of the present application provides a power device, including a substrate, which includes a body region 10, an epitaxial layer 15, a substrate 16 and a substrate contact layer 17 in sequence.

[0082] The body region 10 is a P-type body region, the epitaxial layer 15 is an N-type epitaxial layer, the substrate 16 is an N-type substrate, and the substrate contact layer 17 is a highly doped N+ layer.

[0083] The epitaxial layer 15 is respectively connected to the body region 10 and the substrate 16, and the substrate 16 is respectively connected to the epitaxial layer 15 and the substrate contact layer 17. The substrate is provided with a first surface 18 and a second surface 19, wherein the body region 10 is arranged on one side of the first surface 18, the substrate contact layer 17 is arranged on one side of the second surface 19, and an interlayer dielectric 13 is arranged on the first surface 18; the substrate includes a terminal region 2 and a cell region 1, the terminal region 2 is arranged at the periphery of the cell region 1, and a source metal 8, a gate metal 9 and a gate pad 21 are arranged on the interlayer dielectric of the cell region 1, the gate metal 9 is arranged at the periphery of the source metal 8, the gate pad 21 is arranged between the source metal 8 and the gate metal 9, the gate pad 21 is connected to the gate metal 9, the source metal 8 is provided with a source protrusion 20, the gate metal 9 is provided with a gate protrusion 23, and the source protrusion 20 and the gate protrusion 23 are respectively arranged on the interlayer dielectric 13 of the terminal region 2.

[0084] A cell region groove 3 is provided on the first surface 18 of the cell region 1, and the cell region groove 3 is in a grid-like shape. A terminal groove 4 is provided on the first surface 18 of the terminal region 2, and the terminal groove 4 is in a square shape and is surrounded layer by layer in sequence. Polysilicon 14 is provided in the terminal groove 4 and the cell region groove 3 respectively, and the notch end surface of the polysilicon 14 in the terminal groove 4 and the first surface 18 of the terminal region 2 jointly form a connection surface 22. The source protrusion 20 and the gate protrusion 23 are respectively provided on an edge of the terminal groove 4, and the gate protrusion 23 is symmetrically provided on both sides of the source protrusion 20.

[0085] A highly doped P+ layer 11 is provided between the first surface 18 and the interlayer dielectric 13 between adjacent terminal grooves 4. The highly doped P+ layer 11 is provided below the gate protrusion 23 and the source protrusion 20, respectively, and the highly doped P+ layer 11 is provided inside the first surface 18. A first contact hole 5 is provided on the interlayer dielectric 13 between the source protrusion 20 and the highly doped P+ layer 11. The highly doped P+ layer 11 is led out and connected to the source protrusion 20 through the first contact hole 5. A second contact hole 6 is provided on the interlayer dielectric 13 between the gate protrusion 23 and the highly doped P+ layer 11. 1 is led out and connected to the gate protrusion 23 through the second contact hole 6; a highly doped P+ layer 11 is provided between the interlayer dielectric 13 of the cell area 1 and the first surface 18, a source contact layer 12 is provided between the interlayer dielectric 13 of the cell area 1 and the highly doped P+ layer 11, the highly doped P+ layer 11 and the source contact layer 12 are both pressed into the first surface 18, a third contact hole 7 is provided between the source metal 8 and the highly doped P+ layer 11 thereunder, the third contact hole 7 penetrates the interlayer dielectric 13 and the source contact layer 12, the highly doped P+ layer 11 is connected to the source metal 8 through the third contact hole 7, and the source metal 8 is grounded.

[0086] The source contact layer 12 is a highly doped N+ layer.

[0087] The gate-source resistance of the power device is formed by the polysilicon resistor in the terminal groove 4 connected to the gate protrusion 23 and the source protrusion 20. A pull-down resistor integrated in the device terminal region is formed between the gate protrusion 23 and the source protrusion 20, and the resistance of the pull-down resistor is adjusted by the distance between the source protrusion 20 and the gate protrusion 23. By implementing a power device provided by the present application, the gate-source resistor can be integrated in the terminal area of ​​the power device through the source protrusion and the gate protrusion which are separately arranged on the interlayer dielectric of the terminal area, so as to reduce the complexity of circuit design, reduce the external components of the power device, and thus save the chip area; when the power device is applied to the switching circuit, the pull-down resistor is integrated in the terminal area through the gate protrusion and the source protrusion; when the power is supplied, a level of a certain value is given to the gate metal, and when the power is off, a parasitic capacitance discharge path between the gate and the source is provided, so as to suppress the self-start of the gate and realize the self-protection of the gate of the device; the pull-down resistor of the present application is formed by using the P-type area between the terminal grooves of the power device, and can also be formed by using the polysilicon in the terminal groove, without introducing additional processes and injection conditions, saving costs; the resistance value of the pull-down resistor is flexible and adjustable. By adjusting the distance between the source protrusion and the gate protrusion, the resistance value of the required pull-down resistor can be flexibly selected; the pull-down resistor is integrated in the terminal area of ​​the device, so it does not need to occupy additional chip area, simplifies the circuit design, reduces the use of external components, and improves the reliability of the circuit.

[0088] The above is a detailed introduction to a separation and purification system and method provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technicians in this field, according to the ideas of the present application, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A power device, characterized in that: The invention comprises a substrate, wherein the substrate has a first surface and a second surface, and an interlayer dielectric is arranged on the first surface; the substrate comprises a terminal region and a cell region, and a source metal, a gate metal and a gate pad are arranged on the interlayer dielectric of the cell region, and the gate pad is connected to the gate metal, the source metal is provided with a source protrusion, and the gate metal is provided with a gate protrusion, and the source protrusion and the gate protrusion are respectively arranged on the interlayer dielectric of the terminal region; A cell region groove is formed on the first surface of the cell region, a terminal groove is formed on the first surface of the terminal region, polysilicon is respectively formed in the terminal groove and the cell region groove, and an end surface of the polysilicon notch in the terminal groove and the first surface of the terminal region jointly form a connection surface; The connection surface penetrates the interlayer dielectric and is respectively connected to the source protrusion and the gate protrusion; the first surface between the adjacent cell region grooves is led out, penetrates the interlayer dielectric, and is connected to the source metal.

2. The power device according to claim 1, characterized in that: The gate protrusions are symmetrically arranged on both sides of the source protrusion.

3. The power device according to claim 2, characterized in that: The distance between the source protrusion and the gate protrusion is adjustable, and the distance between the source protrusion and the gate protrusion is used to adjust the resistance value of the pull-down resistor.

4. The power device according to claim 1, characterized in that: The first surface between the adjacent terminal trenches is led out, penetrates the interlayer dielectric, and is respectively connected to the source protrusion and the gate protrusion.

5. The power device according to claim 4, characterized in that: A first impurity layer is disposed between the first surface between adjacent terminal trenches and the interlayer dielectric. The first impurity layer is led out, penetrates the interlayer dielectric, and is respectively connected to the source protrusion and the gate protrusion.

6. The power device according to claim 1, characterized in that: The polysilicon in the terminal trench is led out, passes through the interlayer dielectric, and is respectively connected to the source protrusion and the gate protrusion.

7. The power device according to claim 1, characterized in that: A first impurity layer is provided between the interlayer dielectric of the cell region and the first surface. The first impurity layer is led out, passes through the interlayer dielectric, and is connected to the source metal.

8. The power device according to claim 7, characterized in that: A source contact layer is provided between the interlayer dielectric of the cell region and the first impurity layer. The first impurity layer is led out, passes through the source contact layer and the interlayer dielectric, and is connected to the source metal.

9. The power device according to claim 1, characterized in that: A first contact hole is provided on the interlayer dielectric between the source protrusion and the connection surface, and the connection surface is connected to the source protrusion through the first contact hole; A second contact hole is provided on the interlayer dielectric between the gate protrusion and the connection surface, and the connection surface is connected to the gate protrusion through the second contact hole; A third contact hole is provided on the interlayer dielectric between the source metal and the first surface of the cell region, and the first surface is connected to the source metal through the third contact hole.

10. The power device according to claim 1, characterized in that: The substrate includes a body region, an epitaxial layer, a substrate and a substrate contact layer, the epitaxial layer is arranged between the body region and the substrate contact layer, the substrate is arranged between the epitaxial layer and the substrate contact layer, the surface of the body region in contact with the interlayer dielectric is the first surface, and the surface of the substrate contact layer facing away from the substrate is the second surface; the bottom of the terminal groove and the bottom of the cell region groove are respectively connected to the epitaxial layer.

Images