Power Chip

Abstract

The present invention discloses a power chip, including a chip body, including at least one active area composed of a plurality of cells; an emitter pad arranged corresponding to the active area; a gate pad arranged on the chip body and located on the same side as the emitter pad; a ring-shaped gate bus arranged around the active area and located on the same side as the emitter pad; an on-chip gate resistor connected to the ring-shaped gate bus and the gate pad, respectively; wherein the width of the ring-shaped gate bus is inversely proportional to the distance from the gate pad. That is, the farther the gate bus is from the gate pad, the smaller the width of the gate bus. In this way, the consistency of the gate signal transmitted on the gate bus is improved, thereby improving the switching consistency between cells with different distances to the gate pad, thereby improving the cell current sharing, and improving the robustness and reliability of the power chip operation.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor power devices, and in particular relates to a power chip. Background Art

[0002] Since power chips need to work under high current conditions, they usually need to be used in parallel. As the power capacity requirements of power chips are getting higher and higher, the number of parallel branches or the current capacity of a single branch needs to be continuously improved, which puts higher and higher requirements on the current sharing capacity between parallel branches. Unbalanced current between parallel branches will cause a branch to bear too much current, which may cause irreversible failure due to excessive stress under extreme conditions such as short circuit and high current shutdown; or it may age faster under long-term higher stress than other branches, causing parameter drift, further exacerbating the above-mentioned uneven current phenomenon, and ultimately leading to failure.

[0003] From the perspective of the scope of influence of current sharing, it can be divided into module-level current sharing, liner-level current sharing, chip-level current sharing and cell-level current sharing. Among them, cell-level current sharing is the basis of all the above current sharing. From the perspective of the influence process of current sharing, it can be divided into static current sharing and dynamic current sharing. When the power chip is turned on, the gate drive signal is first applied to the gate pad of the chip, and then transmitted to each cell on the chip through the gate bus. The gate bus has a certain resistance, so when the gate signal is transmitted to each cell at different distances from the gate pad, the gate voltage will be reduced to varying degrees, which will lead to inconsistent turn-on speeds between different cells, resulting in uneven current sharing of the cells. For large-area chips under high-power and high-current applications, this uneven current effect will be stronger, reducing the reliability of the power chip. Summary of the invention

[0004] The main purpose of the present invention is to provide a power chip to solve the problem in the prior art that the cells of the power chip have uneven current, resulting in reduced reliability of the power chip.

[0005] In view of the above problems, the present invention provides a power chip, comprising:

[0006] A chip body, comprising at least one active area composed of a plurality of cells;

[0007] An emitter pad disposed corresponding to the active area;

[0008] A gate pad is disposed on the chip body and is located on the same side as the emitter pad;

[0009] An annular gate bus is arranged around the active area and is located on the same side as the emitter pad;

[0010] On-chip gate resistors, respectively connected to the annular gate bus and the gate pad;

[0011] Wherein, the width of the annular gate bus is inversely proportional to the distance from the gate pad.

[0012] Furthermore, in the power chip described above, the width of at least part of the gate bus lines in the annular gate bus lines gradually decreases in a step-like manner and / or gradually decreases in a linear manner.

[0013] Furthermore, in the power chip described above, the number of the gate pad is 1; the shape of the power chip is a quadrilateral;

[0014] The gate pad is located at the center of any one side of the power chip, or at the junction of any two adjacent sides of the power chip, or at the center of the power chip.

[0015] Furthermore, in the power chip described above, the number of the gate pad is 1; the shape of the power chip is a quadrilateral; the gate pad is located at the center of any side of the power chip;

[0016] The number of active areas is N; the width of the gate bus corresponding to each side satisfies the following expression:

[0017] W bottom >W side_1 >W side_2 >…>W side_N-1 >W middle_1 =W middle_2 =…=W middle_N-1 >Wside_ N =W top ;

[0018] Among them, W bottom W represents the width of the gate bus corresponding to the first side of the power chip; the first side of the power chip is the side where the gate pad is located; side_N-1 W represents the width of the gate bus corresponding to the second sides of the two power chips located at both ends of the first side at the periphery of the N-1th active area; middle_N-1 represents the width of the gate bus corresponding to the third side between the Nth active area and the N-1th active area; the W side_N represents the width of the gate bus corresponding to the second sides of the two power chips located at both ends of the first side at the periphery of the Nth active area; the W top Represents the width of the gate bus corresponding to the fourth side of the periphery of the Nth active area away from the first side.

[0019] Furthermore, in the power chip described above, the number of the gate pads is at least 2, and the gate pads are symmetrically distributed on the chip body.

[0020] Furthermore, in the power chip described above, the shape of the power chip is a quadrilateral; the number of the gate pads is 2;

[0021] The two gate pads are respectively located at the center of two parallel sides of the power chip.

[0022] Furthermore, in the power chip described above, the shape of the power chip is a quadrilateral; the number of the gate pads is 4;

[0023] A gate pad is respectively arranged at the center of each side of the power chip.

[0024] Furthermore, in the power chip described above, at least one annular gate bus is provided with a gap.

[0025] Furthermore, in the power chip described above, the material of the annular gate bus includes at least one of a composite film layer material of metal, metal silicide and polysilicon.

[0026] Furthermore, the power chip described above further includes:

[0027] The terminal area is arranged at the periphery of the annular gate bus.

[0028] Compared with the prior art, one or more embodiments of the above scheme may have the following advantages or beneficial effects:

[0029] The power chip of the present invention is designed by making the width of the annular gate bus inversely proportional to the distance from the gate pad, that is, the farther the gate bus is from the gate pad, the smaller the width of the gate bus. In this way, the consistency of the gate signal transmitted on the gate bus is improved, thereby improving the switching consistency between cells with different distances to the gate pad, thereby improving the cell current sharing, and improving the robustness and reliability of the power chip. At the same time, the power chip is simple to manufacture, fully compatible with conventional processes, does not add any process steps, and is conducive to the development of power chips towards higher power capacity or higher current capacity.

[0030] Other features and advantages of the present invention will be described in the following description, and part of the description will become apparent, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0032] Figure 1 A schematic diagram of the structure of a power chip according to an embodiment of the present invention;

[0033] Figure 2 A schematic diagram of the structure of a stepped gate bus;

[0034] Figure 3 It is a schematic diagram of the structure of a linear gate bus;

[0035] Figure 4 It is a schematic structural diagram of another embodiment of the power chip of the present invention. DETAILED DESCRIPTION

[0036] The following will describe the implementation methods of the present invention in detail with reference to the accompanying drawings and embodiments, so that the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly. It should be noted that as long as there is no conflict, the various embodiments of the present invention and the various features in the embodiments can be combined with each other, and the technical solutions formed are all within the protection scope of the present invention.

[0037] In the related art, in order to improve the consistency of cell switches, the following technical solutions are provided:

[0038] The first technical solution is to reduce the difference in switching speed between cells close to the gate pad and cells far from the gate pad by setting a continuous low-resistivity metal gate bus on the periphery of the power chip, setting metal gate fingers at intervals in the emitter region surrounded by the gate bus, and connecting the gate bus and the gate fingers through metal, thereby improving the switching consistency of the cells.

[0039] The second technical solution: a continuous annular polysilicon gate bus can be set on the periphery of the chip, one or more strip polysilicon gate buses can be set in the emitter area surrounded by the annular gate bus, and the annular gate bus can be connected to the strip gate bus. At the same time, a metal gate flow channel is set on the annular gate bus to reduce the distributed resistance, and an H-type copper metal bridge clip (clipbond) is set in the emitter area to reduce the contact resistance and improve the thermal conductivity and thermal stress. A gate pad is set on the middle strip polysilicon gate bus and on both sides of the H-type bridge clip, and the distance from each cell to the gate pad is shortened by the double pad. Finally, the above methods are combined to achieve better cell switching uniformity.

[0040] However, the above two technical solutions do not take into account the diversion of the gate signal on each branch of the gate bus, resulting in limited improvement effect on the cell current sharing.

[0041] Therefore, in order to solve the above technical problems existing in the related art, an embodiment of the present invention provides a power chip.

[0042] Figure 1 FIG. 1 is a schematic diagram of a structure of a power chip according to an embodiment of the present invention. Figure 1 As shown, the power chip of this embodiment may include a chip body, an emitter pad 11 , a gate pad 12 , a ring-shaped gate bus 13 and an on-chip gate resistor 14 .

[0043] In a specific implementation process, the chip body includes at least one active area 10 composed of a plurality of cells. Each active area 10 is provided with a corresponding emitter pad 11. A gate pad 12 is provided on the chip body, and the gate pad 12 and the emitter pad 11 are located on the same side; a ring-shaped gate bus 13 is provided around the active area 10, and the ring-shaped gate bus 13 and the emitter pad 11 are located on the same side; an on-chip gate resistor 14 is respectively connected to the ring-shaped gate bus 13 and the gate pad 12. That is, the chip body includes at least one active area 10 composed of a plurality of cells, and an emitter pad 11 is provided on each active area 10 in a one-to-one correspondence, and a ring-shaped gate bus 13 is provided around the active area 10, and the ring-shaped gate bus 13 is connected to the gate pad 12 through the on-chip gate resistor 14.

[0044] In a specific implementation process, the width of the annular gate bus 13 is inversely proportional to the distance from the gate pad 12. That is, the width of the annular gate bus 13 changes with the distance from the gate pad 12, and the farther the annular gate bus 13 is from the gate pad 12, the smaller the width of the annular gate bus 13. In this way, whether it is the gate bus on the branch or the gate bus on the trunk, the gate signal is basically transmitted on the gate bus, so that the cells can be current-balanced, which improves the reliability of the power chip.

[0045] In a specific implementation process, the number of the gate pad 12 may be 1; the shape of the power chip may be a quadrilateral. The gate pad 12 is located at the center of any side of the power chip, or at the junction of any two adjacent sides of the power chip, or at the center of the power chip.

[0046] In a specific implementation process, when the number of the gate pads 12 may be 1; the shape of the power chip may be a quadrilateral, and the gate pad 12 is located at the center of any side of the power chip, if the number of the active areas 10 is N; the width corresponding to each side satisfies the following expression:

[0047] W bottom >W side_1 >W side_2 >…>W side_N-1 >W middle_1 =W middle_2 =…=W middle_N-1 >Wside_ N =W top ;

[0048] Among them, W bottom W represents the width of the gate bus corresponding to the first side of the power chip; the first side of the power chip is the side where the gate pad 12 is located; side_N-1 W represents the width of the gate bus corresponding to the second sides of the two power chips located at both ends of the first side at the periphery of the N-1th active area; middle_N-1 represents the width of the gate bus corresponding to the third side between the Nth active area 10 and the N-1th active area 10; the W side_N represents the width of the gate bus corresponding to the second sides of the two power chips located at both ends of the first side at the periphery of the Nth active area 10; the W top It represents the width of the gate bus corresponding to the fourth side of the periphery of the Nth active area 10 away from the first side.

[0049] The first side is the side corresponding to the position of the gate pad 12. Figure 1 The middle is the bottom side in the horizontal direction, and the second side is the two sides of the active area 10 located at both ends of the first side. Figure 1 The middle side is the vertical side, the third side is the side between any two adjacent active areas 10, Figure 1 The middle side is the middle side in the horizontal direction, the fourth side is the side of the Nth active area 10 away from the first side, Figure 1 The middle is the top edge in the horizontal direction.

[0050] In a specific implementation process, the number of the gate pads 12 is at least 2, and the gate pads 12 are symmetrically distributed on the chip body. For example, the shape of the power chip is a quadrilateral; the number of the gate pads 12 is 2, and the two gate pads 12 are respectively located at the center of two parallel sides of the power chip. The shape of the power chip is a quadrilateral; the number of the gate pads 12 is 4; one gate pad 12 is respectively set at the center of each side of the power chip.

[0051] Figure 1 Taking a quadrilateral power chip with one gate pad 12 , the gate pad 12 located at the center of the lower side of the power chip, and including two active areas 10 as an example, the technical solution of the present invention is described.

[0052] Specifically, two emitter pads 11 can be stacked from bottom to top, and the direction of the groove A is arranged vertically from bottom to top, parallel to the stacking direction of the emitter pads 11. An on-chip gate resistor 14 can be connected to the left and right of the gate pad 12, and the on-chip gate resistors 14 have symmetrical structures and equal resistance values; or a gate on-chip resistor can be connected above or below the gate pad 12. Figure 1 Take connecting a gate resistor above the gate pad 12 as an example.

[0053] When making a ring-shaped gate bus 13, it can be made as follows: the gate pad 12 is connected to the gate bus through the on-chip gate resistor 14, and the gate bus extends from the center of the lower edge of the layout to the left and right sides, and after reaching the lower left corner and the lower right corner of the layout respectively, it extends from bottom to top along the left and right edges of the layout, and forms a branch above each emitter pad 11, extending from the left and right sides to the center until the gate bus surrounds all the emitter pads 11 from all sides, thereby surrounding each active area 10.

[0054] The farther away from the gate pad 12, the smaller the width of the gate bus. For example, the lateral gate bus width W at the bottom edge of the chip below the lowest emitter pad 11 where the gate pad 12 is located is bottom The widest, lateral gate bus width W of the chip top edge above the top emitter pad 11 top The narrowest is the width W of all lateral gate buses from bottom to top between the two and between the emitter pads 11. middle_1 , W middle_2 ,…W middle_N-1 Equal to and between the above W bottom and W top The width of Figure 1 The number of active regions 10 in is 2, and only W is taken here. middle_1The width W of all vertical gate bus lines from bottom to top on both sides of the emitter pad 11 is side_1 , W side_2 ,…W side_N gradually narrower, Figure 1 The number of active regions 10 in is 2, and only W is taken here. side_1 , W side_2 The width W of the longitudinal gate bus on the left and right sides of the emitter pad 11 at the bottom of the power chip is side_1 Smaller than the lateral gate bus width W at the bottom edge of the chip below the emitter pad 11 bottom , the vertical gate bus width W on both sides of the emitter pad 11 at the top of the power chip side_2 Equal to the lateral gate bus width W at the top edge of the chip above the emitter pad 11 top , and the longitudinal gate bus width W on both sides of the emitter pad 11 at the top of the power chip side_N Smaller than the lateral gate bus width W between the emitter pad 11 and the lower emitter pad 11 middle_N-1 . Figure 1 W in the middle side_2 <W middle_1 The width W of the longitudinal gate bus lines on the left and right sides of the emitter pad 11 next to the top, that is, the emitter pad 11 next to the top side_N-1 Greater than the above W middle_N-1 . Figure 1 W in the middle side_1 >W middle_1 .

[0055] against Figure 1 The width relationship of the gate bus corresponding to each side is shown in the following expression:

[0056] W bottom >W side _ 1 >Wmiddle_ 1 >Wside_ 2 =W top .

[0057] In a specific implementation process, at least one annular gate bus 13 is provided with a gap to facilitate emitter routing. Figure 1 The gap can be set in the annular gate bus 13 corresponding to the second active area 10.

[0058] In a specific implementation process, the material of the annular gate bus 13 includes at least one of a composite film layer material of metal, metal silicide and polysilicon.

[0059] In a specific implementation process, Figure 1As shown, the power chip may further include a terminal region. The terminal region is arranged at the periphery of the annular gate bus 13 .

[0060] The power chip of this embodiment is designed by making the width of the annular gate bus 13 inversely proportional to the distance from the gate pad 12, that is, the farther the gate bus is from the gate pad 12, the smaller the width of the gate bus. In this way, the consistency of the gate signal transmitted on the gate bus 13 is improved, thereby improving the switching consistency between cells with different distances to the gate pad 12, thereby improving the cell current sharing, and improving the robustness and reliability of the power chip. At the same time, the power chip is simple to manufacture, fully compatible with conventional processes, and does not add any process steps, which is conducive to the development of power chips towards higher power capacity or higher current capacity.

[0061] In a specific implementation process, the width of at least part of the gate bus lines in the annular gate bus line 13 gradually decreases in a step-like manner and / or gradually decreases in a linear manner.

[0062] Figure 2 It is a schematic diagram of the structure of a stepped gate bus. Figure 3 It is a schematic diagram of the structure of a linear gate bus.

[0063] Figure 4 FIG. 1 is a schematic diagram of the structure of another embodiment of the power chip of the present invention. Figure 4 As shown, the power chip of this embodiment is Figure 1 The difference is that the structure of the horizontal ring bus is changed by taking the linear gate bus as an example. The following only describes the difference. For the description of other structures, please refer to the above related records, which will not be repeated here.

[0064] Specifically, the gate bus corresponding to the first side is in a convex shape, and the width of the two edge portions of the gate bus gradually decreases in a linear manner when extending from the junction with the middle portion of the first side to the second side. When the third side extends from the second side to the middle portion of the two second sides, the width gradually decreases in a linear manner. When the fourth side extends from the second side to the middle portion of the two second sides, the width gradually decreases in a linear manner.

[0065] It should be noted that, in this embodiment, only the example of the width of the gate bus corresponding to the horizontal side gradually decreasing in a linear manner is described, but this embodiment is not limited to this method. For example, the width of the gate bus corresponding to the vertical side can also gradually decrease in a linear manner. Examples are not given one by one here.

[0066] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0067] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0068] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0069] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted for facilitating the understanding of the present invention and are not intended to limit the present invention. Any technician in the technical field to which the present invention belongs can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present invention, but the protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A power chip, characterized in that: include: A chip body, comprising at least one active area composed of a plurality of cells; An emitter pad disposed corresponding to the active area; A gate pad is disposed on the chip body and is located on the same side as the emitter pad; An annular gate bus is arranged around the active area and is located on the same side as the emitter pad; On-chip gate resistors, respectively connected to the annular gate bus and the gate pad; Wherein, the width of the annular gate bus is inversely proportional to the distance from the gate pad.

2. The power chip according to claim 1, characterized in that: The width of at least part of the gate bus lines in the annular gate bus lines gradually decreases in a step-like manner and / or gradually decreases in a linear manner.

3. The power chip according to claim 1, characterized in that: The number of the gate pad is 1; the shape of the power chip is a quadrilateral; The gate pad is located at the center of any one side of the power chip, or at the junction of any two adjacent sides of the power chip, or at the center of the power chip.

4. The power chip according to claim 1, characterized in that: The number of the gate pads is 1; the shape of the power chip is a quadrilateral; the gate pad is located at the center of any side of the power chip; The number of active areas is N; the width of the gate bus corresponding to each side satisfies the following expression: IN bottom >In side_1 >In side_2 >…>In side_N-1 >In middle_1 =In middle_2 =…=In middle_N-1 >Inside_ N =In top ; Among them, W bottom W represents the width of the gate bus corresponding to the first side of the power chip; the first side of the power chip is the side where the gate pad is located; side_N-1 W represents the width of the gate bus corresponding to the second sides of the two power chips located at both ends of the first side at the periphery of the N-1th active area; middle_N-1 represents the width of the gate bus corresponding to the third side between the Nth active area and the N-1th active area; the W side_N represents the width of the gate bus corresponding to the second sides of the two power chips located at both ends of the first side at the periphery of the Nth active area; the W top It represents the width of the gate bus corresponding to the fourth side of the periphery of the Nth active area away from the first side.

5. The power chip according to claim 1, characterized in that: The number of the gate pads is at least 2, and the gate pads are symmetrically distributed on the chip body.

6. The power chip according to claim 5, characterized in that: The shape of the power chip is a quadrilateral; the number of the gate pads is 2; The two gate pads are respectively located at the center of two parallel sides of the power chip.

7. The power chip according to claim 5, characterized in that: The shape of the power chip is a quadrilateral; the number of the gate pads is 4; A gate pad is respectively arranged at the center of each side of the power chip.

8. The power chip according to claim 1, characterized in that: At least one annular gate bus line is provided with a notch.

9. The power chip according to claim 6, characterized in that: The material of the annular gate bus includes at least one of a composite film layer material of metal, metal silicide and polysilicon.

10. The power chip according to claim 1, characterized in that: Also includes: The terminal area is arranged at the periphery of the annular gate bus.

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