Nanowire / sheet devices with crystalline sidewalls and methods of fabrication and electronic devices

Abstract

Disclosed are a nanowire / sheet device having a crystal sidewall, a method of manufacturing the same, and an electronic device including the same. According to an embodiment, the nanowire / sheet device can include a substrate, a nanowire / sheet spaced apart from a surface of the substrate and extending in a first direction, source / drain layers located at opposite ends of the nanowire / sheet in the first direction and in contact with the nanowire / sheet, a gate stack extending in a second direction intersecting the first direction to surround the nanowire / sheet, and a sidewall disposed on sidewalls of the gate stack, wherein the sidewall has substantially the same crystal structure as the nanowire / sheet in at least a partial region adjacent to the nanowire / sheet.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more specifically, to nanowire / chip devices having crystal sidewalls, methods of manufacturing the same, and electronic devices including such nanowire / chip devices. Background Technology

[0002] Nanowire or nanosheet (hereinafter referred to as "nanowire / sheet") devices, especially gate-all-around (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs) based on nanowires / sheets, can effectively control short-channel effects and enable further miniaturization of devices. Additionally, epitaxial growth of sources / drains is desirable, for example, to increase the size of the sources / drains to facilitate the fabrication of contacts, or to achieve stress engineering, etc. However, with continuous miniaturization, it is difficult to grow high-quality sources / drains. Summary of the Invention

[0003] In view of this, the purpose of this disclosure is at least in part to provide a nanowire / sheet device having crystal sidewalls, a method for manufacturing the same, and an electronic device including such a nanowire / sheet device.

[0004] According to one aspect of this disclosure, a nanowire / sheet device is provided, comprising: a substrate; nanowires / sheets spaced apart from the surface of the substrate and extending along a first direction; source / drain layers located at opposite ends of the nanowires / sheets in the first direction and in contact with the nanowires / sheets; a gate stack extending along a second direction intersecting the first direction to surround the nanowires / sheets; and sidewalls disposed on the sidewalls of the gate stack, wherein the sidewalls have a crystal structure substantially the same as that of the nanowires / sheets in at least a portion of a region adjacent to the nanowires / sheets.

[0005] According to another aspect of this disclosure, a method for fabricating a nanowire / sheet device is provided, comprising: forming nanowires / sheets spaced apart from the surface of a substrate and extending along a first direction on a substrate; forming a dummy gate extending along a second direction intersecting the first direction and surrounding the nanowires / sheets on the substrate; forming sidewalls on the sidewalls of the dummy gates, wherein the sidewalls have a crystal structure substantially the same as that of the nanowires / sheets in at least a portion of a region adjacent to the nanowires / sheets; and growing a source / drain layer using the ends of the nanowires / sheets in the first direction and the at least a portion of the sidewalls as seeds.

[0006] According to another aspect of this disclosure, an electronic device is provided, including the above-described nanowire / sheet device.

[0007] According to embodiments of this disclosure, the sidewalls can have a crystalline structure substantially identical to that of the nanowires / sheets in at least a portion of their area. Therefore, the growth of the source / drain layer can be seeded not only with the nanowires / sheets but also with the sidewalls (at least a portion of their area). This results in source / drain layers with high crystal quality. Attached Figure Description

[0008] The above and other objects, features, and advantages of this disclosure will become clearer from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0009] Figures 1 to 15(b) The illustrations schematically depict some stages in the process of manufacturing nanowire / sheet devices according to embodiments of the present disclosure;

[0010] Figures 16(a) to 21 The illustration schematically shows some stages in the process of manufacturing nanowire / sheet devices according to another embodiment of the present disclosure;

[0011] Figures 22(a) to 29 The illustration schematically shows some stages in the process of manufacturing nanowire / sheet devices according to another embodiment of the present disclosure;

[0012] Figure 30 A nanowire / sheet device according to another embodiment of this disclosure is schematically illustrated.

[0013] in, Figure 1 , 3(a) Figures 4(a), 5(b), 6, 7, 8(a), 9(a), 9(b), 10(a), 10(c), 11(a), 12(a), 13(a), 14(a), 15(a), 16(b), 17(b), 18, 19, 20(a), 21, 22(b), 23(b), 24(a), and 25 to 30 are cross-sectional views along line AA'.

[0014] Figure 3(b) , 4(b) Figures 8(b), 10(b), 11(b), 12(b), 13(b), 14(b), 15(b), 20(b), and 24(b) are cross-sectional views along line BB'.

[0015] Figure 2(a) , 2(b) Figures 5(a), 16(a), 17(a), 22(a), and 23(a) are top views. Figure 2(a) shows the positions of lines AA' and BB', and Figure 22(a) shows the positions of lines DD' and EE'.

[0016] Figure 23(c) is a cross-sectional view along line DD'.

[0017] Figure 23(d) , 24(c) This is a cross-sectional view along line EE'.

[0018] Figure 20(c) , 24(d) It is a cross-sectional view obtained along the sidewall of the sidewall. Detailed Implementation

[0019] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0020] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0021] According to embodiments of this disclosure, a nanowire / sheet device is provided. Specifically, the device may include one or more nanowires or nanosheets to serve as channels. The nanowires / sheets may be suspended relative to a substrate and may extend substantially parallel to the surface of the substrate. Each nanowire / sheet is aligned in a vertical direction (e.g., substantially perpendicular to the surface of the substrate). The nanowires / sheets may extend in a first direction, and opposite ends in the first direction may be connected to a source / drain layer. The source / drain layer may include a semiconductor material different from the nanowires / sheets to enable stress engineering. Additionally, a gate stack may extend along a second direction intersecting (e.g., perpendicular to) the first direction to intersect with each nanowire / sheet, and thus may surround the outer periphery of each nanowire / sheet to form a gate all around (GAA) structure.

[0022] Sidewalls can be formed on the sidewalls of the gate stack. These sidewalls isolate the gate stack from the source / drain layers. The sidewalls can have a substantially identical crystal structure to the nanowires / sheets in at least a portion of their area (particularly the area adjacent to the nanowires / sheets). As described below, this helps improve the crystal quality of the source / drain layers. The sidewalls can comprise a dielectric material, such as a low-k dielectric material. Alternatively, the sidewalls can comprise a semiconductor material with a bandgap greater than or equal to the bandgap of the nanosheets / wires or the source / drain layers, thus functionally equivalent to a dielectric sidewall.

[0023] An isolation portion may be provided between the gate stack and the substrate. The isolation portion may be self-aligned to the gate stack and substantially aligned with the nanowire / sheet in the vertical direction.

[0024] Such a semiconductor device can be fabricated, for example, as follows: Nanowires / sheets extending in a first direction and spaced apart from the surface of the substrate can be formed on a substrate, and a dummy gate extending in a second direction intersecting (e.g., perpendicular to) the first direction to surround the nanowires / sheets can be formed. Sidewalls can be formed on the sidewalls of the dummy gate. The sidewalls can have a substantially identical crystal structure to the nanowires / sheets in at least a portion of their area (particularly the area adjacent to the nanowires / sheets). Source / drain layers can be grown using the ends of the nanowires / sheets in the first direction and the sidewalls (at least a portion of their area) as seeds. Compared to growing solely using the ends of the nanowires / sheets in the first direction as seeds, the source / drain layers can have very few growth defects, or even be substantially defect-free, and thus improve the crystal quality of the source / drain layers.

[0025] An isolation layer can be formed on a substrate, and nanowires / sheets can be disposed on the isolation layer. The isolation layer can be patterned to be self-aligned to the shape of the nanowires / sheets, which can be achieved by etching the isolation layer using the nanowires / sheets (or, a (hard) mask used to form the nanowires / sheets) as a mask. Subsequently, the self-aligned isolation can be formed by replacing the isolation layer with a dielectric material.

[0026] To fabricate nanowires / sheets, one or more gate defining layers and one or more nanowire / sheet defining layers can be stacked alternately on an isolation defining layer. This stack can be patterned as a preliminary nanowire / sheet extending along a first direction. The length of the preliminary nanowire / sheet in the first direction can be greater than the length of the final nanowire / sheet to be formed in the first direction, so that a nanowire / sheet self-aligned with the dummy gate can be subsequently formed. In this patterning step, the isolation defining layer can also be patterned. Thus, the isolation defining layer can be self-aligned with the preliminary nanowire / sheet. At this point, the gate defining layer also takes the shape of a nanowire / sheet. To form a fully surrounding gate, another gate defining layer can be formed and patterned as a strip extending along a second direction. This strip-shaped gate defining layer can be used as a mask to pattern the underlying preliminary nanowire / sheet. Thus, this strip-shaped gate defining layer, together with other gate defining layers, constitutes a dummy gate extending along the second direction, and the nanowire / sheet defining layer is patterned as a nanowire / sheet self-aligned with the dummy gate, with the nanowire / sheet surrounded by the dummy gate. In this patterning step, the isolation layer can also be patterned. Thus, the isolation layer can be self-aligned to the nanowire / sheet.

[0027] To form self-aligned sidewalls, the pseudogate can be selectively etched to make its sidewalls recessed inward relative to the sidewalls of the nanowire / sheet, and the sidewalls are formed in the recesses thus created.

[0028] This disclosure may be presented in various forms, some of which will be described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation) but also etch selectivity. In the following description, the desired etch selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etch selectivity relative to other layers exposed to the same etch formulation.

[0029] Figures 1 to 15(b) The illustrations schematically depict some stages in the process of manufacturing nanowire / sheet devices according to embodiments of the present disclosure.

[0030] like Figure 1 As shown, a substrate 1001 is provided. This substrate 1001 can be of various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, and compound semiconductor substrates such as SiGe substrates. In the following description, for ease of explanation, a bulk Si substrate will be used as an example. Here, a silicon wafer is provided as the substrate 1001.

[0031] An isolation defining layer 1003 may be formed on the substrate 1001 to define the location of the isolation portion to be formed subsequently. An etch stop layer 1005 may be formed on the isolation defining layer 1003. The etch stop layer 1005 can set a stop position when the isolation defining layer 1003 is subsequently etched, especially when there is no etch selectivity or low etch selectivity between the isolation defining layer 1003 and the subsequently formed gate defining layer (e.g., 1007). Alternatively, if there is etch selectivity between the isolation defining layer 1003 and the subsequently formed gate defining layer, the etch stop layer 1005 may be omitted.

[0032] On the etch stop layer 1005, a stack of gate defining layers 1007, 1011, 1015 and nanowire / sheet defining layers 1009, 1013 can be formed in alternating arrangements. The gate defining layers 1007, 1011, 1015 define the positions of the gate stack to be formed subsequently, and the nanowire / sheet defining layers 1009, 1013 define the positions of the nanowires / sheets to be formed subsequently. In this stack, the uppermost layer can be the gate defining layer 1015, such that each nanowire / sheet defining layer 1009, 1013 is covered above and below by the gate defining layer, so as to subsequently form a gate-all-around configuration. In this example, two nanowire / sheet defining layers 1009, 1013 are formed, and thus two nanowires / sheets are formed in the final device. However, this disclosure is not limited to this; the number of nanowire / sheet defining layers to be formed and the number of gate defining layers to be formed can be determined according to the number of nanowires / sheets to be formed (which can be one or more).

[0033] The isolation layer 1003, etch stop layer 1005, gate limiting layers 1007, 1011, 1015, and nanowire / wafer limiting layers 1009, 1013 can be semiconductor layers formed on the substrate 1001 by, for example, epitaxial growth. Thus, the nanowire / wafer limiting layers 1009, 1013 can have good crystal quality and can be a single-crystal structure to subsequently provide single-crystal nanowires / wafers for use as channels. Adjacent semiconductor layers can have etch selectivity so that they can be processed differently subsequently. For example, the etch stop layer 1005 and nanowire / wafer limiting layers 1009, 1013 can include Si, while the isolation layer 1003 and gate limiting layers 1007, 1011, 1015 can include SiGe (the atomic percentage of Ge is, for example, about 10% to 40%, and can be gradually varied to reduce defects). Each semiconductor layer can have a substantially uniform thickness, thus extending substantially parallel to the surface of the substrate 1001. For example, the thickness of the isolation layer 1003 can be about 30 nm to 80 nm, the thickness of the etch stop layer 1005 can be about 3 nm to 15 nm, the thickness of the gate limiting layers 1007, 1011, and 1015 can be about 20 nm to 40 nm, and the thickness of the nanowire / sheet limiting layers 1009 and 1013 can be about 5 nm to 15 nm.

[0034] Next, nanowires / sheets can be patterned. For example, such as... Figure 2(a) and 2(b)As shown, photoresist 1017a or 1017b can be formed on the above stack, and the photoresist 1017a or 1017b can be patterned into nanowires (Fig. 2(a)) or nanosheets (Fig. 2(b)) by photolithography. In the case of nanosheets, the width W of the nanosheet can determine the device width that provides current to the device. In the following description, the case of nanowires is mainly used as an example, but these descriptions are equally applicable to the case of nanosheets. Then, as Figure 3(a) and 3(b) As shown, photoresist 1017a or 1017 can be used as an etching mask, and each layer on substrate 1001 can be selectively etched sequentially by reactive ion etching (RIE) in the vertical direction, for example, until the etching stops at substrate 1001. In this way, each layer on substrate 1001 is patterned into prepared nanowires or nanosheets corresponding to photoresist 1017a or 1017b. Here, the length of the prepared nanowires / sheets (vertical dimension, i.e., the length in the horizontal direction under the orientation of FIG. 3(a)) can be greater than the length of the nanowires / sheets to be formed as channels, in order to subsequently obtain nanowires / sheets self-aligned with the dummy gate (gate stack) for use as channels. Afterwards, photoresist 1017a or 1017b can be removed.

[0035] For electrical isolation purposes, such as Figure 4(a) and 4(b) As shown, an isolation portion 1019, such as shallow trench isolation (STI), can be formed on the substrate 1001. For example, the STI 1019 can be formed by depositing an oxide (e.g., silicon oxide) on the substrate, planarizing the deposited oxide by a process such as chemical mechanical polishing (CMP), and then etching back the planarized oxide by a process such as wet etching, vapor phase etching, or dry etching. Additionally, on the surface of the substrate 1001 where semiconductor layers have been patterned as a stack of nanowires / sheets, a thin etch stop layer 1019' (e.g., with a thickness of about 1 nm to 5 nm) can be formed by deposition, for example. Here, the etch stop layer 1019' can also include oxide and is therefore shown as a thin layer integral with the STI 1019.

[0036] As described above, gate limiting layers 1007, 1011, and 1015 are located above and below nanowire / sheet limiting layers 1009 and 1013, respectively. To form a fully encircling gate, another gate limiting layer can also be formed on the left and right sides in the orientation shown in Figure 4(b). For example, as Figure 5(a) and 5(b)As shown, a gate defining layer 1021 can be formed on STI 1019 and etch stop layer 1019'. For example, gate defining layer 1021 can be formed by depositing a material that is substantially the same or similar to the previous gate defining layers 1007, 1011, and 1015 (thus having substantially the same or similar etch selectivity for processing together), and planarizing the deposited material using a process such as CMP. In this example, gate defining layer 1021 may comprise SiGe with a Ge atomic percentage substantially the same or similar to that of gate defining layers 1007, 1011, and 1015.

[0037] On the gate defining layer 1021, a hard mask layer 1023 can be formed, for example, by deposition, to facilitate patterning. For example, the hard mask layer 1023 may include silicon carbide with a thickness of about 100 nm – 250 nm.

[0038] The gate defining layers 1021 (and 1007, 1011, 1015) can be patterned as pseudo-gates extending along a direction that intersects, for example, perpendicular to, the extension direction of the prepared nanowire / sheet (referred to as the "first direction," e.g., the horizontal direction in Figures 5(a) and 5(b)) (referred to as the "second direction," e.g., the vertical direction in Figure 5(a), and the direction perpendicular to the plane of the paper in Figure 5(b)). For example, photoresist 1025 can be formed on the hard mask layer 1023 and patterned into stripes extending along the second direction by photolithography. Then, using the photoresist 1025 as a mask, selective etching can be performed sequentially between the STI 1019 layers on the substrate 1001 by, for example, RIE, with the etching stopping at the substrate 1001. As a result, the nanowire / sheet defining layers 1009 and 1013 are formed into nanowires or nanosheets that can subsequently be used to provide channels (hereinafter, the nanowire / sheet defining layers 1009 and 1013 are referred to as nanowires / sheets 1009 and 1013), and are surrounded by gate defining layers 1007, 1011, 1015, and 1021 (which can be collectively referred to as "dummy gates"). The nanowires / sheets 1009 and 1013 can be self-aligned to the dummy gates. Afterward, the photoresist 1025 can be removed.

[0039] Additionally, as shown in Figure 5(b), the surfaces of the substrate 1001 are exposed on both sides of the dummy gate, which can facilitate the subsequent growth of source / drain layers. Furthermore, on opposite sides of the isolation defining layer 1003 in the second direction (the direction perpendicular to the plane of the paper in the figure), the STI 1019 can be connected to the isolation defining layer 1003 and can extend self-aligned to the dummy gate (see Figure 8(b)).

[0040] Considering the constraints of the gate space and the isolation between the gate and the source / drain, sidewalls can be formed on the sidewalls of the dummy gate. To ensure that the gate lengths above and below each nanowire / sheet (1009, 1013) are the same, a self-alignment technique can be used to form the sidewalls. For example, as... Figure 6 As shown, the gate defining layers 1007, 1011, 1015, and 1021 (in this example, SiGe) can be selectively etched relative to the nanowires / sheets 1009 and 1013 (Si in this example), such that their sidewalls are recessed to a certain depth relative to the sidewalls of the hard mask layer 1023 or the sidewalls of the nanowires / sheets 1009 and 1013. Preferably, the recessed depths of the gate defining layers 1007, 1011, 1015, and 1021 are substantially the same, and the recessed depths on both the left and right sides are substantially the same. For example, atomic layer etching (ALE) can be used to achieve good etching control. In this example, the isolation defining layer 1003 is also SiGe, so it can also be recessed to substantially the same depth. Thus, after etching, the corresponding sidewalls of the gate defining layers 1007, 1011, 1015, and 1021 (and the isolation defining layer 1003) can be substantially coplanar.

[0041] Sidewalls can be formed within such recesses. For example... Figure 7 As shown, a dielectric material layer 1027 of a certain thickness can be formed on the substrate 1001 by, for example, deposition. The thickness of the deposited dielectric material layer 1027 is sufficient to fill the aforementioned recess, for example, about 3 nm to 15 nm. Then, as... Figure 8(a) and 8(b) As shown, the lateral extension of the dielectric material layer 1027 can be removed, for example, by a vertical RIE, leaving its vertical extension (including the portion below the hard mask layer 1023), thereby forming the sidewall 1027. The sidewalls of the sidewall 1027 can be substantially coplanar with the sidewalls of the hard mask layer 1023 (and the sidewalls of the nanowires / sheets 1009, 1013).

[0042] According to embodiments of this disclosure, the sidewall 1027 can facilitate crystal growth. Unlike conventional sidewall dielectric materials such as oxides (silicon oxide), nitrides (silicon nitride), and oxynitrides (silicon oxynitride), the dielectric material used for the sidewall 1027 can have a substantially identical crystal structure to the nanowires / sheets 1009 and 1013, and can be filled in the recess by epitaxial growth or deposition followed by RIE. The sidewall 1027 can form a eutectic with the nanowires / sheets 1009 and 1013 or the subsequently formed source / drain layers. For example, the sidewall 1027 can include a single-crystal dielectric material with suitable dielectric properties that can match the lattice of the nanowires / sheets 1009 and 1013, such as oxides or nitrides of strontium (Sr), titanium (Ti), lanthanum (La), aluminum (Al), neodymium (Nd), lutetium (Lu), gadolinium (Gd), or combinations thereof. For example, sidewall 1027 may include at least one of SrTiO3, LaAlO3, NdAlO3, GdAlO3, etc. Alternatively, sidewall 1027 may also include a semiconductor material with a bandgap greater than or equal to the bandgap of the nanowire / sheet 1009, 1013 or the subsequently formed source / drain layer, such as undoped Si. According to embodiments, the lattice constant of sidewall 1027 without strain deviates from the lattice constant of nanowire / sheet 1009, 1013 without strain within ±2%.

[0043] like Figure 8(a) and 8(b) As shown, in the first direction (the horizontal direction in Figure 8(a)), the sidewalls of each nanowire / sheet are exposed (and can be substantially coplanar with the sidewalls of the hard mask layer). Figure 9(a) and 9(b) As shown, the exposed sidewalls of the nanowires / sheets (and the surface of the exposed substrate 1001) serve as seeds, and a source / drain layer 1033 is formed by, for example, selective epitaxial growth. The source / drain layer 1033 can be formed to be in contact with all the exposed sidewalls of the nanowires / sheets. The source / drain layer 1033 can comprise a variety of suitable semiconductor materials. To enhance device performance, the source / drain layer 1033 can comprise a semiconductor material with a lattice constant different from that of the nanowires / sheets to apply stress to the nanowires / sheets in which the channel region will be formed. For example, for n-type devices, the source / drain layer 1033 can comprise Si:C (with a C atomic percentage, for example, about 0.1% to 3%) to apply tensile stress; for p-type devices, the source / drain layer 1033 can comprise SiGe (with a Ge atomic percentage, for example, about 20% to 80%) to apply compressive stress. In addition, the source / drain layer 1033 can be doped to the desired conductivity type (n-type doping for n-type devices and p-type doping for p-type devices) by, for example, in-situ doping or ion implantation.

[0044] In the embodiment shown in FIG9(a), the source / drain layer grown from the sidewall of the nanowire / sheet is adjacent to the source / drain layer grown from the surface of the substrate 1001. This facilitates heat dissipation or enhances stress in the channel, thereby improving device performance. Additionally, in the embodiment shown in FIG9(b), the source / drain layer 1033' grown from the sidewall of the nanowire / sheet is spaced apart from the source / drain layer grown from the surface of the substrate 1001. The following description will primarily focus on the scenario shown in FIG9(a).

[0045] Next, an alternative gate process can be implemented.

[0046] For example, such as Figure 10(a) and 10(b) As shown, an interlayer dielectric layer 1035 can be formed on substrate 1001. For example, the interlayer dielectric layer 1035 can be formed by depositing oxide, planarizing the deposited oxide (e.g., CMP), and etching back the planarized oxide. The interlayer dielectric layer 1035 may expose the hard mask layer 1023 but cover the source / drain layer 1033. Subsequently, the hard mask layer 1023 can be removed by selective etching to expose the gate limiting layer 1021.

[0047] Additionally, in the scenario shown in Figure 9(b) above, the interlayer dielectric layer 1035 is also filled between the source / drain layer and the substrate, as shown in Figure 10(c). This helps reduce leakage current. Furthermore, the filling process can be controlled to create holes in the interlayer dielectric layer 1035 between the source / drain layer and the substrate, as shown by the dashed lines in Figure 10(c). This helps reduce the capacitance between the source / drain layer and the substrate.

[0048] To perform the gate replacement process, all dummy gates, i.e., all gate defining layers, should be removed and replaced with gate stacks. Here, considering the formation of the isolation portion below the bottommost gate defining layer 1007, the isolation portion defining layer 1003 can be processed first; specifically, it can be replaced with the isolation portion. For this purpose, a processing channel to the isolation portion defining layer 1003 can be formed.

[0049] For example, selective etching can be used to reduce the height of the gate limiting layer 1021 so that its top surface is lower than the top surface of the isolation limiting layer 1003, while still maintaining a certain thickness to accommodate the subsequent formation of the mask layer (see...). Figure 11(a) and 11(b) The 1037 layer can shield all gate limiting layers 1007, 1011, and 1015 above the top surface of the isolation limiting layer 1003, while exposing the isolation limiting layer 1003. For example, an ALE (Alternating Layer Etching) can be used to better control the etching depth. Here, due to the presence of the etching stop layer 1019', the other gate limiting layers 1007, 1011, and 1015 can remain unaffected.

[0050] Then, as Figure 11(a) and 11(b) As shown, a mask layer, such as photoresist 1037, can be formed on the gate limiting layer 1021. The photoresist 1037 can be patterned into a strip extending along the extension direction of the nanowire / wafer using photolithography, and can mask the nanowire / wafer and the outer surfaces of the gate limiting layers 1007, 1011, and 1015 (with an etch stop layer 1019' sandwiched between them). Due to the presence of the gate limiting layer 1021, a portion of the surface of the isolation limiting layer 1003 is not masked by the photoresist 1037. Subsequently, selective etching can be used to sequentially remove the gate limiting layer 1021, remove a portion of the etch stop layer 1019' exposed by the removal of the gate limiting layer 1021, and remove the isolation limiting layer 1003 exposed by the removal of that portion of the etch stop layer 1019'. Thus, a void is formed below the etch stop layer 1005. Since the isolation layer 1003 and the upper nanowires / wafers and gate limiting layers are defined by the same hard mask layer, the isolation layer 1003 and the upper nanowires / wafers and gate limiting layers are aligned in the vertical direction. Therefore, the gap caused by the removal of the isolation layer 1003 can be self-aligned with the upper nanowires / wafers and gate limiting layers. Afterwards, the photoresist 1037 can be removed.

[0051] In this example, the etch stop layer 1005 is also a semiconductor material and is connected between the opposing source / drain layers, which results in a leakage path. Therefore, as... Figure 12(a) and 12(b) As shown, the etch stop layer 1005 can be cut between opposing source / drain layers by selective etching, such as wet etching using a TMAH solution. The ends of the etch stop layer 1005 can be retained to avoid affecting the source / drain layers on both sides. Alternatively, the remaining ends of the etch stop layer 1005 may not extend into the inner sidewall to avoid contact with the gate defining layer (which is subsequently replaced by a gate stack) inside the sidewall. That is, the inner sidewall of the remaining etch stop layer 1005 can be recessed relative to the inner sidewall of the sidewall. Since etching starts from the middle, the opposing ends of the remaining etch stop layer 1005 can be substantially symmetrical. Furthermore, in this example, both the etch stop layer 1005 and the substrate 1001 comprise silicon, so a portion of the substrate 1001 can also be etched away. Thus, the gap between the lowermost gate defining layer 1007 and the substrate 1001 can be increased, but it can still maintain substantial alignment with the upper nanowires / wafers and the gate defining layer.

[0052] like Figure 13(a) and 13(b)As shown, the voids thus formed can be filled with a dielectric material, such as a low-k dielectric material, to form the isolation portion 1039. The material of the isolation portion 1039 can be etch-selective relative to the STI 1019, such as oxide nitride (e.g., silicon oxynitride). For example, the isolation portion 1039 can be formed by depositing sufficient oxide nitride on the substrate 1001 and etching back the oxide nitride deposited as in RIE. The isolation portion 1039 thus formed can be self-aligned with the above nanowires / sheets and gate defining layers.

[0053] According to another embodiment, such as Figure 14(a) and 14(b) As shown, when depositing dielectric material, due to the limited space of the aforementioned voids, the isolation portion 1039' can form a hollow structure. In this case, the dielectric constant of the isolation portion 1039' can be further reduced.

[0054] Next, as Figure 15(a) and 15(b) As shown, a thin etch stop layer 1019' can be removed by selective etching to expose the gate limiting layer, and the gate limiting layer can be further removed by selective etching. Thus, a gate trench (corresponding to the space originally occupied by each gate limiting layer) is formed inside the sidewall 1027, above the STI 1019 and the isolation portion 1039. In the gate trench thus formed, the gate dielectric layer 1041 and the gate electrode 1043 can be formed sequentially to obtain the final gate stack. For example, the gate dielectric layer 1041 may include a high-k gate dielectric such as HfO2, with a thickness of approximately 2 nm – 10 nm; the gate electrode 1043 may include a work function adjustment layer such as TiN, TiAlN, TaN, etc., and a gate conductor layer such as W, Co, Ru, etc. Before forming the high-k gate dielectric, an interface layer, such as an oxide formed by an oxidation process or deposition such as atomic layer deposition (ALD), with a thickness of approximately 0.3 nm – 2 nm, can also be formed.

[0055] like Figure 15(a) and 15(b) As shown, the nanowire / sheet device according to the embodiment may include nanowires / sheets 1009, 1013 (the number may be less or more) spaced apart from the substrate 1001 and a gate stack surrounding the nanowires / sheets 1009, 1013, the gate stack including a gate dielectric layer 1041 and a gate electrode 1043.

[0056] Sidewalls 1027 are formed on the sidewalls of the gate stack. The inner sidewalls of sidewall 1027 can be substantially coplanar in the vertical direction, thereby providing the same gate length. Additionally, the outer sidewalls of gate sidewall 1027 can also be coplanar in the vertical direction and can be coplanar with the sidewalls of nanowires / sheets 1009 and 1013. As described above, sidewall 1027 can have substantially the same crystal structure as nanowires / sheets 1009 and 1013 to facilitate the growth of high-quality source / drain layers.

[0057] The nanowire / sheet device may further include an isolation portion 1039. As described above, the isolation portion 1039 may be self-aligned to the gate stack or nanosheets 1009, 1013, such that at least a portion of each sidewall of the isolation portion 1039 may be vertically aligned with the corresponding sidewall of the upper gate stack. For example, as shown in FIG15(a), at least the middle portion of each of the opposing sidewalls of the isolation portion 1039 in the nanowire / sheet extension direction (horizontal direction in the figure) may be vertically aligned with the sidewall of the corresponding gate stack. Additionally, as shown in FIG15(b), at least the upper portion of each of the opposing sidewalls of the isolation portion 1039 in the gate extension direction (horizontal direction in the figure) may be vertically aligned with the sidewall of the corresponding gate stack (at the interface between the gate stack and the nanowire / sheet). The portions of each sidewall of the isolation portion 1039 that are not coplanar with the corresponding sidewall of the gate stack (if present; these portions may also be absent due to process variations) may also extend substantially conformally with the corresponding sidewall of the gate stack.

[0058] Sidewall 1027 may also be formed on the sidewall of isolation section 1039. The upper part of isolation section 1039 may be located between the upper and lower parts of sidewall 1027, but does not extend beyond the outer sidewall of sidewall 1027.

[0059] As described above, the isolation portion 1039 is vertically aligned with the nanowires / sheets 1009 and 1013. Furthermore, as shown in FIG15(b), the isolation portion 1039 is connected to the STI 1019 on opposite sides in the gate extension direction (the horizontal direction in FIG15(b)), thereby isolating the gate stack from the substrate through both the isolation portion 1029 and the STI 1019. The STI 1019 below the gate stack can also be self-aligned with the gate stack, as this portion of the STI 1019 can be aligned using the above-described bonding method. Figure 5(a) and 5(b) The described pseudo-gate patterning technique is patterned to remain below the pseudo-gate (which is subsequently replaced by a gate stack).

[0060] In the above embodiments, the entire sidewall 1027 can be used as a seed layer for the growth source / drain layer. However, this disclosure is not limited thereto. For example, only a portion of the sidewall (especially the portion adjacent to at least one of the nanowires / sheets 1009 and 1013) may have a structure substantially the same as that of the nanowires / sheets 1009 and 1013.

[0061] Figures 16(a) to 21 The illustration schematically shows some stages in the process of manufacturing nanowire / sheet devices according to another embodiment of the present disclosure.

[0062] In the above embodiment, after patterning the gate defining layer 1021, photoresist 1025 is used as an etching mask to pattern the lower gate defining layers 1007, 1011, and 1015, thereby forming a dummy gate together. In this embodiment, the sidewalls can be formed in stages. The advantages of forming the sidewalls in stages will be specifically described below in conjunction with subsequent processes.

[0063] For example, such as Figure 16(a) and 16(b) As shown, firstly, a strip of photoresist 1025 is used to pattern (hard mask layer 1023 and) the gate defining layer 1021. Then, as... Figure 17(a) and 17(b) As shown, a first sub-sidewall 1027a can be formed on the sidewall of the gate defining layer 1021, which has been patterned as a strip extending along the second direction. The method for forming the first sub-sidewall 1027a can be the same as the method for forming the sidewall 1027 described above, and it can also be a nitride. Here, the etch-back depth in the sidewall formation process can be controlled so that the first sub-sidewall 1027a is also formed on the sidewall of the semiconductor layer stack, which helps to guide the growth of the source / drain layers.

[0064] After the first sub-sidewall 1027a is formed, it can be joined in a manner similar to the above. Figures 5(a) to 8(b) The second sub-sidewall is formed on the sidewalls of the gate limiting layers 1007, 1011, and 1015.

[0065] For example, such as Figure 18 As shown, the hard mask layer 1023 and the first sub-sidewall 1027a can be used as etching masks to selectively etch the etch stop layer 1019' and each layer in the semiconductor layer stack, such as RIE, sequentially. The etching can stop at the substrate 1001. As a result, the nanowire / sheet defining layers 1009 and 1013 are formed as nanowires / sheets 1009 and 1013, and are surrounded by gate defining layers 1007, 1011, 1015, and 1021 (together forming a "dummy gate"). The nanowires / sheets 1009 and 1013 can be self-aligned to the dummy gate.

[0066] Then, as Figure 19As shown, the gate defining layers 1007, 1011, and 1015 (in this example, SiGe) can be selectively etched relative to the nanowires / sheets 1009 and 1013 (Si in this example), such that their sidewalls are recessed inward to a certain depth in the lateral direction relative to the sidewalls of the nanowires / sheets 1009 and 1013. Preferably, the recessed depths of the gate defining layers 1007, 1011, and 1015 are substantially the same, and the recessed depths on both the left and right sides are substantially the same (and can be substantially equal to the thickness of the first sidewall 1027). For example, ALE can be used to achieve good etching control. In this example, the isolation defining layer 1003 is also SiGe, so it can also be recessed to substantially the same depth. Thus, the corresponding sidewalls of the gate defining layers 1007, 1011, and 1015 (and the isolation defining layer 1003, and even the gate defining layer 1021) can be substantially coplanar after etching.

[0067] A second sub-sidewall can be formed within this recess. For example... Figure 20(a) , 20(b) As shown in 20(c), a second sub-sidewall 1027b can be formed in the recess by, for example, epitaxial growth or deposition followed by RIE etch-back. The second sub-sidewall 1027b is similar to the sidewall 1027 described above and can have substantially the same crystal structure as the nanowires / sheets 1009 and 1013, and their lattice constants can be matched. The second sub-sidewall 1027b, together with the first sub-sidewall 1027a, forms a sidewall defining the space for gate stacking. The outer sidewall of the second sub-sidewall 1027b can be substantially coplanar with the outer sidewall of the first sub-sidewall 1027a (and the sidewalls of the nanowires / sheets 1009 and 1013), and the inner sidewall of the second sub-sidewall 1027b can be substantially flat (thus defining substantially the same gate length above and below the nanowires / sheets 1009 and 1013).

[0068] like Figure 20(a) and 20(c) As shown, on opposite sides in the first direction, substantially continuous and substantially consistent crystal growth surfaces (the outer wall of the second sub-sidewall 1027' + the sidewalls of nanowires / sheets 1009, 1013) can be formed, which helps to grow high-quality source / drain layers.

[0069] like Figure 21 As shown, the outer wall of the second sub-sidewall 1027b and the exposed sidewalls of the nanowires / sheets 1009, 1013 (and the etch stop layer 1005) (and the surface of the exposed substrate 1001) can be used as seeds to form a source / drain layer 1033 through, for example, selective epitaxial growth. As described above, the first sub-sidewall 1027a can guide the growth of the source / drain layer 1033. For details regarding the source / drain layer 1033, please refer to the embodiments described above.

[0070] Due to the presence of continuously extending and substantially uniform crystal growth surfaces as shown in Figure 20(c), the grown source / drain layer 1033 can possess good crystal quality with few or no crystal defects such as dislocations or interfaces. Furthermore, good crystal quality also helps to increase the stress level under applied stress.

[0071] Additionally, as shown in Figure 20(c), in the second direction, besides the second sub-sidewall 1027b in the middle, there are first sub-sidewalls 1027a on both sides. This can limit the growth range of the source / drain layer in the second direction, thereby avoiding unnecessary connection between the source / drain layers of adjacent devices in the second direction (to reduce unnecessary etching steps).

[0072] Next, a similar alternative gate process can be performed, which will not be elaborated here.

[0073] According to embodiments of this disclosure, pseudo-gates can also be used to form self-aligned isolation portions, such as shallow trench isolation (STI).

[0074] Figures 22(a) to 29 The illustration schematically depicts some stages in the fabrication process of nanowire / sheet devices according to another embodiment of this disclosure. The following will primarily describe the differences from the embodiments described above; for other processes not described in detail, please refer to the embodiments above.

[0075] As described above Figures 1 to 4(b) The semiconductor layers can be stacked on the substrate 1001 and patterned as pre-formed nanowires / sheets. An isolation portion 1019 can be formed around the pre-formed nanowires / sheets, and an etch stop layer 1019' can be formed on its surface.

[0076] like Figure 22(a) and 22(b) As shown, it can be combined as described above. Figure 16(a) and 16(b) The pseudo-gate is thus constructed. Here, the photoresist 1025 is constructed as a plurality (e.g., three) of stripes spaced apart (which may be substantially equal in spacing) in a first direction and extending along a second direction.

[0077] Next, the process can be carried out according to the above embodiments.

[0078] For example, such as Figures 23(a) to 23(d) As shown, it can be combined as described above. Figure 17(a) and 17(b) The first sub-sidewall 1027a is formed on the sidewall of the strip-shaped gate defining layer 1021. This first sub-sidewall 1027a can also be formed on the (bottom) sidewall of the semiconductor layer stack to guide the growth of the source / drain layer. Then, it can be combined as described above. Figures 18 to 20(c)As described above, a second sub-sidewall 1027b can be formed, such as Figures 24(a) to 24(d) As shown. Similarly, as shown in Figure 24(d), substantially continuous and substantially consistent crystal growth surfaces (the outer wall of the second sub-sidewall 1027b + the sidewalls of nanowires / sheets 1009 and 1013) can be formed on opposite sides in the first direction. Then, as described above... Figure 21 As described above, a source / drain layer 1033 can be grown.

[0079] Here, a pseudo-gate can be used to create a self-aligned isolation section.

[0080] For example, such as Figure 26 As shown, an interlayer dielectric layer 1035 can be formed on the substrate 1001. The interlayer dielectric layer 1035 can expose the hard mask layer 1023. Figure 27 As shown, the device area can be masked using photoresist 1051, while exposing the area where the isolation portion needs to be formed (in this example, Figure 27 The rightmost region where the dummy gate is located. In the area exposed by the photoresist 1051, the hard mask layer 1023, the gate defining layers 1021, 1015, 1011, and 1017, the nanowires / wafers 1013 and 1019, the isolation layer 1003 (and the etch stop layers 1019' and 1005) can be removed by selective etching such as RIE. Here, the first sub-sidewall 1027 can also be removed. Thus, a trench corresponding to the dummy gate is formed. Afterwards, the photoresist 1051 can be removed. Figure 28 As shown, a dielectric material such as oxide can be filled into the trench thus formed to form an isolation portion 1053. Here, since both the isolation portion 1053 and the interlayer dielectric layer 1035 comprise oxide, their interface is not shown. However, since they are formed separately, their interface can be observed. Alternatively, the isolation portion 1053 may have a second sub-sidewall 1027', nanowire / sheet residues, etc., on its sidewalls, thus defining the sidewalls of the isolation portion 1053. Alternatively, even if the second sub-sidewall 1027', nanowire / sheet residues, etc., on the trench sidewalls are almost completely removed and difficult to observe due to etching control or other reasons during the trench formation process, the presence of the source / drain layers on both sides of the isolation portion 1053 can still define the sidewalls of the isolation portion 1053.

[0081] Next, the process can be carried out according to the above embodiments, for example, by performing a gate replacement process. Thus, the following can be obtained: Figure 29 The nanowire / sheet device shown.

[0082] In this example, the isolation portion 1053 is formed first, followed by the replacement gate process. However, this disclosure is not limited to this. For example, the replacement gate process can be performed first as described in the above embodiment, and then the isolation portion 1053 can be formed (except that during the etching of the trench, the gate defining layer has been replaced with a gate stack). Thus, a result can be obtained as follows: Figure 30 The nanowire / sheet device shown.

[0083] In the above embodiments, the sidewalls are described using a single material layer (e.g., an oxide) as an example. However, this disclosure is not limited thereto. For example, the sidewalls may comprise a stack of multiple layers (e.g., a nitride layer and an oxide layer). For example, the layers in the stack can be deposited sequentially using an ALD.

[0084] The nanowire / chip devices according to embodiments of this disclosure can be applied to various electronic devices. For example, integrated circuits (ICs) can be formed based on such nanowire / chip devices, and electronic devices can be constructed therefrom. Therefore, this disclosure also provides an electronic device including the above-described nanowire / chip devices. The electronic device may also include components such as a display screen that mates with the integrated circuit and a wireless transceiver that mates with the integrated circuit. Examples of such electronic devices include smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, and power banks.

[0085] According to embodiments of this disclosure, a method for manufacturing a system-on-a-chip (SoC) is also provided. This method may include the methods described above. Specifically, multiple devices may be integrated on the chip, at least some of which are manufactured according to the methods of this disclosure.

[0086] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0087] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A nanowire / chip device, comprising: Substrate; Nanowires / sheets spaced apart from the surface of the substrate and extending along a first direction; Source / drain layers located at opposite ends of the nanowire / sheet in the first direction and in contact with the nanowire / sheet; Extending along a second direction intersecting the first direction to surround the gate stack of the nanowire / sheet, the gate stack including a gate dielectric layer and gate electrodes on the gate dielectric layer; as well as Sidewalls are provided on the sidewalls of the grid stack. The sidewalls have a substantially identical crystal structure to the nanowires / sheets in at least a portion of the region adjacent to them. The sidewalls comprise a semiconductor material, wherein the bandgap of the semiconductor material is greater than or equal to the bandgap of the nanowire / sheet or the source / drain layer. Wherein, the lattice constant of the sidewall in at least a portion of the region matches the lattice constant of the nanowire / sheet. Wherein, the lattice constant of the sidewall in at least a portion of the region without strain differs from the lattice constant of the nanowire / sheet in the same region without strain by less than ±2%. The sidewalls form a eutectic with the nanowires / sheets or the source / drain layers.

2. The nanowire / sheet device according to claim 1, wherein, The semiconductor material includes undoped or lightly doped silicon.

3. The nanowire / sheet device according to claim 1, wherein, A plurality of nanowires / sheets are provided, each nanowire / sheet extending substantially parallel to each other in the first direction and substantially aligned in the vertical direction. Among the plurality of nanowires / sheets, the source / drain layers have substantially consistent and continuous crystal surfaces between at least one pair of adjacent nanowires / sheets.

4. The nanowire / sheet device according to claim 3, wherein, The crystal structure of the source / drain layer is characterized by crystals growing on a substantially uniform crystal surface that extends vertically and continuously between the plurality of nanowires / sheets.

5. The nanowire / sheet device according to claim 1, further comprising: An isolation portion located between the gate stack and the substrate, The isolation section is self-aligned with the gate stack.

6. The nanowire / sheet device according to claim 5, further comprising: At least one of the source / drain layers is provided with another isolation portion on the side opposite to the nanowire / sheet in the first direction, the bottom surface of the other isolation portion being lower than the top surface of the isolation portion. The other isolation portion extends along the second direction.

7. The nanowire / sheet device according to claim 6, further comprising: Another side wall is provided on the side wall of the other isolation section.

8. The nanowire / sheet device according to claim 7, wherein, The sidewall includes a first portion above the nanowire / sheet and a second portion below the nanowire / sheet, and the other sidewall includes a first portion at substantially the same height as the first portion of the sidewall and a second portion at substantially the same height as the second portion of the sidewall.

9. The nanowire / sheet device according to claim 8, further comprising: Nanowire / sheet residue between the first and second portions of the other sidewall, in contact with at least one of the source / drain layers.

10. The nanowire / sheet device according to claim 9, wherein, The nanowire / sheet residue is substantially coplanar with the nanowire / sheet.

11. The nanowire / sheet device according to claim 1, wherein, The sidewalls consist of multiple layers.

12. The nanowire / sheet device according to claim 1, wherein, The sidewall above the nanowire / sheet facing the gate stack is substantially coplanar with the sidewall below the nanowire / sheet facing the gate stack.

13. A method for manufacturing nanowire / chip devices, comprising: Nanowires / sheets are disposed on a substrate, spaced apart from the surface of the substrate and extending along a first direction; A pseudo-gate is formed on the substrate, extending along a second direction intersecting the first direction and surrounding the nanowire / sheet; A sidewall is formed on the sidewall of the pseudogate, wherein the sidewall has a substantially identical crystal structure to the nanowire / sheet in at least a portion of the region adjacent to the nanowire / sheet; Using the ends of the nanowires / sheets in the first direction and at least a portion of the sidewalls as seeds, a source / drain layer is grown. The sidewalls comprise a semiconductor material, wherein the bandgap of the semiconductor material is greater than or equal to the bandgap of the nanowire / sheet or the source / drain layer. Wherein, the lattice constant of the sidewall in at least a portion of the region matches the lattice constant of the nanowire / sheet. Wherein, the lattice constant of the sidewall in at least a portion of the region without strain differs from the lattice constant of the nanowire / sheet in the same region without strain by less than ±2%. The sidewalls form a eutectic with the nanowires / sheets or the source / drain layers.

14. The method according to claim 13, wherein, The semiconductor material includes undoped silicon.

15. The method according to claim 13, wherein, Setting the nanowires / sheets includes: An isolation layer is formed on the substrate; One or more gate limiting layers and one or more nanowire / sheet limiting layers are alternately stacked on the isolation portion limiting layer; The stack and the isolation portion defining layer are patterned as pre-existing nanowires / sheets extending along the first direction; Another gate defining layer is formed on the substrate to cover the stack and the isolation defining layer; The other gate defining layer is patterned as a strip extending along the second direction; and Using the strip-shaped other gate defining layer as a mask, the stack is patterned into a linear or sheet-like structure, wherein the nanowire / sheet defining layer patterned into a linear or sheet-like structure forms the nanowire / sheet.

16. The method according to claim 15, wherein, Forming the dummy gate includes: selectively etching the gate defining layer and the other gate defining layer such that their sidewalls are recessed inward relative to the sidewalls of the nanowire / sheet, wherein the gate defining layer and the other gate defining layer together form the dummy gate. Forming the sidewall includes: forming the sidewall in the recess.

17. The method according to claim 16, wherein, Setting the nanowire / sheet further includes: using the strip-shaped other gate defining layer as a mask to pattern the isolation portion defining layer. Forming the dummy gate further includes: selectively etching the isolation portion defining layer so that its sidewalls are recessed inward relative to the sidewalls of the nanowire / sheet. The method also includes: The isolation layer is removed from opposite sides of the nanowire / sheet in the second direction by selective etching. The space created by the removal of the isolation layer is filled with dielectric material to form the isolation portion.

18. The method according to claim 15, wherein, The stripe comprises two stripes, and the method further includes: After the growth source / drain layer, an isolation portion is formed at one of the two strips, the isolation portion being self-aligned with the sidewall and extending through the nanowire / sheet.

19. An electronic device comprising a nanowire / chip device as claimed in any one of claims 1 to 12.

20. The electronic device according to claim 19, including a smartphone, computer, tablet computer, wearable smart device, artificial intelligence device, and power bank.

Images