Semiconductor device with MIM capacitor and method for manufacturing the same

Abstract

The present invention provides a semiconductor device having a MIM capacitor and a method for fabricating the same. The method comprises: providing a substrate, sequentially forming a bottom electrode layer and a first dielectric layer on the substrate; photolithographically etching the first dielectric layer under the action of a first mask to form a MIM capacitor through-hole located in the MIM capacitor region and a conductive plug through-hole located in the non-MIM capacitor region; sequentially forming an interconnect metal layer and a second dielectric layer; performing a surface planarization process to remove the interconnect metal layer and the second dielectric layer outside the MIM capacitor through-hole and the conductive plug; and forming a top plate metal layer on the surface of the second dielectric layer in the MIM capacitor through-hole and the surface of the conductive plug under the action of a second mask. The interconnect metal layer, the second dielectric layer, and the top plate metal layer located within the MIM capacitor through-hole constitute a MIM capacitor, and the top plate metal layer of the MIM capacitor and the top plate metal layer on the surface of the conductive plug are electrically isolated from each other. The present invention can reduce production costs and improve production efficiency by reducing the use of masks.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device with a MIM capacitor and a preparation method thereof. Background Art

[0002] With the rapid development of integrated circuit technology, traditional capacitor devices can no longer meet the needs of radio frequency and other circuits, and Metal-Insulator-Metal capacitors (MIM capacitors for short) have become a new type of capacitor device to replace traditional capacitors. In an environment where device feature sizes are shrinking and device integration is increasing, MIM capacitors are becoming more and more widely used due to their advantages such as high capacitance density, small capacitance voltage coefficient, and low leakage. However, in the current process, the preparation of metal-insulator-metal (MIM) capacitors requires an additional layer of mask (also known as a photomask, mask plate), which increases costs. The current typical MIM capacitor preparation process includes at least the following steps:

[0003] Provide a substrate including a base layer 311 and a dielectric layer 312, on which a MIM capacitor region and a non-MIM capacitor region are defined, and sequentially form a lower plate metal layer 32, a dielectric layer 33 and an upper plate metal layer 34 on the substrate. The process can be referred to Figure 1-3 As shown (usually after forming the lower plate metal layer 32, the lower plate metal layer 32 needs to be etched to form an isolation trench so that the lower plate metal layers 32 located in the MIM capacitor area and the non-MIM capacitor area are electrically isolated from each other, and the isolation trench will be filled with the material of the subsequent dielectric layer 33);

[0004] The upper plate metal layer 34 is etched under the action of the first mask 38 to remove the upper plate metal layer located in the non-MIM capacitor area. The process is generally as follows: a photoresist layer 39 is coated on the upper plate metal layer 34, and then the photoresist layer 39 is exposed and developed under the action of the first mask 38 to define the required pattern, and then the upper plate metal layer is etched according to the residual photoresist layer. The obtained structure is as shown in FIG. Figure 4 As shown;

[0005] An interlayer dielectric layer 35 is formed, and the interlayer dielectric layer 35 covers the MIM capacitor region and the non-MIM capacitor region. The obtained structure is as follows: Figure 5 As shown;

[0006] Under the action of a second mask (not shown, the action process of the second mask can refer to the action process of the first mask), a first through hole 351 and a second through hole 352 are formed in the interlayer dielectric layer 35. The first through hole 351 is located in the MIM capacitor area and exposes the lower plate metal layer 32. The second through hole 352 is located in the non-MIM capacitor area and exposes the lower plate metal layer 32. The resulting structure is as shown in FIG. Figure 6 As shown, it can be seen that the second through hole 352 needs to pass through the dielectric layer 33 and the interlayer dielectric layer 35, so that the second through hole 352 needs to be etched relatively deep. The deeper the through hole, the more difficult it is to etch and the harder it is to ensure that the bottom opening is open. At the same time, the subsequent metal filling becomes more difficult, which can easily cause voids to be filled, resulting in a decrease in the electrical performance of the device.

[0007] An interconnection metal layer 36 is formed, and the interconnection metal layer 36 fills the first through hole 351 and the second through hole 352 and extends to the surface of the interlayer dielectric layer 35. The obtained structure is as follows Figure 7 As shown;

[0008] Under the action of the third mask (also not shown, the action process is described in the above description of the action process of the first mask), an isolation groove 37 is formed in the interconnection metal layer 36 to electrically isolate the interconnection metal layers 37 located in the MIM capacitor area and the non-MIM capacitor area from each other. The resulting structure is as shown in FIG. Figure 8 As shown, the lower plate metal layer 32, the dielectric layer 33 and the upper plate metal layer 34 of the MIM capacitor region constitute a MIM capacitor.

[0009] From the above preparation process, it can be seen that at least three masks are required to prepare a MIM capacitor using the existing process. If lead electrodes are subsequently formed to electrically lead out the MIM capacitor area and the non-MIM capacitor area respectively, the number of masks required will increase. For example, an upper insulating layer 41 covering the interconnection metal layer is first formed on the surface of the structure obtained in the previous step, and then the upper insulating layer 41 is photoetched under the action of the fourth mask to form a plurality of lead electrode through holes in the upper insulating layer 41, which are respectively located in the MIM capacitor area and the non-MIM capacitor area, to expose the interconnection metal layer 36. The lead electrode through holes are then filled with metal to obtain lead electrodes 42. Then, a lead electrode metal layer 43 is formed under the action of the fifth mask to ensure that the lead electrode metal layer in the MIM capacitor area and the lead electrode metal layer in the non-MIM capacitor area are electrically isolated from each other. The final structure is as shown in FIG. Figure 9 shown.

[0010] As we all know, masks are customized products that are not only expensive but also have a long production cycle. Therefore, using too many masks will lead to increased production costs. In addition, photolithography equipment is the most expensive equipment in a semiconductor factory (a single photolithography machine may cost hundreds of millions of yuan). Each semiconductor factory has very limited photolithography equipment, making the photolithography process a bottleneck process that restricts the increase in semiconductor factory production capacity. Therefore, using too many masks means that a single product needs to go through multiple photolithography processes, which will lead to tight photolithography process capacity and reduced output within the semiconductor factory. In addition, the operation of photolithography equipment is complex, the photolithography process is difficult, and the photolithography yield greatly affects the final product yield. These factors have limited the large-scale promotion and application of MIM capacitors. Summary of the Invention

[0011] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a semiconductor device having a MIM capacitor and a method for preparing the same, so as to solve the problems that at least three masks are required when preparing MIM capacitors using the existing process, resulting in increased production costs and decreased output in semiconductor factories.

[0012] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing a semiconductor device having a MIM capacitor, the method comprising the steps of:

[0013] Providing a substrate, wherein a MIM capacitor region and a non-MIM capacitor region are defined on the substrate, and sequentially forming a bottom electrode layer and a first dielectric layer on the substrate, wherein the bottom electrode layer and the first dielectric layer are located in the MIM capacitor region and the non-MIM capacitor region;

[0014] Performing photolithographic etching on the first dielectric layer under the action of a first mask to form a MIM capacitor through-hole and a conductive plug through-hole in the first dielectric layer, wherein the MIM capacitor through-hole is located in the MIM capacitor region, and the conductive plug through-hole is located in the non-MIM capacitor region, and bottom surfaces of the MIM capacitor through-hole and the conductive plug through-hole both expose the bottom electrode layer;

[0015] forming an interconnect metal layer and a second dielectric layer in sequence, wherein the interconnect metal layer is located on a surface of the MIM capacitor through hole and fills the conductive plug through hole, the interconnect metal layer filled in the conductive plug through hole constitutes a conductive plug, and the second dielectric layer is located on a surface of the interconnect metal layer;

[0016] Performing a surface planarization process to remove the interconnect metal layer and the second dielectric layer outside the MIM capacitor through hole and the conductive plug;

[0017] Under the action of the second mask, an upper plate metal layer is formed on the surface of the second dielectric layer of the MIM capacitor through hole and the surface of the conductive plug. The interconnected metal layer, the second dielectric layer and the upper plate metal layer located in the MIM capacitor through hole constitute a MIM capacitor. The upper plate metal layer of the MIM capacitor and the upper plate metal layer on the surface of the conductive plug are electrically isolated from each other.

[0018] Optionally, there are more than two conductive plug through holes, and the more than two conductive plug through holes are distributed in parallel and at intervals.

[0019] Optionally, the first dielectric layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride; the second dielectric layer includes one or more of silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide silicate, hafnium oxide, lanthanum oxide and zirconium oxide; and the interconnect metal layer includes one or more of titanium, titanium nitride, copper and tungsten.

[0020] Optionally, the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer, the top opening dimensions of the conductive plug through hole and the MIM capacitor through hole are both greater than the bottom opening dimensions, and the top dimension of the conductive plug through hole is smaller than the top dimension of the MIM capacitor through hole.

[0021] Optionally, under the action of the second mask, the process of forming the top plate metal layer on the surface of the second dielectric layer of the MIM capacitor through hole and the surface of the conductive plug includes:

[0022] Optionally, an upper plate metal material layer is formed on the structure obtained after the surface planarization treatment, and the upper plate metal material layer covers the MIM capacitor area and the non-MIM capacitor area;

[0023] Optionally, the upper plate metal material layer is photoetched under the action of the second mask to form an upper plate metal layer on the surface of the second dielectric layer and an upper plate metal layer on the surface of the conductive plug, respectively.

[0024] Optionally, the preparation method further includes the step of forming a plurality of lead-out electrodes after forming the upper plate metal layer, and the plurality of lead-out electrodes are electrically connected to the upper plate metal layer on the surface of the second dielectric layer and the upper plate metal layer on the surface of the conductive plug, respectively.

[0025] More optionally, the method of forming the plurality of extraction electrodes includes:

[0026] forming a third dielectric layer, wherein the third dielectric layer covers the MIM capacitor region and the non-MIM capacitor region;

[0027] Performing photolithographic etching on the third dielectric layer under the action of a third mask to form a first extraction electrode hole and a second extraction electrode hole spaced apart from each other in the third dielectric layer, wherein the first extraction electrode hole exposes the upper plate metal layer of the MIM capacitor, and the second extraction electrode hole exposes the upper plate metal layer on the conductive plug;

[0028] Filling the first lead-out electrode hole and the second lead-out electrode hole with metal to form a first lead-out electrode and a second lead-out electrode respectively;

[0029] forming an extraction electrode metal layer, wherein the extraction electrode metal layer is located on surfaces of the first extraction electrode and the second extraction electrode and extends to the upper surface of the third dielectric layer;

[0030] The lead-out electrode metal layer is photoetched under the action of a fourth mask, so that the lead-out electrode metal layers of the MIM capacitor region and the lead-out electrode metal layers of the non-MIM capacitor region are electrically isolated from each other.

[0031] The present invention also provides a semiconductor device having a MIM capacitor, the semiconductor device comprising a substrate, a bottom electrode layer, an interconnect metal layer, a first dielectric layer, a second dielectric layer, and an upper plate metal layer; a MIM capacitor region and a non-MIM capacitor region are defined on the substrate; the bottom electrode layer is located on the upper surface of the substrate; the first dielectric layer is located on the upper surface of the bottom electrode layer, and a MIM capacitor through-hole and a conductive plug through-hole are formed in the first dielectric layer, the MIM capacitor through-hole is located in the MIM capacitor region, the conductive plug through-hole is located in the non-MIM capacitor region, and the bottom surfaces of the MIM capacitor through-hole and the conductive plug through-hole both expose the bottom electrode layer; The interconnection metal layer is located on the surface of the MIM capacitor through-hole and fills the conductive plug through-hole, and the interconnection metal layer filled in the conductive plug through-hole constitutes a conductive plug; the second dielectric layer is located on the upper surface of the interconnection metal layer in the MIM capacitor through-hole; the upper plate metal layer is located on the surface of the second dielectric layer and the surface of the conductive plug, wherein the interconnection metal layer, the second dielectric layer and the upper plate metal layer located in the MIM capacitor through-hole constitute a MIM capacitor, the upper plate metal layer of the MIM capacitor and the upper plate metal layer on the surface of the conductive plug are electrically isolated from each other, and the interconnection metal layer of the MIM capacitor and the conductive plug are electrically isolated from each other.

[0032] Optionally, there are a plurality of conductive plugs, and portions of the conductive plugs extend into the bottom electrode layer.

[0033] Optionally, the semiconductor device further includes a first lead-out electrode and a second lead-out electrode spaced apart from each other, the first lead-out electrode is electrically connected to the MIM capacitor, and the second lead-out electrode is electrically connected to the conductive plug.

[0034] As described above, the semiconductor device with MIM capacitors and the method for preparing the same according to the present invention have the following beneficial effects: the improved process design of the present invention utilizes through-hole etching to produce high and low steps. When the interconnect metal layer is subjected to surface flattening treatment (e.g., chemical mechanical polishing), the conductive metal at the bottom of the step is not removed and serves as the lower plate, the upper metal serves as the upper plate, and the dielectric layer located between the lower plate and the upper plate together constitutes the MIM capacitor. Compared to the prior art, the present invention can effectively reduce the use of masks, which helps to reduce costs, and by reducing the photolithography process, it helps to improve production efficiency and yield. The performance of the semiconductor device with MIM capacitors prepared according to the present invention can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1-9 It shows a schematic diagram of the cross-sectional structure presented at each step in the process of preparing a MIM capacitor in the prior art.

[0036] Figure 10-17 Shown are schematic cross-sectional structures at various steps in the process of manufacturing a semiconductor device having a MIM capacitor according to the manufacturing method provided by the present invention.

[0037] Figure 18 The flowchart shows a method for manufacturing a semiconductor device having a MIM capacitor provided by the present invention.

[0038] Component number description

[0039] 11 substrate

[0040] 111 basal layer

[0041] 112 interlayer dielectric layer

[0042] 12 bottom electrode layer

[0043] 13. First dielectric layer

[0044] 131 MIM capacitor through-hole

[0045] 132 conductive plug through hole

[0046] 14 Interconnect Metal Layers

[0047] 15. Second dielectric layer

[0048] 16 Conductive plug

[0049] 17 Upper plate metal layer

[0050] 17a Upper plate metal material layer

[0051] 18 MIM capacitors

[0052] 19 Third dielectric layer

[0053] 20 First extraction electrode

[0054] 21 Second extraction electrode

[0055] 22 Lead-out electrode metal layer DETAILED DESCRIPTION

[0056] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional views showing the device structure will not be partially enlarged according to the general proportion, and the schematic views are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0057] For convenience, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0058] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

[0059] It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components relevant to the present invention and are not drawn to the exact number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be varied arbitrarily, and the component layout may be more complex. To minimize the illustrations, not all structures are labeled in the drawings.

[0060] In the prior art, at least three masks are required when manufacturing MIM capacitors, which increases production costs and reduces production efficiency. In response to this, the inventors of this application have proposed an improvement solution after long-term research.

[0061] like Figure 10-18 As shown, the present invention provides a method for preparing a semiconductor device having a MIM capacitor, the preparation method (referring to Figure 18 ) comprises the steps of:

[0062] S1: Provide a substrate 11, on which a MIM capacitor region and a non-MIM capacitor region are defined, and a bottom electrode layer 12 and a first dielectric layer 13 are sequentially formed on the substrate 11, wherein the bottom electrode layer 12 and the first dielectric layer 13 are located in the MIM capacitor region and the non-MIM capacitor region, that is, the bottom electrode layer 12 and the first dielectric layer 13 cover the substrate 11; the MIM capacitor region and the non-MIM capacitor region are usually arranged adjacent to each other, the MIM capacitor region is usually used to prepare functional devices such as MIM capacitors, and the non-MIM capacitor region is usually used to prepare peripheral circuits. Of course, The MIM capacitor region and the non-MIM capacitor region may also be spaced apart and a transition region may be provided between the two. The substrate 11 may be a single-layer structure or a multi-layer structure as shown in this embodiment, such as a base layer 111 and an interlayer dielectric layer 112 located on the surface of the base layer 111. The base layer 111 includes but is not limited to a semiconductor substrate such as a silicon substrate, a germanium substrate, a germanium silicon substrate, a sapphire substrate, or an SOI substrate. The interlayer dielectric layer 112 includes but is not limited to a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or other insulating layer. The formation of the interlayer dielectric layer 112 The method includes but is not limited to vapor deposition; the material of the bottom electrode layer 12 includes but is not limited to one or more materials such as copper, aluminum, metal silicide, etc., the method for forming the bottom electrode layer 12 includes but is not limited to physical vapor deposition, and the bottom electrode layer 12 of the MIM capacitor area and the non-MIM capacitor area is usually electrically isolated, such as by isolation grooves (the isolation grooves can be filled with the material of the first dielectric layer 13) for isolation; the first dielectric layer 13 includes but is not limited to one or more of silicon oxide, silicon nitride and silicon oxynitride, the method for forming the first dielectric layer 13 includes but is not limited to vapor deposition, the thickness of each structural layer can be set according to the needs of the device, for example, the thickness of the bottom electrode layer 12 can be 200nm-1000nm (when describing the numerical range in this specification, unless otherwise specified, the endpoint value is included), the thickness of the first dielectric layer 13 is 500nm-5000nm, preferably 2000nm-3000nm, to ensure that the MIM capacitor through hole 131 etched subsequently has a certain depth and ensure that the inside of the through hole will not be completely filled with metal and retain a step; the structure obtained after this step is as shown Figure 10 As shown;

[0063] S2: Photolithographically etching the first dielectric layer 13 under the action of a first mask (not shown) to form a MIM capacitor through hole 131 and a conductive plug through hole 132 in the first dielectric layer 13, wherein the MIM capacitor through hole 131 is located in the MIM capacitor region; the conductive plug through hole 132 is located in the non-MIM capacitor region; the bottom surfaces of the MIM capacitor through hole 131 and the conductive plug through hole 132 both expose the bottom electrode layer 12; specifically, the process of photolithographically etching the dielectric layer using the first mask can be as follows: first, a photoresist layer is formed on the surface of the first dielectric layer 13, then, under the action of the first mask, the photoresist layer is exposed and developed to define a desired pattern, and then, according to the residual photoresist layer, the first dielectric layer 13 is dry-etched or wet-etched to form the MIM capacitor through hole 131 and the conductive plug through hole 132, and finally, the residual photoresist layer is removed; since the photolithographic etching process is known to those skilled in the art, it is not referred to in this specification. Not shown in the figure; the number of the MIM capacitor through-hole 131 is usually single, or there can be more than two, and the number of the conductive plug through-hole 132 can be single, but usually there are more than two. When the number is more than two, multiple conductive plug through-holes 132 are arranged in parallel and spaced apart; and in a preferred example, the MIM capacitor through-hole 131 and the conductive plug through-hole 132 are both structures with a top opening larger than the bottom opening (that is, a trapezoidal structure with a wide top and a narrow bottom in cross-section), which facilitates subsequent metal filling; the depths of the MIM capacitor through-hole 131 and the conductive plug through-hole 132 can be the same or different, for example, the conductive plug through-hole 132 can be slightly deeper into the bottom electrode layer 12, which will help to ensure the electrical connection of the device, and as an example, the size of the MIM capacitor through-hole 131 is usually larger than the size of the conductive plug through-hole 132 (including the top opening size of the former being larger than the top opening size of the latter and the bottom opening size of the former being larger than the bottom opening size of the latter); the structure obtained after this step is as shown Figure 11 As stated;

[0064] S3: sequentially forming an interconnection metal layer 14 and a second dielectric layer 15, wherein the interconnection metal layer 14 is located on the surface of the MIM capacitor through hole 131 (but does not fill the MIM capacitor through hole 131 and ensures that there is still a certain height difference between the bottom surface and the upper surface of the MIM capacitor through hole 131, i.e., forming a step) and fills the conductive plug through hole 132, and the interconnection metal layer 14 filled in the conductive plug through hole 132 constitutes a conductive plug 16, and the second dielectric layer 15 is located on the surface of the interconnection metal layer 14; as an example, the interconnection metal layer 14 includes but is not limited to one or more of titanium, titanium nitride, copper and tungsten, and its shape The formation method includes but is not limited to sputtering, and the thickness is usually greater than the thickness of the first dielectric layer 13 to ensure that it can extend to the surface of the first dielectric layer 13 after filling the MIM capacitor through hole 131 and the conductive plug through hole 132; as an example, the second dielectric layer 15 includes but is not limited to a combination of one or two of silicon oxide and silicon nitride, and can also use a high-K dielectric material, such as one or more of aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide silicate, hafnium oxide, lanthanum oxide and zirconium oxide, and its formation method includes but is not limited to vapor deposition, and the thickness can be 200nm-500nm; the structure obtained after this step is as follows Figure 12 As shown;

[0065] S4: performing a surface planarization process including but not limited to chemical mechanical polishing (CMP) to remove the interconnection metal layer 14 and the second dielectric layer 15 outside the MIM capacitor through hole 131 and the conductive plug 16, and retaining only the interconnection metal layer 14 and the second dielectric layer 15 located on the inner surface of the MIM capacitor through hole 131, and the interconnection metal layer 14 located in the conductive plug through hole 132, so that the upper surface of the conductive plug 16 is flush with the upper surface of the first dielectric layer 13; after the planarization process, the bottom of the MIM capacitor through hole 131 still has a certain height difference with the upper surface of the device, for example, with the upper surface of the first dielectric layer 13; the structure obtained after this step is as follows Figure 13 As shown;

[0066] S5: Under the action of the second mask, an upper plate metal layer 17 is formed on the surface of the second dielectric layer 15 of the MIM capacitor through hole 131 and the surface of the conductive plug 16. The interconnected metal layer 14, the second dielectric layer 15 and the upper plate metal layer 17 located in the MIM capacitor through hole 131 constitute a MIM capacitor 18. The MIM capacitor 18 may be single or multiple. The upper plate metal layer 17 of the MIM capacitor 18 and the upper plate metal layer 17 on the surface of the conductive plug 16 are electrically isolated from each other. In one example, the process may be: first, physical vapor deposition is used, including but not limited to The method forms an upper plate metal material layer 17a on the surface of the structure obtained after the surface flattening treatment, and the upper plate metal material layer 17a covers the MIM capacitor area and the non-MIM capacitor area, that is, the upper plate metal material layers 17a of the MIM capacitor area and the non-MIM capacitor area are formed simultaneously in the same process and are interconnected. The material of the upper plate metal material layer 17a can be the same as or different from the material of the interconnection metal layer 14, for example, it can also include but is not limited to one or more of titanium, titanium nitride, copper and tungsten, and can also be the same as the material of the bottom electrode layer 12. The structure obtained after this step is as shown in FIG. Figure 14 As shown;

[0067] Under the action of the second mask, the upper plate metal material layer 17a is photoetched to form an isolation trench between the upper plate metal material layer 17a located between the MIM capacitor area and the non-MIM capacitor area, so that the upper plate metal material layers 17a in the two areas are disconnected from each other, so as to form the upper plate metal layer 17 located on the surface of the second dielectric layer 15 (formed by the upper plate metal material layer located on the surface of the second dielectric layer 15) and the upper plate metal layer 17 on the surface of the conductive plug 16 (formed by the upper plate metal material layer located on the surface of the conductive plug 16, and when there are multiple conductive plugs 16, the upper plate metal layers 17 on the surfaces of different conductive plugs 16 are electrically isolated from each other). The structure obtained after this step is as follows: Figure 15 Thus far, the preparation of the MIM capacitor 18 is completed in this embodiment.

[0068] From the above process, it can be seen that in the process of preparing the MIM capacitor, the present invention uses an optimized process design to use through-holes (MIM capacitor through-holes) to etch high and low steps. When the surface of the interconnect metal layer is flattened, the conductive metal at the bottom of the step will not be removed and serves as the MIM lower plate. The upper metal serves as the upper plate, and the dielectric layer located between the lower plate and the upper plate, together with the dielectric layer, constitutes the MIM capacitor. Compared with the prior art, the present invention can effectively reduce the use of masks, which helps to reduce costs. The use of only two masks means that only two photolithography processes are required, which helps to improve the output rate of the photolithography machine. At the same time, due to the reduction of the photolithography process, the overall difficulty of the process is reduced, which helps to improve the product yield. The semiconductor device prepared according to the present invention only needs to etch a single first dielectric layer when etching to form a conductive plug through-hole in the non-MIM area, which helps to ensure that the bottom of the conductive plug through-hole is completely open, and can ensure good filling when subsequently filling the interconnect metal material, reducing the generation of holes and helping to improve the electrical performance of the device.

[0069] As an example, to achieve electrical extraction of the device, the preparation method further includes the step of forming a plurality of extraction electrodes after forming the upper plate metal layer 17, wherein the plurality of extraction electrodes are electrically connected to the upper plate metal layer 17 on the surface of the second dielectric layer 15 and the upper plate metal layer 17 on the surface of the conductive plug 16, respectively. In a further example, the method of forming the plurality of extraction electrodes includes:

[0070] A third dielectric layer 19 is formed, and the third dielectric layer 19 covers the MIM capacitor area and the non-MIM capacitor area. The third dielectric layer 19 can be made of the same material as the first dielectric layer 13, or a different material, including but not limited to silicon nitride, silicon oxide, silicon oxynitride or other insulating materials. The formation process includes but is not limited to a vapor deposition process. After the third dielectric layer 19 is formed, it is usually chemically mechanically polished to make its upper surface flush. The upper surface of the polished third dielectric layer 19 needs to have a certain distance from the upper plate metal layer 17 on the conductive plug 16. The structure obtained after this step is as follows: Figure 16 As shown;

[0071] The third dielectric layer 19 is photoetched under the action of a third mask to form a first extraction electrode hole and a second extraction electrode hole spaced apart from each other in the third dielectric layer 19. The first extraction electrode hole exposes the upper plate metal layer 17 of the MIM capacitor 18, and the second extraction electrode hole exposes the upper plate metal layer 17 on the conductive plug 16. The first extraction electrode hole and the second extraction electrode 21 can each be a single hole or two or more holes.

[0072] Filling the first lead-out electrode hole and the second lead-out electrode hole with metal using a process including but not limited to sputtering deposition to form a first lead-out electrode 20 and a second lead-out electrode 21 respectively, wherein the filled metal includes but is not limited to tungsten and / or copper;

[0073] The extraction electrode metal layer 22 is formed by a process including but not limited to physical vapor deposition. The extraction electrode metal layer 22 is located on the surface of the first extraction electrode 20 and the second extraction electrode 21 and extends to the upper surface of the third dielectric layer 19. The extraction electrode metal layer 22 is made of but not limited to copper, aluminum, gold or metal silicide.

[0074] The extraction electrode metal layer 22 is photoetched under the action of the fourth mask to electrically isolate the extraction electrode metal layers 22 of the MIM capacitor area and the non-MIM capacitor area from each other, that is, the first extraction electrode 20 and the second extraction electrode 21 are not connected, while the plurality of first extraction electrodes 20 are electrically connected to each other, and the plurality of second extraction electrodes 21 can be electrically isolated from each other according to the needs of the device; the structure obtained after this step is as shown Figure 17 Of course, in other examples, the process of forming the lead-out electrode may also include, after etching the first lead-out electrode hole and the second lead-out electrode hole, continuing to use a mask to cover the area where no lead-out metal is required and only performing metal deposition on specific areas (this requires higher requirements for deposition equipment and is therefore relatively difficult), such as only filling the first lead-out electrode hole and the second lead-out electrode hole with metal.

[0075] The present invention also provides a semiconductor device having a MIM capacitor, which can be prepared according to any of the above methods, so the above content can be quoted here in its entirety. Of course, the semiconductor device can also be prepared according to other methods. Figure 17As shown, the semiconductor device includes a substrate 11, a bottom electrode layer 12, an interconnect metal layer 14, a first dielectric layer 13, a second dielectric layer 15 and an upper plate metal layer 17; a MIM capacitor region and a non-MIM capacitor region are defined on the substrate 11, and the MIM capacitor region and the non-MIM capacitor region are usually arranged adjacent to each other, and of course they can also be spaced apart from each other; the bottom electrode layer 12 is located on the upper surface of the substrate 11, and the material of the bottom electrode layer 12 includes but is not limited to copper, aluminum and metal silicide; the first dielectric layer 13 is located on the upper surface of the bottom electrode layer 12, and a MIM capacitor through hole 131 and a conductive plug through hole 132 are formed in the first dielectric layer 13, the MIM capacitor through hole 131 is located in the MIM capacitor region, the conductive plug through hole 132 is located in the non-MIM capacitor region, and the bottom surfaces of the MIM capacitor through hole 131 and the conductive plug through hole 132 both expose the bottom electrode layer 12; the interconnect metal layer 14 The interconnecting metal layer 14 is located on the surface of the MIM capacitor through-hole 131 and fills the conductive plug through-hole 132. The interconnecting metal layer 14 filled in the conductive plug through-hole 132 constitutes a conductive plug 16. The conductive plug 16 can be single or multiple. When there are multiple conductive plugs, the multiple conductive plugs 16 are distributed at intervals. The second dielectric layer 15 is located on the upper surface of the interconnecting metal layer 14 of the MIM capacitor through-hole 131. The top plate metal layer 17 is located on the surface of the second dielectric layer 15 and the surface of the conductive plug 16. The interconnecting metal layer 14, the second dielectric layer 15, and the top plate metal layer 17 located in the MIM capacitor through-hole 131 constitute a MIM capacitor 18. The top plate metal layer 17 of the MIM capacitor 18 and the top plate metal layer 17 on the surface of the conductive plug 16 are electrically isolated from each other. The interconnecting metal layer 14 of the MIM capacitor 18 and the conductive plug 16 are electrically isolated from each other.

[0076] The substrate 11 may be a single-layer structure or a multi-layer structure as shown in this embodiment, for example, including a base layer 111 and an interlayer dielectric layer 112 located on the surface of the base layer 111, wherein the base layer 111 includes but is not limited to a semiconductor substrate such as a silicon substrate, a germanium substrate, a germanium silicon substrate, a sapphire substrate, or an SOI substrate, and the interlayer dielectric layer 112 includes but is not limited to a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or other insulating layers.

[0077] As an example, the material of the interconnect metal layer 14 includes, but is not limited to, one or more of titanium, titanium nitride, copper, and tungsten. The materials of the top plate metal layer 17 and the bottom plate metal layer can be the same or different, such as, but not limited to, one or more of titanium, titanium nitride, copper, and tungsten.

[0078] As an example, the second dielectric layer 15 includes but is not limited to a combination of one or both of silicon oxide and silicon nitride, and may also use a high-K dielectric material, such as one or more of but not limited to aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide silicate, hafnium oxide, lanthanum oxide and zirconium oxide.

[0079] In one example, the conductive plug 16 extends into the bottom electrode layer 12 to ensure electrical connection between the conductive plug 16 and the bottom electrode layer 12 .

[0080] In one example, the semiconductor device further includes a first lead-out electrode 20 and a second lead-out electrode 21 spaced apart from each other, the first lead-out electrode 20 being electrically connected to the MIM capacitor 18, the first lead-out electrodes 20 being multiple and electrically connected to each other, the second lead-out electrode 21 being electrically connected to the conductive plug 16, and the number of the second lead-out electrodes 21 being generally consistent with the number of the conductive plugs 16 and corresponding one to one.

[0081] For more information about the semiconductor device, please refer to the above content, which will not be repeated for the sake of brevity.

[0082] In summary, the present invention provides a semiconductor device with a MIM capacitor and a preparation method thereof. In the process of preparing the MIM capacitor, the present invention uses an optimized process design to produce high and low steps by etching through holes (MIM capacitor through holes). When the surface of the interconnecting metal layer is flattened, the conductive metal at the bottom of the step will not be removed and serves as the MIM lower plate. The upper metal serves as the upper plate, and the dielectric layer located between the lower plate and the upper plate, together with the dielectric layer, constitutes the MIM capacitor. Compared with the prior art, the present invention can effectively reduce the use of masks, which helps to reduce costs, and only using two masks means that only two photolithography processes are required, which helps to improve the output rate of the photolithography machine. At the same time, due to the reduction of the photolithography process, the overall difficulty of the process is reduced, which helps to improve the product yield. In the semiconductor device prepared according to the present invention, when etching to form a conductive plug through hole in the non-MIM area, only a single first dielectric layer needs to be etched, which helps to ensure that the bottom of the conductive plug through hole is completely open, and can ensure good filling when the interconnecting metal material is subsequently filled, which helps to improve the electrical performance of the device. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0083] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor device having a MIM capacitor, characterized in that: The preparation method comprises the steps of: Providing a substrate, wherein a MIM capacitor region and a non-MIM capacitor region are defined on the substrate, and sequentially forming a bottom electrode layer and a first dielectric layer on the substrate, wherein the bottom electrode layer and the first dielectric layer are located in the MIM capacitor region and the non-MIM capacitor region; Performing photolithographic etching on the first dielectric layer under the action of a first mask to form a MIM capacitor through-hole and a conductive plug through-hole in the first dielectric layer, wherein the MIM capacitor through-hole is located in the MIM capacitor region, and the conductive plug through-hole is located in the non-MIM capacitor region, and bottom surfaces of the MIM capacitor through-hole and the conductive plug through-hole both expose the bottom electrode layer; An interconnect metal layer and a second dielectric layer are sequentially formed, wherein the interconnect metal layer is located on a surface of the MIM capacitor through hole and fills the conductive plug through hole, the interconnect metal layer filled in the conductive plug through hole forming a conductive plug, and the second dielectric layer is located on a surface of the interconnect metal layer; and neither the interconnect metal layer nor the second dielectric layer completely fills the MIM capacitor through hole, resulting in a height difference between the bottom surface of the MIM capacitor through hole and the upper surface of the sidewall, forming a step; Performing a surface planarization process to remove the interconnect metal layer and the second dielectric layer outside the MIM capacitor through hole and the conductive plug; Under the action of the second mask, an upper plate metal layer is formed on the surface of the second dielectric layer of the MIM capacitor through hole and the surface of the conductive plug. The interconnected metal layer, the second dielectric layer and the upper plate metal layer located in the MIM capacitor through hole constitute a MIM capacitor. The upper plate metal layer of the MIM capacitor and the upper plate metal layer on the surface of the conductive plug are electrically isolated from each other.

2. The preparation method according to claim 1, characterized in that There are more than two conductive plug through holes, and the more than two conductive plug through holes are distributed in parallel and at intervals.

3. The preparation method according to claim 1, characterized in that The first dielectric layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride; the second dielectric layer includes one or more of silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide silicate, hafnium oxide, lanthanum oxide and zirconium oxide; the interconnect metal layer includes one or more of titanium, titanium nitride, copper and tungsten.

4. The preparation method according to claim 1, characterized in that The thickness of the first dielectric layer is greater than that of the second dielectric layer, the top opening sizes of the conductive plug through hole and the MIM capacitor through hole are both greater than the bottom opening sizes, and the top size of the conductive plug through hole is smaller than the top size of the MIM capacitor through hole.

5. The preparation method according to claim 1, characterized in that The process of forming an upper plate metal layer on the surface of the second dielectric layer of the MIM capacitor through hole and the surface of the conductive plug under the action of the second mask includes: Forming an upper plate metal material layer on the structure obtained after the surface planarization treatment, wherein the upper plate metal material layer covers the MIM capacitor area and the non-MIM capacitor area; The upper plate metal material layer is photoetched under the action of the second mask to form an upper plate metal layer on the surface of the second dielectric layer and an upper plate metal layer on the surface of the conductive plug, respectively.

6. The preparation method according to claim 1, characterized in that The preparation method further includes the step of forming a plurality of lead-out electrodes after forming the upper plate metal layer, wherein the plurality of lead-out electrodes are electrically connected to the upper plate metal layer on the surface of the second dielectric layer and the upper plate metal layer on the surface of the conductive plug, respectively.

7. The preparation method according to claim 6, characterized in that The method of forming the plurality of extraction electrodes includes: forming a third dielectric layer, wherein the third dielectric layer covers the MIM capacitor region and the non-MIM capacitor region; Performing photolithographic etching on the third dielectric layer under the action of a third mask to form a first extraction electrode hole and a second extraction electrode hole spaced apart from each other in the third dielectric layer, wherein the first extraction electrode hole exposes the upper plate metal layer of the MIM capacitor, and the second extraction electrode hole exposes the upper plate metal layer on the conductive plug; Filling the first lead-out electrode hole and the second lead-out electrode hole with metal to form a first lead-out electrode and a second lead-out electrode respectively; forming an extraction electrode metal layer, wherein the extraction electrode metal layer is located on surfaces of the first extraction electrode and the second extraction electrode and extends to the upper surface of the third dielectric layer; The lead-out electrode metal layer is photoetched under the action of a fourth mask, so that the lead-out electrode metal layers of the MIM capacitor region and the lead-out electrode metal layers of the non-MIM capacitor region are electrically isolated from each other.

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