A Current-Reused Wideband Low-Noise Amplifier

Abstract

The present invention discloses a current-reused broadband low-noise amplifier, which is externally connected to a power supply and ground, and includes: a first PMOS transistor, a current biasing circuit, a pre-stage amplifier, a post-stage noise cancellation circuit, and a low-gain control path. The source of the first PMOS transistor is connected to the power supply, and the gate is connected to the drain. One end of the current biasing circuit is connected to the drain of the first PMOS transistor, and the other end is connected to ground. The post-stage noise cancellation circuit is connected to the power supply, ground, the total input terminal, and the total output terminal for canceling the post-stage noise. The pre-stage amplifier is connected to the power supply and ground on the one hand, and connected to the total input terminal, the gate of the first PMOS transistor, and the post-stage noise cancellation circuit on the other hand for achieving broadband matching of the circuit input stage and forming a pre-stage gain. The low-gain control path is connected to the total input terminal and the total output terminal for switching between high and low gains and performing low-gain distribution. The present invention can provide good voltage margin and has small variations with process, temperature, and voltage.

Description

Technical Field

[0001] The present invention relates to a broadband low-noise amplifier. Background Art

[0002] Nowadays, with the rapid development of various wireless communication systems and technologies such as mobile communication, wireless broadcasting, and wireless local area network, radio frequency integrated circuits have become a research and development hotspot in universities, research institutes, and communication-related industries worldwide. The low-noise amplifier is one of the key modules of radio frequency integrated circuits. It is the first active module in the radio frequency front-end of the receiver. Its main function is to amplify radio frequency signals and provide appropriate gain to overcome the noise of subsequent circuits. It should not only have very low noise and a certain amount of gain, but also provide sufficiently high linearity.

[0003] Traditional noise-canceling low-noise broadband amplifiers, such as Figure 2 shown, use PMOS transistor 53 and NMOS transistor 54 as the transconductance for bias current multiplexing, and together with resistor 59, provide corresponding input matching for the low-noise amplifier. The mirror current source (PMOS transistors 57, 58) provides DC bias for PMOS transistor 53 and NMOS transistor 54. NMOS transistors 55, 56 together constitute a noise cancellation stage, whose function is to invert and cancel the thermal noise passing through the DC blocking capacitor 61 and processed by the source follower 56 and the partial signal thermal noise passing through amplifier 55. At this time, the signal is amplified and added in the forward direction through 54, 55, 56. Thus, the noise-canceling amplifier reduces the noise figure to a certain extent and improves the signal-to-noise ratio.

[0004] As the integrated circuit process enters the deep sub-micron era of smaller feature sizes, radio frequency integrated circuits are facing the dilemma of operating at low voltages. As Figure 2 shown, the low-noise amplifiers of the early long-channel process often stack two or three transistors and resistors as loads on the voltage path, which will cause a reduction in voltage margin and cannot be used in a low power supply voltage operating environment. Summary of the Invention

[0005] The purpose of the present invention is to provide a current multiplexing type broadband low-noise amplifier, which can provide good voltage margin and has small variations with process, temperature, and voltage.

[0006] The technical solution to achieve the above purpose is:

[0007] A current multiplexing type broadband low-noise amplifier, externally connected to a power supply and ground, includes: a first PMOS (P-type field effect transistor) transistor, a current bias circuit, a pre-stage amplifier, a post-stage noise cancellation circuit, and a low-gain control path.

[0008] The source of the first PMOS transistor is connected to the power supply, and the gate is connected to the drain.

[0009] One end of the current bias circuit is connected to the drain of the first PMOS transistor, and the other end is connected to ground;

[0010] The post-stage noise cancellation circuit is connected to the power supply, ground, the total input terminal and the total output terminal, and is used to cancel the post-stage noise;

[0011] On the one hand, the pre-stage amplifier is connected to the power supply and ground, and on the other hand, it is connected to the total input terminal, the gate of the first PMOS transistor and the post-stage noise cancellation circuit, and is used to achieve broadband matching of the circuit input stage and form the pre-stage gain;

[0012] The low-gain control path is connected to the total input terminal and the total output terminal, and is used to switch between high and low gains and perform low-gain distribution.

[0013] Preferably, the low-gain control path includes: three capacitive voltage-divider circuits connected in series in sequence to form a three-stage capacitive voltage-divider gain attenuation network,

[0014] The capacitive voltage-divider circuit includes a first capacitor, a second capacitor, a first switch and a second switch;

[0015] One end of the first capacitor is connected to the total input terminal or the output terminal of the previous capacitive voltage-divider circuit, and the other end is connected to the output terminal of the capacitive voltage-divider circuit to which it belongs;

[0016] One end of the second capacitor is connected to the output terminal of the capacitive voltage-divider circuit to which it belongs, and the other end is grounded through the second switch;

[0017] One end of the first switch is connected to the output terminal of the capacitive voltage-divider circuit to which it belongs, and the other end is connected to the total output terminal.

[0018] Preferably, the pre-stage amplifier includes: a second PMOS transistor, a third PMOS transistor, a second capacitor, a third switch, a feedback resistor and a first NMOS transistor (N-type field effect transistor), where,

[0019] The source of the second PMOS transistor is connected to the power supply, the gate is connected to the gate of the first PMOS transistor, and the drain is used as the connection end of the pre-stage amplifier and the post-stage noise cancellation circuit;

[0020] The source of the third PMOS transistor is connected to the power supply, the gate is connected to the gate of the first PMOS transistor, and the drain is connected to the connection end of the pre-stage amplifier and the post-stage noise cancellation circuit;

[0021] One end of the second capacitor is connected to the gate of the first PMOS transistor, and the other end is connected to the total input terminal;

[0022] One end of the third switch is connected to the total input terminal, and the other end is connected to the connection end of the pre-stage amplifier and the post-stage noise cancellation circuit through the feedback resistor;

[0023] The gate of the first NMOS transistor is connected to the total input terminal, the source is grounded, and the drain is connected to the connection end of the pre-stage amplifier and the post-stage noise cancellation circuit.

[0024] Preferably, the post-stage noise cancellation circuit includes: a second NMOS transistor, a third NMOS transistor, a third capacitor, and a fourth switch,

[0025] The drain of the second NMOS transistor is connected to the power supply, the gate is connected to the connection end of the pre-stage amplifier and the post-stage noise cancellation circuit through the series-connected fourth switch and third capacitor, and the source is connected to the total output terminal;

[0026] The source of the third NMOS transistor is grounded, the gate is connected to the total input terminal, and the drain is connected to the total output terminal.

[0027] Preferably, the current bias circuit includes: a startup circuit, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and a resistor,

[0028] The connection end of the sources of the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor serves as the input terminal of the current bias circuit and is connected to the drain of the first PMOS transistor;

[0029] The gates of the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are connected together;

[0030] The gate of the fifth PMOS transistor is connected to the drain;

[0031] The source of the fourth NMOS transistor is grounded, and the gate and drain are both connected to the gate of the fifth NMOS transistor;

[0032] The source of the fifth NMOS transistor is grounded through the resistor, and the drain is connected to the drain of the fifth PMOS transistor;

[0033] The source of the sixth NMOS transistor is grounded, the gate is connected to the drain, and the drain is connected to the drain of the PMOS transistor;

[0034] The source of the seventh NMOS transistor is grounded, and the gate is connected to the gate of the sixth NMOS transistor;

[0035] The first end of the startup circuit is connected to the input terminal of the current bias circuit, the second end is connected to the drain of the fourth NMOS transistor, and the third end is grounded.

[0036] Preferably, the startup circuit includes: a seventh PMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor.

[0037] The source of the seventh PMOS transistor serves as the first terminal, the gate is connected to the drain, and the drain is connected to the gate of the ninth NMOS transistor.

[0038] The drain of the ninth NMOS transistor is connected to the source of the seventh PMOS transistor, and the source serves as the second terminal.

[0039] The source of the eighth NMOS transistor serves as the third terminal, the gate is connected to the drain, and the drain is connected to the drain of the ninth NMOS transistor.

[0040] The beneficial effects of the present invention are as follows: Based on the traditional noise cancellation type amplifier, the present invention establishes a pre-stage current reuse structure, which can provide good voltage margin in an environment powered by a low voltage. In addition, since no passive inductors, capacitors, and resistors are used as the load of the amplification stage, the low-noise amplifier of the present invention changes less with process, temperature, and voltage, facilitating large-scale production. Description of the Drawings

[0041] Figure 1 is the circuit diagram of the current reuse type broadband low-noise amplifier of the present invention;

[0042] Figure 2 is the circuit diagram of the noise cancellation type broadband low-noise amplifier in the prior art;

[0043] Figure 3 is the circuit diagram of the low-gain control path in the present invention;

[0044] Figure 4 is the circuit diagram of the current bias circuit in the present invention;

[0045] Figure 5 is the circuit diagram of the differential structure current reuse noise cancellation type broadband low-noise amplifier in the present invention. Detailed Embodiments

[0046] The present invention will be further described below in conjunction with the drawings.

[0047] Please refer to Figures 1-5 , the current reuse type broadband low-noise amplifier of the present invention, with an external power supply and ground, includes: a first PMOS transistor 11, a current bias circuit 12, a pre-stage amplifier 13, a post-stage noise cancellation circuit 14, and a low-gain control path 15.

[0048] The source of the first PMOS transistor 11 is connected to the power supply VDD, and the gate is connected to the drain. One end of the current bias circuit 12 is connected to the drain of the first PMOS transistor 11, and the other end is connected to the ground VSS. The power supply VDD and the ground VSS are shared. The subsequent stage noise cancellation circuit 14 is connected to the power supply, the ground, the total input terminal IN and the total output terminal OUT, and is used to cancel the subsequent stage noise. The pre-stage amplifier 13 is connected to the power supply and the ground on the one hand, and is connected to the total input terminal IN, the gate of the first PMOS transistor 11 and the subsequent stage noise cancellation circuit on the other hand, and is used to achieve broadband matching of the circuit input stage and form the pre-stage gain. The low-gain control path 15 is connected to the total input terminal IN and the total output terminal OUT, and is used to switch between high and low gains and perform low-gain distribution.

[0049] Specifically, the low-gain control path 15 includes three capacitive voltage-divider circuits 27, 28, and 29 that are connected in series in sequence to form a three-stage capacitive voltage-divider gain attenuation network, so as to achieve three-stage gain distribution.

[0050] The capacitive voltage-divider circuit includes first capacitors 16, 18, 20, second capacitors 17, 19, 21, first switches 22, 24, 63, and second switches 23, 25, 26.

[0051] One end of the first capacitor is connected to the total input terminal IN or the output terminal of the previous capacitive voltage-divider circuit, and the other end is connected to the output terminal of the capacitive voltage-divider circuit to which it belongs. One end of the second capacitor is connected to the output terminal of the capacitive voltage-divider circuit to which it belongs, and the other end is grounded through the second switch. One end of the first switch is connected to the output terminal of the capacitive voltage-divider circuit to which it belongs, and the other end is connected to the total output terminal OUT.

[0052] The pre-stage amplifier 13 includes a second PMOS transistor 5, a third PMOS transistor 6, a second capacitor 52, a third switch 3, a feedback resistor 2, and a first NMOS transistor 4.

[0053] The source of the second PMOS transistor 5 is connected to the power supply, the gate is connected to the gate of the first PMOS transistor 11, and the drain serves as the connection end between the pre-stage amplifier 13 and the subsequent stage noise cancellation circuit 14. The source of the third PMOS transistor 6 is connected to the power supply, the gate is connected to the gate of the first PMOS transistor 11, and the drain is connected to the connection end between the pre-stage amplifier 13 and the subsequent stage noise cancellation circuit 14. One end of the second capacitor 52 is connected to the gate of the first PMOS transistor 11, and the other end is connected to the total input terminal IN. One end of the third switch 3 is connected to the total input terminal IN, and the other end is connected to the connection end between the pre-stage amplifier 13 and the subsequent stage noise cancellation circuit 14 through the feedback resistor 2. The gate of the first NMOS transistor 4 is connected to the total input terminal IN, the source is grounded, and the drain is connected to the connection end between the pre-stage amplifier 13 and the subsequent stage noise cancellation circuit 14.

[0054] The post-stage noise cancellation circuit 14 includes: a second NMOS transistor 8, a third NMOS transistor 7, a third capacitor 9, and a fourth switch 10. The drain of the second NMOS transistor 8 is connected to the power supply. The gate is connected to the connection terminal of the pre-stage amplifier 13 and the post-stage noise cancellation circuit 14 through the serially connected fourth switch 10 and third capacitor 9. The source is connected to the total output terminal OUT. The source of the third NMOS transistor 7 is grounded. The gate is connected to the total input terminal IN. The drain is connected to the total output terminal OUT.

[0055] The current bias circuit 12 includes: a startup circuit 41, a fourth PMOS transistor 35, a fifth PMOS transistor 36, a sixth PMOS transistor 37, a fourth NMOS transistor 33, a fifth NMOS transistor 34, a sixth NMOS transistor 38, a seventh NMOS transistor 39, and a resistor 40.

[0056] The connection terminal of the sources of the fourth PMOS transistor 35, the fifth PMOS transistor 36, and the sixth PMOS transistor 37 serves as the input terminal of the current bias circuit 12 and is connected to the drain of the first PMOS transistor 11. The gates of the fourth PMOS transistor 35, the fifth PMOS transistor 36, and the sixth PMOS transistor 37 are connected together. The gate of the fifth PMOS transistor 36 is connected to the drain. The source of the fourth NMOS transistor 33 is grounded. The gate and the drain are both connected to the gate of the fifth NMOS transistor 34. The source of the fifth NMOS transistor 34 is grounded through the resistor 40. The drain is connected to the drain of the fifth PMOS transistor 36. The source of the sixth NMOS transistor 38 is grounded. The gate is connected to the drain. The drain is connected to the drain of the PMOS transistor 37. The source of the seventh NMOS transistor 39 is grounded. The gate is connected to the gate of the sixth NMOS transistor 38. The first terminal of the startup circuit 41 is connected to the input terminal of the current bias circuit 12. The second terminal is connected to the drain of the fourth NMOS transistor 33. The third terminal is grounded.

[0057] The startup circuit 41 includes: a seventh PMOS transistor 30, an eighth NMOS transistor 31, and a ninth NMOS transistor 32. The source of the seventh PMOS transistor 30 serves as the first terminal. The gate is connected to the drain. The drain is connected to the gate of the ninth NMOS transistor 32. The drain of the ninth NMOS transistor 32 is connected to the source of the seventh PMOS transistor 30. The source serves as the second terminal. The source of the eighth NMOS transistor 31 serves as the third terminal. The gate is connected to the drain. The drain is connected to the drain of the cable car ninth NMOS transistor 32.

[0058] Among them, the fourth PMOS transistor 35, the fifth PMOS transistor 36, the fourth NMOS transistor 33, the fifth NMOS transistor 34, and the resistor 40 form a constant transconductance current source (the transconductance changes very little with temperature). The seventh PMOS transistor 30, the eighth NMOS transistor 31, and the ninth NMOS transistor 32 form a startup circuit. The current mirrors of the sixth PMOS transistor 37, the sixth NMOS transistor 38, and the seventh NMOS transistor 39 copy the current generated by the constant transconductance current source to generate a bias current for the low-noise amplifier at point P.

[0059] In summary, by multiplexing the bias circuit with the signal amplification path on the load of the preamplifier 13, connecting the input signal IN to the first PMOS transistor 11 and the second PMOS transistor 5 at point B through the second capacitor 52, the gain of the preamplifier circuit is improved, and the power consumption of part of the bias current is saved. A feedback resistor 2 controlled by the third switch 3 is connected between nodes A and C, and is connected in parallel with the transconductance of the first NMOS transistor 4, the first PMOS transistor 11, the second PMOS transistor 5, and the third PMOS transistor 6 to jointly achieve broadband matching of the input stage of the circuit. The transconductance of the first NMOS transistor 4, the second PMOS transistor 5, and the third PMOS transistor 6 is multiplexed at point C to improve the current utilization rate of the circuit. The post-amplifier circuit uses the second NMOS transistor 8 and the third NMOS transistor 7 to form a noise cancellation circuit to improve the signal-to-noise ratio of the circuit and reduce the noise figure. Since only two amplifier stages are cascaded in the path from the power supply to the ground in the present invention, it can be applied to very low power supply voltages. The second PMOS transistor 5 and the third PMOS transistor 6 can be adjusted with different sizes respectively to control the input transconductance and bias current.

[0060] The output terminal E of the post-stage noise cancellation circuit 14 is connected to the total output terminal OUT. A low-gain control path 15 is connected in parallel between the input node A and the output node E. Through the third switch 3 connected to A and F and the fourth switch 10 connected to D and the power supply VDD, the present invention can switch between two modes of high gain and low gain. In the low-gain path, the capacitors 16, 17, 18, 19, 20, 21 are controlled by the switches 22, 23, 24, 25, 26, 63 to achieve different gain distributions.

[0061] The CMOS low-noise amplifier involved in the present invention not only has a simple design, but also has the characteristics of monolithic integration.

[0062] As Figure 5 shown, a differential structure is formed by two Figure 1 current-multiplexing broadband low-noise amplifiers described in the present invention. In the figure, the preamplifier 13 and the preamplifier 51 have the same structure, and each device inside corresponds one by one. The post-stage noise cancellation circuit 14' is symmetrically constituted by two post-stage noise cancellation circuits 14 in the present invention, and each device inside corresponds one by one.

[0063] The above embodiments are only for illustrating the present invention, rather than limiting the present invention. Those skilled in the relevant technical fields can make various transformations or variations without departing from the spirit and scope of the present invention. Therefore, all equivalent technical solutions should also belong to the scope of the present invention and should be defined by each claim.

Claims

1. A current-reused broadband low-noise amplifier, externally connected to a power supply and ground, characterized in that Comprising: A first PMOS transistor (11), a current bias circuit (12), a pre - amplifier (13), a post - stage noise cancellation circuit (14), and a low - gain control path (15), The source of the first PMOS transistor (11) is connected to the power supply, and the gate is connected to the drain; One end of the current bias circuit (12) is connected to the drain of the first PMOS transistor (11), and the other end is connected to the ground; The post - stage noise cancellation circuit (14) is connected to the power supply, the ground, the total input terminal, and the total output terminal, and is used to cancel the post - stage noise; The pre - amplifier (13) is connected to the power supply and the ground on one hand, and is connected to the total input terminal, the gate of the first PMOS transistor (11), and the post - stage noise cancellation circuit on the other hand, and is used to achieve broadband matching of the circuit input stage and form a pre - stage gain; The low - gain control path (15) is connected to the total input terminal and the total output terminal, and is used to switch between high and low gains and perform low - gain distribution; The low - gain control path (15) includes: three capacitive voltage - dividing circuits connected in series in sequence to form a three - stage capacitive voltage - dividing gain attenuation network, The capacitive voltage - dividing circuit includes a first capacitor, a second capacitor, a first switch, and a second switch; One end of the first capacitor is connected to the total input terminal or the output terminal of the previous capacitive voltage - dividing circuit, and the other end is connected to the output terminal of the capacitive voltage - dividing circuit to which it belongs; One end of the second capacitor is connected to the output terminal of the capacitive voltage - dividing circuit to which it belongs, and the other end is grounded through the second switch; One end of the first switch is connected to the output terminal of the capacitive voltage - dividing circuit to which it belongs, and the other end is connected to the total output terminal.

2. The current multiplexing type broadband low-noise amplifier according to claim 1, wherein The pre - amplifier (13) includes: a second PMOS transistor (5), a third PMOS transistor (6), a second capacitor (52), a third switch (3), a feedback resistor (2), and a first NMOS transistor (4), where, The source of the second PMOS transistor (5) is connected to the power supply, the gate is connected to the gate of the first PMOS transistor (11), and the drain is used as the connection end between the pre - amplifier (13) and the post - stage noise cancellation circuit (14); The source of the third PMOS transistor (6) is connected to the power supply, the gate is connected to the gate of the first PMOS transistor (11), and the drain is connected to the connection end between the pre - amplifier (13) and the post - stage noise cancellation circuit (14); One end of the second capacitor (52) is connected to the gate of the first PMOS transistor (11), and the other end is connected to the total input terminal; One end of the third switch (3) is connected to the total input terminal, and the other end is connected to the connection end between the pre - amplifier (13) and the post - stage noise cancellation circuit (14) through the feedback resistor (2); The gate of the first NMOS transistor (4) is connected to the total input terminal, the source is grounded, and the drain is connected to the connection end between the pre - amplifier (13) and the post - stage noise cancellation circuit (14).

3. The current multiplexing broadband low-noise amplifier according to claim 1, wherein The post - stage noise cancellation circuit (14) includes: a second NMOS transistor (8), a third NMOS transistor (7), a third capacitor (9), and a fourth switch (10), The drain of the second NMOS transistor (8) is connected to the power supply, the gate is connected to the connection terminal of the pre-amplifier (13) and the post-stage noise cancellation circuit (14) through the series-connected fourth switch (10) and third capacitor (9), and the source is connected to the total output terminal; The source of the third NMOS transistor (7) is grounded, the gate is connected to the total input terminal, and the drain is connected to the total output terminal.

4. The current multiplexing type broadband low-noise amplifier according to claim 1, wherein The current bias circuit (12) includes: a startup circuit (41), a fourth PMOS transistor (35), a fifth PMOS transistor (36), a sixth PMOS transistor (37), a fourth NMOS transistor (33), a fifth NMOS transistor (34), a sixth NMOS transistor (38), a seventh NMOS transistor (39), and a resistor (40). The connection terminal of the sources of the fourth PMOS transistor (35), the fifth PMOS transistor (36), and the sixth PMOS transistor (37) serves as the input terminal of the current bias circuit (12) and is connected to the drain of the first PMOS transistor (11). The gates of the fourth PMOS transistor (35), the fifth PMOS transistor (36), and the sixth PMOS transistor (37) are connected together. The gate of the fifth PMOS transistor (36) is connected to the drain. The source of the fourth NMOS transistor (33) is grounded, and the gate and drain are both connected to the gate of the fifth NMOS transistor (34). The source of the fifth NMOS transistor (34) is grounded through the resistor (40), and the drain is connected to the drain of the fifth PMOS transistor (36). The source of the sixth NMOS transistor (38) is grounded, the gate is connected to the drain, and the drain is connected to the drain of the PMOS transistor (37). The source of the seventh NMOS transistor (39) is grounded, and the gate is connected to the gate of the sixth NMOS transistor (38). The first terminal of the startup circuit (41) is connected to the input terminal of the current bias circuit (12), the second terminal is connected to the drain of the fourth NMOS transistor (33), and the third terminal is grounded.

5. The current multiplexing type broadband low-noise amplifier according to claim 4, wherein The startup circuit (41) includes: a seventh PMOS transistor (30), an eighth NMOS transistor (31), and a ninth NMOS transistor (32). The source of the seventh PMOS transistor (30) serves as the first terminal, the gate is connected to the drain, and the drain is connected to the gate of the ninth NMOS transistor (32). The drain of the ninth NMOS transistor (32) is connected to the source of the seventh PMOS transistor (30), and the source serves as the second terminal. The source of the eighth NMOS transistor (31) serves as the third terminal, the gate is connected to the drain, and the drain is connected to the drain of the ninth NMOS transistor (32).

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