Digital Calibration Circuit and Method for Time-of-Flight (TOF) Detector for Time-Amplitude Conversion

Abstract

The present invention relates to a digital calibration circuit and method for a time-amplitude conversion TOF detector. The calibration circuit includes a parameter presetting module, a weight factor extraction module, and a weight factor calibration module. The output end of the parameter presetting module is connected to the input end of the weight factor extraction module, and the output end of the weight factor extraction module is connected to the input end of the weight factor calibration module. On the premise of ensuring that the fill factor of the pixel unit and the array integration meet the requirements of array detection, the present invention simplifies the calibration timing to the greatest extent, reduces the circuit area, lowers the circuit power consumption and delay, and significantly improves the calibration accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of photon time-of-flight (TOF) detection, and particularly to a digital calibration circuit and method for TOF array detection based on time-amplitude conversion. Background Art

[0002] TOF detection is divided into two detection methods: direct and indirect. Among them, direct TOF detection depends on the photon flight time, and the time measurement accuracy does not change significantly with the increase of the test distance, and the performance is relatively stable. Therefore, the direct TOF detection technology has broad application prospects in laser ranging, 3D imaging and other aspects.

[0003] The TOF array detection imaging chip based on the direct TOF detection technology mainly adopts a time-to-digital conversion (TDC) circuit, which can obtain high time resolution and large measurement range. However, it generally requires many delay units, D flip-flops and logic gate circuits, and is not suitable for pixel units used in high-density array detection. The time-amplitude conversion (TAC) circuit is relatively simpler in structure and lower in power consumption, meeting the requirements of the array detection readout circuit. At the same time, it also needs to cooperate with the subsequent analog-to-digital conversion (ADC) circuit for quantization output.

[0004] The essence of the TAC circuit is that different photon flight times correspond to different voltage values obtained by time integration on the capacitor in the circuit, and then are uploaded to the host computer after analog-to-digital conversion by the ADC circuit. There are several pixel units in the TOF array detection, and the TAC circuit in each pixel unit contains capacitors of the same size. Many factors such as layout parasitic capacitance and process corner put forward high requirements for the matching of a large number of capacitors. The capacitance mismatch of each pixel unit in the TOF array detection will lead to inaccurate detection.

[0005] The traditional analog domain methods for improving the matching of the TAC circuit in array detection mainly introduce feedback calibration, switches and a large number of logic circuits to adjust the capacitance and current magnitude in the TAC circuit. However, adding these circuits will also bring problems such as high power consumption, high time delay, and decrease in pixel unit fill factor. At the same time, the increase of a large number of front-end circuits makes its advantages not obvious compared with the TDC circuit. Summary of the Invention

[0006] To solve the problems existing in the calibration of the detection value by the TOF array detection analog domain compensation circuit based on time-amplitude conversion, such as insufficient calibration accuracy, high power consumption, high time delay, and the decrease of the pixel unit fill factor, the present invention proposes a digital circuit calibration circuit and its calibration method for calibration in the digital domain. On the premise of ensuring that the pixel unit fill factor and the array integration meet the requirements of array detection, the calibration timing is simplified to the greatest extent, the circuit area is reduced, the circuit power consumption and time delay are reduced, and the calibration accuracy is significantly improved.

[0007] To achieve the above object, the present invention is realized by the following technical solutions:

[0008] The present invention is a digital calibration circuit and method for a time-of-flight (TOF) array detector for time-amplitude conversion. The digital calibration circuit includes: a parameter presetting module, a weight factor extraction module, and a weight factor calibration module. The output end of the parameter presetting module is connected to the input end of the weight factor extraction module, and the output end of the weight factor extraction module is connected to the input end of the weight factor calibration module. The external input signals of the parameter presetting module include an external clock signal clk, a reset signal rst_n, a working mode selection signal mode_select, a delay selection signal latency, a setting window signal set_win, an integer precision setting signal set_integer, and a decimal precision setting signal set_decimal. The output end of the parameter presetting module inputs a delay selection signal out_latency, an integer precision determination signal out_integer, and a decimal precision determination signal out_decimal to the weight factor extraction module. The external input signals of the weight factor extraction module include an external clock signal clk, a reset signal rst_n, a working mode selection signal mode_select, an ideal threshold signal threshold, an analog-to-digital conversion signal adc_value, and an integer result signal result_integer, a decimal result signal result_decimal, and a module completion signal done output to the weight factor calibration module. The input signals of the weight factor calibration module include an external clock signal clk, a reset signal rst_n, and an analog-to-digital conversion signal adc_value. The integer result signal integer_verify and the decimal result signal decimal_verify at the output end of the weight factor calibration module are connected to the external output end.

[0009] The function of the parameter presetting module is to set the accuracy and performance of the entire digital calibration circuit, which belongs to the preparation stage of digital calibration. The externally input working mode selection signal mode_select is an enabling signal. When this signal is at a low level, the parameter presetting module works. The externally input clock signal clk and reset signal rst_n determine the calibration period of the entire digital calibration circuit, enabling it to better match and work with the entire array detection system. The externally input signal set_win is a periodic window signal with a fixed width. The externally input delay time selection signal latency, integer accuracy setting signal set_integer, and fractional accuracy setting signal set_decimal are counted through the clock signal clk in the window signal set_win. In the digital calibration circuit, the delay time selection signal latency directly determines the area and power consumption of the digital calibration circuit, while the integer accuracy setting signal set_integer and fractional accuracy setting signal set_decimal can determine the accuracy of the digital calibration circuit. Since these three signals are directly input externally and their frequencies can be controlled, different circuit areas, power consumption, and accuracies required for different array detection applications can be controlled by different values counted in the window signal. Finally, the output delay selection signal out_latency, integer accuracy determination signal out_integer, and fractional accuracy determination signal out_decimal obtained by counting are connected to the weight factor extraction module.

[0010] The function of the weight factor extraction module is to find the deviation between the actual value and the ideal value of all pixel units, which is a key stage of digital calibration. The delay selection signal out_latency, integer precision determination signal out_integer and decimal precision determination signal out_decimal input to the weight factor extraction module of the parameter presetting module determine the area and accuracy of the entire digital calibration circuit. The external input clock signal clk, reset signal rst_n, and mode selection signal mode_select are consistent with the parameter presetting module. The clock and reset signals make the weight factor extraction module match the entire array detection system module in timing. At the same time, the weight factor extraction module will only work when the mode selection signal mode_select is high. After the weight factor extraction module works, it will perform a linear regression according to the timing. The main steps of a linear regression are: enable each pixel unit to work three times before the formal array detection, send the three different actual output values ​​of the TAC circuit of each pixel unit to the weight factor extraction module through the analog-to-digital conversion signal adc_value, fit the actual voltage value of the full-scale operation of the TAC circuit of each pixel unit, so that it has the ideal high linearity characteristics of the TAC circuit, and finally store it, so that the first linear regression ends. The main steps of the secondary linear regression are: after obtaining the actual voltage value of each pixel unit working at full scale, due to the high linearity characteristics of the TAC circuit, the ideal threshold signal threshold input externally is linearly operated with the actual value of each pixel unit, and the weight factor composed of the integer result signal result_integer and the decimal result signal result_decimal at the output end of each pixel unit is obtained under the premise of presetting the circuit size and accuracy, and saved in the storage circuit. At this point, the secondary linear regression ends, and when the weight factor extraction module is completed, a module completion signal done will be generated at the output end, which is valid at a high level and is used to enable the weight factor calibration module to work.

[0011] The function of the weight factor calibration module is to perform a linear operation on the detection value of each pixel unit and its corresponding weight factor during the formal array detection after the weight factor is successfully extracted, so as to achieve the purpose of digital calibration. Once the module completion signal done input by the weight factor extraction module becomes high level, the weight factor calibration module starts to work. The external input clock signal clk, reset signal rst_n are the same as those of the weight factor extraction module. The clock and reset signals make the weight factor calibration module match the entire array detection system in terms of timing. The external input analog-to-digital conversion signal adc_value sends the real-time detection values of each pixel unit into the weight factor calibration module in sequence. The weight factors of each pixel unit input by the weight factor extraction module are finally digitally calibrated with the actual detection values. The finally calibrated array detection values are composed of the integer result signal integer_verify and the decimal result signal decimal_verify at the output end and are transmitted to the host computer for data processing.

[0012] The present invention discloses a digital calibration method for a TOF array detector for time-amplitude conversion, including the following steps:

[0013] First step, under the control of the logic circuit, convert the photon flight time analog signals of each pixel unit in the array detector into digital signals. Under the control of the logic circuit, convert the photon flight time analog signals of each pixel unit in the array detection into digital signals through an ADC, that is, perform an orderly analog-to-digital conversion on the photon flight time corresponding to the capacitor voltage in the TAC circuit of each pixel unit in the TOF array detection according to the order of each pixel unit in the array.

[0014] Second step, the parameter preset value module works. When the working mode selection signal is at a low level, the parameter preset value module works. Determine the period, area, and calibration accuracy of the entire digital calibration circuit through the externally input signals, so as to control the indicators and performance of the digital calibration circuit.

[0015] Third step, the weight factor extraction module performs a linear regression once. The main steps of the linear regression are as follows: First, enable each pixel unit to work three times in advance. Through the actual outputs of the TAC circuits of each pixel unit three times, fit out the actual voltage values of the TAC circuits of each pixel unit when working at full scale, so that they have the ideal high linearity characteristics of the TAC circuit. Finally, after analog-to-digital conversion, store them through the storage circuit.

[0016] Step 4: The weight factor extraction module performs quadratic linear regression. The main steps of quadratic linear regression are as follows: The purpose of the entire digital calibration circuit is to find the gap between the actual value and the ideal value during each array detection. Since the actual voltage values of each pixel unit at full scale have been obtained in Step 3, and the ideal values of each pixel unit are known at the same time, under the control of the digital logic circuit, the ideal value and the actual value are linearly calculated in the order of array detection of each pixel unit. Finally, the weight factors corresponding to each pixel unit in the array detection are obtained and stored in the circuit.

[0017] Step 5: The array detection works normally. After the weight factor extraction in Step 4 is successful, a module completion signal will be sent to the weight factor calibration module, which is active high. At this time, the weight factor calibration module works, that is, when the array detection works normally, the ADC quantization data of the pixel units are sent to the weight factor calibration module in sequence. This module normally linearly digitally calibrates each read actual value of a pixel unit with the corresponding weight factor every time, and finally sends the calibrated array detection value to the host computer for data processing.

[0018] The beneficial effects of the present invention are as follows:

[0019] Compared with introducing feedback calibration, switches, and a large number of logic circuits in the analog domain to adjust the capacitance and current magnitude in the TAC circuit, the present invention improves the fill factor of each pixel unit in the array detection, enhances the stability of the array detection, and the front-end circuit has the characteristics of low latency and low power consumption.

[0020] Compared with introducing a complex feedback calibration circuit in the traditional analog circuit, the parameter presetting module included in the present invention can achieve real-time adjustment of the calibration accuracy and the circuit area size, and at the same time, the calibration period can be adjusted through an external signal, making the digital calibration module controllable and flexible.

[0021] Since the weight factors required for calibration are extracted and saved in the circuit in advance before formal calibration in the present invention, only repeated linear model calculations need to be performed with them during the normal operation of the array detection, which makes the calibration circuit structure simple and the hardware consumption low.

[0022] In the present invention, the digital calibration results are combined with integers and decimals, which improves the calibration accuracy. The characteristics of large digital signals make the entire digital calibration module highly stable and strong in anti-interference ability. Description of the Drawings

[0023] Figure 1 It is a schematic diagram of the pixel unit of the present invention.

[0024] Figure 2 It is a flowchart of the method steps of the present invention.

[0025] Figure 3 It is the schematic diagram of the primary and secondary linear regression of the weight factor extraction module of the present invention.

[0026] Figure 4 It is the hardware circuit framework diagram of the present invention.

[0027] Figure 5 It is the working timing diagram of the present invention.

[0028] Figure 6 It is the timing verification diagram of the present invention. Specific embodiments

[0029] The embodiments of the present invention will be disclosed below with reference to the drawings. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is to say, in some embodiments of the present invention, these practical details are not necessary.

[0030] As Figure 1 As shown in the schematic diagram of the digital calibration circuit and method pixel unit of the present invention, the entire pixel unit mainly includes a TOF photon detection device and a TAC circuit. When photons are detected by the photon detection device, the corresponding TAC circuit will generate a TOF voltage value. Different arrival times of photons correspond to different TOF voltage values. In an ideal situation, there is a linear relationship between the photon arrival time and the TOF voltage. In actual situations, due to the influence of parasitic capacitance in the analog circuit, etc., the actual TOF voltage value will be smaller than the ideal voltage value and non-linear, which directly leads to the inability of the array detector to accurately detect. Therefore, the present invention proposes to use a digital calibration circuit to make the actual TOF voltage value and the time curve infinitely approach the ideal curve, avoiding misdetection by the array detector.

[0031] The core of the entire digital calibration circuit is the weight factor extraction module, and the weight factor extraction module is composed of primary and secondary linear regression. As Figure 3As shown in the figure, the abscissa represents the photon flight time, and the ordinate represents the digital voltage value corresponding to each pixel unit after passing through the analog-to-digital conversion circuit at each time point. Theoretically, the photon flight time is proportional to the voltage, that is, the ideal value after quadratic regression. However, due to the influence of parasitic capacitance effects in the analog circuit, it can be seen that there is non-linearity when the actual pixel unit works, that is, the actual value before the first linear regression. The main steps of the first linear regression are as follows: First, enable each pixel unit to work three times, namely t1, t2, and t3. Fit the actual voltage output values of the three different TAC circuits of each pixel unit to obtain the actual voltage value when the TAC circuit of each pixel unit works at full scale. After storing it in the circuit, the first linear regression ends. At this time, the actual value and the ideal value when the TAC circuit works at full scale only differ by a linear weight factor. The steps of the second linear regression are as follows: Perform a linear operation on the ideal value input by the external circuit and the actual value of the pixel unit under the conditions such as the calibration accuracy defined by the parameter presetting module. The final result after the operation is the weight factor required to extract a single pixel unit. If an N×N array needs to be extracted, the above process is carried out N×N times in sequence.

[0032] As Figure 4 shown, the overall hardware circuit includes a logic control circuit, an array detection circuit, a digital calibration circuit, and an analog-to-digital conversion (ADC) interface circuit. The array detection circuit includes N×N pixel units. Among them, the digital calibration circuit is composed of three parts, namely a parameter presetting module, a weight factor extraction module, and a weight factor calibration module.

[0033] As Figure 5 shown, the calibration circuit of the present invention mainly includes three modules, a parameter presetting module, a weight factor extraction module, and a weight factor calibration module. According to these three modules, the timing of the entire digital calibration circuit is divided into three stages: parameter presetting, weight factor extraction, and weight factor calibration.

[0034] In the first stage, the externally input working mode selection signal mode_select is an enabling signal. When this signal is at a low level, the parameter presetting module works. The externally input clock signal clk and the reset signal rst_n determine the calibration period of the entire digital calibration circuit, enabling it to better match and work with the entire array detection system. The externally input signal set_win is a periodic window signal with a fixed width. The externally input delay time selection signal latency, integer precision setting signal set_integer, and decimal precision setting signal set_decimal are counted through the clock signal clk within the set_win window signal. In the digital calibration circuit, the delay time selection signal latency directly determines the area and power consumption of the circuit, while the integer precision setting signal set_integer and the decimal precision setting signal set_decimal can determine the precision of the digital calibration circuit. Since these three signals are directly input externally and their frequencies can be controlled, different values counted within the window signal can be used to control the different circuit areas, power consumptions, and precisions required for different array detection applications. Finally, the output delay selection signal out_latency, integer precision determination signal out_integer, and decimal precision determination signal out_decimal obtained by counting are sent to the weight factor extraction module.

[0035] In the second stage, after the parameter preset value is completed, the weight factor extraction module starts to work. The delay selection signal out_latency, integer precision determination signal out_integer and decimal precision determination signal out_decimal input to the weight factor extraction module of the parameter preset module determine the area and accuracy of the entire digital calibration circuit. The external input clock signal clk, reset signal rst_n, and mode selection signal mode_select are consistent with the parameter preset module. The clock and reset signals make the weight factor extraction module match the entire array detection system module in timing. At the same time, the weight factor extraction module will only work when the mode selection signal mode_select is high. After the module works, a linear regression will be performed according to the timing. The main steps of a linear regression are: enable each pixel unit to work three times before the formal array detection, and send the three different actual output values ​​of the TAC circuit of each pixel unit to the weight factor extraction module through the analog-to-digital conversion signal adc_value, fit the actual voltage value of the full-scale operation of the TAC circuit of each pixel unit, so that it has the ideal high linearity characteristics of the TAC circuit, and finally store it, so that a linear regression ends. The main steps of the quadratic linear regression are: after obtaining the actual voltage value of each pixel unit at full scale, due to the high linearity of the TAC circuit, the ideal threshold signal threshold input from the outside is linearly operated with the actual value of each pixel unit, and the weight factor composed of the integer result signal result_integer and the decimal result signal result_decimal at the output end of each pixel unit is obtained under the premise of preset circuit size and accuracy, and saved in the storage circuit. At this point, the quadratic linear regression ends, and when the weight factor extraction module is completed, a module completion signal done will be generated at the output end, which is valid at a high level and is used to enable the weight factor calibration module to work.

[0036] In the third stage, the weight factor extraction module ends the done signal delay mode selection signal for two clk cycles, the done signal is valid at high level, and the weight factor calibration module starts working. During the formal array detection, the detection value of each pixel unit and its corresponding weight factor are linearly operated to achieve the purpose of digital calibration. The external input clock signal clk and reset signal rst_n are consistent with the weight factor calibration module. The clock and reset signals make the weight factor extraction module match the entire array detection system in timing. The external input analog-to-digital conversion signal adc_value sends the real-time detection value of each pixel unit to the weight factor calibration module in sequence. The weight factor of each pixel unit input by the weight factor extraction module is finally linearly calibrated with the real-time detection value. The final calibrated array detection value is composed of the output integer result signal integer_verify and the decimal result signal decimal_verify and transmitted to the host computer.

[0037] As Figure 2 shown in the flowchart of the calibration method for the digital calibration circuit, the calibration method of the present invention includes the following steps:

[0038] Step 1: Array detection data time digital conversion. Convert the photon flight time analog signals of each pixel unit in the array detector into digital signals through an ADC, that is, perform an orderly analog-to-digital conversion on the photon flight times corresponding to the TAC capacitor voltages of each pixel unit in the TOF detection array according to the order of each pixel unit in the array.

[0039] Step 2: Parameter presetting module working mode selection. Determine whether the system working mode is low level. When it is low level, the parameter presetting module works. Set the integer and decimal digits of the data of the subsequent weight factor extraction module through signals such as external input window counting, and then determine the accuracy of the digital calibration circuit. Determine the working cycle and delay time of the digital calibration circuit module through the externally input clock and reset signals.

[0040] Step 3: Weight factor extraction module one-time linear regression data preparation. The establishment of a one-time linear regression model requires the array to perform three detections with known inputs. Perform ADC analog-to-digital conversion on the actual voltage values of the three groups of TAC circuits of each pixel unit detected and store them in the circuit.

[0041] Step 4: The weight factor extraction module starts one-time linear regression. According to the accuracy and delay set in Step 2 for weight factor extraction, perform one-time linear regression through the actual voltage values of the three groups of TAC circuits of each pixel unit in Step 3, and then store the actual voltage value when the TAC circuit corresponding to each pixel unit is working at full scale after one-time linear regression in the circuit.

[0042] Step 5: The weight factor extraction module starts two-time linear regression. On the premise of known inputs, the actual values of each pixel unit detected by the array are known. Under the control of the logic circuit, externally input the ideal values of each pixel unit in an orderly manner. While inputting the ideal values, perform two-time linear regression with the corresponding actual values. The output after two-time linear regression is the weight factor corresponding to each pixel unit, and finally store it in the circuit in an orderly manner. The weight factor extraction module finishes working, pulls up the module completion signal, and enables the weight factor calibration module to work.

[0043] Step 6: When the array detection is normal, orderly read the values of each pixel unit into the weight factor calibration module. The enable signal sent after the weight factor extraction is completed is valid at high level. After the weight factor calibration module determines that the working mode is high level, it normally reads the photon flight time data of each pixel unit after analog-to-digital conversion in an orderly manner to prepare for formal calibration.

[0044] Step 7, the weight factor calibration module works properly. The enable signal sent by the weight factor extraction module enables the weight factor calibration module to work. When the array detection works properly, the actual values after analog-to-digital conversion of each pixel unit are read into the calibration module in order, and at the same time, the weight factors of each pixel unit stored in the circuit in Step 5 are also read into the calibration module in order, and a linear model calculation is performed with the actual value of the corresponding pixel unit.

[0045] Step 8, the digital calibration of the array detection ends. After performing a linear model calculation on the actual value of the pixel unit and the corresponding weight factor, the calibrated photon flight time is obtained, and finally, it is read out in order through the output terminal to the host computer for data processing.

[0046] As Figure 6 shown, the entire digital calibration involves 14 external input and output signals, which are respectively included in the parameter presetting module circuit, the weight factor extraction module circuit, and the weight factor calibration module circuit. The input signals of the parameter presetting module circuit include an external clock signal clk, a reset signal rst_n, a working mode selection signal mode_select, a delay selection signal latency, a setting window signal set_win, an integer precision setting signal set_integer, and a decimal precision setting signal set_decimal. The output terminal of the parameter presetting module circuit inputs a delay selection signal out_latency, an integer precision determination signal out_integer, and a decimal precision determination signal out_decimal to the weight factor extraction module. The input signals of the weight factor extraction module circuit include an external clock signal clk, a reset signal rst_n, a working mode selection signal mode_select, an ideal threshold signal threshold, an analog-to-digital conversion signal adc_value, as well as an integer result signal result_integer, a decimal result signal result_decimal, and a module completion signal done output to the weight factor calibration module circuit. The input signals of the weight factor calibration module circuit include an external clock signal clk, a reset signal rst_n, and an analog-to-digital conversion signal adc_value. The integer result signal integer_verify and the decimal result signal decimal_verify at the output terminal of the weight factor calibration module circuit are connected to the external output terminal.

[0047] The synthesized and simulated verilog code of the designed digital circuit for detecting multiple pixel units is performed through the vivado software of Xilinx, Inc. By Figure 6Analysis of each signal in it reveals that the timing of the entire digital circuit can be divided into three parts: parameter presetting, weight factor extraction, and weight factor calibration. In the parameter presetting part, we determine that the delay of this digital calibration is 2 clks through the externally input delay selection signal latency, setting window signal set_win, integer precision setting signal set_integer, and fractional precision setting signal set_decimal. Since the calibrated value contains 16-bit integers and 16-bit decimals, and the calibration accuracy is determined by the decimals, the calibration accuracy is 0.00001526 LSB (the smallest unit of ADC quantization). The voltage values of each externally input pixel unit are used to obtain the weight factor integer result signal result_integer and fractional result signal result_decimal through first-order and second-order linear regression over 2 clks. When the enable signal done is pulled high, the weight factor calibration module works. Since this experiment is based on the known ideal values input for each pixel unit, after obtaining the weight factors, they are directly linearly fitted with the actual values of the pixel units. The integer result signal result_integer and fractional result signal result_decimal at the output represent the ideal values of each calibrated pixel unit. Comparing the results at the output directly with the ideal values of each externally input pixel unit, it is found that it is consistent with Figure 5 the designed theoretical timing. At the same time, through a large number of statistical calculations, the maximum difference in accuracy loss actually brought by the method of introducing weight factor calibration compared with the ideal value is 0.00001 LSB, meeting the expectations of digital calibration. This verifies the feasibility of the digital calibration circuit and method for the TOF array detector used for time-to-amplitude conversion.

[0048] The present invention realizes the function of digital calibration for array detection in the digital domain. Compared with introducing feedback calibration, switches, and a large number of logic circuits in the analog domain to adjust the capacitance and current magnitudes in the TAC circuit, the present invention improves the fill factor of each pixel unit in array detection, enhances the stability of array detection, and enables the front-end circuit to have the characteristics of low latency and low power consumption. In addition, the included parameter presetting module can realize real-time adjustment of calibration accuracy and circuit area size, and at the same time, the calibration period can be adjusted through external signals, making the digital calibration module controllable and flexible. Since the weight factors required for calibration are extracted once and stored in the circuit in advance before formal calibration in the present invention, during the normal operation of array detection, only linear model calculations need to be repeated with them, which makes the calibration circuit structure simple and the hardware consumption low. Finally, through the combined use of integers and decimals for the digital calibration results, the calibration accuracy is improved, and the characteristics of large digital signals make the entire digital calibration module have strong anti-interference ability.

[0049] The above are only embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the scope of the claims of the present invention.

Claims

1. A digital calibration circuit for a time-of-flight (TOF) detector, characterized in that: The calibration circuit includes a parameter presetting module, a weight factor extraction module, and a weight factor calibration module. The output end of the parameter presetting module is connected to the input end of the weight factor extraction module, and the output end of the weight factor extraction module is connected to the weight factor calibration input end module. The function of the weight factor calibration module is to find the deviation between the actual value and the ideal value of all pixel units. The external input signal of the weight factor extraction module includes an external clock signal clk, a reset signal rst_n, a working mode selection signal mode_select, an ideal threshold signal threshold, an analog-to-digital conversion signal adc_value, and an integer result signal result_integer, a decimal result signal result_decimal, and a module completion signal done output to the weight factor calibration module. The external clock signal clk, the reset signal rst_n, and the working mode selection signal mode_select are consistent with the parameter presetting module. The external clock signal clk and the reset signal rst_n make the weight factor calibration module match the entire array detection system module in terms of timing. When the working mode selection signal mode_select is at a high level, the weight factor extraction module works.

2. The digital calibration circuit for a time - of - flight (TOF) detector according to claim 1, wherein: The weight factor extraction module will perform a linear regression and a secondary linear regression according to the timing. The primary linear regression is specifically as follows: each pixel unit is enabled to work three times before the formal array detection, and the three different actual output values ​​of the TAC circuit of each pixel unit are sent to the weight factor extraction module through the analog-to-digital conversion signal adc_value, and the actual voltage value of the TAC circuit of each pixel unit working at full scale is fitted to make it have the ideal high linearity characteristics of the TAC circuit, and finally store it. At this point, the primary linear regression ends. The secondary linear regression is specifically as follows: after obtaining the actual voltage value of each pixel unit working at full scale, due to the high linearity characteristics of the TAC circuit, the ideal threshold signal threshold input externally is linearly operated with the actual value of each pixel unit, and the weight factor composed of the integer result signal result_integer and the decimal result signal result_decimal at the output end of each pixel unit is obtained under the premise of preset circuit size and accuracy, and is stored in the storage circuit. At this point, the secondary linear regression ends, and the weight factor extraction module completes the work and generates a module completion signal done at the output end. The high level is valid and is used to enable the weight factor calibration module to work.

3. The digital calibration circuit for the time-of-flight (TOF) detector according to claim 2, characterized in that: The function of the weight factor calibration module is to perform a linear operation on the detection value of each pixel unit and its corresponding weight factor during formal array detection after successfully extracting the weight factor, so as to achieve the purpose of digital calibration. The input signals of the weight factor calibration module include an external clock signal clk, a reset signal rst_n, and an analog-to-digital conversion signal adc_value. The integer result signal integer_verify and the fractional result signal decimal_verify at the output end of the weight factor calibration module are connected to the external output end. Once the module completion signal done input to the weight factor extraction module becomes high level, the weight factor calibration module starts to work. The external clock signal clk and the reset signal rst_n of the weight factor calibration module are the same as those of the weight factor extraction module. The external clock signal clk and the reset signal rst_n make the weight factor calibration module match the entire array detection system in terms of timing. During formal detection, the analog-to-digital conversion signal adc_value of the weight factor calibration module sequentially sends the real-time detection values of each pixel unit into the weight factor calibration module. The weight factors of each pixel unit input by the weight factor extraction module are finally digitally calibrated with the actual detection values. The finally calibrated array detection values are composed of the integer result signal integer_verify and the fractional result signal decimal_verify at the output end and are transmitted to the host computer for data processing.

4. The digital calibration circuit for a time-of-flight (TOF) detector according to claim 1, characterized in that: The function of the parameter presetting module is to set the accuracy and performance of the entire digital calibration circuit. The external input signals of the parameter presetting module include an external clock signal clk, a reset signal rst_n, a working mode selection signal mode_select, a delay selection signal latency, a setting window signal set_win, an integer accuracy setting signal set_integer, and a fractional accuracy setting signal set_decimal. The output end of the parameter presetting module inputs a delay selection signal out_latency, an integer accuracy determination signal out_integer, and a fractional accuracy determination signal out_decimal to the weight factor extraction module. The externally input working mode selection signal mode_select is an enabling signal. When this signal is at a low level, the parameter presetting module works. The externally input external clock signal clk and reset signal rst_n determine the calibration period of the entire digital calibration circuit. The delay selection signal latency, the integer accuracy setting signal set_integer, and the fractional accuracy setting signal set_decimal are counted through the external clock signal clk in the set_win window signal, and the counted output delay selection signal out_latency, integer accuracy determination signal out_integer, and fractional accuracy determination signal out_decimal are connected to the weight factor extraction module.

5. The calibration method of the digital calibration circuit for the time-of-flight (TOF) detector according to claim 1, wherein: The circuit is calibrated according to the following steps: Step 1: Under the control of the logic circuit, convert the photon flight time analog signals of each pixel unit in the array detection into digital signals through an ADC, that is, perform an orderly analog-to-digital conversion on the photon flight time corresponding to the capacitor voltage in the TAC circuit of each pixel unit in the TOF array detection according to the order of each pixel unit in the array; Step 2: The parameter preset value module works: When the working mode selection signal is at a low level, the parameter preset value module works, and determines the period, area, and calibration accuracy of the entire digital calibration circuit through the externally input signals, the external clock signal clk and the reset signal rst_n, so as to control the indicators and performance of the digital calibration circuit; Step 3: The weight factor extraction module performs a linear regression once: Before the formal array detection, enable each pixel unit to work three times. Through the first-order and second-order linear regressions of the three different actual outputs of the TAC circuit of each pixel unit, fit out the actual voltage value of the full-scale operation of the TAC circuit of each pixel unit, so that it has the ideal high linearity characteristic of the TAC circuit, and finally store it; Step 4: Under the control of the digital logic circuit, perform a linear calculation on the ideal value and the actual value in the order of each pixel unit in the array detection, and finally obtain the weight factor corresponding to each pixel unit in the array detection, and store them in the circuit; Step 5: The array detection works normally: After the weight factor extraction in Step 4 is successful, a module completion signal will be sent to the weight factor calibration module, which is active high. At this time, the weight factor calibration module works, that is, when the array detection works normally, the ADC quantization data of the pixel unit is sent to the weight factor calibration module in order. This module normally linearly digitally calibrates each read actual value of a pixel unit with the corresponding weight factor every time, and finally sends the calibrated array detection value to the host computer for data processing.

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