Verification method, device, electronic device and computer-readable storage medium

Abstract

A verification method, a verification device, an electronic device and a computer-readable storage medium. The verification method comprises: obtaining a microinstruction as a verification stimulus; having an execution unit as a verified object process the microinstruction to obtain an execution result; having a reference model unit obtain a reference result corresponding to the microinstruction; and comparing the execution result with the reference result to verify the execution unit. The verification method can verify the execution of the microinstruction obtained by decoding the instruction, thereby improving the verification efficiency.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a verification method, apparatus, electronic device, and computer-readable storage medium. Background Art

[0002] With the improvement of processor manufacturing technology, the design scale of high-performance processors is increasing, and the design complexity is also increasing. Large-scale design poses a challenge to the functional verification of processors. Currently, processor verification mainly includes formal verification, simulation verification, hardware simulation acceleration and other methods.

[0003] Formal verification verifies whether there are functional defects in the processor design by traversing all possible behaviors of the processor through mathematical methods. Simulation verification verifies the correctness of the processor design by checking whether the function of the processor design is correct under test stimulus. Hardware simulation acceleration verifies the functional correctness through hardware with frequency indicators lower than the processor design indicators. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a verification method, comprising: obtaining a microinstruction as a verification stimulus; having an execution unit as a verified object process the microinstruction to obtain an execution result; having a reference model unit obtain a reference result corresponding to the microinstruction; and comparing the execution result with the reference result to verify the execution unit.

[0005] For example, in a verification method provided in one embodiment of the present disclosure, an execution unit as a verified object processes a microinstruction to obtain an execution result, including: the execution unit generates a processing request based on the microinstruction, and sends the processing request to a data processing unit; obtains a processing result of the processing request from the data processing unit; and obtains an execution result based on the processing result.

[0006] For example, in a verification method provided in an embodiment of the present disclosure, a reference result corresponding to a microinstruction is obtained by a reference model unit, including: the reference model unit obtains a processing result from a data processing unit; and obtains a reference result based on the processing result.

[0007] For example, in the verification method provided in an embodiment of the present disclosure, the data processing unit includes: a memory access unit and / or a fixed-floating point conversion unit, and the corresponding processing requests include read and write requests and / or fixed-floating point conversion requests, the read and write requests are used to access the memory access unit, and the fixed-floating point conversion requests are used to access the fixed-floating point conversion unit.

[0008] For example, in a verification method provided in an embodiment of the present disclosure, a reference result corresponding to a microinstruction is obtained by a reference model unit, including: performing an execution exception check on the microinstruction by the reference model unit; and obtaining a reference result based on the check result of the execution exception check.

[0009] For example, in the verification method provided in one embodiment of the present disclosure, in a situation where the execution unit accesses the data processing unit to obtain an execution result, the reference model unit performs an execution exception check on the microinstruction, including: in response to the microinstruction being dependent on the processing result obtained from the data processing unit, the reference model unit performs an execution exception check on the microinstruction based on the processing result.

[0010] For example, in a verification method provided in an embodiment of the present disclosure, a reference result is obtained according to a result of performing an abnormality check, including: in response to a detection result of performing an abnormality check that the microinstruction has no abnormality, executing the microinstruction to obtain a reference result.

[0011] For example, in a verification method provided in an embodiment of the present disclosure, in response to the detection result of performing an exception check being that there is no exception in the microinstruction, executing the microinstruction to obtain a reference result, including: determining the operand type corresponding to the microinstruction; and performing fixed-point type operations or floating-point type operations on the operands according to the operand type to obtain a reference result.

[0012] For example, in a verification method provided in an embodiment of the present disclosure, the execution result is compared with the reference result to verify the execution unit, including: determining the instruction type of the microinstruction; determining the comparison information between the execution result and the reference result based on the instruction type; and comparing whether the comparison information in the execution result is consistent with the comparison information in the reference result.

[0013] For example, in the verification method provided in an embodiment of the present disclosure, based on the instruction type, it is determined that the comparison information between the execution result and the reference result includes at least one of the following: in response to the instruction type being a read-write type, the comparison information includes the read-write address information and the data information corresponding to the read-write address; in response to the instruction type being a fixed-floating point conversion type, the comparison information includes the fixed-floating point conversion data; in response to the instruction type being an update of the target register, the comparison information includes the data information in the target register; or in response to the instruction type being an update of the flag bit, the comparison information includes the data information of the flag bit.

[0014] For example, in a verification method provided in an embodiment of the present disclosure, a reference result is obtained according to the inspection result of performing an exception check, including: in response to the inspection result being a microinstruction exception, generating reference exception information, and using the reference exception information as a reference result.

[0015] For example, in a verification method provided in an embodiment of the present disclosure, the execution result is compared with the reference result to verify the execution unit, including: in response to the existence of an exception record in the execution result, the exception record is compared with the reference exception information to verify the execution unit.

[0016] For example, in a verification method provided in an embodiment of the present disclosure, a reference model unit obtains a reference result corresponding to a microinstruction, including: in response to an execution unit retiring a microinstruction, the reference model unit obtains a reference result corresponding to the microinstruction.

[0017] For example, in a verification method provided in an embodiment of the present disclosure, obtaining microinstructions as verification stimuli includes: decoding instructions to obtain microinstructions as verification stimuli.

[0018] At least one embodiment of the present disclosure provides a verification device, including: a reference model unit and a scoreboard, the reference model unit is configured to obtain microinstructions as verification stimuli and obtain reference results corresponding to the microinstructions; the scoreboard is configured to obtain reference results and execution results, and compare the reference results and the execution results, the execution results are obtained by processing the microinstructions by the execution unit as the verified object.

[0019] For example, in the verification device provided in an embodiment of the present disclosure, it also includes an instruction decoding unit, which is configured to decode the instruction to obtain the microinstruction, and send the microinstruction to the reference model unit and the execution unit as the verification stimulus.

[0020] For example, in the verification device provided in one embodiment of the present disclosure, it also includes: at least one data processing unit, each data processing unit is configured to accept a processing request from an execution unit, and generate a processing result of the processing request, and provide the processing result to the execution unit; the execution unit generates a processing request according to the microinstruction, and sends the processing request to the data processing unit that responds to the processing request in at least one data processing unit, and the execution unit obtains the execution result according to the processing result.

[0021] At least one embodiment of the present disclosure provides an electronic device, comprising: a processor; a memory, comprising one or more computer program instructions; wherein the one or more computer program instructions are stored in the memory and, when executed by the processor, implement instructions of the verification method provided by at least one embodiment of the present disclosure.

[0022] At least one embodiment of the present disclosure provides a computer-readable storage medium that non-temporarily stores computer-readable instructions. When the computer-readable instructions are executed by a processor, the verification method provided by at least one embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0024] Figure 1AA flowchart of a verification method provided by at least one embodiment of the present disclosure is shown;

[0025] Figure 1B A schematic diagram of a verification device provided by at least one embodiment of the present disclosure is shown;

[0026] Figure 2 It shows that at least one embodiment of the present disclosure provides Figure 1A The method flow chart of step S20 in FIG.

[0027] Figure 3 It shows that at least one embodiment of the present disclosure provides Figure 1A The method flow chart of step S30 in FIG.

[0028] Figure 4 It shows that at least one embodiment of the present disclosure provides Figure 1A Another method flow chart of step S30;

[0029] Figure 5 A flowchart of another verification method provided by at least one embodiment of the present disclosure is shown;

[0030] Figure 6 A block diagram of a reference model unit provided by at least one embodiment of the present disclosure is shown;

[0031] Figure 7 A schematic block diagram of an electronic device provided for some embodiments of the present disclosure;

[0032] Figure 8 A schematic block diagram of another electronic device provided for some embodiments of the present disclosure; and

[0033] Fig. 9 A schematic diagram of a storage medium provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0035] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0036] The architecture of processors is constantly changing, and the X86 instruction set has also increased, resulting in a huge verification space for processor design verification, and the optimization and improvement of processor microarchitecture is the focus and difficulty of functional verification. Faced with the industry's difficult problem of high-performance microprocessor verification, processor companies around the world have invested a lot of manpower and financial resources. If the processor design is verified using formal verification methods, it is necessary to traverse all possible behaviors of the processor design through mathematical methods. The verification space for large-scale processor designs is huge, which exceeds the verification capabilities of current tools. Formal verification is generally used for the verification of local complex logic. Using simulation verification methods to verify processor designs is generally not limited to the scale of processor designs. It is difficult to locate problems in processor designs when using hardware simulation methods to verify processor designs.

[0037] The structure of the central processing unit can be divided into the front-end architecture and the back-end architecture. The processor front-end mainly includes modules for calling instructions, such as branch prediction, instruction fetching, and instruction decoding. The processor back-end mainly includes modules for executing instructions. In order to increase the operating speed of the processor, the processor front-end should provide more instructions to the processor back-end as soon as possible for execution. In the pipeline of the processor, in addition to subsequent execution operations in the form of machine instructions (also referred to as "instructions"), machine instructions can also be decoded into one or more micro-instructions (Micro-operation, Uop), and the micro-instructions are sent to the processor back-end execution unit for subsequent execution operations. At present, most processors use out-of-order execution and sequential retirement (or retirement) technology to improve the parallelism of instructions (or micro-instructions). After an instruction (or micro-instruction) is executed and submitted, the last step is to retire.

[0038] At least one embodiment of the present disclosure provides a verification method, which includes: obtaining a microinstruction as a verification stimulus; processing the microinstruction by an execution unit as a verified object to obtain an execution result; obtaining a reference result corresponding to the microinstruction by a reference model unit; and comparing the execution result with the reference result to verify the execution unit. The verification method can verify the execution of the microinstruction obtained by decoding the instruction, thereby improving the verification efficiency.

[0039] Figure 1A A flowchart of a verification method provided by at least one embodiment of the present disclosure is shown.

[0040] like Figure 1A As shown, the verification method may include steps S10 to S40.

[0041] Step S10: Obtain microinstructions as verification stimuli.

[0042] Step S20: The execution unit to be verified processes the microinstruction to obtain an execution result.

[0043] Step S30: obtaining a reference result corresponding to the microinstruction by the reference model unit.

[0044] Step S40: Compare the execution result with the reference result to verify the execution unit.

[0045] Figure 1B A schematic diagram of a verification device provided by at least one embodiment of the present disclosure is shown. Figure 1B right Figure 1A The verification method in is described below.

[0046] like Figure 1B As shown, the verification device 100 is used to verify the function of the execution unit 102. The verification device 100 may include a reference model unit 103 and a scoreboard 104.

[0047] The reference model unit 103 is configured to obtain microinstructions as verification stimuli. The scoreboard 104 is configured to obtain reference results and execution results, and compare the reference results with the execution results, where the execution results are obtained by processing the microinstructions by the execution unit as the object of verification.

[0048] like Figure 1B As shown, the verification device 100 may further include an instruction decoding unit 101 .

[0049] The instruction decoding unit 101 is configured to decode instructions to obtain microinstructions, and send the microinstructions to the reference model unit 103 and the execution unit 102 .

[0050] For example, the instruction decoding unit 101 may decode an instruction to obtain one or more microinstructions, and then provide the one or more microinstructions to the reference model unit 103 and the execution unit 102 .

[0051] for Figure 1A In step S10, for example, the reference model unit 103 obtains the microinstructions obtained by the instruction decoding unit 101 decoding the instructions, and the obtained microinstructions are used as verification stimuli.

[0052] The execution unit 102 may be a verified object. The execution unit 102 may be, for example, a verified hardware circuit model, which may be written in a hardware language (e.g., Verilog). The verified hardware circuit model may be a partial functional module in a processor design or may be the entire processor design.

[0053] For example, the execution unit 102 may be a functional module that performs fixed-point operations or floating-point operations, but is not limited thereto and may also be other types of execution units.

[0054] for Figure 1A In step S20, for example, the execution unit 102 receives one or more microinstructions from the instruction decoding unit 101, and processes the one or more microinstructions in sequence to obtain an execution result of each microinstruction.

[0055] In some embodiments of the present disclosure, the execution result may include an exception record generated by executing a microinstruction exception, and a calculation result obtained by executing the microinstruction when there is no exception in the microinstruction.

[0056] In some embodiments of the present disclosure, the execution unit 102 may include, for example, a microinstruction queue to sequentially store a plurality of microinstructions to be executed, and the plurality of microinstructions to be executed are sequentially executed by the execution unit 102, for example, on a first-in-first-out basis. Alternatively, the instruction decoding unit 101 includes a microinstruction queue to sequentially store a plurality of microinstructions to be executed, and sequentially provides (transmits) the microinstructions to be executed to the execution unit 102 according to the subsequent processing status of the execution unit 102. In this case, the execution unit 102 may not include a microinstruction queue, for example.

[0057] In some embodiments of the present disclosure, the execution unit 102 may access the data processing unit to obtain the execution result.

[0058] The data processing unit may include, for example, a memory access unit and / or a fixed-point to floating-point conversion unit. Figure 1B As shown, the verification device may include a memory access unit 105 and a fixed-to-floating point conversion unit 106 in addition to the instruction decoding unit 101 , the execution unit 102 , the reference model unit 103 and the scoreboard 104 .

[0059] The memory access unit 105 and the fixed-to-floating point conversion unit 106 receive processing requests from the execution unit 102 , and in response to the processing requests, provide processing results to the execution unit 102 and the reference model unit 103 .

[0060] For example, the execution unit 102 sends a processing request 2 to the fixed-floating point conversion unit 106 , and the fixed-floating point conversion unit 106 generates a processing result 2 in response to the processing request 2 and sends the processing result 2 to the execution unit 102 and the reference model unit 103 .

[0061] For another example, the execution unit 102 sends a processing request 1 to the memory access unit 105 , and the memory access unit 105 generates a processing result 1 in response to the processing request 1 , and sends the processing result 1 to the execution unit 102 and the reference model unit 103 .

[0062] Below Figure 2 An embodiment in which the execution unit accesses the data processing unit to obtain the execution result has been described, which will not be repeated here.

[0063] In other embodiments of the present disclosure, the execution unit 102 may obtain the execution result without accessing the data processing unit. For example, if the microinstruction operates on an immediate number or an operand that has been obtained by other microinstructions, the execution unit does not need to access the data processing unit, and the execution of the entire microinstruction is completed entirely by the execution unit itself.

[0064] for Figure 1AIn step S30, for example, the reference model unit 103 receives one or more microinstructions from the instruction decoding unit 101, and processes the one or more microinstructions to obtain a reference result of each microinstruction.

[0065] In some embodiments of the present disclosure, the reference model unit 103 may include a microinstruction queue, configured to receive one or more microinstructions sent by the instruction decoding unit, and maintain the microinstruction content recorded in the microinstruction queue according to the first-in-first-out principle. Similarly, in the case where the instruction decoding unit 101 includes a microinstruction queue, the reference model unit 103 may not include a microinstruction queue.

[0066] In some embodiments of the present disclosure, the reference model unit 103 may output a correct reference result based on a verification stimulus.

[0067] For example, the reference model unit 103 may store the reference result of each verification stimulus in the form of a table. In this embodiment, step S30 may be that the reference model unit 103 obtains the reference result of the verification stimulus by querying the table.

[0068] For another example, the reference model unit 103 includes a verified functional module, which has the same function as the execution unit. In this embodiment, step S30 may be that the reference model unit 103 uses the verified functional module to respond to the verification stimulus to obtain a reference result.

[0069] In some embodiments of the present disclosure, the execution of the microinstruction by the reference model unit 103 does not require timing, and the moment when the execution unit 102 retires the microinstruction can be selected as the starting point of the reference model unit 103. Therefore, step S30 may include: in response to the execution unit executing the microinstruction retirement, the reference model unit obtains a reference result corresponding to the microinstruction. That is, after the execution unit finishes executing the microinstruction, the reference model unit generates a reference result based on the microinstruction.

[0070] The scoreboard 104 is configured, for example, to receive the reference result from the reference model unit 103 and the execution result from the execution unit, and compare the reference result and the execution result.

[0071] for Figure 1A Step S40 in, for example, by Figure 1B The scoreboard 104 in is used to compare the execution result with the reference result.

[0072] The correctness of the execution of the microinstructions by the execution unit is verified by comparing the execution result with the reference result.

[0073] For example, if the execution result of a certain microinstruction is consistent with the reference result, then the execution unit executes the microinstruction correctly. For another example, if the execution result of a certain microinstruction is inconsistent with the reference result, then there is a problem in the execution of the microinstruction by the execution unit.

[0074] This verification method can check the execution of multiple microinstructions split from an instruction, which is convenient for problem location. In addition, this verification method does not need to wait until the entire instruction is executed to obtain the verification result, which improves the efficiency of problem location. At the same time, this verification method has good reusability and can be used to verify various execution units. For example, the reference model unit and the execution unit to be verified can have the same interface, which makes it easier to access higher-level system verification, thereby improving the reusability of the verification method.

[0075] Figure 2 It shows that at least one embodiment of the present disclosure provides Figure 1A Flow chart of the method of step S20 in FIG.

[0076] like Figure 2 As shown, step S20 may include steps S21 to S23.

[0077] Step S21: the execution unit generates a processing request according to the microinstruction, and sends the processing request to the data processing unit.

[0078] Step S22: Obtain the processing result of the processing request from the data processing unit.

[0079] Step S23: Obtaining an execution result based on the processing result.

[0080] The execution unit in this embodiment can access the data processing unit, thereby obtaining the execution result using the processing result obtained from the data processing unit, making the verification of the execution unit more comprehensive. For example, the instruction decoding unit 101, the execution unit 102, the memory access unit 105 and the fixed-floating point conversion unit 106 can be used as a processor.

[0081] For step S21, Figure 1B As shown, for example, if the microinstruction is a read-write type microinstruction, the execution unit 102 generates a processing request for accessing the memory access unit 105 according to the microinstruction, and sends the processing request to the memory access unit 105. In this embodiment, the processing request may be a read-write request for accessing the memory access unit 105. For example, the read-write request is used to request to read data information (e.g., an operand) from the memory access unit 105, or to request to write data information to the memory access unit 105.

[0082] like Figure 1BAs shown, for example, if the microinstruction is a fixed-floating point conversion type microinstruction, the execution unit 102 generates a processing request for accessing the fixed-floating point conversion unit 106 according to the microinstruction, and sends the processing request to the fixed-floating point conversion unit 106. In this embodiment, the processing request may be a fixed-floating point conversion request for accessing the fixed-floating point conversion unit 106. For example, the fixed-floating point conversion request is used to request the fixed-floating point conversion unit 106 to convert a fixed-point number into a floating point number, or to convert a floating point number into a fixed point number.

[0083] For step S22, for example, the execution unit 102 receives a processing result from the memory access unit 105. The processing result is obtained by the memory access unit 105 in response to the read / write request. The processing result may be, for example, an operand read by the memory access unit 105 from the storage space corresponding to the address in the read / write request.

[0084] For another example, the execution unit 102 receives a processing result from the fixed-to-floating point conversion unit 106. The processing result is obtained by the fixed-to-floating point conversion unit 106 in response to the fixed-to-floating point conversion request. The processing result can be, for example, a floating point number obtained by converting a fixed point number, or a fixed point number obtained by converting a floating point number.

[0085] Regarding step S23, in some embodiments of the present disclosure, step S23 may include performing operations on the processing result to obtain an execution result. For example, the execution unit performs fixed-point operations such as addition, subtraction, multiplication, and division on the processing result to obtain the operation result.

[0086] In some other embodiments of the present disclosure, step S23 may include storing the processing result in the target register, and the execution result is updating the data in the target register with the data included in the processing result.

[0087] Figure 3 It shows that at least one embodiment of the present disclosure provides Figure 1A Flow chart of the method of step S30 in FIG.

[0088] like Figure 3 As shown, step S30 may include steps S31 to S32.

[0089] Step S31: The reference model unit obtains the processing result from the data processing unit.

[0090] Step S32: Obtain a reference result based on the processing result.

[0091] This embodiment can ensure that the processing result obtained by the reference model unit is the same as the processing result obtained by the execution unit, and at least partially avoids the problem of inaccurate verification results caused by the reference model unit and the execution unit processing different processing results respectively.

[0092] For step S31, for example, the reference model unit monitors the interface of the data processing unit, thereby obtaining the processing result from the interface of the data processing unit. That is, in response to receiving the processing request from the execution unit, the data processing unit sends the processing result to the execution unit and also sends the processing result to the reference model unit.

[0093] For example, Figure 1B As shown, in response to receiving a processing request from the execution unit 102 , the memory access unit 105 sends the processing result to the execution unit 102 and also sends the processing result to the reference model unit 103 , so that the reference model unit 103 receives the processing result from the memory access unit 105 .

[0094] For example, Figure 1B As shown, in response to receiving a processing request from the execution unit 102, the fixed-floating point conversion unit 106 sends the processing result to the execution unit 102 and also sends the processing result to the reference model unit 103, so that the reference model unit 103 receives the processing result from the fixed-floating point conversion unit 106.

[0095] For step S32, for example, the reference model unit calculates the processing result to obtain the reference result, or the reference model unit stores the processing result in the target register to obtain the reference result.

[0096] It should be understood that in the scenario where the execution unit stores the processing result in the target register, and the reference model unit stores the processing result in the target register, although both the execution unit and the reference model unit store the processing result in the same target register, the physical address of the target register where the execution unit stores the processing result and the physical address of the target register where the reference model unit stores the processing result are different.

[0097] Figure 4 It shows that at least one embodiment of the present disclosure provides Figure 1A Another method flow chart of step S30 in FIG.

[0098] like Figure 4 As shown, step S30 may include steps S33 to S34.

[0099] Step S33: The reference model unit performs execution exception check on the microinstructions.

[0100] Step S34: Obtain a reference result based on the inspection result of performing the abnormality inspection.

[0101] For step S33, performing an exception check may refer to checking whether an exception will be generated during the execution of the microinstruction.

[0102] In some embodiments of the present disclosure, the reference model unit may check whether an exception will occur during the execution of the microinstruction according to the current system state.

[0103] The current system state may include, for example, the value in the target register, the value of the flag bit, etc. For example, if the microinstruction is to perform a division operation on two operands, and the value in the target register corresponding to the divisor is 0, an exception will be generated during the execution of the microinstruction. For another example, if the microinstruction is to perform a square root operation on an operand, and the operand is a negative number, an exception will be generated during the execution of the microinstruction.

[0104] In some embodiments of the present disclosure, the microinstruction depends on the processing result obtained from the data processing unit, and the reference model unit checks whether an exception will be generated during the execution of the microinstruction according to the current system state, including: the reference model unit performs an execution exception check on the microinstruction according to the processing result. That is, the current system state is the state of the verification device or processor after obtaining the processing result.

[0105] For example, for a microinstruction of a division operation, the memory access unit updates the data in the target storage space according to the read / write request, and the data in the target storage space is used as the divisor. Therefore, after obtaining the processing result of the memory access unit, the microinstruction is executed for an exception check.

[0106] For step S34, in response to the checking result being that the microinstruction is abnormal (ie, the microinstruction will generate an exception during execution), reference exception information is generated, and the reference exception information is used as a reference result.

[0107] In some embodiments of the present disclosure, when the check result is that the microinstruction is abnormal, the reference model unit no longer performs subsequent processing on the microinstruction and directly generates reference abnormal information, i.e., a reference result. For example, the reference model unit may include an abnormality cache component configured to store the reference abnormal information for comparison with the execution result in the execution unit.

[0108] For example, step S40 may be to determine whether there is an abnormal record in the execution result, and if there is an abnormal record, compare the abnormal record with the reference abnormal information to verify the execution unit.

[0109] For step S34 , in response to the detection result of performing the abnormality check being that the microinstruction has no abnormality (ie, the microinstruction will not generate an abnormality during execution), the microinstruction is executed to obtain a reference result.

[0110] For example, the operand type corresponding to the microinstruction is determined, and according to the operand type, a fixed-point type operation or a floating-point type operation is performed on the operand to obtain a reference result.

[0111] In some embodiments of the present disclosure, for example, the reference model unit includes an operation component, which may be a fixed-point instruction operation component and / or a floating-point instruction operation component. The fixed-point instruction operation component is configured to operate on fixed-point type microinstructions, and the floating-point instruction operation component is configured to operate on floating-point type microinstructions.

[0112] In these embodiments, step S40 includes: determining the instruction type of the microinstruction; determining comparison information between the execution result and the reference result according to the instruction type; and comparing whether the comparison information in the execution result is consistent with the comparison information in the reference result.

[0113] In some embodiments of the present disclosure, in response to the instruction type being a read-write type, the comparison information includes read-write address information and data information corresponding to the read-write address.

[0114] The read-write type microinstruction may be, for example, to read data information from a memory access unit or to write data information into a memory access unit.

[0115] For example, if the microinstruction is to write data information into a storage space corresponding to a certain address, the comparison information includes the target address of the written data information and the operand written to the target address.

[0116] For read-write type microinstructions, for example, the target address in the reference result and the target address in the execution result can be compared to determine whether the target address in the reference result and the target address in the execution result are consistent, and compare and determine whether the operands in the target address in the reference result and the operands in the target address in the execution result are consistent.

[0117] In response to the instruction type being a fixed-floating point conversion type, the comparison information includes fixed-floating point conversion data.

[0118] For example, the fixed-floating point conversion data includes initial data that has not been converted to a fixed-floating point and target data obtained by converting the initial data to a fixed-floating point.

[0119] In response to the instruction type being to update the target register, the comparison information includes data information in the target register.

[0120] In response to the instruction type being to update the flag bit, the comparison information includes data information of the flag bit. For example, the data information of the flag bit may be the value of the flag bit.

[0121] It should be noted that the execution result and the reference result can be compared with multiple comparison information as needed, for example, the fixed-point and floating-point conversion data and flag data information of the execution result and the reference result can be compared.

[0122] Figure 5A flowchart of another verification method provided by at least one embodiment of the present disclosure is shown.

[0123] like Figure 5 As shown, the verification method may include steps S501 to S515.

[0124] Step S501: The reference model unit waits for the execution unit to retire microinstructions.

[0125] Step S502: Determine whether there is a retired microinstruction by referring to the model unit; if there is a retired microinstruction, execute step S503; if there is no retired microinstruction, return to step S501 and continue to wait for the execution unit to retire the microinstruction.

[0126] Step S503: The reference model unit performs execution exception checking on the retired microinstructions.

[0127] Step S504: Refer to the model unit to determine whether the microinstruction will cause an exception. If the microinstruction will cause an exception, execute step S505. If the microinstruction will not cause an exception, execute step S506.

[0128] Step S505: The scoreboard compares the reference exception information from the reference model unit and the exception record from the execution unit, and waits for the next microinstruction.

[0129] Step S506: Determine the microinstruction type with reference to the model unit, and perform microinstruction operations.

[0130] Step S507: If the microinstruction is a read-write type microinstruction, execute step S508.

[0131] Step S508: The scoreboard compares the reference result with the read / write address information in the execution result and the data information corresponding to the read / write address to see if they are consistent.

[0132] Step S509: If the microinstruction is a fixed-to-floating-point conversion type microinstruction, execute step S510.

[0133] Step S510: The scoreboard compares the fixed-to-floating-point conversion data information in the reference result and the execution result to see if they are consistent.

[0134] Step S511: If the microinstruction is a microinstruction for updating the target register, then execute step S512.

[0135] Step S512: The scoreboard compares the data information in the target register.

[0136] Step S513: If the microinstruction is a microinstruction for updating the flag bit, then execute step S514.

[0137] Step S514: the scoreboard compares the data information of the flag bit.

[0138] Step S515: The scoreboard generates a comparison result, and the reference model unit continues to wait for the next microinstruction.

[0139] It is important to understand that Figure 5 Steps S508, S510, S512 and S514 in the flowchart shown are not mutually exclusive. For the comparison between the execution result of a microinstruction and the reference result, one or more steps of S508, S510, S512 and S514 can be executed.

[0140] In some embodiments of the present disclosure, the comparison result may include information that does not match the execution result and the reference result. For example, the information that does not match the execution result and the reference result is recorded in a log to facilitate problem location, and then the match is terminated and the next microinstruction is retired.

[0141] At least one embodiment of the present disclosure provides a verification device, which includes a reference model unit and a scoreboard. The reference model unit is configured to obtain a microinstruction and obtain a reference result corresponding to the microinstruction. The scoreboard is configured to obtain a reference result and an execution result, and compare the reference result and the execution result, wherein the execution result is obtained by processing the microinstruction by the execution unit as the object to be verified. The verification device can verify the execution of the microinstruction obtained by decoding the instruction, thereby improving the verification efficiency.

[0142] The verification device may be, for example, Figure 1B The verification device 100 shown in FIG. Figure 1B As shown, the verification apparatus 100 may include a reference model unit 103 and a scoreboard 104. Figure 1B As shown, the verification apparatus 100 may include an instruction decoding unit in addition to the reference model unit 103 and the scoreboard 104. The instruction decoding unit is configured to decode instructions to obtain microinstructions and send the microinstructions to the reference model unit and the execution unit.

[0143] For example, the verification device 100 is used to verify the function of the execution unit 102. The execution unit 102 can, for example, execute the above reference Figure 1A Described step S20.

[0144] The instruction decoding unit 101 is configured to decode instructions to obtain microinstructions, and send the microinstructions to the reference model unit and the execution unit as verification stimuli.

[0145] The reference model unit 103 is configured to obtain microinstructions obtained by decoding instructions and obtain reference results corresponding to the microinstructions.

[0146] The reference model unit 103 performs the above reference Figure 1AStep S10 and step S30 are described.

[0147] The scoreboard 104 is configured to obtain a reference result and an execution result, and compare the reference result and the execution result. The execution result is obtained by processing the microinstruction by the execution unit as the object to be verified.

[0148] The scoreboard 104 performs, for example, the above reference Figure 1A Described step S40.

[0149] In some embodiments of the present disclosure, the verification device may include at least one data processing unit in addition to the instruction decoding unit, the reference model unit and the scoreboard. Each data processing unit is configured to accept a processing request from an execution unit, generate a processing result of the processing request, and provide the processing result to the execution unit. The execution unit generates a processing request according to the microinstruction, and sends the processing request to the data processing unit that responds to the processing request in at least one data processing unit, and the execution unit obtains an execution result according to the processing result.

[0150] For example, Figure 1B As shown, the verification device 100 includes, in addition to the instruction decoding unit 101, the reference model unit 103 and the scoreboard 104, a memory access unit 105 and a fixed-floating point conversion unit 106. The memory access unit 105 and the fixed-floating point conversion unit 106 are data processing units.

[0151] For example, the memory access unit 105 is configured to receive read and write requests from the execution unit 102, generate processing results of the read and write requests, and provide the processing results to the execution unit 102 and the reference model unit 103, so that the execution unit 102 obtains the execution result based on the processing result, and the reference model unit 103 obtains the reference result based on the processing result.

[0152] For example, the memory access unit 105 receives a read request from the execution unit 102 , obtains data information from a storage space corresponding to an address carried in the read request, and provides the data information to the execution unit 102 and the reference model unit 103 .

[0153] For another example, the memory access unit 105 receives a write request from the execution unit 102, and provides the processing result of executing the write request to the execution unit 102 and the reference model unit 103. Here, the processing result may indicate, for example, whether the processing of the write request is successful, whether there is an exception, the address written, the data written, and at least one of the following information.

[0154] For example, the fixed-floating point conversion unit 106 is configured to accept a fixed-floating point conversion request from the execution unit 102, generate a processing result of the fixed-floating point conversion, and provide the processing result to the execution unit 102, so that the execution unit 102 obtains an execution result according to the processing result.

[0155] Figure 6 A block diagram of the reference model unit 103 provided by at least one embodiment of the present disclosure is shown.

[0156] like Figure 6 As shown, the reference model unit 103 may include a microinstruction queue 113 and an operation component 123 .

[0157] The microinstruction queue 113 is configured to receive the microinstructions sent by the instruction decoding module unit 101 and maintain the microinstruction contents recorded in the queue according to the first-in-first-out principle.

[0158] The operation component 123 is configured to generate a reference result based on the microinstruction. The operation component 123 can, for example, perform the above reference Figure 1A Step S30.

[0159] In some embodiments of the present disclosure, the computing component 123 may include, for example, a fixed-point instruction computing component and / or a floating-point instruction computing component. For details about the fixed-point instruction computing component and / or the floating-point instruction computing component, please refer to the above description.

[0160] In the embodiment of the present disclosure, the operation component 123 is relatively independent and has good scalability. In the case of adding or changing microinstructions, it is only necessary to add or change the corresponding algorithm in the operation component 123 without affecting the workflow of the reference model unit 103.

[0161] In some embodiments of the present disclosure, Figure 6 As shown, the reference model unit further includes an anomaly detection component 133 and an anomaly cache component 143 .

[0162] The abnormality detection component 133 is configured to check whether an abnormality occurs during the execution of the microinstruction according to the current system state. Figure 4 In step S33, the microinstruction is checked for execution exceptions.

[0163] If it is determined that an exception will occur during the execution of the microinstruction, the exception information is recorded in the exception cache component 143 for comparison with the result of the execution unit 102 .

[0164] In some embodiments of the present disclosure, the reference model unit 103 further includes an acquisition component, which is configured to obtain a processing result of the processing request from the data processing unit, so that the operation component 123 obtains a reference result based on the processing result.

[0165] In some embodiments of the present disclosure, the reference model unit 103 may further include, for example, a read / write address queue, a read / write data queue, and a fixed-to-floating-point conversion queue.

[0166] The read / write address queue and the read / write data queue are used to record the reference results obtained by the reference model unit executing microinstructions, and the reference results include read / write address information and data information.

[0167] For example, in response to the reference model unit 103 performing an execution exception check on the microinstruction and the result of the check being that there is no exception, if the microinstruction is a read-write type microinstruction, the read-write address information obtained by executing the microinstruction is allocated to the read-write address queue, and the data information obtained by executing the microinstruction is allocated to the read-write data queue. The read-write address information and the data information are respectively waiting in the read-write address queue and the read-write data queue for the scoreboard to compare them with the execution results obtained by the execution unit.

[0168] The fixed-floating point conversion queue is used to record the fixed-floating point conversion data obtained by the microinstructions for executing the fixed-floating point data conversion.

[0169] For another example, in response to the reference model unit 103 performing an execution exception check on a microinstruction and the result being that there is no exception, if the microinstruction is a fixed-floating-point conversion type microinstruction, the fixed-floating-point conversion data in the reference result obtained by executing the microinstruction is allocated to a fixed-floating-point conversion queue to wait for the scoreboard to compare the fixed-floating-point conversion data with the execution result obtained by the execution unit.

[0170] The reference results of microinstructions of different instruction types are stored using different queues, which facilitates scoreboard comparison and improves verification efficiency.

[0171] The instruction decoding unit 101, the reference model unit 103, the scoreboard 104, the memory access unit 105 and the fixed-to-floating point conversion unit 106 may be hardware circuits written in a hardware language, for example.

[0172] It should be noted that in the embodiment of the present disclosure, each unit of the verification device 100 corresponds to each step of the aforementioned verification method. For the specific functions of the verification device 100, reference can be made to the relevant description of the verification method, which will not be repeated here. Figure 1B The components and structures of the verification device 100 shown are merely exemplary and non-limiting. The verification device 100 may further include other components and structures as required.

[0173] At least one embodiment of the present disclosure also provides an electronic device, which includes a processor; a memory, including one or more computer program instructions; one or more computer program instructions are stored in the memory, and when executed by the processor, the instructions of the verification method provided by at least one embodiment of the present disclosure are implemented. The electronic device can verify the execution of the microinstructions obtained by decoding the instructions, thereby improving the verification efficiency.

[0174] Figure 7 A schematic block diagram of an electronic device provided in some embodiments of the present disclosure. Figure 7 As shown, the electronic device 700 includes a processor 710 and a memory 720. The memory 720 is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 710 is used to run non-transitory computer-readable instructions, and when the non-transitory computer-readable instructions are run by the processor 710, one or more steps in the verification method described above can be executed. The memory 720 and the processor 710 can be interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0175] For example, the processor 710 may be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units having data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) may be an X86 or ARM architecture, etc. The processor 710 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 700 to perform desired functions.

[0176] For example, the memory 720 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 710 may run one or more computer program modules to implement various functions of the electronic device 700. Various applications and various data, as well as various data used and / or generated by the application, etc. may also be stored in the computer-readable storage medium.

[0177] It should be noted that, in the embodiment of the present disclosure, the specific functions and technical effects of the electronic device 700 can refer to the above description of the verification method, which will not be repeated here.

[0178] Figure 8 This is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. The electronic device 800 is suitable for implementing the verification method provided in the embodiments of the present disclosure. The electronic device 800 may be a terminal device, etc. It should be noted that: Figure 8 The electronic device 800 shown is merely an example and does not impose any limitation on the functions and scope of use of the embodiments of the present disclosure.

[0179] like Figure 8 As shown, the electronic device 800 may include a processing device (e.g., a central processing unit, a graphics processor, etc.) 810, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 820 or a program loaded from a storage device 880 into a random access memory (RAM) 830. In the RAM 830, various programs and data required for the operation of the electronic device 800 are also stored. The processing device 810, the ROM 820, and the RAM 830 are connected to each other via a bus 840. An input / output (I / O) interface 850 is also connected to the bus 840.

[0180] Typically, the following devices may be connected to the I / O interface 850: an input device 860 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 870 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 880 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 890. The communication device 890 may allow the electronic device 800 to communicate with other electronic devices wirelessly or by wire to exchange data. Although Figure 8 The electronic device 800 is shown to have various devices, but it should be understood that it is not required to implement or possess all of the devices shown, and the electronic device 800 may alternatively implement or possess more or fewer devices.

[0181] For example, according to an embodiment of the present disclosure, the above-mentioned verification method can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes a program code for executing the above-mentioned verification method. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 890, or installed from the storage device 880, or installed from the ROM 820. When the computer program is executed by the processing device 810, the functions defined in the verification method provided in the embodiment of the present disclosure can be implemented.

[0182] At least one embodiment of the present disclosure further provides a computer-readable storage medium, which is used to store non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are executed by a computer, the above-mentioned verification method can be implemented. The computer-readable storage medium is used to verify the execution of the microinstructions obtained by decoding the instructions, thereby improving the verification efficiency.

[0183] Fig. 9 A schematic diagram of a storage medium provided in some embodiments of the present disclosure. Fig. 9 As shown, the storage medium 900 is used to store non-transitory computer-readable instructions 910. For example, when the non-transitory computer-readable instructions 910 are executed by a computer, one or more steps in the verification method described above can be performed.

[0184] For example, the storage medium 900 may be applied to the electronic device 700. Figure 7 The memory 720 in the electronic device 700 is shown. For example, the description of the storage medium 900 can refer to Figure 7 The corresponding description of the memory 720 in the electronic device 700 is shown and will not be repeated here.

[0185] There are a few points to note:

[0186] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0187] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0188] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A verification method, comprising: Get microinstructions as validation stimulus; The execution unit as the verified object processes the microinstruction to obtain an execution result; Obtaining a reference result corresponding to the microinstruction by a reference model unit; as well as comparing the execution result with the reference result to verify the execution unit, Wherein, obtaining the reference result corresponding to the microinstruction by the reference model unit includes: The reference model unit performs execution exception checking on the microinstruction; and The reference result is obtained according to the inspection result of performing the abnormal inspection, Wherein, obtaining the reference result according to the inspection result of performing the abnormal inspection includes: In response to the detection result of the execution exception check being that the microinstruction has no exception, the microinstruction is executed to obtain the reference result.

2. The method according to claim 1, wherein: The execution unit as the verified object processes the microinstruction to obtain the execution result, including: The execution unit generates a processing request according to the microinstruction, and sends the processing request to the data processing unit; Obtaining a processing result of the processing request from the data processing unit; and The execution result is obtained based on the processing result.

3. The method according to claim 2, wherein: Obtaining the reference result corresponding to the microinstruction by the reference model unit includes: The reference model unit obtains the processing result from the data processing unit; and The reference result is obtained based on the processing result.

4. The method according to claim 2 or 3, wherein: The data processing unit includes: a memory access unit and / or a fixed-point floating-point conversion unit, Correspondingly, the processing request includes a read / write request and / or a fixed-point / floating-point conversion request. The read / write request is used to access the memory access unit, and the fixed-floating point conversion request is used to access the fixed-floating point conversion unit.

5. The method according to claim 1, wherein: In the case where the execution unit accesses the data processing unit to obtain the execution result, the reference model unit performs an execution exception check on the microinstruction, including: In response to the microinstruction being dependent on a processing result obtained from the data processing unit, the reference model unit performs the execution exception check on the microinstruction according to the processing result.

6. The method according to claim 1, wherein: In response to the detection result of the execution abnormality check being that the microinstruction has no abnormality, executing the microinstruction to obtain the reference result includes: Determining the operand type corresponding to the microinstruction; and According to the operand type, a fixed-point type operation or a floating-point type operation is performed on the operand to obtain the reference result.

7. The method according to claim 1, wherein: Comparing the execution result with the reference result to verify the execution unit includes: Determining the instruction type of the microinstruction; Determining, according to the instruction type, comparison information between the execution result and the reference result; and Compare the comparison information in the execution result with the comparison information in the reference result to see whether they are consistent.

8. The method according to claim 7, wherein: Determining, according to the instruction type, comparison information between the execution result and the reference result includes at least one of the following: In response to the instruction type being a read-write type, the comparison information includes read-write address information and data information corresponding to the read-write address; In response to the instruction type being a fixed-floating point conversion type, the comparison information includes fixed-floating point conversion data; In response to the instruction type being to update the target register, the comparison information includes data information in the target register; or In response to the instruction type being to update a flag bit, the comparison information includes data information of the flag bit.

9. The method according to claim 1, wherein: Obtaining the reference result according to the inspection result of performing the abnormal inspection further includes: In response to the inspection result being that the microinstruction is abnormal, reference abnormality information is generated, wherein the reference abnormality information serves as the reference result.

10. The method according to claim 9, wherein: Comparing the execution result with the reference result to verify the execution unit includes: In response to the presence of an exception record in the execution result, the exception record is compared with the reference exception information to verify the execution unit.

11. The method according to claim 1, wherein: Obtaining the reference result corresponding to the microinstruction by the reference model unit includes: In response to the execution unit executing the microinstruction retirement, the reference model unit obtains the reference result corresponding to the microinstruction.

12. The method according to claim 1, wherein: Obtaining the microinstruction as the verification stimulus includes: The instruction is decoded to obtain the microinstruction to serve as the verification stimulus.

13. A verification device, comprising: Reference model unit and scoreboard, where The reference model unit is configured to obtain a microinstruction as a verification stimulus and obtain a reference result corresponding to the microinstruction; The scoreboard is configured to obtain the reference result and the execution result, and compare the reference result with the execution result, wherein the execution result is obtained by processing the microinstruction by the execution unit as the verified object, Wherein, the reference model unit is further configured as: performing execution exception checking on the microinstruction; and The reference result is obtained according to the inspection result of performing the abnormal inspection, Wherein, the reference model unit is further configured to: in response to the detection result of the execution abnormality check being that the microinstruction has no abnormality, execute the microinstruction to obtain the reference result.

14. The verification device according to claim 13, further comprising: The instruction decoding unit is configured to decode the instruction to obtain the microinstruction, and send the microinstruction to the reference model unit and the execution unit as the verification stimulus.

15. The verification device according to claim 13, further comprising: at least one data processing unit, wherein each data processing unit is configured to accept a processing request from the execution unit, generate a processing result of the processing request, and provide the processing result to the execution unit; The execution unit generates the processing request according to the microinstruction, and sends the processing request to a data processing unit in the at least one data processing unit that responds to the processing request, and the execution unit obtains the execution result according to the processing result.

16. An electronic device, comprising: processor; a memory including one or more computer program instructions; The one or more computer program instructions are stored in the memory and, when executed by the processor, implement the verification method according to any one of claims 1 to 12.

17. A computer-readable storage medium non-temporarily storing computer-readable instructions, wherein: When the computer-readable instructions are executed by a processor, the verification method according to any one of claims 1 to 12 is implemented.

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